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NEON Intrinsics

+

Click on the intrinsic name to display more information about the intrinsic. To search for an intrinsic, enter the name of the intrinsic in the search box. As you type, the matching intrinsics will be displayed.

+
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+

+ + + + + + + +
+ +
+ +
+

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Add (vector). This instruction adds corresponding vector elements in the two source SIMD&FP registers, writes the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FADD Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Add (vector). This instruction adds corresponding elements in the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SADDL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SADDL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SADDL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SADDL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SADDL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SADDL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Add Long (vector). This instruction adds each vector element in the lower or upper half of the first source SIMD&FP register to the corresponding vector element of the second source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.

+

A64 Instruction

SADDW Vd.8H,Vn.8H,Vm.8B
+

Argument Preparation

a → Vn.8H 
+b → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.

+

A64 Instruction

SADDW Vd.4S,Vn.4S,Vm.4H
+

Argument Preparation

a → Vn.4S 
+b → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.

+

A64 Instruction

SADDW Vd.2D,Vn.2D,Vm.2S
+

Argument Preparation

a → Vn.2D 
+b → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDW Vd.8H,Vn.8H,Vm.8B
+

Argument Preparation

a → Vn.8H 
+b → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDW Vd.4S,Vn.4S,Vm.4H
+

Argument Preparation

a → Vn.4S 
+b → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDW Vd.2D,Vn.2D,Vm.2S
+

Argument Preparation

a → Vn.2D 
+b → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.

+

A64 Instruction

SADDW2 Vd.8H,Vn.8H,Vm.16B
+

Argument Preparation

a → Vn.8H 
+b → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.

+

A64 Instruction

SADDW2 Vd.4S,Vn.4S,Vm.8H
+

Argument Preparation

a → Vn.4S 
+b → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Add Wide. This instruction adds vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the results in a vector, and writes the vector to the SIMD&FP destination register.

+

A64 Instruction

SADDW2 Vd.2D,Vn.2D,Vm.4S
+

Argument Preparation

a → Vn.2D 
+b → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDW2 Vd.8H,Vn.8H,Vm.16B
+

Argument Preparation

a → Vn.8H 
+b → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDW2 Vd.4S,Vn.4S,Vm.8H
+

Argument Preparation

a → Vn.4S 
+b → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Add Wide. This instruction adds the vector elements of the first source SIMD&FP register to the corresponding vector elements in the lower or upper half of the second source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. The vector elements of the destination register and the first source register are twice as long as the vector elements of the second source register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDW2 Vd.2D,Vn.2D,Vm.4S
+

Argument Preparation

a → Vn.2D 
+b → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UHADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UHADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UHADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UHADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UHADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UHADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    Elem[result, e, esize] = sum<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SRHADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SRHADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SRHADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SRHADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SRHADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Halving Add. This instruction adds corresponding signed integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SRHADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URHADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URHADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URHADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URHADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URHADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Halving Add. This instruction adds corresponding unsigned integer values from the two source SIMD&FP registers, shifts each result right one bit, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URHADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, esize] = (element1+element2+1)<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQADD Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQADD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQADD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQADD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQADD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQADD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQADD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQADD Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQADD Bd,Bn,Bm
+

Argument Preparation

a → Bn 
+b → Bm

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQADD Hd,Hn,Hm
+

Argument Preparation

a → Hn 
+b → Hm

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQADD Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQADD Bd,Bn,Bm
+

Argument Preparation

a → Bn 
+b → Bm

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQADD Hd,Hn,Hm
+

Argument Preparation

a → Hn 
+b → Hm

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQADD Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Add. This instruction adds the values of corresponding elements of the two source SIMD&FP registers, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQADD Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer sum;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    sum = element1 + element2;
+    (Elem[result, e, esize], sat) = SatQ(sum, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.

+

A64 Instruction

SUQADD Vd.8B,Vn.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.

+

A64 Instruction

SUQADD Vd.16B,Vn.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.

+

A64 Instruction

SUQADD Vd.4H,Vn.4H
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.

+

A64 Instruction

SUQADD Vd.8H,Vn.8H
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.

+

A64 Instruction

SUQADD Vd.2S,Vn.2S
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.

+

A64 Instruction

SUQADD Vd.4S,Vn.4S
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.

+

A64 Instruction

SUQADD Dd,Dn
+

Argument Preparation

a → Dd 
+b → Dn

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.

+

A64 Instruction

SUQADD Vd.2D,Vn.2D
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.

+

A64 Instruction

SUQADD Bd,Bn
+

Argument Preparation

a → Bd 
+b → Bn

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.

+

A64 Instruction

SUQADD Hd,Hn
+

Argument Preparation

a → Hd 
+b → Hn

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.

+

A64 Instruction

SUQADD Sd,Sn
+

Argument Preparation

a → Sd 
+b → Sn

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Accumulate of Unsigned value. This instruction adds the unsigned integer values of the vector elements in the source SIMD&FP register to corresponding signed integer values of the vector elements in the destination SIMD&FP register, and writes the resulting signed integer values to the destination SIMD&FP register.

+

A64 Instruction

SUQADD Dd,Dn
+

Argument Preparation

a → Dd 
+b → Dn

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

USQADD Vd.8B,Vn.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

USQADD Vd.16B,Vn.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

USQADD Vd.4H,Vn.4H
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

USQADD Vd.8H,Vn.8H
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

USQADD Vd.2S,Vn.2S
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

USQADD Vd.4S,Vn.4S
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

USQADD Dd,Dn
+

Argument Preparation

a → Dd 
+b → Dn

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

USQADD Vd.2D,Vn.2D
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

USQADD Bd,Bn
+

Argument Preparation

a → Bd 
+b → Bn

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

USQADD Hd,Hn
+

Argument Preparation

a → Hd 
+b → Hn

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

USQADD Sd,Sn
+

Argument Preparation

a → Sd 
+b → Sn

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Accumulate of Signed value. This instruction adds the signed integer values of the vector elements in the source SIMD&FP register to corresponding unsigned integer values of the vector elements in the destination SIMD&FP register, and accumulates the resulting unsigned integer values with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

USQADD Dd,Dn
+

Argument Preparation

a → Dd 
+b → Dn

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(datasize) operand2 = V[d];
+integer op1;
+integer op2;
+boolean sat;
+
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, e, esize], !unsigned);
+    op2 = Int(Elem[operand2, e, esize], unsigned);
+    (Elem[result, e, esize], sat) = SatQ(op1 + op2, esize, unsigned);
+    if sat then FPSR.QC = '1';
+V[d] = result;
+

Supported architectures

A64

Description

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

ADDHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

ADDHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

ADDHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

ADDHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

ADDHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

ADDHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

ADDHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+b → Vm.8H

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

ADDHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+b → Vm.4S

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

ADDHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+b → Vm.2D

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

ADDHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+b → Vm.8H

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

ADDHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+b → Vm.4S

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

ADDHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+b → Vm.2D

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RADDHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RADDHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RADDHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RADDHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RADDHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RADDHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RADDHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+b → Vm.8H

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RADDHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+b → Vm.4S

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RADDHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+b → Vm.2D

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RADDHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+b → Vm.8H

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RADDHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+b → Vm.4S

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Add returning High Narrow. This instruction adds each vector element in the first source SIMD&FP register to the corresponding vector element in the second source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RADDHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+b → Vm.2D

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Polynomial Multiply. This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

PMUL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Polynomial Multiply. This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

PMUL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dn 
+v → Vm.1D
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vn.2D 
+v → Vm.1D
+0 << lane << 0

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 
+v → Vm.2S
+0 << lane << 1

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dn 
+v → Vm.1D
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dn 
+v → Vm.2D
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vn.2D 
+v → Vm.2D
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 
+v → Vm.4S
+0 << lane << 3

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply extended (by element). This instruction multiplies the floating-point values in the vector elements in the first source SIMD&FP register by the specified floating-point value in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMULX Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dn 
+v → Vm.2D
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(idxdsize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2 = Elem[operand2, index, esize];
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    if mulx_op then
+        Elem[result, e, esize] = FPMulX(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FDIV Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPDiv(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FDIV Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPDiv(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FDIV Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPDiv(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Divide (vector). This instruction divides the floating-point values in the elements in the first source SIMD&FP register, by the floating-point values in the corresponding elements in the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FDIV Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPDiv(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+c → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+c → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+c → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+c → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+c → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+c → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1
+

Argument Preparation

a → N/A 
+b → N/A
+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 3
+

Argument Preparation

a → N/A 
+b → N/A
+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0
+

Argument Preparation

a → N/A 
+b → N/A
+c → N/A

Results

N/A → result
+

Supported architectures

A64

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c[i]) for i = 0 to 1
+

Argument Preparation

a → N/A 
+b → N/A
+c → N/A

Results

N/A → result
+

Supported architectures

A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8H 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+c → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8H 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+c → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.8H 
+b → Vn.16B
+c → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+c → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+c → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.8H 
+b → Vn.16B
+c → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+c → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+c → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+c → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+c → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+c → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+c → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+c → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+c → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1
+

Argument Preparation

a → N/A 
+b → N/A
+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 3
+

Argument Preparation

a → N/A 
+b → N/A
+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0
+

Argument Preparation

a → N/A 
+b → N/A
+c → N/A

Results

N/A → result
+

Supported architectures

A64

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c[i]) for i = 0 to 1
+

Argument Preparation

a → N/A 
+b → N/A
+c → N/A

Results

N/A → result
+

Supported architectures

A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8H 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+c → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8H 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+c → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.8H 
+b → Vn.16B
+c → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+c → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+c → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.8H 
+b → Vn.16B
+c → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+c → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+c → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+c → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point fused Multiply-Add (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, adds the product to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FMADD Dd,Dn,Dm,Da
+

Argument Preparation

a → Da 
+b → Dn
+c → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) result;
+bits(datasize) operanda = V[a];
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+
+result = FPMulAdd(operanda, operand1, operand2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+c → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+v → Vm.2S
+0 << lane << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 
+b → Dn
+v → Vm.1D
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+v → Vm.1D
+0 << lane << 0

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sd 
+b → Sn
+v → Vm.2S
+0 << lane << 1

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 
+b → Dn
+v → Vm.1D
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+v → Vm.4S
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 
+b → Dn
+v → Vm.2D
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+v → Vm.2D
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sd 
+b → Sn
+v → Vm.4S
+0 << lane << 3

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 
+b → Dn
+v → Vm.2D
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+c → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, negates the product, adds that to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FMSUB Dd,Dn,Dm,Da
+

Argument Preparation

a → Da 
+b → Dn
+c → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) result;
+bits(datasize) operanda = V[a];
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+
+operand1 = FPNeg(operand1);
+result = FPMulAdd(operanda, operand1, operand2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+c → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+v → Vm.2S
+0 << lane << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 
+b → Dn
+v → Vm.1D
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+v → Vm.1D
+0 << lane << 0

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sd 
+b → Sn
+v → Vm.2S
+0 << lane << 1

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 
+b → Dn
+v → Vm.1D
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+v → Vm.4S
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 
+b → Dn
+v → Vm.2D
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+v → Vm.2D
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sd 
+b → Sn
+v → Vm.4S
+0 << lane << 3

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dd 
+b → Dn
+v → Vm.2D
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Hd,Hn,Hm
+

Argument Preparation

a → Hn 
+b → Hm

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Hd,Hn,Hm
+

Argument Preparation

a → Hn 
+b → Hm

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+c → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL Sd,Hn,Hm
+

Argument Preparation

a → Sd 
+b → Hn
+c → Hm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL Dd,Sn,Sm
+

Argument Preparation

a → Dd 
+b → Sn
+c → Sm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+c → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+c → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+c → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL Sd,Hn,Hm
+

Argument Preparation

a → Sd 
+b → Hn
+c → Hm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL Dd,Sn,Sm
+

Argument Preparation

a → Dd 
+b → Sn
+c → Sm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+c → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+c → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Polynomial Multiply Long. This instruction multiplies corresponding elements in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

PMULL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, 2*esize] = PolynomialMult(element1, element2);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Polynomial Multiply Long. This instruction multiplies corresponding elements in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

PMULL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, 2*esize] = PolynomialMult(element1, element2);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL Sd,Hn,Hm
+

Argument Preparation

a → Hn 
+b → Hm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL Dd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FSUB Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FSUB Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FSUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Subtract (vector). This instruction subtracts the elements in the vector in the second source SIMD&FP register, from the corresponding elements in the vector in the first source SIMD&FP register, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FSUB Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;
+

Supported architectures

A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Subtract (vector). This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then
+        Elem[result, e, esize] = element1 - element2;
+    else
+        Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SSUBL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SSUBL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SSUBL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USUBL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USUBL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USUBL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SSUBL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SSUBL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SSUBL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USUBL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USUBL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Subtract Long. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USUBL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.

+

A64 Instruction

SSUBW Vd.8H,Vn.8H,Vm.8B
+

Argument Preparation

a → Vn.8H 
+b → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.

+

A64 Instruction

SSUBW Vd.4S,Vn.4S,Vm.4H
+

Argument Preparation

a → Vn.4S 
+b → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.

+

A64 Instruction

SSUBW Vd.2D,Vn.2D,Vm.2S
+

Argument Preparation

a → Vn.2D 
+b → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.

+

A64 Instruction

USUBW Vd.8H,Vn.8H,Vm.8B
+

Argument Preparation

a → Vn.8H 
+b → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.

+

A64 Instruction

USUBW Vd.4S,Vn.4S,Vm.4H
+

Argument Preparation

a → Vn.4S 
+b → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.

+

A64 Instruction

USUBW Vd.2D,Vn.2D,Vm.2S
+

Argument Preparation

a → Vn.2D 
+b → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.

+

A64 Instruction

SSUBW2 Vd.8H,Vn.8H,Vm.16B
+

Argument Preparation

a → Vn.8H 
+b → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.

+

A64 Instruction

SSUBW2 Vd.4S,Vn.4S,Vm.8H
+

Argument Preparation

a → Vn.4S 
+b → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Subtract Wide. This instruction subtracts each vector element in the lower or upper half of the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.

+

A64 Instruction

SSUBW2 Vd.2D,Vn.2D,Vm.4S
+

Argument Preparation

a → Vn.2D 
+b → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.

+

A64 Instruction

USUBW2 Vd.8H,Vn.8H,Vm.16B
+

Argument Preparation

a → Vn.8H 
+b → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.

+

A64 Instruction

USUBW2 Vd.4S,Vn.4S,Vm.8H
+

Argument Preparation

a → Vn.4S 
+b → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Subtract Wide. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element in the lower or upper half of the first source SIMD&FP register, places the result in a vector, and writes the vector to the SIMD&FP destination register. All the values in this instruction are signed integer values.

+

A64 Instruction

USUBW2 Vd.2D,Vn.2D,Vm.4S
+

Argument Preparation

a → Vn.2D 
+b → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+integer sum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, 2*esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    Elem[result, e, 2*esize] = sum<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHSUB Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHSUB Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHSUB Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHSUB Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHSUB Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Halving Subtract. This instruction subtracts the elements in the vector in the second source SIMD&FP register from the corresponding elements in the vector in the first source SIMD&FP register, shifts each result right one bit, places each result into elements of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHSUB Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UHSUB Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UHSUB Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UHSUB Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UHSUB Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UHSUB Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Halving Subtract. This instruction subtracts the vector elements in the second source SIMD&FP register from the corresponding vector elements in the first source SIMD&FP register, shifts each result right one bit, places each result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UHSUB Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    Elem[result, e, esize] = diff<esize:1>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSUB Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSUB Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSUB Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSUB Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSUB Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSUB Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSUB Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSUB Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSUB Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSUB Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSUB Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSUB Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSUB Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSUB Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSUB Bd,Bn,Bm
+

Argument Preparation

a → Bn 
+b → Bm

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSUB Hd,Hn,Hm
+

Argument Preparation

a → Hn 
+b → Hm

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSUB Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSUB Bd,Bn,Bm
+

Argument Preparation

a → Bn 
+b → Bm

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSUB Hd,Hn,Hm
+

Argument Preparation

a → Hn 
+b → Hm

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSUB Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Subtract. This instruction subtracts the element values of the second source SIMD&FP register from the corresponding element values of the first source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSUB Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer diff;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    diff = element1 - element2;
+    (Elem[result, e, esize], sat) = SatQ(diff, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SUBHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SUBHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SUBHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SUBHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SUBHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SUBHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SUBHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+b → Vm.8H

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SUBHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+b → Vm.4S

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SUBHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+b → Vm.2D

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SUBHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+b → Vm.8H

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SUBHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+b → Vm.4S

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Subtract returning High Narrow. This instruction subtracts each vector element in the second source SIMD&FP register from the corresponding vector element in the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SUBHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+b → Vm.2D

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RSUBHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RSUBHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RSUBHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RSUBHN Vd.8B,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RSUBHN Vd.4H,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RSUBHN Vd.2S,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RSUBHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+b → Vm.8H

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RSUBHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+b → Vm.4S

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RSUBHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+b → Vm.2D

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RSUBHN2 Vd.16B,Vn.8H,Vm.8H
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+b → Vm.8H

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RSUBHN2 Vd.8H,Vn.4S,Vm.4S
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+b → Vm.4S

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Subtract returning High Narrow. This instruction subtracts each vector element of the second source SIMD&FP register from the corresponding vector element of the first source SIMD&FP register, places the most significant half of the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register.

+

A64 Instruction

RSUBHN2 Vd.4S,Vn.2D,Vm.2D
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+b → Vm.2D

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand1 = V[n];
+bits(2*datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if round then 1 << (esize - 1) else 0;
+bits(2*esize) element1;
+bits(2*esize) element2;
+bits(2*esize) sum;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, 2*esize];
+    element2 = Elem[operand2, e, 2*esize];
+    if sub_op then
+        sum = element1 - element2;
+    else
+        sum = element1 + element2;
+    sum = sum + round_const;
+    Elem[result, e, esize] = sum<2*esize-1:esize>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMEQ Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMEQ Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMEQ Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMEQ Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMEQ Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMEQ Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.8B,Vn.8B,#0
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.16B,Vn.16B,#0
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.4H,Vn.4H,#0
+

Argument Preparation

a → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.8H,Vn.8H,#0
+

Argument Preparation

a → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.8B,Vn.8B,#0
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.16B,Vn.16B,#0
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.4H,Vn.4H,#0
+

Argument Preparation

a → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.8H,Vn.8H,#0
+

Argument Preparation

a → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMEQ Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMEQ Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.8B,Vn.8B,#0
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.16B,Vn.16B,#0
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMEQ Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMEQ Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMEQ Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMEQ Sd,Sn,#0
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMEQ Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.8B,Vm.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.16B,Vm.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.4H,Vm.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.8H,Vm.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Vd.8B,Vm.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Vd.16B,Vm.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Vd.4H,Vm.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Vd.8H,Vm.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.8B,Vn.8B,#0
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.16B,Vn.16B,#0
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.4H,Vn.4H,#0
+

Argument Preparation

a → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.8H,Vn.8H,#0
+

Argument Preparation

a → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Sd,Sn,#0
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.8B,Vm.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.16B,Vm.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.4H,Vm.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.8H,Vm.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Vd.8B,Vm.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Vd.16B,Vm.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Vd.4H,Vm.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Vd.8H,Vm.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGE Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare unsigned Higher or Same (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than or equal to the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHS Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Sd,Sm,Sn
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGE Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLE Vd.8B,Vn.8B,#0
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLE Vd.16B,Vn.16B,#0
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLE Vd.4H,Vn.4H,#0
+

Argument Preparation

a → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLE Vd.8H,Vn.8H,#0
+

Argument Preparation

a → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLE Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLE Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLE Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLE Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLE Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMLE Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMLE Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMLE Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than or Equal to zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLE Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMLE Sd,Sn,#0
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Less than or Equal to zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than or equal to zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMLE Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.8B,Vn.8B,#0
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.16B,Vn.16B,#0
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.4H,Vn.4H,#0
+

Argument Preparation

a → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.8H,Vn.8H,#0
+

Argument Preparation

a → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Sd,Sn,#0
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.8B,Vm.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.16B,Vm.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.4H,Vm.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.8H,Vm.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Vd.8B,Vm.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Vd.16B,Vm.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Vd.4H,Vm.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Vd.8H,Vm.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Greater than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMGT Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare unsigned Higher (vector). This instruction compares each vector element in the first source SIMD&FP register with the corresponding vector element in the second source SIMD&FP register and if the first unsigned integer value is greater than the second unsigned integer value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMHI Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    test_passed = if cmp_eq then element1 >= element2 else element1 > element2;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Sd,Sm,Sn
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Greater than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is greater than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMGT Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLT Vd.8B,Vn.8B,#0
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLT Vd.16B,Vn.16B,#0
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLT Vd.4H,Vn.4H,#0
+

Argument Preparation

a → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLT Vd.8H,Vn.8H,#0
+

Argument Preparation

a → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLT Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLT Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLT Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLT Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMLT Vd.2S,Vn.2S,#0
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMLT Vd.4S,Vn.4S,#0
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMLT Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMLT Vd.2D,Vn.2D,#0
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare signed Less than zero (vector). This instruction reads each vector element in the source SIMD&FP register and if the signed integer value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMLT Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    case comparison of
+        when CompareOp_GT test_passed = element > 0;
+        when CompareOp_GE test_passed = element >= 0;
+        when CompareOp_EQ test_passed = element == 0;
+        when CompareOp_LE test_passed = element <= 0;
+        when CompareOp_LT test_passed = element < 0;
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMLT Sd,Sn,#0
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Compare Less than zero (vector). This instruction reads each floating-point value in the source SIMD&FP register and if the value is less than zero sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FCMLT Dd,Dn,#0
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) zero = FPZero('0');
+bits(esize) element;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    case comparison of
+        when CompareOp_GT test_passed = FPCompareGT(element, zero, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element, zero, FPCR);
+        when CompareOp_EQ test_passed = FPCompareEQ(element, zero, FPCR);
+        when CompareOp_LE test_passed = FPCompareGE(zero, element, FPCR);
+        when CompareOp_LT test_passed = FPCompareGT(zero, element, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGE Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGE Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGE Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGE Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGE Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGE Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGE Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGE Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGE Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGE Vd.2D,Vm.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGE Sd,Sm,Sn
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than or Equal (vector). This instruction compares the absolute value of each floating-point value in the first source SIMD&FP register with the absolute value of the corresponding floating-point value in the second source SIMD&FP register and if the first value is greater than or equal to the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGE Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGT Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGT Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGT Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGT Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGT Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGT Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGT Vd.2S,Vm.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGT Vd.4S,Vm.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGT Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGT Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGT Sd,Sm,Sn
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Compare Greater than (vector). This instruction compares the absolute value of each vector element in the first source SIMD&FP register with the absolute value of the corresponding vector element in the second source SIMD&FP register and if the first value is greater than the second value sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

FACGT Dd,Dm,Dn
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if abs then
+        element1 = FPAbs(element1);
+        element2 = FPAbs(element2);
+    case cmp of
+        when CompareOp_EQ test_passed = FPCompareEQ(element1, element2, FPCR);
+        when CompareOp_GE test_passed = FPCompareGE(element1, element2, FPCR);
+        when CompareOp_GT test_passed = FPCompareGT(element1, element2, FPCR);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Compare bitwise Test bits nonzero (vector). This instruction reads each vector element in the first source SIMD&FP register, performs an AND with the corresponding vector element in the second source SIMD&FP register, and if the result is not zero, sets every bit of the corresponding vector element in the destination SIMD&FP register to one, otherwise sets every bit of the corresponding vector element in the destination SIMD&FP register to zero.

+

A64 Instruction

CMTST Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+boolean test_passed;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if and_test then
+        test_passed = !IsZero(element1 AND element2);
+    else
+        test_passed = (element1 == element2);
+    Elem[result, e, esize] = if test_passed then Ones() else Zeros();
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SABD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SABD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SABD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SABD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SABD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute Difference. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SABD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UABD Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UABD Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UABD Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UABD Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UABD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute Difference (vector). This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, places the the absolute values of the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UABD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FABD Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FABD Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FABD Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FABD Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FABD Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute Difference (vector). This instruction subtracts the floating-point values in the elements of the second source SIMD&FP register, from the corresponding floating-point values in the elements of the first source SIMD&FP register, places the absolute value of each result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FABD Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) diff;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    diff = FPSub(element1, element2, FPCR);
+    Elem[result, e, esize] = if abs then FPAbs(diff) else diff;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SABDL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SABDL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SABDL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UABDL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UABDL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UABDL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SABDL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

A64

Description

Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SABDL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

A64

Description

Signed Absolute Difference Long. This instruction subtracts the vector elements of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the results into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SABDL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UABDL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UABDL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Absolute Difference Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, places the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UABDL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

A64

Description

Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.

+

A64 Instruction

SABA Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.

+

A64 Instruction

SABA Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.

+

A64 Instruction

SABA Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+c → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.

+

A64 Instruction

SABA Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+c → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.

+

A64 Instruction

SABA Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.

+

A64 Instruction

SABA Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+c → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.

+

A64 Instruction

UABA Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.

+

A64 Instruction

UABA Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.

+

A64 Instruction

UABA Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+c → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.

+

A64 Instruction

UABA Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+c → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.

+

A64 Instruction

UABA Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute difference and Accumulate. This instruction subtracts the elements of the vector of the second source SIMD&FP register from the corresponding elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the elements of the vector of the destination SIMD&FP register.

+

A64 Instruction

UABA Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+c → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+bits(esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<esize-1:0>;
+    Elem[result, e, esize] = Elem[result, e, esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SABAL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8H 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SABAL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+c → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SABAL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UABAL Vd.8H,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8H 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UABAL Vd.4S,Vn.4H,Vm.4H
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+c → Vm.4H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UABAL Vd.2D,Vn.2S,Vm.2S
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+c → Vm.2S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SABAL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.8H 
+b → Vn.16B
+c → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

A64

Description

Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SABAL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+c → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

A64

Description

Signed Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SABAL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+c → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UABAL2 Vd.8H,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.8H 
+b → Vn.16B
+c → Vm.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UABAL2 Vd.4S,Vn.8H,Vm.8H
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+c → Vm.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Absolute difference and Accumulate Long. This instruction subtracts the vector elements in the lower or upper half of the second source SIMD&FP register from the corresponding vector elements of the first source SIMD&FP register, and accumulates the absolute values of the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UABAL2 Vd.2D,Vn.4S,Vm.4S
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+c → Vm.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) absdiff;
+
+result = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    absdiff = Abs(element1-element2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + absdiff;
+V[d] = result;
+

Supported architectures

A64

Description

Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMAX Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMAX Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMAX Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMAX Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMAX Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMAX Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMAX Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMAX Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMAX Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMAX Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMAX Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMAX Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMAX Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMAX Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMAX Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Maximum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the larger of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMAX Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMIN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMIN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMIN Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMIN Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMIN Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMIN Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMIN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMIN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMIN Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMIN Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMIN Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Minimum (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, places the smaller of each of the two unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMIN Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMIN Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMIN Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMIN Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point minimum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the smaller of each of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMIN Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMAXNM Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMAXNM Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMAXNM Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Maximum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the larger of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMAXNM Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMINNM Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMINNM Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMINNM Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Minimum Number (vector). This instruction compares corresponding vector elements in the two source SIMD&FP registers, writes the smaller of the two floating-point values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMINNM Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SSHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SSHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SSHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SSHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SSHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SSHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SSHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

USHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

USHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

USHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

USHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

USHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

USHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

USHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

USHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts each value by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

USHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Bd,Bn,Bm
+

Argument Preparation

a → Bn 
+b → Bm

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Hd,Hn,Hm
+

Argument Preparation

a → Hn 
+b → Hm

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Bd,Bn,Bm
+

Argument Preparation

a → Bn 
+b → Bm

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Hd,Hn,Hm
+

Argument Preparation

a → Hn 
+b → Hm

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SRSHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SRSHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SRSHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SRSHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SRSHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SRSHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SRSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SRSHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URSHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URSHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URSHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URSHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URSHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URSHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URSHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Left (register). This instruction takes each signed integer value in the vector of the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SRSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Rounding Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRSHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRSHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRSHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRSHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRSHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRSHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRSHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQRSHL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQRSHL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQRSHL Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQRSHL Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQRSHL Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQRSHL Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQRSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQRSHL Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRSHL Bd,Bn,Bm
+

Argument Preparation

a → Bn 
+b → Bm

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRSHL Hd,Hn,Hm
+

Argument Preparation

a → Hn 
+b → Hm

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRSHL Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Rounding Shift Left (register). This instruction takes each vector element in the first source SIMD&FP register, shifts it by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQRSHL Bd,Bn,Bm
+

Argument Preparation

a → Bn 
+b → Bm

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQRSHL Hd,Hn,Hm
+

Argument Preparation

a → Hn 
+b → Hm

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQRSHL Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Rounding Shift Left (register). This instruction takes each vector element of the first source SIMD&FP register, shifts the vector element by a value from the least significant byte of the corresponding vector element of the second source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQRSHL Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.

+

A64 Instruction

SSHR Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.

+

A64 Instruction

SSHR Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.

+

A64 Instruction

SSHR Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.

+

A64 Instruction

SSHR Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.

+

A64 Instruction

SSHR Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.

+

A64 Instruction

SSHR Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.

+

A64 Instruction

SSHR Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.

+

A64 Instruction

SSHR Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 64

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.

+

A64 Instruction

USHR Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.

+

A64 Instruction

USHR Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.

+

A64 Instruction

USHR Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.

+

A64 Instruction

USHR Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.

+

A64 Instruction

USHR Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.

+

A64 Instruction

USHR Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.

+

A64 Instruction

USHR Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.

+

A64 Instruction

USHR Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 64

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSHR.

+

A64 Instruction

SSHR Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSHR.

+

A64 Instruction

USHR Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 
+0 << n << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 
+0 << n << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 
+0 << n << 15

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+0 << n << 15

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+0 << n << 31

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+0 << n << 31

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Dd,Dn,#n
+

Argument Preparation

a → Dn 
+0 << n << 63

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+0 << n << 63

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 
+0 << n << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 
+0 << n << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 
+0 << n << 15

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+0 << n << 15

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+0 << n << 31

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+0 << n << 31

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Dd,Dn,#n
+

Argument Preparation

a → Dn 
+0 << n << 63

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+0 << n << 63

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Dd,Dn,#n
+

Argument Preparation

a → Dn 
+0 << n << 63

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

A64

Description

Shift Left (immediate). This instruction reads each value from a vector, left shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SHL Dd,Dn,#n
+

Argument Preparation

a → Dn 
+0 << n << 63

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = LSL(Elem[operand, e, esize], shift);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.

+

A64 Instruction

SRSHR Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.

+

A64 Instruction

SRSHR Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.

+

A64 Instruction

SRSHR Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.

+

A64 Instruction

SRSHR Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.

+

A64 Instruction

SRSHR Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.

+

A64 Instruction

SRSHR Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.

+

A64 Instruction

SRSHR Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.

+

A64 Instruction

SRSHR Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 64

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.

+

A64 Instruction

URSHR Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.

+

A64 Instruction

URSHR Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.

+

A64 Instruction

URSHR Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.

+

A64 Instruction

URSHR Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.

+

A64 Instruction

URSHR Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.

+

A64 Instruction

URSHR Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.

+

A64 Instruction

URSHR Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.

+

A64 Instruction

URSHR Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 64

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, places the final result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSHR.

+

A64 Instruction

SRSHR Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Rounding Shift Right (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USHR.

+

A64 Instruction

URSHR Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.

+

A64 Instruction

SSRA Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.

+

A64 Instruction

SSRA Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.

+

A64 Instruction

SSRA Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.

+

A64 Instruction

SSRA Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.

+

A64 Instruction

SSRA Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.

+

A64 Instruction

SSRA Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.

+

A64 Instruction

SSRA Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.

+

A64 Instruction

SSRA Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+1 << n << 64

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.

+

A64 Instruction

USRA Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.

+

A64 Instruction

USRA Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.

+

A64 Instruction

USRA Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.

+

A64 Instruction

USRA Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.

+

A64 Instruction

USRA Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.

+

A64 Instruction

USRA Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.

+

A64 Instruction

USRA Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.

+

A64 Instruction

USRA Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+1 << n << 64

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are truncated. For rounded results, see SRSRA.

+

A64 Instruction

SSRA Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see URSRA.

+

A64 Instruction

USRA Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.

+

A64 Instruction

SRSRA Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.

+

A64 Instruction

SRSRA Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.

+

A64 Instruction

SRSRA Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.

+

A64 Instruction

SRSRA Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.

+

A64 Instruction

SRSRA Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.

+

A64 Instruction

SRSRA Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.

+

A64 Instruction

SRSRA Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.

+

A64 Instruction

SRSRA Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+1 << n << 64

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.

+

A64 Instruction

URSRA Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.

+

A64 Instruction

URSRA Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.

+

A64 Instruction

URSRA Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.

+

A64 Instruction

URSRA Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.

+

A64 Instruction

URSRA Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.

+

A64 Instruction

URSRA Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.

+

A64 Instruction

URSRA Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.

+

A64 Instruction

URSRA Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+1 << n << 64

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are signed integer values. The results are rounded. For truncated results, see SSRA.

+

A64 Instruction

SRSRA Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Rounding Shift Right and Accumulate (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, and accumulates the final results with the vector elements of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see USRA.

+

A64 Instruction

URSRA Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2;
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+operand2 = if accumulate then V[d] else Zeros();
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, esize], unsigned) + round_const) >> shift;
+    Elem[result, e, esize] = Elem[operand2, e, esize] + element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 
+0 << n << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 
+0 << n << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 
+0 << n << 15

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+0 << n << 15

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+0 << n << 31

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+0 << n << 31

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Dd,Dn,#n
+

Argument Preparation

a → Dn 
+0 << n << 63

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+0 << n << 63

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 
+0 << n << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 
+0 << n << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 
+0 << n << 15

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+0 << n << 15

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+0 << n << 31

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+0 << n << 31

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Dd,Dn,#n
+

Argument Preparation

a → Dn 
+0 << n << 63

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+0 << n << 63

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Bd,Bn,#n
+

Argument Preparation

a → Bn 
+0 << n << 7

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Hd,Hn,#n
+

Argument Preparation

a → Hn 
+0 << n << 15

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Sd,Sn,#n
+

Argument Preparation

a → Sn 
+0 << n << 31

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts each element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQSHL Dd,Dn,#n
+

Argument Preparation

a → Dn 
+0 << n << 63

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Bd,Bn,#n
+

Argument Preparation

a → Bn 
+0 << n << 7

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Hd,Hn,#n
+

Argument Preparation

a → Hn 
+0 << n << 15

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Sd,Sn,#n
+

Argument Preparation

a → Sn 
+0 << n << 31

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned saturating Shift Left (register). This instruction takes each element in the vector of the first source SIMD&FP register, shifts the element by a value from the least significant byte of the corresponding element of the second source SIMD&FP register, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UQSHL Dd,Dn,#n
+

Argument Preparation

a → Dn 
+0 << n << 63

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer round_const = 0;
+integer shift;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    shift = SInt(Elem[operand2, e, esize]<7:0>);
+    if rounding then
+        round_const = 1 << (-shift - 1);    // 0 for left shift, 2^(n-1) for right shift 
+    element = (Int(Elem[operand1, e, esize], unsigned) + round_const) << shift;
+    if saturating then
+        (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+        if sat then FPSR.QC = '1';
+    else
+        Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.

+

A64 Instruction

SQSHLU Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 
+0 << n << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.

+

A64 Instruction

SQSHLU Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 
+0 << n << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.

+

A64 Instruction

SQSHLU Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 
+0 << n << 15

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.

+

A64 Instruction

SQSHLU Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+0 << n << 15

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.

+

A64 Instruction

SQSHLU Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+0 << n << 31

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.

+

A64 Instruction

SQSHLU Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+0 << n << 31

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.

+

A64 Instruction

SQSHLU Dd,Dn,#n
+

Argument Preparation

a → Dn 
+0 << n << 63

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.

+

A64 Instruction

SQSHLU Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+0 << n << 63

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.

+

A64 Instruction

SQSHLU Bd,Bn,#n
+

Argument Preparation

a → Bn 
+0 << n << 7

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.

+

A64 Instruction

SQSHLU Hd,Hn,#n
+

Argument Preparation

a → Hn 
+0 << n << 15

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.

+

A64 Instruction

SQSHLU Sd,Sn,#n
+

Argument Preparation

a → Sn 
+0 << n << 31

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Left Unsigned (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, shifts each value by an immediate value, saturates the shifted result to an unsigned integer value, places the result in a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see UQRSHL.

+

A64 Instruction

SQSHLU Dd,Dn,#n
+

Argument Preparation

a → Dn 
+0 << n << 63

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], src_unsigned) << shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, dst_unsigned);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.

+

A64 Instruction

SHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.

+

A64 Instruction

SHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.

+

A64 Instruction

SHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.

+

A64 Instruction

SHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.

+

A64 Instruction

SHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.

+

A64 Instruction

SHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.

+

A64 Instruction

SHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.

+

A64 Instruction

SHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.

+

A64 Instruction

SHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.

+

A64 Instruction

SHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.

+

A64 Instruction

SHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are truncated. For rounded results, see RSHRN.

+

A64 Instruction

SHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.

+

A64 Instruction

SQSHRUN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.

+

A64 Instruction

SQSHRUN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.

+

A64 Instruction

SQSHRUN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.

+

A64 Instruction

SQSHRUN Bd,Hn,#n
+

Argument Preparation

a → Hn 
+1 << n << 8

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.

+

A64 Instruction

SQSHRUN Hd,Sn,#n
+

Argument Preparation

a → Sn 
+1 << n << 16

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.

+

A64 Instruction

SQSHRUN Sd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 32

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.

+

A64 Instruction

SQSHRUN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.

+

A64 Instruction

SQSHRUN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are truncated. For rounded results, see SQRSHRUN.

+

A64 Instruction

SQSHRUN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.

+

A64 Instruction

SQRSHRUN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.

+

A64 Instruction

SQRSHRUN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.

+

A64 Instruction

SQRSHRUN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.

+

A64 Instruction

SQRSHRUN Bd,Hn,#n
+

Argument Preparation

a → Hn 
+1 << n << 8

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.

+

A64 Instruction

SQRSHRUN Hd,Sn,#n
+

Argument Preparation

a → Sn 
+1 << n << 16

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.

+

A64 Instruction

SQRSHRUN Sd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 32

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.

+

A64 Instruction

SQRSHRUN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.

+

A64 Instruction

SQRSHRUN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Rounded Shift Right Unsigned Narrow (immediate). This instruction reads each signed integer value in the vector of the source SIMD&FP register, right shifts each value by an immediate value, saturates the result to an unsigned integer value that is half the original width, places the final result into a vector, and writes the vector to the destination SIMD&FP register. The results are rounded. For truncated results, see SQSHRUN.

+

A64 Instruction

SQRSHRUN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (SInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = UnsignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.

+

A64 Instruction

SQSHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.

+

A64 Instruction

SQSHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.

+

A64 Instruction

SQSHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.

+

A64 Instruction

UQSHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.

+

A64 Instruction

UQSHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.

+

A64 Instruction

UQSHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.

+

A64 Instruction

SQSHRN Bd,Hn,#n
+

Argument Preparation

a → Hn 
+1 << n << 8

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.

+

A64 Instruction

SQSHRN Hd,Sn,#n
+

Argument Preparation

a → Sn 
+1 << n << 16

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.

+

A64 Instruction

SQSHRN Sd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 32

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.

+

A64 Instruction

UQSHRN Bd,Hn,#n
+

Argument Preparation

a → Hn 
+1 << n << 8

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.

+

A64 Instruction

UQSHRN Hd,Sn,#n
+

Argument Preparation

a → Sn 
+1 << n << 16

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.

+

A64 Instruction

UQSHRN Sd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 32

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.

+

A64 Instruction

SQSHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.

+

A64 Instruction

SQSHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts and truncates each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. For rounded results, see SQRSHRN.

+

A64 Instruction

SQSHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.

+

A64 Instruction

UQSHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.

+

A64 Instruction

UQSHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are truncated. For rounded results, see UQRSHRN.

+

A64 Instruction

UQSHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.

+

A64 Instruction

RSHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.

+

A64 Instruction

RSHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.

+

A64 Instruction

RSHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.

+

A64 Instruction

RSHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.

+

A64 Instruction

RSHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.

+

A64 Instruction

RSHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.

+

A64 Instruction

RSHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.

+

A64 Instruction

RSHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.

+

A64 Instruction

RSHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.

+

A64 Instruction

RSHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.

+

A64 Instruction

RSHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Rounding Shift Right Narrow (immediate). This instruction reads each unsigned integer value from the vector in the source SIMD&FP register, right shifts each result by an immediate value, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SHRN.

+

A64 Instruction

RSHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → 32(Vd) 
+a → Vn.2D
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+
+for e = 0 to elements-1
+    element = (UInt(Elem[operand, e, 2*esize]) + round_const) >> shift;
+    Elem[result, e, esize] = element<esize-1:0>;
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.

+

A64 Instruction

SQRSHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.

+

A64 Instruction

SQRSHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.

+

A64 Instruction

SQRSHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.

+

A64 Instruction

UQRSHRN Vd.8B,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.

+

A64 Instruction

UQRSHRN Vd.4H,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.

+

A64 Instruction

UQRSHRN Vd.2S,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.

+

A64 Instruction

SQRSHRN Bd,Hn,#n
+

Argument Preparation

a → Hn 
+1 << n << 8

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.

+

A64 Instruction

SQRSHRN Hd,Sn,#n
+

Argument Preparation

a → Sn 
+1 << n << 16

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.

+

A64 Instruction

SQRSHRN Sd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 32

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.

+

A64 Instruction

UQRSHRN Bd,Hn,#n
+

Argument Preparation

a → Hn 
+1 << n << 8

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.

+

A64 Instruction

UQRSHRN Hd,Sn,#n
+

Argument Preparation

a → Sn 
+1 << n << 16

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.

+

A64 Instruction

UQRSHRN Sd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 32

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.

+

A64 Instruction

SQRSHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.

+

A64 Instruction

SQRSHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, saturates each shifted result to a value that is half the original width, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are signed integer values. The destination vector elements are half as long as the source vector elements. The results are rounded. For truncated results, see SQSHRN.

+

A64 Instruction

SQRSHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.

+

A64 Instruction

UQRSHRN2 Vd.16B,Vn.8H,#n
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.

+

A64 Instruction

UQRSHRN2 Vd.8H,Vn.4S,#n
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating Rounded Shift Right Narrow (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each result by an immediate value, puts the final result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. All the values in this instruction are unsigned integer values. The results are rounded. For truncated results, see UQSHRN.

+

A64 Instruction

UQRSHRN2 Vd.4S,Vn.2D,#n
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize*2) operand = V[n];
+bits(datasize) result;
+integer round_const = if round then (1 << (shift - 1)) else 0;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = (Int(Elem[operand, e, 2*esize], unsigned) + round_const) >> shift;
+    (Elem[result, e, esize], sat) = SatQ(element, esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SSHLL Vd.8H,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 
+0 << n << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SSHLL Vd.4S,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 
+0 << n << 15

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SSHLL Vd.2D,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+0 << n << 31

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USHLL Vd.8H,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 
+0 << n << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USHLL Vd.4S,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 
+0 << n << 15

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USHLL Vd.2D,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+0 << n << 31

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SSHLL2 Vd.8H,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 
+0 << n << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SSHLL2 Vd.4S,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+0 << n << 15

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SSHLL2 Vd.2D,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+0 << n << 31

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USHLL2 Vd.8H,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 
+0 << n << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USHLL2 Vd.4S,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+0 << n << 15

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USHLL2 Vd.2D,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+0 << n << 31

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SHLL Vd.8H,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 
+8 << n << 8

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SHLL Vd.4S,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 
+16 << n << 16

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SHLL Vd.2D,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+32 << n << 32

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SHLL Vd.8H,Vn.8B,#n
+

Argument Preparation

a → Vn.8B 
+8 << n << 8

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SHLL Vd.4S,Vn.4H,#n
+

Argument Preparation

a → Vn.4H 
+16 << n << 16

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SHLL Vd.2D,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+32 << n << 32

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SHLL2 Vd.8H,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 
+8 << n << 8

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SHLL2 Vd.4S,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+16 << n << 16

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SHLL2 Vd.2D,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+32 << n << 32

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SHLL2 Vd.8H,Vn.16B,#n
+

Argument Preparation

a → Vn.16B 
+8 << n << 8

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SHLL2 Vd.4S,Vn.8H,#n
+

Argument Preparation

a → Vn.8H 
+16 << n << 16

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Shift Left Long (by element size). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, left shifts each result by the element size, writes the final result to a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SHLL2 Vd.2D,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+32 << n << 32

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+1 << n << 64

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+1 << n << 64

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+1 << n << 64

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+1 << n << 8

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+1 << n << 8

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+1 << n << 16

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+1 << n << 16

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

A64

Description

Shift Right and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, right shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the right of each vector element of the source register are lost.

+

A64 Instruction

SRI Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSR(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSR(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+0 << n << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+0 << n << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+0 << n << 15

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+0 << n << 15

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+0 << n << 31

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+0 << n << 31

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+0 << n << 63

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+0 << n << 63

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+0 << n << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+0 << n << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+0 << n << 15

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+0 << n << 15

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+0 << n << 31

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+0 << n << 31

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+0 << n << 63

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+0 << n << 63

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+0 << n << 63

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+0 << n << 63

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.8B,Vn.8B,#n
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+0 << n << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.16B,Vn.16B,#n
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+0 << n << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.4H,Vn.4H,#n
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+0 << n << 15

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Vd.8H,Vn.8H,#n
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+0 << n << 15

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+0 << n << 63

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

A64

Description

Shift Left and Insert (immediate). This instruction reads each vector element in the source SIMD&FP register, left shifts each vector element by an immediate value, and inserts the result into the corresponding vector element in the destination SIMD&FP register such that the new zero bits created by the shift are not inserted but retain their existing value. Bits shifted out of the left of each vector element in the source register are lost.

+

A64 Instruction

SLI Dd,Dn,#n
+

Argument Preparation

a → Dd 
+b → Dn
+0 << n << 63

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) operand2 = V[d];
+bits(datasize) result;
+bits(esize) mask = LSL(Ones(esize), shift);
+bits(esize) shifted;
+
+for e = 0 to elements-1
+    shifted = LSL(Elem[operand, e, esize], shift);
+    Elem[result, e, esize] = (Elem[operand2, e, esize] AND NOT(mask)) OR shifted;
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZU Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZU Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTNS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTNS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTNU Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTNU Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTMS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTMS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTMU Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTMU Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTPS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTPS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTPU Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTPU Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTAS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTAS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTAU Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTAU Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZS Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZU Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTNS Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTNU Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTMS Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTMU Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTPS Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTPU Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTAS Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTAU Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZS Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZU Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZU Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTNS Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTNS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTNU Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTNU Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTMS Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTMS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTMU Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTMU Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTPS Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTPS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTPU Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTPU Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTAS Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTAS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTAU Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTAU Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZS Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZU Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTNS Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTNU Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTMS Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTMU Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTPS Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTPU Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to a signed integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTAS Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector). This instruction converts each element in a vector from a floating-point value to an unsigned integer value using the Round to Nearest with Ties to Away rounding mode and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTAU Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZS Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZS Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZU Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZU Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZS Sd,Sn,#n
+

Argument Preparation

a → Sn 
+1 << n << 32

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZU Sd,Sn,#n
+

Argument Preparation

a → Sn 
+1 << n << 32

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZS Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZS Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 64

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZU Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZU Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 64

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Signed integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to a signed integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZS Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to Unsigned integer, rounding toward Zero (vector). This instruction converts a scalar or each element in a vector from a floating-point value to an unsigned integer value using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FCVTZU Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPToFixed(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

SCVTF Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

SCVTF Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

UCVTF Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

UCVTF Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

SCVTF Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

UCVTF Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

SCVTF Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

SCVTF Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

UCVTF Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

UCVTF Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

SCVTF Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

UCVTF Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

SCVTF Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

SCVTF Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

UCVTF Vd.2S,Vn.2S,#n
+

Argument Preparation

a → Vn.2S 
+1 << n << 32

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

UCVTF Vd.4S,Vn.4S,#n
+

Argument Preparation

a → Vn.4S 
+1 << n << 32

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

SCVTF Sd,Sn,#n
+

Argument Preparation

a → Sn 
+1 << n << 32

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

UCVTF Sd,Sn,#n
+

Argument Preparation

a → Sn 
+1 << n << 32

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

SCVTF Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

SCVTF Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 64

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

UCVTF Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

UCVTF Vd.2D,Vn.2D,#n
+

Argument Preparation

a → Vn.2D 
+1 << n << 64

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed integer Convert to Floating-point (vector). This instruction converts each element in a vector from signed integer to floating-point using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

SCVTF Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned integer Convert to Floating-point (vector). This instruction converts each element in a vector from an unsigned integer value to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

UCVTF Dd,Dn,#n
+

Argument Preparation

a → Dn 
+1 << n << 64

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+FPRounding rounding = FPRoundingMode(FPCR);
+bits(esize) element;
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FixedToFP(element, 0, unsigned, FPCR, rounding);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the FPCR.

+

A64 Instruction

FCVTN Vd.4H,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR);
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the FPCR.

+

A64 Instruction

FCVTN2 Vd.8H,Vn.4S
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR);
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the FPCR.

+

A64 Instruction

FCVTN Vd.2S,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR);
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Floating-point Convert to lower precision Narrow (vector). This instruction reads each vector element in the SIMD&FP source register, converts each result to half the precision of the source element, writes the final result to a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. The rounding mode is determined by the FPCR.

+

A64 Instruction

FCVTN2 Vd.4S,Vn.2D
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR);
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the FPCR, and writes each result to the equivalent element of the vector in the SIMD&FP destination register.

+

A64 Instruction

FCVTL Vd.4S,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, 2*esize] = FPConvert(Elem[operand, e, esize], FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the FPCR, and writes each result to the equivalent element of the vector in the SIMD&FP destination register.

+

A64 Instruction

FCVTL2 Vd.4S,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, 2*esize] = FPConvert(Elem[operand, e, esize], FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the FPCR, and writes each result to the equivalent element of the vector in the SIMD&FP destination register.

+

A64 Instruction

FCVTL Vd.2D,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, 2*esize] = FPConvert(Elem[operand, e, esize], FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to higher precision Long (vector). This instruction reads each element in a vector in the SIMD&FP source register, converts each value to double the precision of the source element using the rounding mode that is determined by the FPCR, and writes each result to the equivalent element of the vector in the SIMD&FP destination register.

+

A64 Instruction

FCVTL2 Vd.2D,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(2*datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, 2*esize] = FPConvert(Elem[operand, e, esize], FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FCVTXN Vd.2S,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR, FPRounding_ODD);
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FCVTXN Sd,Dn
+

Argument Preparation

a → Dn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR, FPRounding_ODD);
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Floating-point Convert to lower precision Narrow, rounding to odd (vector). This instruction reads each vector element in the source SIMD&FP register, narrows each value to half the precision of the source element using the Round to Odd rounding mode, writes the result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FCVTXN2 Vd.4S,Vn.2D
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = FPConvert(Elem[operand, e, 2*esize], FPCR, FPRounding_ODD);
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTZ Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTZ Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTZ Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Round to Integral, toward Zero (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Zero rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTZ Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTN Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTN Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTN Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTN Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral, to nearest with ties to even (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTN Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTM Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTM Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTM Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Round to Integral, toward Minus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Minus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTM Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTP Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTP Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTP Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Round to Integral, toward Plus infinity (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTP Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTA Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTA Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTA Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Round to Integral, to nearest with ties to Away (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the Round to Nearest with Ties to Away rounding mode, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTA Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTI Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTI Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTI Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Round to Integral, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTI Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTX Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTX Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTX Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Round to Integral exact, using current rounding mode (vector). This instruction rounds a vector of floating-point values in the SIMD&FP source register to integral floating-point values of the same size using the rounding mode that is determined by the FPCR, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FRINTX Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRoundInt(element, FPCR, rounding, exact);
+
+V[d] = result;
+

Supported architectures

A64

Description

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

XTN Vd.8B,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

XTN Vd.4H,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

XTN Vd.2S,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

XTN Vd.8B,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

XTN Vd.4H,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

XTN Vd.2S,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

XTN2 Vd.16B,Vn.8H
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

XTN2 Vd.8H,Vn.4S
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

XTN2 Vd.4S,Vn.2D
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

XTN2 Vd.16B,Vn.8H
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

XTN2 Vd.8H,Vn.4S
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Extract Narrow. This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

XTN2 Vd.4S,Vn.2D
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    Elem[result, e, esize] = element<esize-1:0>;
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SSHLL Vd.8H,Vn.8B,#0
+

Argument Preparation

a → Vn.8B 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SSHLL Vd.4S,Vn.4H,#0
+

Argument Preparation

a → Vn.4H 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SSHLL Vd.2D,Vn.2S,#0
+

Argument Preparation

a → Vn.2S 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USHLL Vd.8H,Vn.8B,#0
+

Argument Preparation

a → Vn.8B 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USHLL Vd.4S,Vn.4H,#0
+

Argument Preparation

a → Vn.4H 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USHLL Vd.2D,Vn.2S,#0
+

Argument Preparation

a → Vn.2S 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SSHLL2 Vd.8H,Vn.16B,#0
+

Argument Preparation

a → Vn.16B 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SSHLL2 Vd.4S,Vn.8H,#0
+

Argument Preparation

a → Vn.8H 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Shift Left Long (immediate). This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SSHLL2 Vd.2D,Vn.4S,#0
+

Argument Preparation

a → Vn.4S 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USHLL2 Vd.8H,Vn.16B,#0
+

Argument Preparation

a → Vn.16B 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USHLL2 Vd.4S,Vn.8H,#0
+

Argument Preparation

a → Vn.8H 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Shift Left Long (immediate). This instruction reads each vector element in the lower or upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

USHLL2 Vd.2D,Vn.4S,#0
+

Argument Preparation

a → Vn.4S 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = Vpart[n, part];
+bits(datasize*2) result;
+integer element;
+
+for e = 0 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned) << shift;
+    Elem[result, e, 2*esize] = element<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SQXTN Vd.8B,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SQXTN Vd.4H,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SQXTN Vd.2S,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UQXTN Vd.8B,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UQXTN Vd.4H,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UQXTN Vd.2S,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SQXTN Bd,Hn
+

Argument Preparation

a → Hn 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SQXTN Hd,Sn
+

Argument Preparation

a → Sn 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SQXTN Sd,Dn
+

Argument Preparation

a → Dn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UQXTN Bd,Hn
+

Argument Preparation

a → Hn 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UQXTN Hd,Sn
+

Argument Preparation

a → Sn 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UQXTN Sd,Dn
+

Argument Preparation

a → Dn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SQXTN2 Vd.16B,Vn.8H
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SQXTN2 Vd.8H,Vn.4S
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates the value to half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SQXTN2 Vd.4S,Vn.2D
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UQXTN2 Vd.16B,Vn.8H
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UQXTN2 Vd.8H,Vn.4S
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Unsigned saturating extract Narrow. This instruction reads each vector element from the source SIMD&FP register, saturates each value to half the original width, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UQXTN2 Vd.4S,Vn.2D
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = SatQ(Int(element, unsigned), esize, unsigned);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

SQXTUN Vd.8B,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

SQXTUN Vd.4H,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

SQXTUN Vd.2S,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

SQXTUN Bd,Hn
+

Argument Preparation

a → Hn 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

SQXTUN Hd,Sn
+

Argument Preparation

a → Sn 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

SQXTUN Sd,Dn
+

Argument Preparation

a → Dn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

SQXTUN2 Vd.16B,Vn.8H
+

Argument Preparation

r → Vd.8B 
+a → Vn.8H

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

SQXTUN2 Vd.8H,Vn.4S
+

Argument Preparation

r → Vd.4H 
+a → Vn.4S

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Signed saturating extract Unsigned Narrow. This instruction reads each signed integer value in the vector of the source SIMD&FP register, saturates the value to an unsigned integer value that is half the original width, places the result into a vector, and writes the vector to the lower or upper half of the destination SIMD&FP register. The destination vector elements are half as long as the source vector elements.

+

A64 Instruction

SQXTUN2 Vd.4S,Vn.2D
+

Argument Preparation

r → Vd.2S 
+a → Vn.2D

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(2*datasize) operand = V[n];
+bits(datasize) result;
+bits(2*esize) element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 2*esize];
+    (Elem[result, e, esize], sat) = UnsignedSatQ(SInt(element), esize);
+    if sat then FPSR.QC = '1';
+
+Vpart[d, part] = result;
+

Supported architectures

A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+v → Vm.4H
+0 << lane << 3

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+v → Vm.2S
+0 << lane << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+v → Vm.4H
+0 << lane << 3

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+v → Vm.2S
+0 << lane << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 1
+

Argument Preparation

0 << lane << 1 

Results

N/A → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 3
+

Argument Preparation

0 << lane << 1 

Results

N/A → result
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+v → Vm.8H
+0 << lane << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+v → Vm.4S
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+v → Vm.8H
+0 << lane << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+v → Vm.4S
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 1
+

Argument Preparation

0 << lane << 3 

Results

N/A → result
+

Supported architectures

A64

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * v[lane]) for i = 0 to 3
+

Argument Preparation

0 << lane << 3 

Results

N/A → result
+

Supported architectures

A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL Sd,Hn,Vm.H[lane]
+

Argument Preparation

a → Sd 
+b → Hn
+v → Vm.4H
+0 << lane << 3

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL Dd,Sn,Vm.S[lane]
+

Argument Preparation

a → Dd 
+b → Sn
+v → Vm.2S
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL Sd,Hn,Vm.H[lane]
+

Argument Preparation

a → Sd 
+b → Hn
+v → Vm.8H
+0 << lane << 7

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL Dd,Sn,Vm.S[lane]
+

Argument Preparation

a → Dd 
+b → Sn
+v → Vm.4S
+0 << lane << 3

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+v → Vm.4H
+0 << lane << 3

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+v → Vm.2S
+0 << lane << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+v → Vm.4H
+0 << lane << 3

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+v → Vm.2S
+0 << lane << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 1
+

Argument Preparation

0 << lane << 1 

Results

N/A → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 3
+

Argument Preparation

0 << lane << 1 

Results

N/A → result
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+v → Vm.8H
+0 << lane << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+v → Vm.4S
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+v → Vm.8H
+0 << lane << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+v → Vm.4S
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

A64

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 1
+

Argument Preparation

0 << lane << 3 

Results

N/A → result
+

Supported architectures

A64

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * v[lane]) for i = 0 to 3
+

Argument Preparation

0 << lane << 3 

Results

N/A → result
+

Supported architectures

A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL Sd,Hn,Vm.H[lane]
+

Argument Preparation

a → Sd 
+b → Hn
+v → Vm.4H
+0 << lane << 3

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL Dd,Sn,Vm.S[lane]
+

Argument Preparation

a → Dd 
+b → Sn
+v → Vm.2S
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL Sd,Hn,Vm.H[lane]
+

Argument Preparation

a → Sd 
+b → Hn
+v → Vm.8H
+0 << lane << 7

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL Dd,Sn,Vm.S[lane]
+

Argument Preparation

a → Dd 
+b → Sn
+v → Vm.4S
+0 << lane << 3

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vn.4H 
+b → Vm.H[0]

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vn.8H 
+b → Vm.H[0]

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 
+b → Vm.S[0]

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 
+b → Vm.S[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vn.4H 
+b → Vm.H[0]

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vn.8H 
+b → Vm.H[0]

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 
+b → Vm.S[0]

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 
+b → Vm.S[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 
+b → Vm.S[0]

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 
+b → Vm.S[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Dd,Dn,Vm.D[0]
+

Argument Preparation

a → Dn 
+b → Vm.D[0]

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Vd.2D,Vn.2D,Vm.D[0]
+

Argument Preparation

a → Vn.2D 
+b → Vm.D[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 
+v → Vm.4H
+0 << lane << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 
+v → Vm.4H
+0 << lane << 3

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 
+v → Vm.4H
+0 << lane << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 
+v → Vm.4H
+0 << lane << 3

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dn 
+v → Vm.1D
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vn.2D 
+v → Vm.1D
+0 << lane << 0

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 
+v → Vm.2S
+0 << lane << 1

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Dd,Dn,Vm.S[lane]
+

Argument Preparation

a → Dn 
+v → Vm.1D
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 
+v → Vm.8H
+0 << lane << 7

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 
+v → Vm.8H
+0 << lane << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 
+v → Vm.8H
+0 << lane << 7

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 
+v → Vm.8H
+0 << lane << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MUL Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if poly then
+        product = PolynomialMult(element1, element2)<esize-1:0>;
+    else
+        product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    Elem[result, e, esize] = product;
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dn 
+v → Vm.2D
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Vd.2D,Vn.2D,Vm.D[lane]
+

Argument Preparation

a → Vn.2D 
+v → Vm.2D
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 
+v → Vm.4S
+0 << lane << 3

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FMUL Dd,Dn,Vm.D[lane]
+

Argument Preparation

a → Dn 
+v → Vm.2D
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPMul(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vn.4H 
+b → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 
+b → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vn.4H 
+b → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 
+b → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vn.8H 
+b → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 
+b → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vn.8H 
+b → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 
+b → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMULL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMULL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    Elem[result, e, 2*esize] = (element1*element2)<2*esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vn.4H 
+b → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 
+b → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vn.8H 
+b → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 
+b → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL Sd,Hn,Vm.H[lane]
+

Argument Preparation

a → Hn 
+v → Vm.4H
+0 << lane << 3

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL Dd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 
+v → Vm.2S
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 
+v → Vm.4H
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL Vd.4S,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL Vd.2D,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL Sd,Hn,Vm.H[lane]
+

Argument Preparation

a → Hn 
+v → Vm.8H
+0 << lane << 7

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL Dd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 
+v → Vm.4S
+0 << lane << 3

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL2 Vd.4S,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 
+v → Vm.8H
+0 << lane << 7

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply Long. This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, doubles the results, places the final results in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULL2 Vd.2D,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    Elem[result, e, 2*esize] = product;
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vn.4H 
+b → Vm.H[0]

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vn.8H 
+b → Vm.H[0]

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 
+b → Vm.S[0]

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 
+b → Vm.S[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 
+v → Vm.4H
+0 << lane << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 
+v → Vm.4H
+0 << lane << 3

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Hd,Hn,Vm.H[lane]
+

Argument Preparation

a → Hn 
+v → Vm.4H
+0 << lane << 3

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Sd,Sn,Vm.H[lane]
+

Argument Preparation

a → Sn 
+v → Vm.2S
+0 << lane << 1

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 
+v → Vm.8H
+0 << lane << 7

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 
+v → Vm.8H
+0 << lane << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Hd,Hn,Vm.H[lane]
+

Argument Preparation

a → Hn 
+v → Vm.8H
+0 << lane << 7

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQDMULH Sd,Sn,Vm.H[lane]
+

Argument Preparation

a → Sn 
+v → Vm.4S
+0 << lane << 3

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vn.4H 
+b → Vm.H[0]

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vn.8H 
+b → Vm.H[0]

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vn.2S 
+b → Vm.S[0]

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vn.4S 
+b → Vm.S[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 
+v → Vm.4H
+0 << lane << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 
+v → Vm.4H
+0 << lane << 3

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.2S
+0 << lane << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Hd,Hn,Vm.H[lane]
+

Argument Preparation

a → Hn 
+v → Vm.4H
+0 << lane << 3

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 
+v → Vm.2S
+0 << lane << 1

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.4H,Vn.4H,Vm.H[lane]
+

Argument Preparation

a → Vn.4H 
+v → Vm.8H
+0 << lane << 7

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.8H,Vn.8H,Vm.H[lane]
+

Argument Preparation

a → Vn.8H 
+v → Vm.8H
+0 << lane << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.2S,Vn.2S,Vm.S[lane]
+

Argument Preparation

a → Vn.2S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Vd.4S,Vn.4S,Vm.S[lane]
+

Argument Preparation

a → Vn.4S 
+v → Vm.4S
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Hd,Hn,Vm.H[lane]
+

Argument Preparation

a → Hn 
+v → Vm.8H
+0 << lane << 7

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Rounding Doubling Multiply returning High half. This instruction multiplies the values of corresponding elements of the two source SIMD&FP registers, doubles the results, places the most significant half of the final results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SQRDMULH Sd,Sn,Vm.S[lane]
+

Argument Preparation

a → Sn 
+v → Vm.4S
+0 << lane << 3

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+integer round_const = if rounding then 1 << (esize - 1) else 0;
+integer element1;
+integer element2;
+integer product;
+boolean sat;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    product = (2 * element1 * element2) + round_const;
+    (Elem[result, e, esize], sat) = SignedSatQ(product >> esize, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+c → Vm.H[0]

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+c → Vm.H[0]

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+c → Vm.S[0]

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+c → Vm.S[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+c → Vm.H[0]

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+c → Vm.H[0]

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+c → Vm.S[0]

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Add to accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLA Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+c → Vm.S[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c) for i = 0 to 1
+

Argument Preparation

a → N/A 
+b → N/A
+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

RESULT[I] = a[i] + (b[i] * c) for i = 0 to 3
+

Argument Preparation

a → N/A 
+b → N/A
+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Add Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLAL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Add Long (vector). This instruction multiplies the vector elements in the lower or upper half of the first source SIMD&FP register by the corresponding vector elements of the second source SIMD&FP register, and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

UMLAL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Add Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and accumulates the final results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLAL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+c → Vm.H[0]

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+c → Vm.H[0]

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+c → Vm.S[0]

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+c → Vm.S[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4H,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4H 
+b → Vn.4H
+c → Vm.H[0]

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.8H,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.8H 
+b → Vn.8H
+c → Vm.H[0]

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+c → Vm.S[0]

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register.

+

A64 Instruction

MLS Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+c → Vm.S[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+bits(esize) product;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    product = (UInt(element1)*UInt(element2))<esize-1:0>;
+    if sub_op then
+        Elem[result, e, esize] = Elem[operand3, e, esize] - product;
+    else
+        Elem[result, e, esize] = Elem[operand3, e, esize] + product;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c) for i = 0 to 1
+

Argument Preparation

a → N/A 
+b → N/A
+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

RESULT[I] = a[i] - (b[i] * c) for i = 0 to 3
+

Argument Preparation

a → N/A 
+b → N/A
+c → N/A

Results

N/A → result
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Multiply-Subtract Long (vector). This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SMLSL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Multiply-Subtract Long (vector). This instruction multiplies corresponding vector elements in the lower or upper half of the two source SIMD&FP registers, and subtracts the results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMLSL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+bits(2*esize) accum;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[operand1, e, esize], unsigned);
+    element2 = Int(Elem[operand2, e, esize], unsigned);
+    product = (element1*element2)<2*esize-1:0>;
+    if sub_op then
+        accum = Elem[operand3, e, 2*esize] - product;
+    else
+        accum = Elem[operand3, e, 2*esize] + product;
+    Elem[result, e, 2*esize] = accum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL Vd.4S,Vn.4H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4H
+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL Vd.2D,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2S
+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL2 Vd.4S,Vn.8H,Vm.H[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H
+c → Vm.H[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Doubling Multiply-Subtract Long. This instruction multiplies corresponding signed integer values in the lower or upper half of the vectors of the two source SIMD&FP registers, doubles the results, and subtracts the final results from the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

SQDMLSL2 Vd.2D,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S
+c → Vm.S[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) operand3 = V[d];
+bits(2*datasize) result;
+integer element1;
+integer element2;
+bits(2*esize) product;
+integer accum;
+boolean sat1;
+boolean sat2;
+
+for e = 0 to elements-1
+    element1 = SInt(Elem[operand1, e, esize]);
+    element2 = SInt(Elem[operand2, e, esize]);
+    (product, sat1) = SignedSatQ(2 * element1 * element2, 2 * esize);
+    if sub_op then
+        accum = SInt(Elem[operand3, e, 2*esize]) - SInt(product);
+    else
+        accum = SInt(Elem[operand3, e, 2*esize]) + SInt(product);
+    (Elem[result, e, 2*esize], sat2) = SignedSatQ(accum, 2 * esize);
+    if sat1 || sat2 then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ABS Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ABS Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ABS Vd.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ABS Vd.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ABS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ABS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FABS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FABS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ABS Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ABS Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ABS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FABS Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Absolute value (vector). This instruction calculates the absolute value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FABS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQABS Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQABS Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQABS Vd.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQABS Vd.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQABS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQABS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQABS Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQABS Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQABS Bd,Bn
+

Argument Preparation

a → Bn 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQABS Hd,Hn
+

Argument Preparation

a → Hn 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQABS Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Absolute value. This instruction reads each vector element from the source SIMD&FP register, puts the absolute value of the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQABS Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

NEG Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

NEG Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

NEG Vd.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

NEG Vd.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

NEG Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

NEG Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FNEG Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FNEG Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

NEG Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

NEG Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Negate (vector). This instruction reads each vector element from the source SIMD&FP register, negates each value, puts the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

NEG Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    Elem[result, e, esize] = element<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FNEG Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Negate (vector). This instruction negates the value of each vector element in the source SIMD&FP register, writes the result to a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FNEG Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    if neg then
+        element = FPNeg(element);
+    else
+        element = FPAbs(element);
+    Elem[result, e, esize] = element;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQNEG Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQNEG Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQNEG Vd.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQNEG Vd.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQNEG Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQNEG Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQNEG Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQNEG Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQNEG Bd,Bn
+

Argument Preparation

a → Bn 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQNEG Hd,Hn
+

Argument Preparation

a → Hn 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQNEG Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed saturating Negate. This instruction reads each vector element from the source SIMD&FP register, negates each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SQNEG Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element;
+boolean sat;
+
+for e = 0 to elements-1
+    element = SInt(Elem[operand, e, esize]);
+    if neg then
+        element = -element;
+    else
+        element = Abs(element);
+    (Elem[result, e, esize], sat) = SignedSatQ(element, esize);
+    if sat then FPSR.QC = '1';
+
+V[d] = result;
+

Supported architectures

A64

Description

Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.

+

A64 Instruction

CLS Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.

+

A64 Instruction

CLS Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.

+

A64 Instruction

CLS Vd.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.

+

A64 Instruction

CLS Vd.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.

+

A64 Instruction

CLS Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Sign bits (vector). This instruction counts the number of consecutive bits following the most significant bit that are the same as the most significant bit in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The count does not include the most significant bit itself.

+

A64 Instruction

CLS Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CLZ Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CLZ Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CLZ Vd.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CLZ Vd.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CLZ Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CLZ Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CLZ Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CLZ Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CLZ Vd.4H,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CLZ Vd.8H,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CLZ Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Count Leading Zero bits (vector). This instruction counts the number of consecutive zeros, starting from the most significant bit, in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CLZ Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    if countop == CountOp_CLS then
+        count = CountLeadingSignBits(Elem[operand, e, esize]);
+    else
+        count = CountLeadingZeroBits(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CNT Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    count = BitCount(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CNT Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    count = BitCount(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CNT Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    count = BitCount(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CNT Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    count = BitCount(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CNT Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    count = BitCount(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Population Count per byte. This instruction counts the number of bits that have a value of one in each vector element in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

CNT Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+integer count;
+for e = 0 to elements-1
+    count = BitCount(Elem[operand, e, esize]);
+    Elem[result, e, esize] = count<esize-1:0>;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Reciprocal Estimate. This instruction reads each vector element from the source SIMD&FP register, calculates an approximate inverse for the unsigned integer value, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URECPE Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(32) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 32];
+    Elem[result, e, 32] = UnsignedRecipEstimate(element);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Reciprocal Estimate. This instruction reads each vector element from the source SIMD&FP register, calculates an approximate inverse for the unsigned integer value, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

URECPE Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(32) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 32];
+    Elem[result, e, 32] = UnsignedRecipEstimate(element);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRECPE Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecipEstimate(element, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRECPE Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecipEstimate(element, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRECPE Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecipEstimate(element, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRECPE Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecipEstimate(element, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRECPE Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecipEstimate(element, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal Estimate. This instruction finds an approximate reciprocal estimate for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRECPE Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecipEstimate(element, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRECPS Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRecipStepFused(element1, element2);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRECPS Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRecipStepFused(element1, element2);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRECPS Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRecipStepFused(element1, element2);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRECPS Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRecipStepFused(element1, element2);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRECPS Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRecipStepFused(element1, element2);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal Step. This instruction multiplies the corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 2.0, places the resulting floating-point values in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRECPS Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRecipStepFused(element1, element2);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FSQRT Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPSqrt(element, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FSQRT Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPSqrt(element, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FSQRT Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPSqrt(element, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Square Root (vector). This instruction calculates the square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FSQRT Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPSqrt(element, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Reciprocal Square Root Estimate. This instruction reads each vector element from the source SIMD&FP register, calculates an approximate inverse square root for each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

URSQRTE Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(32) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 32];
+    Elem[result, e, 32] = UnsignedRSqrtEstimate(element);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Reciprocal Square Root Estimate. This instruction reads each vector element from the source SIMD&FP register, calculates an approximate inverse square root for each value, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

URSQRTE Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(32) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, 32];
+    Elem[result, e, 32] = UnsignedRSqrtEstimate(element);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRSQRTE Vd.2S,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRSqrtEstimate(element, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRSQRTE Vd.4S,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRSqrtEstimate(element, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRSQRTE Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRSqrtEstimate(element, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRSQRTE Vd.2D,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRSqrtEstimate(element, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRSQRTE Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRSqrtEstimate(element, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal Square Root Estimate. This instruction calculates an approximate square root for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRSQRTE Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRSqrtEstimate(element, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRSQRTS Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRSqrtStepFused(element1, element2);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRSQRTS Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRSqrtStepFused(element1, element2);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRSQRTS Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRSqrtStepFused(element1, element2);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRSQRTS Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRSqrtStepFused(element1, element2);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRSQRTS Sd,Sn,Sm
+

Argument Preparation

a → Sn 
+b → Sm

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRSqrtStepFused(element1, element2);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRSQRTS Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPRSqrtStepFused(element1, element2);
+
+V[d] = result;
+

Supported architectures

A64

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MVN Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MVN Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MVN Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MVN Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MVN Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MVN Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MVN Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MVN Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MVN Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MVN Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MVN Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MVN Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MVN Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

Description

Bitwise NOT (vector). This instruction reads each vector element from the source SIMD&FP register, places the inverse of each value into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

MVN Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

The description of + NOT + gives the operational pseudocode for this instruction.

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Dd,Dn,Dm
+

Argument Preparation

a → Dn 
+b → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise AND (vector). This instruction performs a bitwise AND between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

AND Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR (vector, register). This instruction performs a bitwise OR between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Exclusive OR (vector). This instruction performs a bitwise Exclusive OR operation between the two source SIMD&FP registers, and places the result in the destination SIMD&FP register.

+

A64 Instruction

EOR Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand2;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand2 = Zeros();
+operand3 = Ones();
+V[d] = operand1 EOR ((operand2 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise bit Clear (vector, register). This instruction performs a bitwise AND between the first source SIMD&FP register and the complement of the second source SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

BIC Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 AND operand2;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

ORN Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+operand2 = NOT(operand2);
+
+result = operand1 OR operand2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vd.8B 
+b → Vn.8B
+c → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

A64

Description

Bitwise Select. This instruction sets each bit in the destination SIMD&FP register to the corresponding bit from the first source SIMD&FP register when the original destination bit was 1, otherwise from the second source SIMD&FP register.

+

A64 Instruction

BSL Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vd.16B 
+b → Vn.16B
+c → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[m];
+operand3 = V[d];
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.8B 
+0 << lane1 << 7
+b → Vn.8B
+0 << lane2 << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.16B 
+0 << lane1 << 15
+b → Vn.8B
+0 << lane2 << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.4H 
+0 << lane1 << 3
+b → Vn.4H
+0 << lane2 << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.8H 
+0 << lane1 << 7
+b → Vn.4H
+0 << lane2 << 3

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.2S 
+0 << lane1 << 1
+b → Vn.2S
+0 << lane2 << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.4S 
+0 << lane1 << 3
+b → Vn.2S
+0 << lane2 << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 
+0 << lane1 << 0
+b → Vn.1D
+0 << lane2 << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 
+0 << lane1 << 1
+b → Vn.1D
+0 << lane2 << 0

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.8B 
+0 << lane1 << 7
+b → Vn.8B
+0 << lane2 << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.16B 
+0 << lane1 << 15
+b → Vn.8B
+0 << lane2 << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.4H 
+0 << lane1 << 3
+b → Vn.4H
+0 << lane2 << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.8H 
+0 << lane1 << 7
+b → Vn.4H
+0 << lane2 << 3

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.2S 
+0 << lane1 << 1
+b → Vn.2S
+0 << lane2 << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.4S 
+0 << lane1 << 3
+b → Vn.2S
+0 << lane2 << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 
+0 << lane1 << 0
+b → Vn.1D
+0 << lane2 << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 
+0 << lane1 << 1
+b → Vn.1D
+0 << lane2 << 0

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 
+0 << lane1 << 0
+b → Vn.1D
+0 << lane2 << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 
+0 << lane1 << 1
+b → Vn.1D
+0 << lane2 << 0

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.2S 
+0 << lane1 << 1
+b → Vn.2S
+0 << lane2 << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.4S 
+0 << lane1 << 3
+b → Vn.2S
+0 << lane2 << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 
+0 << lane1 << 0
+b → Vn.1D
+0 << lane2 << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 
+0 << lane1 << 1
+b → Vn.1D
+0 << lane2 << 0

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.8B 
+0 << lane1 << 7
+b → Vn.8B
+0 << lane2 << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.16B 
+0 << lane1 << 15
+b → Vn.8B
+0 << lane2 << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.4H 
+0 << lane1 << 3
+b → Vn.4H
+0 << lane2 << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.8H 
+0 << lane1 << 7
+b → Vn.4H
+0 << lane2 << 3

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.8B 
+0 << lane1 << 7
+b → Vn.16B
+0 << lane2 << 15

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.16B 
+0 << lane1 << 15
+b → Vn.16B
+0 << lane2 << 15

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.4H 
+0 << lane1 << 3
+b → Vn.8H
+0 << lane2 << 7

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.8H 
+0 << lane1 << 7
+b → Vn.8H
+0 << lane2 << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.2S 
+0 << lane1 << 1
+b → Vn.4S
+0 << lane2 << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.4S 
+0 << lane1 << 3
+b → Vn.4S
+0 << lane2 << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 
+0 << lane1 << 0
+b → Vn.2D
+0 << lane2 << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 
+0 << lane1 << 1
+b → Vn.2D
+0 << lane2 << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.8B 
+0 << lane1 << 7
+b → Vn.16B
+0 << lane2 << 15

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.16B 
+0 << lane1 << 15
+b → Vn.16B
+0 << lane2 << 15

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.4H 
+0 << lane1 << 3
+b → Vn.8H
+0 << lane2 << 7

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.8H 
+0 << lane1 << 7
+b → Vn.8H
+0 << lane2 << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.2S 
+0 << lane1 << 1
+b → Vn.4S
+0 << lane2 << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.4S 
+0 << lane1 << 3
+b → Vn.4S
+0 << lane2 << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 
+0 << lane1 << 0
+b → Vn.2D
+0 << lane2 << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 
+0 << lane1 << 1
+b → Vn.2D
+0 << lane2 << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 
+0 << lane1 << 0
+b → Vn.2D
+0 << lane2 << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 
+0 << lane1 << 1
+b → Vn.2D
+0 << lane2 << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.2S 
+0 << lane1 << 1
+b → Vn.4S
+0 << lane2 << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane1],Vn.S[lane2]
+

Argument Preparation

a → Vd.4S 
+0 << lane1 << 3
+b → Vn.4S
+0 << lane2 << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane2]
+

Argument Preparation

a → UNUSED 
+0 << lane1 << 0
+b → Vn.2D
+0 << lane2 << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane1],Vn.D[lane2]
+

Argument Preparation

a → Vd.2D 
+0 << lane1 << 1
+b → Vn.2D
+0 << lane2 << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.8B 
+0 << lane1 << 7
+b → Vn.16B
+0 << lane2 << 15

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane1],Vn.B[lane2]
+

Argument Preparation

a → Vd.16B 
+0 << lane1 << 15
+b → Vn.16B
+0 << lane2 << 15

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.4H 
+0 << lane1 << 3
+b → Vn.8H
+0 << lane2 << 7

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane1],Vn.H[lane2]
+

Argument Preparation

a → Vd.8H 
+0 << lane1 << 7
+b → Vn.8H
+0 << lane2 << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

RBIT Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+bits(esize) rev;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    for i = 0 to esize-1
+        rev<esize-1-i> = element<i>;
+    Elem[result, e, esize] = rev;
+
+V[d] = result;
+

Supported architectures

A64

Description

Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

RBIT Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+bits(esize) rev;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    for i = 0 to esize-1
+        rev<esize-1-i> = element<i>;
+    Elem[result, e, esize] = rev;
+
+V[d] = result;
+

Supported architectures

A64

Description

Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

RBIT Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+bits(esize) rev;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    for i = 0 to esize-1
+        rev<esize-1-i> = element<i>;
+    Elem[result, e, esize] = rev;
+
+V[d] = result;
+

Supported architectures

A64

Description

Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

RBIT Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+bits(esize) rev;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    for i = 0 to esize-1
+        rev<esize-1-i> = element<i>;
+    Elem[result, e, esize] = rev;
+
+V[d] = result;
+

Supported architectures

A64

Description

Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

RBIT Vd.8B,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+bits(esize) rev;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    for i = 0 to esize-1
+        rev<esize-1-i> = element<i>;
+    Elem[result, e, esize] = rev;
+
+V[d] = result;
+

Supported architectures

A64

Description

Reverse Bit order (vector). This instruction reads each vector element from the source SIMD&FP register, reverses the bits of the element, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

RBIT Vd.16B,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+bits(esize) rev;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    for i = 0 to esize-1
+        rev<esize-1-i> = element<i>;
+    Elem[result, e, esize] = rev;
+
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[0],Xn
+

Argument Preparation

a → Xn 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8B,rn
+

Argument Preparation

value → rn 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.16B,rn
+

Argument Preparation

value → rn 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4H,rn
+

Argument Preparation

value → rn 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8H,rn
+

Argument Preparation

value → rn 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2S,rn
+

Argument Preparation

value → rn 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4S,rn
+

Argument Preparation

value → rn 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Dd.D[0],xn
+

Argument Preparation

value → rn 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2D,rn
+

Argument Preparation

value → rn 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8B,rn
+

Argument Preparation

value → rn 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.16B,rn
+

Argument Preparation

value → rn 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4H,rn
+

Argument Preparation

value → rn 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8H,rn
+

Argument Preparation

value → rn 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2S,rn
+

Argument Preparation

value → rn 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4S,rn
+

Argument Preparation

value → rn 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Dd.D[0],xn
+

Argument Preparation

value → rn 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2D,rn
+

Argument Preparation

value → rn 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Dd.D[0],xn
+

Argument Preparation

value → rn 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2D,rn
+

Argument Preparation

value → rn 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2S,rn
+

Argument Preparation

value → rn 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4S,rn
+

Argument Preparation

value → rn 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8B,rn
+

Argument Preparation

value → rn 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.16B,rn
+

Argument Preparation

value → rn 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4H,rn
+

Argument Preparation

value → rn 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8H,rn
+

Argument Preparation

value → rn 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Dd.D[0],xn
+

Argument Preparation

value → rn 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2D,rn
+

Argument Preparation

value → rn 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8B,rn
+

Argument Preparation

value → rn 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.16B,rn
+

Argument Preparation

value → rn 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4H,rn
+

Argument Preparation

value → rn 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8H,rn
+

Argument Preparation

value → rn 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2S,rn
+

Argument Preparation

value → rn 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4S,rn
+

Argument Preparation

value → rn 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,rn
+

Argument Preparation

value → rn 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2D,rn
+

Argument Preparation

value → rn 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8B,rn
+

Argument Preparation

value → rn 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.16B,rn
+

Argument Preparation

value → rn 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4H,rn
+

Argument Preparation

value → rn 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8H,rn
+

Argument Preparation

value → rn 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2S,rn
+

Argument Preparation

value → rn 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4S,rn
+

Argument Preparation

value → rn 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,rn
+

Argument Preparation

value → rn 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2D,rn
+

Argument Preparation

value → rn 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2S,rn
+

Argument Preparation

value → rn 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4S,rn
+

Argument Preparation

value → rn 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8B,rn
+

Argument Preparation

value → rn 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.16B,rn
+

Argument Preparation

value → rn 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4H,rn
+

Argument Preparation

value → rn 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8H,rn
+

Argument Preparation

value → rn 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,rn
+

Argument Preparation

value → rn 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2D,rn
+

Argument Preparation

value → rn 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8B,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 
+0 << lane << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.16B,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 
+0 << lane << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4H,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 
+0 << lane << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8H,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 
+0 << lane << 3

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2S,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4S,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 
+0 << lane << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 
+0 << lane << 0

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8B,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 
+0 << lane << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.16B,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 
+0 << lane << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4H,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 
+0 << lane << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8H,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 
+0 << lane << 3

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2S,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4S,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 
+0 << lane << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 
+0 << lane << 0

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 
+0 << lane << 0

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2S,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4S,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 
+0 << lane << 1

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8B,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 
+0 << lane << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.16B,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 
+0 << lane << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4H,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 
+0 << lane << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8H,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 
+0 << lane << 3

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 
+0 << lane << 0

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8B,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 
+0 << lane << 15

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.16B,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 
+0 << lane << 15

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4H,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 
+0 << lane << 7

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8H,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 
+0 << lane << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2S,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 
+0 << lane << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4S,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8B,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 
+0 << lane << 15

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.16B,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 
+0 << lane << 15

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4H,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 
+0 << lane << 7

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8H,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 
+0 << lane << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2S,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 
+0 << lane << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4S,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2S,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 
+0 << lane << 3

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4S,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8B,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 
+0 << lane << 15

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.16B,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 
+0 << lane << 15

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.4H,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 
+0 << lane << 7

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.8H,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 
+0 << lane << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.2D,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.8B 
+high → Vm.8B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.4H 
+high → Vm.4H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.2S 
+high → Vm.2S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.1D 
+high → Vm.1D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.8B 
+high → Vm.8B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.4H 
+high → Vm.4H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.2S 
+high → Vm.2S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.1D 
+high → Vm.1D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.1D 
+high → Vm.1D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.4H 
+high → Vm.4H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.2S 
+high → Vm.2S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.8B 
+high → Vm.8B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.4H 
+high → Vm.4H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+INS Vd.D[1],Vm.D[0]
+

Argument Preparation

low → Vn.1D 
+high → Vm.1D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.16B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.8H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.4S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.2D 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.16B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.8H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.4S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.2D 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.2D 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.8H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.4S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.16B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.8H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[1]
+

Argument Preparation

a → Vn.2D 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.16B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.8H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.4S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.2D 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.16B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.8H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.4S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.2D 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.2D 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.8H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.4S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.16B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.8H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Vd.1D,Vn.D[0]
+

Argument Preparation

a → Vn.2D 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Bd,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 
+0 << lane << 7

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 
+0 << lane << 3

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 
+0 << lane << 1

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Bd,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 
+0 << lane << 7

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 
+0 << lane << 3

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 
+0 << lane << 1

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

vec → Vn.2S 
+0 << lane << 1

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.1D 
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Bd,Vn.B[lane]
+

Argument Preparation

vec → Vn.8B 
+0 << lane << 7

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

vec → Vn.4H 
+0 << lane << 3

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Bd,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 
+0 << lane << 15

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 
+0 << lane << 7

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 
+0 << lane << 3

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Bd,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 
+0 << lane << 15

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 
+0 << lane << 7

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 
+0 << lane << 3

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

vec → Vn.4S 
+0 << lane << 3

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

vec → Vn.2D 
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Bd,Vn.B[lane]
+

Argument Preparation

vec → Vn.16B 
+0 << lane << 15

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

vec → Vn.8H 
+0 << lane << 7

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.8B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.16B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.4H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.8H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.2S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.4S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.1D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.2D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.8B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.16B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.4H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.8H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.2S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.4S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.1D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.2D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.1D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.2D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.4H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.8H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.2S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.4S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.8B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.16B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.4H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.8H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.1D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.2D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.8B
+0 << lane << 7

Results

Vt.8B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.16B
+0 << lane << 15

Results

Vt.16B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.4H
+0 << lane << 3

Results

Vt.4H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.8H
+0 << lane << 7

Results

Vt.8H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.S}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.2S
+0 << lane << 1

Results

Vt.2S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.S}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.4S
+0 << lane << 3

Results

Vt.4S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.1D
+0 << lane << 0

Results

Vt.1D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.2D
+0 << lane << 1

Results

Vt.2D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.B}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.8B
+0 << lane << 7

Results

Vt.8B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.B}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.16B
+0 << lane << 15

Results

Vt.16B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.4H
+0 << lane << 3

Results

Vt.4H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.8H
+0 << lane << 7

Results

Vt.8H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.S}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.2S
+0 << lane << 1

Results

Vt.2S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.S}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.4S
+0 << lane << 3

Results

Vt.4S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.1D
+0 << lane << 0

Results

Vt.1D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.2D
+0 << lane << 1

Results

Vt.2D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.1D
+0 << lane << 0

Results

Vt.1D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.2D
+0 << lane << 1

Results

Vt.2D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.4H
+0 << lane << 3

Results

Vt.4H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.8H
+0 << lane << 7

Results

Vt.8H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.S}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.2S
+0 << lane << 1

Results

Vt.2S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.S}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.4S
+0 << lane << 3

Results

Vt.4S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.B}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.8B
+0 << lane << 7

Results

Vt.8B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.B}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.16B
+0 << lane << 15

Results

Vt.16B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.4H
+0 << lane << 3

Results

Vt.4H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.H}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.8H
+0 << lane << 7

Results

Vt.8H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.1D
+0 << lane << 0

Results

Vt.1D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.D}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src → Vt.2D
+0 << lane << 1

Results

Vt.2D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.8B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.16B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.4H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.8H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.2S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.4S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.1D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.2D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.8B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.16B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.4H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.8H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.2S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.4S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.1D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.2D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.1D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.2D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.4H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.8H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.2S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.4S → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.8B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.16B → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.4H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.8H → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.1D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load one single-element structure and Replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all the lanes of the SIMD&FP register.

+

A64 Instruction

LD1R {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt.2D → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.8B
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.16B
+0 << lane << 15

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.2S
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.4S
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.2D
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.8B
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.16B
+0 << lane << 15

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.2S
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.4S
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.2D
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.2D
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.2S
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.4S
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.8B
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.16B
+0 << lane << 15

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val → Vt.2D
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure and Replicate to all lanes of two registers. This instruction loads a 2-element structure from memory and replicates the structure to all the lanes of the two SIMD&FP registers.

+

A64 Instruction

LD2R {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure and Replicate to all lanes of three registers. This instruction loads a 3-element structure from memory and replicates the structure to all the lanes of the three SIMD&FP registers.

+

A64 Instruction

LD3R {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure and Replicate to all lanes of four registers. This instruction loads a 4-element structure from memory and replicates the structure to all the lanes of the four SIMD&FP registers.

+

A64 Instruction

LD4R {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8B
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.16B
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4H
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8H
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2S
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4S
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8B
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.16B
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4H
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8H
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2S
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4S
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4H
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8H
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2S
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4S
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8B
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.16B
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4H
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8H
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.1D
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.1D
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.1D
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2D
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2D
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2D
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.1D
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2D
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.4H
+src.val[0] → Vt.4H
+0 << lane << 3

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.8H
+src.val[0] → Vt.8H
+0 << lane << 7

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.2S
+src.val[0] → Vt.2S
+0 << lane << 1

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.4S
+src.val[0] → Vt.4S
+0 << lane << 3

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.4H
+src.val[0] → Vt.4H
+0 << lane << 3

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.8H
+src.val[0] → Vt.8H
+0 << lane << 7

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.2S
+src.val[0] → Vt.2S
+0 << lane << 1

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.4S
+src.val[0] → Vt.4S
+0 << lane << 3

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.4H
+src.val[0] → Vt.4H
+0 << lane << 3

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.8H
+src.val[0] → Vt.8H
+0 << lane << 7

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.2S
+src.val[0] → Vt.2S
+0 << lane << 1

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.4S
+src.val[0] → Vt.4S
+0 << lane << 3

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.4H
+src.val[0] → Vt.4H
+0 << lane << 3

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.8H
+src.val[0] → Vt.8H
+0 << lane << 7

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.8B
+src.val[0] → Vt.8B
+0 << lane << 7

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.8B
+src.val[0] → Vt.8B
+0 << lane << 7

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.8B
+src.val[0] → Vt.8B
+0 << lane << 7

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.16B
+src.val[0] → Vt.16B
+0 << lane << 15

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.16B
+src.val[0] → Vt.16B
+0 << lane << 15

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.16B
+src.val[0] → Vt.16B
+0 << lane << 15

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.1D
+src.val[0] → Vt.1D
+0 << lane << 0

Results

ptr → Xn
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.2D
+src.val[0] → Vt.2D
+0 << lane << 1

Results

ptr → Xn
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.1D
+src.val[0] → Vt.1D
+0 << lane << 0

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.2D
+src.val[0] → Vt.2D
+0 << lane << 1

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.1D
+src.val[0] → Vt.1D
+0 << lane << 0

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.2D
+src.val[0] → Vt.2D
+0 << lane << 1

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.1D
+src.val[0] → Vt.1D
+0 << lane << 0

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 2-element structure to one lane of two registers. This instruction loads a 2-element structure from memory and writes the result to the corresponding elements of the two SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[1] → Vt2.2D
+src.val[0] → Vt.2D
+0 << lane << 1

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.4H
+src.val[1] → Vt2.4H
+src.val[0] → Vt.4H
+0 << lane << 3

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.8H
+src.val[1] → Vt2.8H
+src.val[0] → Vt.8H
+0 << lane << 7

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.2S
+src.val[1] → Vt2.2S
+src.val[0] → Vt.2S
+0 << lane << 1

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.4S
+src.val[1] → Vt2.4S
+src.val[0] → Vt.4S
+0 << lane << 3

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.4H
+src.val[1] → Vt2.4H
+src.val[0] → Vt.4H
+0 << lane << 3

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.8H
+src.val[1] → Vt2.8H
+src.val[0] → Vt.8H
+0 << lane << 7

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.2S
+src.val[1] → Vt2.2S
+src.val[0] → Vt.2S
+0 << lane << 1

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.4S
+src.val[1] → Vt2.4S
+src.val[0] → Vt.4S
+0 << lane << 3

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.4H
+src.val[1] → Vt2.4H
+src.val[0] → Vt.4H
+0 << lane << 3

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.8H
+src.val[1] → Vt2.8H
+src.val[0] → Vt.8H
+0 << lane << 7

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.2S
+src.val[1] → Vt2.2S
+src.val[0] → Vt.2S
+0 << lane << 1

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.4S
+src.val[1] → Vt2.4S
+src.val[0] → Vt.4S
+0 << lane << 3

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.4H
+src.val[1] → Vt2.4H
+src.val[0] → Vt.4H
+0 << lane << 3

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.8H
+src.val[1] → Vt2.8H
+src.val[0] → Vt.8H
+0 << lane << 7

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.8B
+src.val[1] → Vt2.8B
+src.val[0] → Vt.8B
+0 << lane << 7

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.8B
+src.val[1] → Vt2.8B
+src.val[0] → Vt.8B
+0 << lane << 7

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.8B
+src.val[1] → Vt2.8B
+src.val[0] → Vt.8B
+0 << lane << 7

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.16B
+src.val[1] → Vt2.16B
+src.val[0] → Vt.16B
+0 << lane << 15

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.16B
+src.val[1] → Vt2.16B
+src.val[0] → Vt.16B
+0 << lane << 15

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.16B
+src.val[1] → Vt2.16B
+src.val[0] → Vt.16B
+0 << lane << 15

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.1D
+src.val[1] → Vt2.1D
+src.val[0] → Vt.1D
+0 << lane << 0

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.2D
+src.val[1] → Vt2.2D
+src.val[0] → Vt.2D
+0 << lane << 1

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.1D
+src.val[1] → Vt2.1D
+src.val[0] → Vt.1D
+0 << lane << 0

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.2D
+src.val[1] → Vt2.2D
+src.val[0] → Vt.2D
+0 << lane << 1

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.1D
+src.val[1] → Vt2.1D
+src.val[0] → Vt.1D
+0 << lane << 0

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.2D
+src.val[1] → Vt2.2D
+src.val[0] → Vt.2D
+0 << lane << 1

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.1D
+src.val[1] → Vt2.1D
+src.val[0] → Vt.1D
+0 << lane << 0

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 3-element structure to one lane of three registers). This instruction loads a 3-element structure from memory and writes the result to the corresponding elements of the three SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[2] → Vt3.2D
+src.val[1] → Vt2.2D
+src.val[0] → Vt.2D
+0 << lane << 1

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.4H
+src.val[2] → Vt3.4H
+src.val[1] → Vt2.4H
+src.val[0] → Vt.4H
+0 << lane << 3

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.8H
+src.val[2] → Vt3.8H
+src.val[1] → Vt2.8H
+src.val[0] → Vt.8H
+0 << lane << 7

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.2S
+src.val[2] → Vt3.2S
+src.val[1] → Vt2.2S
+src.val[0] → Vt.2S
+0 << lane << 1

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.4S
+src.val[2] → Vt3.4S
+src.val[1] → Vt2.4S
+src.val[0] → Vt.4S
+0 << lane << 3

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.4H
+src.val[2] → Vt3.4H
+src.val[1] → Vt2.4H
+src.val[0] → Vt.4H
+0 << lane << 3

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.8H
+src.val[2] → Vt3.8H
+src.val[1] → Vt2.8H
+src.val[0] → Vt.8H
+0 << lane << 7

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.2S
+src.val[2] → Vt3.2S
+src.val[1] → Vt2.2S
+src.val[0] → Vt.2S
+0 << lane << 1

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.4S
+src.val[2] → Vt3.4S
+src.val[1] → Vt2.4S
+src.val[0] → Vt.4S
+0 << lane << 3

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.4H
+src.val[2] → Vt3.4H
+src.val[1] → Vt2.4H
+src.val[0] → Vt.4H
+0 << lane << 3

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.8H
+src.val[2] → Vt3.8H
+src.val[1] → Vt2.8H
+src.val[0] → Vt.8H
+0 << lane << 7

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.2S
+src.val[2] → Vt3.2S
+src.val[1] → Vt2.2S
+src.val[0] → Vt.2S
+0 << lane << 1

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.4S
+src.val[2] → Vt3.4S
+src.val[1] → Vt2.4S
+src.val[0] → Vt.4S
+0 << lane << 3

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.4H
+src.val[2] → Vt3.4H
+src.val[1] → Vt2.4H
+src.val[0] → Vt.4H
+0 << lane << 3

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.8H
+src.val[2] → Vt3.8H
+src.val[1] → Vt2.8H
+src.val[0] → Vt.8H
+0 << lane << 7

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.8B
+src.val[2] → Vt3.8B
+src.val[1] → Vt2.8B
+src.val[0] → Vt.8B
+0 << lane << 7

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.8B
+src.val[2] → Vt3.8B
+src.val[1] → Vt2.8B
+src.val[0] → Vt.8B
+0 << lane << 7

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.8B
+src.val[2] → Vt3.8B
+src.val[1] → Vt2.8B
+src.val[0] → Vt.8B
+0 << lane << 7

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.16B
+src.val[2] → Vt3.16B
+src.val[1] → Vt2.16B
+src.val[0] → Vt.16B
+0 << lane << 15

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.16B
+src.val[2] → Vt3.16B
+src.val[1] → Vt2.16B
+src.val[0] → Vt.16B
+0 << lane << 15

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.16B
+src.val[2] → Vt3.16B
+src.val[1] → Vt2.16B
+src.val[0] → Vt.16B
+0 << lane << 15

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.1D
+src.val[2] → Vt3.1D
+src.val[1] → Vt2.1D
+src.val[0] → Vt.1D
+0 << lane << 0

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.2D
+src.val[2] → Vt3.2D
+src.val[1] → Vt2.2D
+src.val[0] → Vt.2D
+0 << lane << 1

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.1D
+src.val[2] → Vt3.1D
+src.val[1] → Vt2.1D
+src.val[0] → Vt.1D
+0 << lane << 0

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.2D
+src.val[2] → Vt3.2D
+src.val[1] → Vt2.2D
+src.val[0] → Vt.2D
+0 << lane << 1

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.1D
+src.val[2] → Vt3.1D
+src.val[1] → Vt2.1D
+src.val[0] → Vt.1D
+0 << lane << 0

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.2D
+src.val[2] → Vt3.2D
+src.val[1] → Vt2.2D
+src.val[0] → Vt.2D
+0 << lane << 1

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.1D
+src.val[2] → Vt3.1D
+src.val[1] → Vt2.1D
+src.val[0] → Vt.1D
+0 << lane << 0

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load single 4-element structure to one lane of four registers. This instruction loads a 4-element structure from memory and writes the result to the corresponding elements of the four SIMD&FP registers without affecting the other bits of the registers.

+

A64 Instruction

LD4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+src.val[3] → Vt4.2D
+src.val[2] → Vt3.2D
+src.val[1] → Vt2.2D
+src.val[0] → Vt.2D
+0 << lane << 1

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8B
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8B
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8B
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.s - Vt2.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.h - Vt2.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B
+0 << lane << 15

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B
+0 << lane << 15

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.b - Vt2.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B
+0 << lane << 15

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 2-element structure from one lane of two registers. This instruction stores a 2-element structure to memory from corresponding elements of two SIMD&FP registers.

+

A64 Instruction

ST2 {Vt.d - Vt2.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D
+0 << lane << 2

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.s - Vt3.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.h - Vt3.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B
+0 << lane << 15

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B
+0 << lane << 15

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.b - Vt3.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B
+0 << lane << 15

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 3-element structure from one lane of three registers. This instruction stores a 3-element structure to memory from corresponding elements of three SIMD&FP registers.

+

A64 Instruction

ST3 {Vt.d - Vt3.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4H
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8H
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2S
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4S
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4H
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8H
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2S
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4S
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4H
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8H
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2S
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.s - Vt4.s}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4S
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4H
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H
+0 << lane << 3

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.h - Vt4.h}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8H
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H
+0 << lane << 7

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.16B
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B
+0 << lane << 15

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.16B
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B
+0 << lane << 15

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.b - Vt4.b}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.16B
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B
+0 << lane << 15

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.1D
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2D
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.1D
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2D
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.1D
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2D
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.1D
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D
+0 << lane << 0

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store single 4-element structure from one lane of four registers. This instruction stores a 4-element structure to memory from corresponding elements of four SIMD&FP registers.

+

A64 Instruction

ST4 {Vt.d - Vt4.d}[lane],[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2D
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D
+0 << lane << 1

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8B
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.16B
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4H
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8H
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2S
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4S
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8B
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.16B
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4H
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8H
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2S
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4S
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4H
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8H
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2S
+val.val[2] → Vt3.2S
+val.val[1] → Vt2.2S
+val.val[0] → Vt.2S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4S
+val.val[2] → Vt3.4S
+val.val[1] → Vt2.4S
+val.val[0] → Vt.4S

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8B
+val.val[2] → Vt3.8B
+val.val[1] → Vt2.8B
+val.val[0] → Vt.8B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.16B
+val.val[2] → Vt3.16B
+val.val[1] → Vt2.16B
+val.val[0] → Vt.16B

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.4H
+val.val[2] → Vt3.4H
+val.val[1] → Vt2.4H
+val.val[0] → Vt.4H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.8H
+val.val[2] → Vt3.8H
+val.val[1] → Vt2.8H
+val.val[0] → Vt.8H

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.1D
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.1D
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.1D
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2D
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2D
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2D
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.1D
+val.val[2] → Vt3.1D
+val.val[1] → Vt2.1D
+val.val[0] → Vt.1D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Store a single-element structure from one lane of one register. This instruction stores the specified element of a SIMD&FP register to memory.

+

A64 Instruction

ST1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 
+val.val[3] → Vt4.2D
+val.val[2] → Vt3.2D
+val.val[1] → Vt2.2D
+val.val[0] → Vt.2D

Results

void → result
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2S - Vt2.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4S - Vt2.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8B - Vt2.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.16B - Vt2.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H - Vt2.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H - Vt2.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt2.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D - Vt2.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2S - Vt3.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4S - Vt3.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8B - Vt3.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.16B - Vt3.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H - Vt3.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H - Vt3.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt3.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D - Vt3.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2S - Vt4.2S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2S → result.val[3]
+Vt3.2S → result.val[2]
+Vt2.2S → result.val[1]
+Vt.2S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4S - Vt4.4S},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4S → result.val[3]
+Vt3.4S → result.val[2]
+Vt2.4S → result.val[1]
+Vt.4S → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8B - Vt4.8B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8B → result.val[3]
+Vt3.8B → result.val[2]
+Vt2.8B → result.val[1]
+Vt.8B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.16B - Vt4.16B},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.16B → result.val[3]
+Vt3.16B → result.val[2]
+Vt2.16B → result.val[1]
+Vt.16B → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.4H - Vt4.4H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.4H → result.val[3]
+Vt3.4H → result.val[2]
+Vt2.4H → result.val[1]
+Vt.4H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.8H - Vt4.8H},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.8H → result.val[3]
+Vt3.8H → result.val[2]
+Vt2.8H → result.val[1]
+Vt.8H → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

v7/A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A32/A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.1D - Vt4.1D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.1D → result.val[3]
+Vt3.1D → result.val[2]
+Vt2.1D → result.val[1]
+Vt.1D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Load one single-element structure to one lane of one register. This instruction loads a single-element structure from memory and writes the result to the specified lane of the SIMD&FP register without affecting the other bits of the register.

+

A64 Instruction

LD1 {Vt.2D - Vt4.2D},[Xn]
+

Argument Preparation

ptr → Xn 

Results

Vt4.2D → result.val[3]
+Vt3.2D → result.val[2]
+Vt2.2D → result.val[1]
+Vt.2D → result.val[0]
+

Operation

+
if HaveMTEExt() then
+    SetNotTagCheckedInstruction(!wback && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+
+bits(64) address;
+bits(64) offs;
+bits(128) rval;
+bits(esize) element;
+constant integer ebytes = esize DIV 8;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+offs = Zeros();
+if replicate then
+    // load and replicate to all elements
+    for s = 0 to selem-1
+        element = Mem[address+offs, ebytes, AccType_VEC];
+        // replicate to fill 128- or 64-bit register
+        V[t] = Replicate(element, datasize DIV esize);
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+else
+    // load/store one element per register
+    for s = 0 to selem-1
+        rval = V[t];
+        if memop == MemOp_LOAD then
+            // insert into one lane of 128-bit register
+            Elem[rval, index, esize] = Mem[address+offs, ebytes, AccType_VEC];
+            V[t] = rval;
+        else // memop == MemOp_STORE
+            // extract from one lane of 128-bit register
+            Mem[address+offs, ebytes, AccType_VEC] = Elem[rval, index, esize];
+        offs = offs + ebytes;
+        t = (t + 1) MOD 32;
+
+if wback then
+    if m != 31 then
+        offs = X[m];
+    if n == 31 then
+        SP[] = address + offs;
+    else
+        X[n] = address + offs;
+

Supported architectures

A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FADDP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FADDP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FADDP Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SADDLP Vd.4H,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SADDLP Vd.8H,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SADDLP Vd.2S,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SADDLP Vd.4S,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SADDLP Vd.1D,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SADDLP Vd.2D,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

UADDLP Vd.4H,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

UADDLP Vd.8H,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

UADDLP Vd.2S,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

UADDLP Vd.4S,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

UADDLP Vd.1D,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

UADDLP Vd.2D,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SADALP Vd.4H,Vn.8B
+

Argument Preparation

a → Vd.4H 
+b → Vn.8B

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SADALP Vd.8H,Vn.16B
+

Argument Preparation

a → Vd.8H 
+b → Vn.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SADALP Vd.2S,Vn.4H
+

Argument Preparation

a → Vd.2S 
+b → Vn.4H

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SADALP Vd.4S,Vn.8H
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SADALP Vd.1D,Vn.2S
+

Argument Preparation

a → Vd.1D 
+b → Vn.2S

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register and accumulates the results into the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SADALP Vd.2D,Vn.4S
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

UADALP Vd.4H,Vn.8B
+

Argument Preparation

a → Vd.4H 
+b → Vn.8B

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

UADALP Vd.8H,Vn.16B
+

Argument Preparation

a → Vd.8H 
+b → Vn.16B

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

UADALP Vd.2S,Vn.4H
+

Argument Preparation

a → Vd.2S 
+b → Vn.4H

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

UADALP Vd.4S,Vn.8H
+

Argument Preparation

a → Vd.4S 
+b → Vn.8H

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

UADALP Vd.1D,Vn.2S
+

Argument Preparation

a → Vd.1D 
+b → Vn.2S

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Add and Accumulate Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register and accumulates the results with the vector elements of the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

UADALP Vd.2D,Vn.4S
+

Argument Preparation

a → Vd.2D 
+b → Vn.4S

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMAXP Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMAXP Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMAXP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMAXP Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMAXP Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMAXP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Maximum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMAXP Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMAXP Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMAXP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMAXP Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMAXP Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMAXP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Maximum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Maximum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXP Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMINP Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMINP Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMINP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMINP Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMINP Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMINP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point Minimum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMINP Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMINP Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMINP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMINP Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMINP Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMINP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Minimum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Minimum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINP Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXNMP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXNMP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXNMP Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Minimum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINNMP Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Minimum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINNMP Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Minimum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINNMP Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FADDP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FADDP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Maximum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Maximum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Minimum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Minimum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXNMP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXNMP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Minimum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINNMP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Minimum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINNMP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

+

A64 Instruction

ADDV Bd,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);
+

Supported architectures

A64

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

+

A64 Instruction

ADDV Bd,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);
+

Supported architectures

A64

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

+

A64 Instruction

ADDV Hd,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);
+

Supported architectures

A64

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

+

A64 Instruction

ADDV Hd,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);
+

Supported architectures

A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP  Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+a → Vm.2S

Results

Vd.S[0] → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

+

A64 Instruction

ADDV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);
+

Supported architectures

A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

+

A64 Instruction

ADDV Bd,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);
+

Supported architectures

A64

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

+

A64 Instruction

ADDV Bd,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);
+

Supported architectures

A64

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

+

A64 Instruction

ADDV Hd,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);
+

Supported architectures

A64

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

+

A64 Instruction

ADDV Hd,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);
+

Supported architectures

A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP  Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+a → Vm.2S

Results

Vd.S[0] → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Add across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register.

+

A64 Instruction

ADDV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_ADD, operand, esize);
+

Supported architectures

A64

Description

Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

ADDP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[concat, 2*e, esize];
+    element2 = Elem[concat, (2*e)+1, esize];
+    Elem[result, e, esize] = element1 + element2;
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FADDP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FADDP Vt.4S,Vn.4S,Vm.4S
+FADDP Sd,Vt.2S
+

Argument Preparation

a → Vn.4S 
+a → Vm.4S

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Add Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FADDP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+    Elem[result, e, esize] = FPAdd(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SADDLV Hd,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;
+

Supported architectures

A64

Description

Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SADDLV Hd,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;
+

Supported architectures

A64

Description

Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SADDLV Sd,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;
+

Supported architectures

A64

Description

Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SADDLV Sd,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;
+

Supported architectures

A64

Description

Signed Add Long Pairwise. This instruction adds pairs of adjacent signed integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

SADDLP Vd.1D,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Add Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are signed integer values.

+

A64 Instruction

SADDLV Dd,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;
+

Supported architectures

A64

Description

Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDLV Hd,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;
+

Supported architectures

A64

Description

Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDLV Hd,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;
+

Supported architectures

A64

Description

Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDLV Sd,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;
+

Supported architectures

A64

Description

Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDLV Sd,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;
+

Supported architectures

A64

Description

Unsigned Add Long Pairwise. This instruction adds pairs of adjacent unsigned integer values from the vector in the source SIMD&FP register, places the result into a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the source vector elements.

+

A64 Instruction

UADDLP Vd.1D,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+
+bits(2*esize) sum;
+integer op1;
+integer op2;
+
+result = if acc then V[d] else Zeros();
+for e = 0 to elements-1
+    op1 = Int(Elem[operand, 2*e+0, esize], unsigned);
+    op2 = Int(Elem[operand, 2*e+1, esize], unsigned);
+    sum = (op1+op2)<2*esize-1:0>;
+    Elem[result, e, 2*esize] = Elem[result, e, 2*esize] + sum;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned sum Long across Vector. This instruction adds every vector element in the source SIMD&FP register together, and writes the scalar result to the destination SIMD&FP register. The destination scalar is twice as long as the source vector elements. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UADDLV Dd,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer sum;
+
+sum = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    sum = sum + Int(Elem[operand, e, esize], unsigned);
+
+V[d] = sum<2*esize-1:0>;
+

Supported architectures

A64

Description

Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SMAXV Bd,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SMAXV Bd,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SMAXV Hd,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SMAXV Hd,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Signed Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMAXP  Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+a → Vm.2S

Results

Vd.S[0] → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SMAXV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMAXV Bd,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMAXV Bd,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMAXV Hd,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMAXV Hd,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Unsigned Maximum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMAXP  Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+a → Vm.2S

Results

Vd.S[0] → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMAXV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Floating-point Maximum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Maximum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_FMAX, operand, esize);
+

Supported architectures

A64

Description

Floating-point Maximum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the larger of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SMINV Bd,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SMINV Bd,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SMINV Hd,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SMINV Hd,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Signed Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

SMINP  Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+a → Vm.2S

Results

Vd.S[0] → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Signed Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are signed integer values.

+

A64 Instruction

SMINV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMINV Bd,Vn.8B
+

Argument Preparation

a → Vn.8B 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMINV Bd,Vn.16B
+

Argument Preparation

a → Vn.16B 

Results

Bd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMINV Hd,Vn.4H
+

Argument Preparation

a → Vn.4H 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMINV Hd,Vn.8H
+

Argument Preparation

a → Vn.8H 

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Unsigned Minimum Pairwise. This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of unsigned integer values into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UMINP  Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+a → Vm.2S

Results

Vd.S[0] → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+integer element1;
+integer element2;
+integer maxmin;
+
+for e = 0 to elements-1
+    element1 = Int(Elem[concat, 2*e, esize], unsigned);
+    element2 = Int(Elem[concat, (2*e)+1, esize], unsigned);
+    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
+    Elem[result, e, esize] = maxmin<esize-1:0>;
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are unsigned integer values.

+

A64 Instruction

UMINV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+integer maxmin;
+integer element;
+
+maxmin = Int(Elem[operand, 0, esize], unsigned);
+for e = 1 to elements-1
+    element = Int(Elem[operand, e, esize], unsigned);
+    maxmin = if min then Min(maxmin, element) else Max(maxmin, element);
+
+V[d] = maxmin<esize-1:0>;
+

Supported architectures

A64

Description

Floating-point Minimum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_FMIN, operand, esize);
+

Supported architectures

A64

Description

Floating-point Minimum Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, writes the smaller of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINP Dd,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMin(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMax(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXNMP Sd,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Maximum Number across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the largest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXNMV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_FMAXNUM, operand, esize);
+

Supported architectures

A64

Description

Floating-point Maximum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the largest of each pair of values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMAXNMP  Dd,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Minimum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINNMP  Sd,Vn.2S
+

Argument Preparation

a → Vn.2S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Minimum Number across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINNMV Sd,Vn.4S
+

Argument Preparation

a → Vn.4S 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+V[d] = Reduce(ReduceOp_FMINNUM, operand, esize);
+

Supported architectures

A64

Description

Floating-point Minimum Number Pairwise (vector). This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements in the two source SIMD&FP registers, writes the smallest of each pair of floating-point values into a vector, and writes the vector to the destination SIMD&FP register. All the values in this instruction are floating-point values.

+

A64 Instruction

FMINNMP  Dd,Vn.2D
+

Argument Preparation

a → Vn.2D 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+bits(2*datasize) concat = operand2:operand1;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    if pair then
+        element1 = Elem[concat, 2*e, esize];
+        element2 = Elem[concat, (2*e)+1, esize];
+    else
+        element1 = Elem[operand1, e, esize];
+        element2 = Elem[operand2, e, esize];
+
+    if minimum then
+        Elem[result, e, esize] = FPMinNum(element1, element2, FPCR);
+    else
+        Elem[result, e, esize] = FPMaxNum(element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#n
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B
+0 << n << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#n
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B
+0 << n << 15

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<1)
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B
+0 << n << 3

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<1)
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B
+0 << n << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<2)
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B
+0 << n << 1

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<2)
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B
+0 << n << 3

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3)
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B
+0 << n << 0

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<3)
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B
+0 << n << 1

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#n
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B
+0 << n << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#n
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B
+0 << n << 15

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<1)
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B
+0 << n << 3

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<1)
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B
+0 << n << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<2)
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B
+0 << n << 1

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<2)
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B
+0 << n << 3

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3)
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B
+0 << n << 0

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<3)
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B
+0 << n << 1

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3)
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B
+0 << n << 0

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<3)
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B
+0 << n << 1

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<2)
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B
+0 << n << 1

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<2)
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B
+0 << n << 3

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<3)
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B
+0 << n << 0

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<3)
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B
+0 << n << 1

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#n
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B
+0 << n << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#n
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B
+0 << n << 15

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.8B,Vn.8B,Vm.8B,#(n<<1)
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B
+0 << n << 3

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Extract vector from pair of vectors. This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled.

+

A64 Instruction

EXT Vd.16B,Vn.16B,Vm.16B,#(n<<1)
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B
+0 << n << 7

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) hi = V[m];
+bits(datasize) lo = V[n];
+bits(datasize*2) concat = hi:lo;
+
+V[d] = concat<position+datasize-1:position>;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.4H,Vn.4H
+

Argument Preparation

vec → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.8H,Vn.8H
+

Argument Preparation

vec → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.2S,Vn.2S
+

Argument Preparation

vec → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.4S,Vn.4S
+

Argument Preparation

vec → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.4H,Vn.4H
+

Argument Preparation

vec → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.8H,Vn.8H
+

Argument Preparation

vec → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.2S,Vn.2S
+

Argument Preparation

vec → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.4S,Vn.4S
+

Argument Preparation

vec → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.2S,Vn.2S
+

Argument Preparation

vec → Vn.2S 

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.4S,Vn.4S
+

Argument Preparation

vec → Vn.4S 

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.4H,Vn.4H
+

Argument Preparation

vec → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 64-bit doublewords (vector). This instruction reverses the order of 8-bit, 16-bit, or 32-bit elements in each doubleword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV64 Vd.8H,Vn.8H
+

Argument Preparation

vec → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV32 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV32 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV32 Vd.4H,Vn.4H
+

Argument Preparation

vec → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV32 Vd.8H,Vn.8H
+

Argument Preparation

vec → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV32 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV32 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV32 Vd.4H,Vn.4H
+

Argument Preparation

vec → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV32 Vd.8H,Vn.8H
+

Argument Preparation

vec → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV32 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV32 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV32 Vd.4H,Vn.4H
+

Argument Preparation

vec → Vn.4H 

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 32-bit words (vector). This instruction reverses the order of 8-bit or 16-bit elements in each word of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV32 Vd.8H,Vn.8H
+

Argument Preparation

vec → Vn.8H 

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV16 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV16 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV16 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV16 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV16 Vd.8B,Vn.8B
+

Argument Preparation

vec → Vn.8B 

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Reverse elements in 16-bit halfwords (vector). This instruction reverses the order of 8-bit elements in each halfword of the vector in the source SIMD&FP register, places the results into a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

REV16 Vd.16B,Vn.16B
+

Argument Preparation

vec → Vn.16B 

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+integer element = 0;
+integer rev_element;
+for c = 0 to containers-1
+    rev_element = element + elements_per_container - 1;
+    for e = 0 to elements_per_container-1
+        Elem[result, rev_element, esize] = Elem[operand, element, esize];
+        element = element + 1;
+        rev_element = rev_element - 1;
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (primary). This instruction reads adjacent vector elements from the upper half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (primary). This instruction reads corresponding even-numbered vector elements from the two source SIMD&FP registers, starting at zero, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.2D,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN2 Vd.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

Vn → Zeros(64):a 
+b → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

Vn → Zeros(64):a 
+b → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

Vn → Zeros(64):a 
+b → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&FP register into the destination SIMD&FP register if the corresponding bit of the second source SIMD&FP register is 0, otherwise leaves the bit in the destination register unchanged.

+

A64 Instruction

MOVI Vtmp.8B,#8
+CMHS Vtmp.8B,Vm.8B,Vtmp.8B
+TBL Vtmp1.8B,{Vn.16B},Vm.8B
+BIF Vd.8B,Vtmp1.8B,Vtmp.8B
+

Argument Preparation

a → Vd 
+Vn → Zeros(64):b
+c → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[d];
+operand3 = NOT(V[m]);
+
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&FP register into the destination SIMD&FP register if the corresponding bit of the second source SIMD&FP register is 0, otherwise leaves the bit in the destination register unchanged.

+

A64 Instruction

MOVI Vtmp.8B,#8
+CMHS Vtmp.8B,Vm.8B,Vtmp.8B
+TBL Vtmp1.8B,{Vn.16B},Vm.8B
+BIF Vd.8B,Vtmp1.8B,Vtmp.8B
+

Argument Preparation

a → Vd 
+Vn → Zeros(64):b
+c → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[d];
+operand3 = NOT(V[m]);
+
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&FP register into the destination SIMD&FP register if the corresponding bit of the second source SIMD&FP register is 0, otherwise leaves the bit in the destination register unchanged.

+

A64 Instruction

MOVI Vtmp.8B,#8
+CMHS Vtmp.8B,Vm.8B,Vtmp.8B
+TBL Vtmp1.8B,{Vn.16B},Vm.8B
+BIF Vd.8B,Vtmp1.8B, Vtmp.8B
+

Argument Preparation

a → Vd 
+Vn → Zeros(64):b
+c → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[d];
+operand3 = NOT(V[m]);
+
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 
+b → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 
+b → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 
+b → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 
+Vn+1 → Zeros(64):a.val[2]
+b → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 
+Vn+1 → Zeros(64):a.val[2]
+b → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 
+Vn+1 → Zeros(64):a.val[2]
+b → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 
+Vn+1 → a.val[3]:a.val[2]
+b → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 
+Vn+1 → a.val[3]:a.val[2]
+b → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

Vn → a.val[1]:a.val[0] 
+Vn+1 → a.val[3]:a.val[2]
+b → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

a → Vd 
+Vn → b.val[1]:b.val[0]
+c → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

a → Vd 
+Vn → b.val[1]:b.val[0]
+c → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

a → Vd 
+Vn → b.val[1]:b.val[0]
+c → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&FP register into the destination SIMD&FP register if the corresponding bit of the second source SIMD&FP register is 0, otherwise leaves the bit in the destination register unchanged.

+

A64 Instruction

MOVI Vtmp.8B,#24
+CMHS Vtmp.8B,Vm.8B,Vtmp.8B
+TBL Vtmp1.8B,{Vn.16B,Vn+1.16B},Vm.8
+BIF Vd.8B,Vtmp1.8B,Vtmp.8B
+

Argument Preparation

a → Vd 
+Vn → b.val[1]:b.val[0]
+Vn+1 → Zeros(64):b.val[2]
+c → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[d];
+operand3 = NOT(V[m]);
+
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&FP register into the destination SIMD&FP register if the corresponding bit of the second source SIMD&FP register is 0, otherwise leaves the bit in the destination register unchanged.

+

A64 Instruction

MOVI Vtmp.8B,#24
+CMHS Vtmp.8B,Vm.8B,Vtmp.8B
+TBL Vtmp1.8B,{Vn.16B,Vn+1.16B},Vm.8B
+BIF Vd.8B,Vtmp1.8B,Vtmp.8B
+

Argument Preparation

a → Vd 
+Vn → b.val[1]:b.val[0]
+Vn+1 → Zeros(64):b.val[2]
+c → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[d];
+operand3 = NOT(V[m]);
+
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Bitwise Insert if False. This instruction inserts each bit from the first source SIMD&FP register into the destination SIMD&FP register if the corresponding bit of the second source SIMD&FP register is 0, otherwise leaves the bit in the destination register unchanged.

+

A64 Instruction

MOVI Vtmp.8B,#24
+CMHS Vtmp.8B,Vm.8B,Vtmp.8B
+TBL Vtmp1.8B,{Vn.16B,Vn+1.16B},Vm.8B
+BIF Vd.8B,Vtmp1.8B,Vtmp.8B
+

Argument Preparation

a → Vd 
+Vn → b.val[1]:b.val[0]
+Vn+1 → Zeros(64):b.val[2]
+c → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1;
+bits(datasize) operand3;
+bits(datasize) operand4 = V[n];
+
+operand1 = V[d];
+operand3 = NOT(V[m]);
+
+V[d] = operand1 EOR ((operand1 EOR operand4) AND operand3);
+

Supported architectures

v7/A32/A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

a → Vd 
+Vn → b.val[1]:b.val[0]
+Vn+1 → b.val[3]:b.val[2]
+c → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

a → Vd 
+Vn → b.val[1]:b.val[0]
+Vn+1 → b.val[3]:b.val[2]
+c → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B,Vn+1.16B},Vm.8B
+

Argument Preparation

a → Vd 
+Vn → b.val[1]:b.val[0]
+Vn+1 → b.val[3]:b.val[2]
+c → Vm

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

t → Vn.16B 
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.16B,{Vn.16B},Vm.16B
+

Argument Preparation

t → Vn.16B 
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

t → Vn.16B 
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.16B,{Vn.16B},Vm.16B
+

Argument Preparation

t → Vn.16B 
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

t → Vn.16B 
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.16B,{Vn.16B},Vm.16B
+

Argument Preparation

t → Vn.16B 
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 
+t → Vn.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.16B,{Vn.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 
+t → Vn.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 
+t → Vn.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.16B,{Vn.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 
+t → Vn.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 
+t → Vn.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.16B,{Vn.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 
+t → Vn.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+t.val[3] → Vn+3.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+t.val[3] → Vn+3.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+t.val[3] → Vn+3.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+t.val[3] → Vn+3.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+t.val[3] → Vn+3.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector Lookup. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the result for that lookup is 0. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBL Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+

Argument Preparation

t.val[0] → Vn.16B 
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+t.val[3] → Vn+3.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+1.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+1.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+2.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+2.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+t.val[3] → Vn+3.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+t.val[3] → Vn+3.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+t.val[3] → Vn+3.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+t.val[3] → Vn+3.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.8B,{Vn.16B - Vn+3.16B},Vm.8B
+

Argument Preparation

a → Vd.8B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+t.val[3] → Vn+3.16B
+idx → Vm.8B

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Table vector lookup extension. This instruction reads each value from the vector elements in the index source SIMD&FP register, uses each result as an index to perform a lookup in a table of bytes that is described by one to four source table SIMD&FP registers, places the lookup result in a vector, and writes the vector to the destination SIMD&FP register. If an index is out of range for the table, the existing value in the vector element of the destination register is left unchanged. If more than one source register is used to describe the table, the first source register describes the lowest bytes of the table.

+

A64 Instruction

TBX Vd.16B,{Vn.16B - Vn+3.16B},Vm.16B
+

Argument Preparation

a → Vd.16B 
+t.val[0] → Vn.16B
+t.val[1] → Vn+1.16B
+t.val[2] → Vn+2.16B
+t.val[3] → Vn+3.16B
+idx → Vm.16B

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) indices = V[m];
+bits(128*regs) table = Zeros();
+bits(datasize) result;
+integer index;
+
+// Create table from registers
+for i = 0 to regs-1
+    table<128*i+127:128*i> = V[n];
+    n = (n + 1) MOD 32;
+
+result = if is_tbl then Zeros() else V[d];
+for i = 0 to elements-1
+    index = UInt(Elem[indices, i, 8]);
+    if index < 16 * regs then
+        Elem[result, i, 8] = Elem[table, index, 8];
+
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.B[lane]
+

Argument Preparation

v → Vn.8B 
+0 << lane << 7

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.H[lane]
+

Argument Preparation

v → Vn.4H 
+0 << lane << 3

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.S[lane]
+

Argument Preparation

v → Vn.2S 
+0 << lane << 1

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.D[lane]
+

Argument Preparation

v → Vn.1D 
+0 << lane << 0

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.D[lane]
+

Argument Preparation

v → Vn.1D 
+0 << lane << 0

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

A32/A64

Description

Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.

+

A64 Instruction

SMOV Rd,Vn.B[lane]
+

Argument Preparation

v → Vn.8B 
+0 << lane << 7

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = SignExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.

+

A64 Instruction

SMOV Rd,Vn.H[lane]
+

Argument Preparation

v → Vn.4H 
+0 << lane << 3

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = SignExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.

+

A64 Instruction

SMOV Rd,Vn.S[lane]
+

Argument Preparation

v → Vn.2S 
+0 << lane << 1

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = SignExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.D[lane]
+

Argument Preparation

v → Vn.1D 
+0 << lane << 0

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.B[lane]
+

Argument Preparation

v → Vn.8B 
+0 << lane << 7

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.H[lane]
+

Argument Preparation

v → Vn.4H 
+0 << lane << 3

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

v → Vn.2S 
+0 << lane << 1

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

v → Vn.1D 
+0 << lane << 0

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.B[lane]
+

Argument Preparation

v → Vn.16B 
+0 << lane << 15

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.H[lane]
+

Argument Preparation

v → Vn.8H 
+0 << lane << 7

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.S[lane]
+

Argument Preparation

v → Vn.4S 
+0 << lane << 3

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.D[lane]
+

Argument Preparation

v → Vn.2D 
+0 << lane << 1

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.D[lane]
+

Argument Preparation

v → Vn.2D 
+0 << lane << 1

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

A32/A64

Description

Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.

+

A64 Instruction

SMOV Rd,Vn.B[lane]
+

Argument Preparation

v → Vn.16B 
+0 << lane << 15

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = SignExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.

+

A64 Instruction

SMOV Rd,Vn.H[lane]
+

Argument Preparation

v → Vn.8H 
+0 << lane << 7

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = SignExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Signed Move vector element to general-purpose register. This instruction reads the signed integer from the source SIMD&FP register, sign-extends it to form a 32-bit or 64-bit value, and writes the result to destination general-purpose register.

+

A64 Instruction

SMOV Rd,Vn.S[lane]
+

Argument Preparation

v → Vn.4S 
+0 << lane << 3

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = SignExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.D[lane]
+

Argument Preparation

v → Vn.2D 
+0 << lane << 1

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.B[lane]
+

Argument Preparation

v → Vn.16B 
+0 << lane << 15

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Unsigned Move vector element to general-purpose register. This instruction reads the unsigned integer from the source SIMD&FP register, zero-extends it to form a 32-bit or 64-bit value, and writes the result to the destination general-purpose register.

+

A64 Instruction

UMOV Rd,Vn.H[lane]
+

Argument Preparation

v → Vn.8H 
+0 << lane << 7

Results

Rd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(idxdsize) operand = V[n];
+
+X[d] = ZeroExtend(Elem[operand, index, esize], datasize);
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

v → Vn.4H 
+0 << lane << 3

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Hd,Vn.H[lane]
+

Argument Preparation

v → Vn.8H 
+0 << lane << 7

Results

Hd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Sd,Vn.S[lane]
+

Argument Preparation

v → Vn.4S 
+0 << lane << 3

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Duplicate general-purpose register to vector. This instruction duplicates the contents of the source general-purpose register into a scalar or each element in a vector, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

DUP Dd,Vn.D[lane]
+

Argument Preparation

v → Vn.2D 
+0 << lane << 1

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(datasize) result;
+
+for e = 0 to elements-1
+    Elem[result, e, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.8B
+0 << lane << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.4H
+0 << lane << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.2S
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.1D
+0 << lane << 0

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.1D
+0 << lane << 0

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.8B
+0 << lane << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.4H
+0 << lane << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.2S
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.1D
+0 << lane << 0

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.8B
+0 << lane << 7

Results

Vd.8B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.4H
+0 << lane << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane],Vn.H[0]
+

Argument Preparation

a → VnH 
+v → Vd.4H
+0 << lane << 3

Results

Vd.4H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane],Vn.H[0]
+

Argument Preparation

a → VnH 
+v → Vd.8H
+0 << lane << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.2S
+0 << lane << 1

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.1D
+0 << lane << 0

Results

Vd.1D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.16B
+0 << lane << 15

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.8H
+0 << lane << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.4S
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.2D
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.2D
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.16B
+0 << lane << 15

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.8H
+0 << lane << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.4S
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.2D
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.B[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.16B
+0 << lane << 15

Results

Vd.16B → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.H[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.8H
+0 << lane << 7

Results

Vd.8H → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.S[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.4S
+0 << lane << 3

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Insert vector element from general-purpose register. This instruction copies the contents of the source general-purpose register to the specified vector element in the destination SIMD&FP register.

+

A64 Instruction

INS Vd.D[lane],Rn
+

Argument Preparation

a → Rn 
+v → Vd.2D
+0 << lane << 1

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(esize) element = X[n];
+bits(128) result;
+
+result = V[d];
+Elem[result, index, esize] = element;
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal exponent (scalar). This instruction finds an approximate reciprocal exponent for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRECPX Sd,Sn
+

Argument Preparation

a → Sn 

Results

Sd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecpX(element, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Reciprocal exponent (scalar). This instruction finds an approximate reciprocal exponent for each vector element in the source SIMD&FP register, places the result in a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

FRECPX Dd,Dn
+

Argument Preparation

a → Dn 

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand = V[n];
+bits(datasize) result;
+bits(esize) element;
+
+for e = 0 to elements-1
+    element = Elem[operand, e, esize];
+    Elem[result, e, esize] = FPRecpX(element, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+n → Vm.S[0]

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+n → Vm.S[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Vd.2S,Vn.2S,Vm.S[0]
+

Argument Preparation

a → Vd.2S 
+b → Vn.2S
+n → Vm.S[0]

Results

Vd.2S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Vd.4S,Vn.4S,Vm.S[0]
+

Argument Preparation

a → Vd.4S 
+b → Vn.4S
+n → Vm.S[0]

Results

Vd.4S → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, adds the product to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FMADD Dd,Dn,Dm,Da
+

Argument Preparation

a → Da 
+b → Dn
+n → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) result;
+bits(datasize) operanda = V[a];
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+
+result = FPMulAdd(operanda, operand1, operand2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Add to accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, adds the product to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLA Vd.2D,Vn.2D,Vm.D[0]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+n → Vm.D[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point Fused Multiply-Subtract (scalar). This instruction multiplies the values of the first two SIMD&FP source registers, negates the product, adds that to the value of the third SIMD&FP source register, and writes the result to the SIMD&FP destination register.

+

A64 Instruction

FMSUB Dd,Dn,Dm,Da
+

Argument Preparation

a → Da 
+b → Dn
+n → Dm

Results

Dd → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) result;
+bits(datasize) operanda = V[a];
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+
+operand1 = FPNeg(operand1);
+result = FPMulAdd(operanda, operand1, operand2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Floating-point fused Multiply-Subtract from accumulator (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, negates the product, adds the result to the corresponding vector element of the destination SIMD&FP register, and writes the result to the destination SIMD&FP register.

+

A64 Instruction

FMLS Vd.2D,Vn.2D,Vm.D[0]
+

Argument Preparation

a → Vd.2D 
+b → Vn.2D
+n → Vm.D[0]

Results

Vd.2D → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) operand3 = V[d];
+bits(datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    if sub_op then element1 = FPNeg(element1);
+    Elem[result, e, esize] = FPMulAdd(Elem[operand3, e, esize], element1, element2, FPCR);
+
+V[d] = result;
+

Supported architectures

A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.8B,Vn.8B,Vm.8B
+TRN2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.4H,Vn.4H,Vm.4H
+TRN2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.8B,Vn.8B,Vm.8B
+TRN2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.4H,Vn.4H,Vm.4H
+TRN2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.8B,Vn.8B,Vm.8B
+TRN2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.4H,Vn.4H,Vm.4H
+TRN2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.2S,Vn.2S,Vm.2S
+TRN2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.2S,Vn.2S,Vm.2S
+TRN2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.2S,Vn.2S,Vm.2S
+TRN2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.16B,Vn.16B,Vm.16B
+TRN2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.8H,Vn.8H,Vm.8H
+TRN2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.4S,Vn.4S,Vm.4S
+TRN2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.4S,Vn.4S,Vm.4S
+TRN2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.16B,Vn.16B,Vm.16B
+TRN2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.8H,Vn.8H,Vm.8H
+TRN2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.4S,Vn.4S,Vm.4S
+TRN2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.16B,Vn.16B,Vm.16B
+TRN2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Transpose vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places each result into consecutive elements of a vector, and writes the vector to the destination SIMD&FP register. Vector elements from the first source register are placed into even-numbered elements of the destination vector, starting at zero, while vector elements from the second source register are placed into odd-numbered elements of the destination vector.

+

A64 Instruction

TRN1 Vd1.8H,Vn.8H,Vm.8H
+TRN2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, 2*p+part, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, 2*p+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.8B,Vn.8B,Vm.8B
+ZIP2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.4H,Vn.4H,Vm.4H
+ZIP2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.8B,Vn.8B,Vm.8B
+ZIP2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.4H,Vn.4H,Vm.4H
+ZIP2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.8B,Vn.8B,Vm.8B
+ZIP2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.4H,Vn.4H,Vm.4H
+ZIP2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.2S,Vn.2S,Vm.2S
+ZIP2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.2S,Vn.2S,Vm.2S
+ZIP2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.2S,Vn.2S,Vm.2S
+ZIP2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.16B,Vn.16B,Vm.16B
+ZIP2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.8H,Vn.8H,Vm.8H
+ZIP2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.4S,Vn.4S,Vm.4S
+ZIP2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.4S,Vn.4S,Vm.4S
+ZIP2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.16B,Vn.16B,Vm.16B
+ZIP2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.8H,Vn.8H,Vm.8H
+ZIP2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.4S,Vn.4S,Vm.4S
+ZIP2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.16B,Vn.16B,Vm.16B
+ZIP2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Zip vectors (secondary). This instruction reads adjacent vector elements from the lower half of two source SIMD&FP registers as pairs, interleaves the pairs and places them into a vector, and writes the vector to the destination SIMD&FP register. The first pair from the first source register is placed into the two lowest vector elements, with subsequent pairs taken alternately from each source register.

+

A64 Instruction

ZIP1 Vd1.8H,Vn.8H,Vm.8H
+ZIP2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = V[n];
+bits(datasize) operand2 = V[m];
+bits(datasize) result;
+
+integer base = part * pairs;
+
+for p = 0 to pairs-1
+    Elem[result, 2*p+0, esize] = Elem[operand1, base+p, esize];
+    Elem[result, 2*p+1, esize] = Elem[operand2, base+p, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.8B,Vn.8B,Vm.8B
+UZP2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.4H,Vn.4H,Vm.4H
+UZP2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.2S,Vn.2S,Vm.2S
+UZP2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.2S,Vn.2S,Vm.2S
+UZP2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.8B,Vn.8B,Vm.8B
+UZP2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.4H,Vn.4H,Vm.4H
+UZP2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.2S,Vn.2S,Vm.2S
+UZP2 Vd2.2S,Vn.2S,Vm.2S
+

Argument Preparation

a → Vn.2S 
+b → Vm.2S

Results

Vd1.2S → result.val[0]
+Vd2.2S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.8B,Vn.8B,Vm.8B
+UZP2 Vd2.8B,Vn.8B,Vm.8B
+

Argument Preparation

a → Vn.8B 
+b → Vm.8B

Results

Vd1.8B → result.val[0]
+Vd2.8B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.4H,Vn.4H,Vm.4H
+UZP2 Vd2.4H,Vn.4H,Vm.4H
+

Argument Preparation

a → Vn.4H 
+b → Vm.4H

Results

Vd1.4H → result.val[0]
+Vd2.4H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.16B,Vn.16B,Vm.16B
+UZP2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.8H,Vn.8H,Vm.8H
+UZP2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.4S,Vn.4S,Vm.4S
+UZP2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.4S,Vn.4S,Vm.4S
+UZP2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.16B,Vn.16B,Vm.16B
+UZP2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.8H,Vn.8H,Vm.8H
+UZP2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.4S,Vn.4S,Vm.4S
+UZP2 Vd2.4S,Vn.4S,Vm.4S
+

Argument Preparation

a → Vn.4S 
+b → Vm.4S

Results

Vd1.4S → result.val[0]
+Vd2.4S → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.16B,Vn.16B,Vm.16B
+UZP2 Vd2.16B,Vn.16B,Vm.16B
+

Argument Preparation

a → Vn.16B 
+b → Vm.16B

Results

Vd1.16B → result.val[0]
+Vd2.16B → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

Unzip vectors (secondary). This instruction reads corresponding odd-numbered vector elements from the two source SIMD&FP registers, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector, and writes the vector to the destination SIMD&FP register.

+

A64 Instruction

UZP1 Vd1.8H,Vn.8H,Vm.8H
+UZP2 Vd2.8H,Vn.8H,Vm.8H
+

Argument Preparation

a → Vn.8H 
+b → Vm.8H

Results

Vd1.8H → result.val[0]
+Vd2.8H → result.val[1]
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operandl = V[n];
+bits(datasize) operandh = V[m];
+bits(datasize) result;
+
+bits(datasize*2) zipped = operandh:operandl;
+for e = 0 to elements-1
+    Elem[result, e, esize] = Elem[zipped, 2*e+part, esize];
+
+V[d] = result;
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.1D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.1D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.1D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.1D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.1D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2S 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.1D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8B 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.1D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.1D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.2S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.8B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.4H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4H 

Results

Vd.1D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.1Q → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.1Q → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.1Q → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.1Q → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.1Q → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.1Q → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.1Q → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.4S 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.1Q → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.16B 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.1Q → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.4S → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.16B → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.8H → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

v7/A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.8H 

Results

Vd.1Q → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.8B → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.2S → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.8B → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.2S → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.8B → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.2S → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.16B → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.4S → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.16B → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.4S → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.16B → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.4S → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.8B → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.2S → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.8B → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.2S → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.8B → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.1D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.1D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.1D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1D 

Results

Vd.4H → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.16B → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.4S → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.16B → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.4S → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.16B → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.2D 

Results

Vd.8H → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q 

Results

Vd.16B → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q 

Results

Vd.8H → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q 

Results

Vd.4S → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q 

Results

Vd.16B → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q 

Results

Vd.8H → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q 

Results

Vd.4S → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q 

Results

Vd.16B → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q 

Results

Vd.8H → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q 

Results

Vd.2D → result
+

Supported architectures

A32/A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q 

Results

Vd.2D → result
+

Supported architectures

A64

Description

A64 Instruction

NOP 
+

Argument Preparation

a → Vd.1Q 

Results

Vd.8H → result
+

Supported architectures

A32/A64

Description

Load SIMD&FP Register (register offset). This instruction loads a SIMD&FP register from memory. The address that is used for the load is calculated from a base register value and an offset register value. The offset can be optionally shifted and extended.

+

A64 Instruction

LDR Qd,[Xn]
+

Argument Preparation

ptr → Xn 

Results

Qd → result
+

Operation

+
bits(64) offset = ExtendReg(m, extend_type, shift);
+if HaveMTEExt() then
+    boolean is_load_store = memop IN {MemOp_STORE, MemOp_LOAD};
+    SetNotTagCheckedInstruction(is_load_store && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+bits(64) address;
+bits(datasize) data;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+address = address + offset;
+
+case memop of
+    when MemOp_STORE
+        data = V[t];
+        Mem[address, datasize DIV 8, AccType_VEC] = data;
+
+    when MemOp_LOAD
+        data = Mem[address, datasize DIV 8, AccType_VEC];
+        V[t] = data;
+

Supported architectures

A32/A64

Description

Store SIMD&FP register (register offset). This instruction stores a single SIMD&FP register to memory. The address that is used for the store is calculated from a base register value and an offset register value. The offset can be optionally shifted and extended.

+

A64 Instruction

STR Qt,[Xn]
+

Argument Preparation

ptr → Xn 
+val → Qt

Results

void → result
+

Operation

+
bits(64) offset = ExtendReg(m, extend_type, shift);
+if HaveMTEExt() then
+    boolean is_load_store = memop IN {MemOp_STORE, MemOp_LOAD};
+    SetNotTagCheckedInstruction(is_load_store && n == 31);
+
+CheckFPAdvSIMDEnabled64();
+bits(64) address;
+bits(datasize) data;
+
+if n == 31 then
+    CheckSPAlignment();
+    address = SP[];
+else
+    address = X[n];
+
+address = address + offset;
+
+case memop of
+    when MemOp_STORE
+        data = V[t];
+        Mem[address, datasize DIV 8, AccType_VEC] = data;
+
+    when MemOp_LOAD
+        data = Mem[address, datasize DIV 8, AccType_VEC];
+        V[t] = data;
+

Supported architectures

A32/A64

Description

AES single round encryption.

+

A64 Instruction

AESE Vd.16B,Vn.16B
+

Argument Preparation

data → Vd.16B 
+key → Vn.16B

Results

Vd.16B → result
+

Operation

+
AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand1 = V[d];
+bits(128) operand2 = V[n];
+bits(128) result;
+result = operand1 EOR operand2;
+result = AESSubBytes(AESShiftRows(result));
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

AES single round decryption.

+

A64 Instruction

AESD Vd.16B,Vn.16B
+

Argument Preparation

data → Vd.16B 
+key → Vn.16B

Results

Vd.16B → result
+

Operation

+
AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand1 = V[d];
+bits(128) operand2 = V[n];
+bits(128) result;
+result = operand1 EOR operand2;
+result = AESInvSubBytes(AESInvShiftRows(result));
+V[d] = result;
+

Supported architectures

A32/A64

Description

AES mix columns.

+

A64 Instruction

AESMC Vd.16B,Vn.16B
+

Argument Preparation

data → Vn.16B 

Results

Vd.16B → result
+

Operation

+
AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand = V[n];
+bits(128) result;
+result = AESMixColumns(operand);
+V[d] = result;
+

Supported architectures

A32/A64

Description

AES inverse mix columns.

+

A64 Instruction

AESIMC Vd.16B,Vn.16B
+

Argument Preparation

data → Vn.16B 

Results

Vd.16B → result
+

Operation

+
AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand = V[n];
+bits(128) result;
+result = AESInvMixColumns(operand);
+V[d] = result;
+

Supported architectures

A32/A64

Description

SHA1 hash update (choose).

+

A64 Instruction

SHA1C Qd,Sn,Vm.4S
+

Argument Preparation

hash_abcd → Qd 
+hash_e → Sn
+wk → Vm.4S

Results

Qd → result
+

Operation

+
AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) X = V[d];
+bits(32) Y = V[n];    // Note: 32 not 128 bits wide
+bits(128) W = V[m];
+bits(32) t;
+
+for e = 0 to 3
+    t = SHAchoose(X<63:32>, X<95:64>, X<127:96>);
+    Y = Y + ROL(X<31:0>, 5) + t + Elem[W, e, 32];
+    X<63:32> = ROL(X<63:32>, 30);
+    <Y, X> = ROL(Y:X, 32);
+V[d] = X;
+

Supported architectures

A32/A64

Description

SHA1 hash update (parity).

+

A64 Instruction

SHA1P Qd,Sn,Vm.4S
+

Argument Preparation

hash_abcd → Qd 
+hash_e → Sn
+wk → Vm.4S

Results

Qd → result
+

Operation

+
AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) X = V[d];
+bits(32) Y = V[n];    // Note: 32 not 128 bits wide
+bits(128) W = V[m];
+bits(32) t;
+
+for e = 0 to 3
+    t = SHAparity(X<63:32>, X<95:64>, X<127:96>);
+    Y = Y + ROL(X<31:0>, 5) + t + Elem[W, e, 32];
+    X<63:32> = ROL(X<63:32>, 30);
+    <Y, X> = ROL(Y:X, 32);
+V[d] = X;
+

Supported architectures

A32/A64

Description

SHA1 hash update (majority).

+

A64 Instruction

SHA1M Qd,Sn,Vm.4S
+

Argument Preparation

hash_abcd → Qd 
+hash_e → Sn
+wk → Vm.4S

Results

Qd → result
+

Operation

+
AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) X = V[d];
+bits(32) Y = V[n];    // Note: 32 not 128 bits wide
+bits(128) W = V[m];
+bits(32) t;
+
+for e = 0 to 3
+    t = SHAmajority(X<63:32>, X<95:64>, X<127:96>);
+    Y = Y + ROL(X<31:0>, 5) + t + Elem[W, e, 32];
+    X<63:32> = ROL(X<63:32>, 30);
+    <Y, X> = ROL(Y:X, 32);
+V[d] = X;
+

Supported architectures

A32/A64

Description

SHA1 fixed rotate.

+

A64 Instruction

SHA1H Sd,Sn
+

Argument Preparation

hash_e → Sn 

Results

Sd → result
+

Operation

+
AArch64.CheckFPAdvSIMDEnabled();
+
+bits(32) operand = V[n];    // read element [0] only,  [1-3] zeroed
+V[d] = ROL(operand, 30);
+

Supported architectures

A32/A64

Description

SHA1 schedule update 0.

+

A64 Instruction

SHA1SU0 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

w0_3 → Vd.4S 
+w4_7 → Vn.4S
+w8_11 → Vm.4S

Results

Vd.4S → result
+

Operation

+
AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand1 = V[d];
+bits(128) operand2 = V[n];
+bits(128) operand3 = V[m];
+bits(128) result;
+
+result = operand2<63:0>:operand1<127:64>;
+result = result EOR operand1 EOR operand3;
+V[d] = result;
+

Supported architectures

A32/A64

Description

SHA1 schedule update 1.

+

A64 Instruction

SHA1SU1 Vd.4S,Vn.4S
+

Argument Preparation

tw0_3 → Vd.4S 
+w12_15 → Vn.4S

Results

Vd.4S → result
+

Operation

+
AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand1 = V[d];
+bits(128) operand2 = V[n];
+bits(128) result;
+bits(128) T = operand1 EOR LSR(operand2, 32);
+result<31:0> = ROL(T<31:0>, 1);
+result<63:32> = ROL(T<63:32>, 1);
+result<95:64> = ROL(T<95:64>, 1);
+result<127:96> = ROL(T<127:96>, 1) EOR ROL(T<31:0>, 2);
+V[d] = result;
+

Supported architectures

A32/A64

Description

SHA256 hash update (part 1).

+

A64 Instruction

SHA256H Qd,Qn,Vm.4S
+

Argument Preparation

hash_abcd → Qd 
+hash_efgh → Qn
+wk → Vm.4S

Results

Qd → result
+

Operation

+
AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) result;
+result = SHA256hash(V[d], V[n], V[m], TRUE);
+V[d] = result;
+

Supported architectures

A32/A64

Description

SHA256 hash update (part 2).

+

A64 Instruction

SHA256H2 Qd,Qn,Vm.4S
+

Argument Preparation

hash_efgh → Qd 
+hash_abcd → Qn
+wk → Vm.4S

Results

Qd → result
+

Operation

+
AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) result;
+result = SHA256hash(V[n], V[d], V[m], FALSE);
+V[d] = result;
+

Supported architectures

A32/A64

Description

SHA256 schedule update 0.

+

A64 Instruction

SHA256SU0 Vd.4S,Vn.4S
+

Argument Preparation

w0_3 → Vd.4S 
+w4_7 → Vn.4S

Results

Vd.4S → result
+

Operation

+
AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand1 = V[d];
+bits(128) operand2 = V[n];
+bits(128) result;
+bits(128) T = operand2<31:0>:operand1<127:32>;
+bits(32) elt;
+
+for e = 0 to 3
+    elt = Elem[T, e, 32];
+    elt = ROR(elt, 7) EOR ROR(elt, 18) EOR LSR(elt, 3);
+    Elem[result, e, 32] = elt + Elem[operand1, e, 32];
+V[d] = result;
+

Supported architectures

A32/A64

Description

SHA256 schedule update 1.

+

A64 Instruction

SHA256SU1 Vd.4S,Vn.4S,Vm.4S
+

Argument Preparation

tw0_3 → Vd.4S 
+w8_11 → Vn.4S
+w12_15 → Vm.4S

Results

Vd.4S → result
+

Operation

+
AArch64.CheckFPAdvSIMDEnabled();
+
+bits(128) operand1 = V[d];
+bits(128) operand2 = V[n];
+bits(128) operand3 = V[m];
+bits(128) result;
+bits(128) T0 = operand3<31:0>:operand2<127:32>;
+bits(64) T1;
+bits(32) elt;
+
+T1 = operand3<127:64>;
+for e = 0 to 1
+    elt = Elem[T1, e, 32];
+    elt = ROR(elt, 17) EOR ROR(elt, 19) EOR LSR(elt, 10);
+    elt = elt + Elem[operand1, e, 32] + Elem[T0, e, 32];
+    Elem[result, e, 32] = elt;
+
+T1 = result<63:0>;
+for e = 2 to 3
+    elt = Elem[T1, e-2, 32];
+    elt = ROR(elt, 17) EOR ROR(elt, 19) EOR LSR(elt, 10);
+    elt = elt + Elem[operand1, e, 32] + Elem[T0, e, 32];
+    Elem[result, e, 32] = elt;
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Polynomial Multiply Long. This instruction multiplies corresponding elements in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

PMULL Vd.1Q,Vn.1D,Vm.1D
+

Argument Preparation

a → Vn.1D 
+b → Vm.1D

Results

Vd.1Q → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, 2*esize] = PolynomialMult(element1, element2);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

Polynomial Multiply Long. This instruction multiplies corresponding elements in the lower or upper half of the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register. The destination vector elements are twice as long as the elements that are multiplied.

+

A64 Instruction

PMULL2 Vd.1Q,Vn.2D,Vm.2D
+

Argument Preparation

a → Vn.2D 
+b → Vm.2D

Results

Vd.1Q → result
+

Operation

+
CheckFPAdvSIMDEnabled64();
+bits(datasize) operand1 = Vpart[n, part];
+bits(datasize) operand2 = Vpart[m, part];
+bits(2*datasize) result;
+bits(esize) element1;
+bits(esize) element2;
+
+for e = 0 to elements-1
+    element1 = Elem[operand1, e, esize];
+    element2 = Elem[operand2, e, esize];
+    Elem[result, e, 2*esize] = PolynomialMult(element1, element2);
+
+V[d] = result;
+

Supported architectures

A32/A64

Description

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.

+

A64 Instruction

CRC32B Wd,Wn,Wm
+

Argument Preparation

a → Wn 
+b → Wm

Results

Wd → result
+

Operation

+
bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x04C11DB7<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));
+

Supported architectures

A32/A64

Description

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.

+

A64 Instruction

CRC32H Wd,Wn,Wm
+

Argument Preparation

a → Wn 
+b → Wm

Results

Wd → result
+

Operation

+
bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x04C11DB7<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));
+

Supported architectures

A32/A64

Description

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.

+

A64 Instruction

CRC32W Wd,Wn,Wm
+

Argument Preparation

a → Wn 
+b → Wm

Results

Wd → result
+

Operation

+
bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x04C11DB7<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));
+

Supported architectures

A32/A64

Description

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x04C11DB7 is used for the CRC calculation.

+

A64 Instruction

CRC32X Wd,Wn,Xm
+

Argument Preparation

a → Wn 
+b → Xm

Results

Wd → result
+

Operation

+
bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x04C11DB7<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));
+

Supported architectures

A32/A64

Description

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the CRC calculation.

+

A64 Instruction

CRC32CB Wd,Wn,Wm
+

Argument Preparation

a → Wn 
+b → Wm

Results

Wd → result
+

Operation

+
bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x1EDC6F41<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));
+

Supported architectures

A32/A64

Description

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the CRC calculation.

+

A64 Instruction

CRC32CH Wd,Wn,Wm
+

Argument Preparation

a → Wn 
+b → Wm

Results

Wd → result
+

Operation

+
bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x1EDC6F41<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));
+

Supported architectures

A32/A64

Description

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the CRC calculation.

+

A64 Instruction

CRC32CW Wd,Wn,Wm
+

Argument Preparation

a → Wn 
+b → Wm

Results

Wd → result
+

Operation

+
bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x1EDC6F41<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));
+

Supported architectures

A32/A64

Description

CRC32 checksum performs a cyclic redundancy check (CRC) calculation on a value held in a general-purpose register. It takes an input CRC value in the first source operand, performs a CRC on the input value in the second source operand, and returns the output CRC value. The second source operand can be 8, 16, 32, or 64 bits. To align with common usage, the bit order of the values is reversed as part of the operation, and the polynomial 0x1EDC6F41 is used for the CRC calculation.

+

A64 Instruction

CRC32CX Wd,Wn,Xm
+

Argument Preparation

a → Wn 
+b → Xm

Results

Wd → result
+

Operation

+
bits(32) acc = X[n];    // accumulator
+bits(size) val = X[m];    // input value
+bits(32) poly = 0x1EDC6F41<31:0>;
+
+bits(32+size) tempacc = BitReverse(acc):Zeros(size);
+bits(size+32) tempval = BitReverse(val):Zeros(32);
+
+// Poly32Mod2 on a bitstring does a polynomial Modulus over {0,1} operation
+X[d] = BitReverse(Poly32Mod2(tempacc EOR tempval, poly));
+

Supported architectures

A32/A64

+
+ +
+
+
+ +
+ + +