From dc0db358abe19481e475e10c32149b53370f1a1c Mon Sep 17 00:00:00 2001
From: Daniel Baumann <daniel.baumann@progress-linux.org>
Date: Thu, 30 May 2024 05:57:31 +0200
Subject: Merging upstream version 1.72.1+dfsg1.

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
---
 .../inline_instruction_set.default.Inline.diff     | 56 +++++++++-------------
 1 file changed, 22 insertions(+), 34 deletions(-)

(limited to 'tests/mir-opt/inline/inline_instruction_set.default.Inline.diff')

diff --git a/tests/mir-opt/inline/inline_instruction_set.default.Inline.diff b/tests/mir-opt/inline/inline_instruction_set.default.Inline.diff
index a1d2423ae..6f8b730b4 100644
--- a/tests/mir-opt/inline/inline_instruction_set.default.Inline.diff
+++ b/tests/mir-opt/inline/inline_instruction_set.default.Inline.diff
@@ -2,59 +2,47 @@
 + // MIR for `default` after Inline
   
   fn default() -> () {
-      let mut _0: ();                      // return place in scope 0 at $DIR/inline_instruction_set.rs:+0:18: +0:18
-      let _1: ();                          // in scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
-      let _2: ();                          // in scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
-      let _3: ();                          // in scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
-      let _4: ();                          // in scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
-+     scope 1 (inlined instruction_set_default) { // at $DIR/inline_instruction_set.rs:59:5: 59:30
+      let mut _0: ();
+      let _1: ();
+      let _2: ();
+      let _3: ();
+      let _4: ();
++     scope 1 (inlined instruction_set_default) {
 +     }
-+     scope 2 (inlined inline_always_and_using_inline_asm) { // at $DIR/inline_instruction_set.rs:60:5: 60:41
++     scope 2 (inlined inline_always_and_using_inline_asm) {
 +         scope 3 {
 +         }
 +     }
   
       bb0: {
-          StorageLive(_1);                 // scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
-          _1 = instruction_set_a32() -> [return: bb1, unwind unreachable]; // scope 0 at $DIR/inline_instruction_set.rs:+1:5: +1:26
-                                           // mir::Constant
-                                           // + span: $DIR/inline_instruction_set.rs:57:5: 57:24
-                                           // + literal: Const { ty: fn() {instruction_set_a32}, val: Value(<ZST>) }
+          StorageLive(_1);
+          _1 = instruction_set_a32() -> [return: bb1, unwind unreachable];
       }
   
       bb1: {
-          StorageDead(_1);                 // scope 0 at $DIR/inline_instruction_set.rs:+1:26: +1:27
-          StorageLive(_2);                 // scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
-          _2 = instruction_set_t32() -> [return: bb2, unwind unreachable]; // scope 0 at $DIR/inline_instruction_set.rs:+2:5: +2:26
-                                           // mir::Constant
-                                           // + span: $DIR/inline_instruction_set.rs:58:5: 58:24
-                                           // + literal: Const { ty: fn() {instruction_set_t32}, val: Value(<ZST>) }
+          StorageDead(_1);
+          StorageLive(_2);
+          _2 = instruction_set_t32() -> [return: bb2, unwind unreachable];
       }
   
       bb2: {
-          StorageDead(_2);                 // scope 0 at $DIR/inline_instruction_set.rs:+2:26: +2:27
-          StorageLive(_3);                 // scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
--         _3 = instruction_set_default() -> [return: bb3, unwind unreachable]; // scope 0 at $DIR/inline_instruction_set.rs:+3:5: +3:30
--                                          // mir::Constant
--                                          // + span: $DIR/inline_instruction_set.rs:59:5: 59:28
--                                          // + literal: Const { ty: fn() {instruction_set_default}, val: Value(<ZST>) }
+          StorageDead(_2);
+          StorageLive(_3);
+-         _3 = instruction_set_default() -> [return: bb3, unwind unreachable];
 -     }
 - 
 -     bb3: {
-          StorageDead(_3);                 // scope 0 at $DIR/inline_instruction_set.rs:+3:30: +3:31
-          StorageLive(_4);                 // scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
--         _4 = inline_always_and_using_inline_asm() -> [return: bb4, unwind unreachable]; // scope 0 at $DIR/inline_instruction_set.rs:+4:5: +4:41
--                                          // mir::Constant
--                                          // + span: $DIR/inline_instruction_set.rs:60:5: 60:39
--                                          // + literal: Const { ty: fn() {inline_always_and_using_inline_asm}, val: Value(<ZST>) }
-+         asm!("/* do nothing */", options((empty))) -> [return: bb3, unwind unreachable]; // scope 3 at $DIR/inline_instruction_set.rs:43:14: 43:38
+          StorageDead(_3);
+          StorageLive(_4);
+-         _4 = inline_always_and_using_inline_asm() -> [return: bb4, unwind unreachable];
++         asm!("/* do nothing */", options((empty))) -> [return: bb3, unwind unreachable];
       }
   
 -     bb4: {
 +     bb3: {
-          StorageDead(_4);                 // scope 0 at $DIR/inline_instruction_set.rs:+4:41: +4:42
-          _0 = const ();                   // scope 0 at $DIR/inline_instruction_set.rs:+0:18: +5:2
-          return;                          // scope 0 at $DIR/inline_instruction_set.rs:+5:2: +5:2
+          StorageDead(_4);
+          _0 = const ();
+          return;
       }
   }
   
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