From 698f8c2f01ea549d77d7dc3338a12e04c11057b9 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Wed, 17 Apr 2024 14:02:58 +0200 Subject: Adding upstream version 1.64.0+dfsg1. Signed-off-by: Daniel Baumann --- vendor/crc32fast/.cargo-checksum.json | 1 + vendor/crc32fast/Cargo.toml | 40 ++ vendor/crc32fast/LICENSE-APACHE | 202 +++++++++ vendor/crc32fast/LICENSE-MIT | 21 + vendor/crc32fast/README.md | 93 ++++ vendor/crc32fast/benches/bench.rs | 53 +++ vendor/crc32fast/build.rs | 35 ++ vendor/crc32fast/src/baseline.rs | 94 ++++ vendor/crc32fast/src/combine.rs | 77 ++++ vendor/crc32fast/src/lib.rs | 235 ++++++++++ vendor/crc32fast/src/specialized/aarch64.rs | 88 ++++ vendor/crc32fast/src/specialized/mod.rs | 37 ++ vendor/crc32fast/src/specialized/pclmulqdq.rs | 225 +++++++++ vendor/crc32fast/src/table.rs | 629 ++++++++++++++++++++++++++ 14 files changed, 1830 insertions(+) create mode 100644 vendor/crc32fast/.cargo-checksum.json create mode 100644 vendor/crc32fast/Cargo.toml create mode 100644 vendor/crc32fast/LICENSE-APACHE create mode 100644 vendor/crc32fast/LICENSE-MIT create mode 100644 vendor/crc32fast/README.md create mode 100644 vendor/crc32fast/benches/bench.rs create mode 100644 vendor/crc32fast/build.rs create mode 100644 vendor/crc32fast/src/baseline.rs create mode 100644 vendor/crc32fast/src/combine.rs create mode 100644 vendor/crc32fast/src/lib.rs create mode 100644 vendor/crc32fast/src/specialized/aarch64.rs create mode 100644 vendor/crc32fast/src/specialized/mod.rs create mode 100644 vendor/crc32fast/src/specialized/pclmulqdq.rs create mode 100644 vendor/crc32fast/src/table.rs (limited to 'vendor/crc32fast') diff --git a/vendor/crc32fast/.cargo-checksum.json b/vendor/crc32fast/.cargo-checksum.json new file mode 100644 index 000000000..f2f56c55a --- /dev/null +++ b/vendor/crc32fast/.cargo-checksum.json @@ -0,0 +1 @@ +{"files":{"Cargo.toml":"be80bad9c3fe51a936b76e4ea82cdb13afb747f445e642280996f110ed584517","LICENSE-APACHE":"c6596eb7be8581c18be736c846fb9173b69eccf6ef94c5135893ec56bd92ba08","LICENSE-MIT":"61d383b05b87d78f94d2937e2580cce47226d17823c0430fbcad09596537efcf","README.md":"4b1a2bfbbda9923f78565bd52bd68cd172a188482061b0d2d159ff1a3b57127d","benches/bench.rs":"fb71f17c9f472d0985aead2c71e4ac4f717e5a1eeedc2fbfe75de8709033542d","build.rs":"4ccc50c3da67eb27f0b622440d2b7aee2f73fa9c71884571f3c041122231d105","src/baseline.rs":"bbe8fe49ceccbf9749052fa9c2756cf95f0fc79a063e5d3b509e3600283464ea","src/combine.rs":"7147fc4002190d36d253ea5e194e0419035b087304bcb17887efe09a8a198815","src/lib.rs":"5543027ec0594dd7cb9d67010912871b50d96ca1d255bc527ec9d01cabfc849a","src/specialized/aarch64.rs":"537c316b2e313421b7075e545d52ef1a32d6fe29808575742006247c6a4628f8","src/specialized/mod.rs":"267634816329f32d95b66e2fcc1a8eca6652334bddd454446f4d78b66470b06d","src/specialized/pclmulqdq.rs":"90ef05b5044eaeea736c6877e60820d6c5abfb90759e40fc81b9cc8feb36e96b","src/table.rs":"1a566a6311b32b654fa05b324301611e0866b10db63692b53e8c1b9b529d4c17"},"package":"b540bd8bc810d3885c6ea91e2018302f68baba2129ab3e88f32389ee9370880d"} \ No newline at end of file diff --git a/vendor/crc32fast/Cargo.toml b/vendor/crc32fast/Cargo.toml new file mode 100644 index 000000000..79c0b04b3 --- /dev/null +++ b/vendor/crc32fast/Cargo.toml @@ -0,0 +1,40 @@ +# THIS FILE IS AUTOMATICALLY GENERATED BY CARGO +# +# When uploading crates to the registry Cargo will automatically +# "normalize" Cargo.toml files for maximal compatibility +# with all versions of Cargo and also rewrite `path` dependencies +# to registry (e.g., crates.io) dependencies. +# +# If you are reading this file be aware that the original Cargo.toml +# will likely look very different (and much more reasonable). +# See Cargo.toml.orig for the original contents. + +[package] +name = "crc32fast" +version = "1.3.2" +authors = ["Sam Rijs ", "Alex Crichton "] +description = "Fast, SIMD-accelerated CRC32 (IEEE) checksum computation" +readme = "README.md" +keywords = ["checksum", "crc", "crc32", "simd", "fast"] +license = "MIT OR Apache-2.0" +repository = "https://github.com/srijs/rust-crc32fast" + +[[bench]] +name = "bench" +harness = false +[dependencies.cfg-if] +version = "1.0" +[dev-dependencies.bencher] +version = "0.1" + +[dev-dependencies.quickcheck] +version = "1.0" +default-features = false + +[dev-dependencies.rand] +version = "0.8" + +[features] +default = ["std"] +nightly = [] +std = [] diff --git a/vendor/crc32fast/LICENSE-APACHE b/vendor/crc32fast/LICENSE-APACHE new file mode 100644 index 000000000..8f71f43fe --- /dev/null +++ b/vendor/crc32fast/LICENSE-APACHE @@ -0,0 +1,202 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/vendor/crc32fast/README.md b/vendor/crc32fast/README.md new file mode 100644 index 000000000..b0a4827e5 --- /dev/null +++ b/vendor/crc32fast/README.md @@ -0,0 +1,93 @@ +# crc32fast [![Build Status][travis-img]][travis] [![Crates.io][crates-img]][crates] [![Documentation][docs-img]][docs] + +[travis-img]: https://travis-ci.com/srijs/rust-crc32fast.svg?branch=master +[travis]: https://travis-ci.com/srijs/rust-crc32fast +[crates-img]: https://img.shields.io/crates/v/crc32fast.svg +[crates]: https://crates.io/crates/crc32fast +[docs-img]: https://docs.rs/crc32fast/badge.svg +[docs]: https://docs.rs/crc32fast + +_Fast, SIMD-accelerated CRC32 (IEEE) checksum computation_ + +## Usage + +### Simple usage + +For simple use-cases, you can call the `hash` convenience function to +directly compute the CRC32 checksum for a given byte slice: + +```rust +let checksum = crc32fast::hash(b"foo bar baz"); +``` + +### Advanced usage + +For use-cases that require more flexibility or performance, for example when +processing large amounts of data, you can create and manipulate a `Hasher`: + +```rust +use crc32fast::Hasher; + +let mut hasher = Hasher::new(); +hasher.update(b"foo bar baz"); +let checksum = hasher.finalize(); +``` + +## Performance + +This crate contains multiple CRC32 implementations: + +- A fast baseline implementation which processes up to 16 bytes per iteration +- An optimized implementation for modern `x86` using `sse` and `pclmulqdq` instructions +- An optimized implementation for `aarch64` using `crc32` instructions + +Calling the `Hasher::new` constructor at runtime will perform a feature detection to select the most +optimal implementation for the current CPU feature set. + +| crate | version | variant | ns/iter | MB/s | +| ----------------------------------- | ------- | --------- | ------- | ---- | +| [crc](https://crates.io/crates/crc) | 1.8.1 | n/a | 4,926 | 207 | +| crc32fast (this crate) | 1.0.0 | baseline | 683 | 1499 | +| crc32fast (this crate) | 1.0.0 | pclmulqdq | 140 | 7314 | + +## Memory Safety + +Due to the use of SIMD intrinsics for the optimized implementations, this crate contains some amount of `unsafe` code. + +In order to ensure memory safety, the relevant code has been fuzz tested using [afl.rs](https://github.com/rust-fuzz/afl.rs) with millions of iterations in both `debug` and `release` build settings. You can inspect the test setup in the `fuzz` sub-directory, which also has instructions on how to run the tests yourself. + +On top of that, every commit is tested using an address sanitizer in CI to catch any out of bounds memory accesses. + +Even though neither fuzzing nor sanitization has revealed any safety bugs yet, please don't hesitate to file an issue if you run into any crashes or other unexpected behaviour. + +## Available feature flags + +### `std` (default: enabled) + +This library supports being built without the Rust `std` library, which is useful for low-level use-cases such as embedded where no operating system is available. To build the crate in a `no_std` context, disable the default `std` feature. + +Note: Because runtime CPU feature detection requires OS support, the specialized SIMD implementations will be unavailable when the `std` feature is disabled. + +### `nightly` (default: disabled) + +This feature flag enables unstable features that are only available on the `nightly` channel. Keep in mind that when enabling this feature flag, you +might experience breaking changes when updating compiler versions. + +Currently, enabling this feature flag will make the optimized `aarch64` implementation available. + +## License + +This project is licensed under either of + +- Apache License, Version 2.0, ([LICENSE-APACHE](LICENSE-APACHE) or + http://www.apache.org/licenses/LICENSE-2.0) +- MIT license ([LICENSE-MIT](LICENSE-MIT) or + http://opensource.org/licenses/MIT) + +at your option. + +### Contribution + +Unless you explicitly state otherwise, any contribution intentionally submitted +for inclusion in this project by you, as defined in the Apache-2.0 license, +shall be dual licensed as above, without any additional terms or conditions. diff --git a/vendor/crc32fast/benches/bench.rs b/vendor/crc32fast/benches/bench.rs new file mode 100644 index 000000000..53b3d838e --- /dev/null +++ b/vendor/crc32fast/benches/bench.rs @@ -0,0 +1,53 @@ +#[macro_use] +extern crate bencher; +extern crate crc32fast; +extern crate rand; + +use bencher::Bencher; +use crc32fast::Hasher; +use rand::Rng; + +fn bench(b: &mut Bencher, size: usize, hasher_init: Hasher) { + let mut bytes = vec![0u8; size]; + rand::thread_rng().fill(&mut bytes[..]); + + b.iter(|| { + let mut hasher = hasher_init.clone(); + hasher.update(&bytes); + bencher::black_box(hasher.finalize()) + }); + + b.bytes = size as u64; +} + +fn bench_kilobyte_baseline(b: &mut Bencher) { + bench(b, 1024, Hasher::internal_new_baseline(0, 0)) +} + +fn bench_kilobyte_specialized(b: &mut Bencher) { + bench(b, 1024, Hasher::internal_new_specialized(0, 0).unwrap()) +} + +fn bench_megabyte_baseline(b: &mut Bencher) { + bench(b, 1024 * 1024, Hasher::internal_new_baseline(0, 0)) +} + +fn bench_megabyte_specialized(b: &mut Bencher) { + bench( + b, + 1024 * 1024, + Hasher::internal_new_specialized(0, 0).unwrap(), + ) +} + +benchmark_group!( + bench_baseline, + bench_kilobyte_baseline, + bench_megabyte_baseline +); +benchmark_group!( + bench_specialized, + bench_kilobyte_specialized, + bench_megabyte_specialized +); +benchmark_main!(bench_baseline, bench_specialized); diff --git a/vendor/crc32fast/build.rs b/vendor/crc32fast/build.rs new file mode 100644 index 000000000..563cb2173 --- /dev/null +++ b/vendor/crc32fast/build.rs @@ -0,0 +1,35 @@ +use std::env; +use std::process::Command; +use std::str; + +fn main() { + println!("cargo:rerun-if-changed=build.rs"); + + let minor = match rustc_minor_version() { + Some(n) => n, + None => return, + }; + + if minor >= 27 { + println!("cargo:rustc-cfg=crc32fast_stdarchx86"); + } +} + +fn rustc_minor_version() -> Option { + macro_rules! otry { + ($e:expr) => { + match $e { + Some(e) => e, + None => return None, + } + }; + } + let rustc = otry!(env::var_os("RUSTC")); + let output = otry!(Command::new(rustc).arg("--version").output().ok()); + let version = otry!(str::from_utf8(&output.stdout).ok()); + let mut pieces = version.split('.'); + if pieces.next() != Some("rustc 1") { + return None; + } + otry!(pieces.next()).parse().ok() +} diff --git a/vendor/crc32fast/src/baseline.rs b/vendor/crc32fast/src/baseline.rs new file mode 100644 index 000000000..fbc4136ba --- /dev/null +++ b/vendor/crc32fast/src/baseline.rs @@ -0,0 +1,94 @@ +use table::CRC32_TABLE; + +#[derive(Clone)] +pub struct State { + state: u32, +} + +impl State { + pub fn new(state: u32) -> Self { + State { state } + } + + pub fn update(&mut self, buf: &[u8]) { + self.state = update_fast_16(self.state, buf); + } + + pub fn finalize(self) -> u32 { + self.state + } + + pub fn reset(&mut self) { + self.state = 0; + } + + pub fn combine(&mut self, other: u32, amount: u64) { + self.state = ::combine::combine(self.state, other, amount); + } +} + +pub(crate) fn update_fast_16(prev: u32, mut buf: &[u8]) -> u32 { + const UNROLL: usize = 4; + const BYTES_AT_ONCE: usize = 16 * UNROLL; + + let mut crc = !prev; + + while buf.len() >= BYTES_AT_ONCE { + for _ in 0..UNROLL { + crc = CRC32_TABLE[0x0][buf[0xf] as usize] + ^ CRC32_TABLE[0x1][buf[0xe] as usize] + ^ CRC32_TABLE[0x2][buf[0xd] as usize] + ^ CRC32_TABLE[0x3][buf[0xc] as usize] + ^ CRC32_TABLE[0x4][buf[0xb] as usize] + ^ CRC32_TABLE[0x5][buf[0xa] as usize] + ^ CRC32_TABLE[0x6][buf[0x9] as usize] + ^ CRC32_TABLE[0x7][buf[0x8] as usize] + ^ CRC32_TABLE[0x8][buf[0x7] as usize] + ^ CRC32_TABLE[0x9][buf[0x6] as usize] + ^ CRC32_TABLE[0xa][buf[0x5] as usize] + ^ CRC32_TABLE[0xb][buf[0x4] as usize] + ^ CRC32_TABLE[0xc][buf[0x3] as usize ^ ((crc >> 0x18) & 0xFF) as usize] + ^ CRC32_TABLE[0xd][buf[0x2] as usize ^ ((crc >> 0x10) & 0xFF) as usize] + ^ CRC32_TABLE[0xe][buf[0x1] as usize ^ ((crc >> 0x08) & 0xFF) as usize] + ^ CRC32_TABLE[0xf][buf[0x0] as usize ^ ((crc >> 0x00) & 0xFF) as usize]; + buf = &buf[16..]; + } + } + + update_slow(!crc, buf) +} + +pub(crate) fn update_slow(prev: u32, buf: &[u8]) -> u32 { + let mut crc = !prev; + + for &byte in buf.iter() { + crc = CRC32_TABLE[0][((crc as u8) ^ byte) as usize] ^ (crc >> 8); + } + + !crc +} + +#[cfg(test)] +mod test { + #[test] + fn slow() { + assert_eq!(super::update_slow(0, b""), 0); + + // test vectors from the iPXE project (input and output are bitwise negated) + assert_eq!(super::update_slow(!0x12345678, b""), !0x12345678); + assert_eq!(super::update_slow(!0xffffffff, b"hello world"), !0xf2b5ee7a); + assert_eq!(super::update_slow(!0xffffffff, b"hello"), !0xc9ef5979); + assert_eq!(super::update_slow(!0xc9ef5979, b" world"), !0xf2b5ee7a); + + // Some vectors found on Rosetta code + assert_eq!(super::update_slow(0, b"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"), 0x190A55AD); + assert_eq!(super::update_slow(0, b"\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF\xFF"), 0xFF6CAB0B); + assert_eq!(super::update_slow(0, b"\x00\x01\x02\x03\x04\x05\x06\x07\x08\x09\x0A\x0B\x0C\x0D\x0E\x0F\x10\x11\x12\x13\x14\x15\x16\x17\x18\x19\x1A\x1B\x1C\x1D\x1E\x1F"), 0x91267E8A); + } + + quickcheck! { + fn fast_16_is_the_same_as_slow(crc: u32, bytes: Vec) -> bool { + super::update_fast_16(crc, &bytes) == super::update_slow(crc, &bytes) + } + } +} diff --git a/vendor/crc32fast/src/combine.rs b/vendor/crc32fast/src/combine.rs new file mode 100644 index 000000000..4dd0ee065 --- /dev/null +++ b/vendor/crc32fast/src/combine.rs @@ -0,0 +1,77 @@ +const GF2_DIM: usize = 32; + +fn gf2_matrix_times(mat: &[u32; GF2_DIM], mut vec: u32) -> u32 { + let mut sum = 0; + let mut idx = 0; + while vec > 0 { + if vec & 1 == 1 { + sum ^= mat[idx]; + } + vec >>= 1; + idx += 1; + } + return sum; +} + +fn gf2_matrix_square(square: &mut [u32; GF2_DIM], mat: &[u32; GF2_DIM]) { + for n in 0..GF2_DIM { + square[n] = gf2_matrix_times(mat, mat[n]); + } +} + +pub(crate) fn combine(mut crc1: u32, crc2: u32, mut len2: u64) -> u32 { + let mut row: u32; + let mut even = [0u32; GF2_DIM]; /* even-power-of-two zeros operator */ + let mut odd = [0u32; GF2_DIM]; /* odd-power-of-two zeros operator */ + + /* degenerate case (also disallow negative lengths) */ + if len2 <= 0 { + return crc1; + } + + /* put operator for one zero bit in odd */ + odd[0] = 0xedb88320; /* CRC-32 polynomial */ + row = 1; + for n in 1..GF2_DIM { + odd[n] = row; + row <<= 1; + } + + /* put operator for two zero bits in even */ + gf2_matrix_square(&mut even, &odd); + + /* put operator for four zero bits in odd */ + gf2_matrix_square(&mut odd, &even); + + /* apply len2 zeros to crc1 (first square will put the operator for one + zero byte, eight zero bits, in even) */ + loop { + /* apply zeros operator for this bit of len2 */ + gf2_matrix_square(&mut even, &odd); + if len2 & 1 == 1 { + crc1 = gf2_matrix_times(&even, crc1); + } + len2 >>= 1; + + /* if no more bits set, then done */ + if len2 == 0 { + break; + } + + /* another iteration of the loop with odd and even swapped */ + gf2_matrix_square(&mut odd, &even); + if len2 & 1 == 1 { + crc1 = gf2_matrix_times(&odd, crc1); + } + len2 >>= 1; + + /* if no more bits set, then done */ + if len2 == 0 { + break; + } + } + + /* return combined crc */ + crc1 ^= crc2; + return crc1; +} diff --git a/vendor/crc32fast/src/lib.rs b/vendor/crc32fast/src/lib.rs new file mode 100644 index 000000000..8c4f9a90a --- /dev/null +++ b/vendor/crc32fast/src/lib.rs @@ -0,0 +1,235 @@ +//! Fast, SIMD-accelerated CRC32 (IEEE) checksum computation. +//! +//! ## Usage +//! +//! ### Simple usage +//! +//! For simple use-cases, you can call the [`hash()`] convenience function to +//! directly compute the CRC32 checksum for a given byte slice: +//! +//! ```rust +//! let checksum = crc32fast::hash(b"foo bar baz"); +//! ``` +//! +//! ### Advanced usage +//! +//! For use-cases that require more flexibility or performance, for example when +//! processing large amounts of data, you can create and manipulate a [`Hasher`]: +//! +//! ```rust +//! use crc32fast::Hasher; +//! +//! let mut hasher = Hasher::new(); +//! hasher.update(b"foo bar baz"); +//! let checksum = hasher.finalize(); +//! ``` +//! +//! ## Performance +//! +//! This crate contains multiple CRC32 implementations: +//! +//! - A fast baseline implementation which processes up to 16 bytes per iteration +//! - An optimized implementation for modern `x86` using `sse` and `pclmulqdq` instructions +//! +//! Calling the [`Hasher::new`] constructor at runtime will perform a feature detection to select the most +//! optimal implementation for the current CPU feature set. + +#![cfg_attr(not(feature = "std"), no_std)] +#![cfg_attr( + all(feature = "nightly", target_arch = "aarch64"), + feature(stdsimd, aarch64_target_feature) +)] + +#[deny(missing_docs)] +#[cfg(test)] +#[macro_use] +extern crate quickcheck; + +#[macro_use] +extern crate cfg_if; + +#[cfg(feature = "std")] +use std as core; + +use core::fmt; +use core::hash; + +mod baseline; +mod combine; +mod specialized; +mod table; + +/// Computes the CRC32 hash of a byte slice. +/// +/// Check out [`Hasher`] for more advanced use-cases. +pub fn hash(buf: &[u8]) -> u32 { + let mut h = Hasher::new(); + h.update(buf); + h.finalize() +} + +#[derive(Clone)] +enum State { + Baseline(baseline::State), + Specialized(specialized::State), +} + +#[derive(Clone)] +/// Represents an in-progress CRC32 computation. +pub struct Hasher { + amount: u64, + state: State, +} + +const DEFAULT_INIT_STATE: u32 = 0; + +impl Hasher { + /// Create a new `Hasher`. + /// + /// This will perform a CPU feature detection at runtime to select the most + /// optimal implementation for the current processor architecture. + pub fn new() -> Self { + Self::new_with_initial(DEFAULT_INIT_STATE) + } + + /// Create a new `Hasher` with an initial CRC32 state. + /// + /// This works just like `Hasher::new`, except that it allows for an initial + /// CRC32 state to be passed in. + pub fn new_with_initial(init: u32) -> Self { + Self::new_with_initial_len(init, 0) + } + + /// Create a new `Hasher` with an initial CRC32 state. + /// + /// As `new_with_initial`, but also accepts a length (in bytes). The + /// resulting object can then be used with `combine` to compute `crc(a || + /// b)` from `crc(a)`, `crc(b)`, and `len(b)`. + pub fn new_with_initial_len(init: u32, amount: u64) -> Self { + Self::internal_new_specialized(init, amount) + .unwrap_or_else(|| Self::internal_new_baseline(init, amount)) + } + + #[doc(hidden)] + // Internal-only API. Don't use. + pub fn internal_new_baseline(init: u32, amount: u64) -> Self { + Hasher { + amount, + state: State::Baseline(baseline::State::new(init)), + } + } + + #[doc(hidden)] + // Internal-only API. Don't use. + pub fn internal_new_specialized(init: u32, amount: u64) -> Option { + { + if let Some(state) = specialized::State::new(init) { + return Some(Hasher { + amount, + state: State::Specialized(state), + }); + } + } + None + } + + /// Process the given byte slice and update the hash state. + pub fn update(&mut self, buf: &[u8]) { + self.amount += buf.len() as u64; + match self.state { + State::Baseline(ref mut state) => state.update(buf), + State::Specialized(ref mut state) => state.update(buf), + } + } + + /// Finalize the hash state and return the computed CRC32 value. + pub fn finalize(self) -> u32 { + match self.state { + State::Baseline(state) => state.finalize(), + State::Specialized(state) => state.finalize(), + } + } + + /// Reset the hash state. + pub fn reset(&mut self) { + self.amount = 0; + match self.state { + State::Baseline(ref mut state) => state.reset(), + State::Specialized(ref mut state) => state.reset(), + } + } + + /// Combine the hash state with the hash state for the subsequent block of bytes. + pub fn combine(&mut self, other: &Self) { + self.amount += other.amount; + let other_crc = other.clone().finalize(); + match self.state { + State::Baseline(ref mut state) => state.combine(other_crc, other.amount), + State::Specialized(ref mut state) => state.combine(other_crc, other.amount), + } + } +} + +impl fmt::Debug for Hasher { + fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { + f.debug_struct("crc32fast::Hasher").finish() + } +} + +impl Default for Hasher { + fn default() -> Self { + Self::new() + } +} + +impl hash::Hasher for Hasher { + fn write(&mut self, bytes: &[u8]) { + self.update(bytes) + } + + fn finish(&self) -> u64 { + u64::from(self.clone().finalize()) + } +} + +#[cfg(test)] +mod test { + use super::Hasher; + + quickcheck! { + fn combine(bytes_1: Vec, bytes_2: Vec) -> bool { + let mut hash_a = Hasher::new(); + hash_a.update(&bytes_1); + hash_a.update(&bytes_2); + let mut hash_b = Hasher::new(); + hash_b.update(&bytes_2); + let mut hash_c = Hasher::new(); + hash_c.update(&bytes_1); + hash_c.combine(&hash_b); + + hash_a.finalize() == hash_c.finalize() + } + + fn combine_from_len(bytes_1: Vec, bytes_2: Vec) -> bool { + let mut hash_a = Hasher::new(); + hash_a.update(&bytes_1); + let a = hash_a.finalize(); + + let mut hash_b = Hasher::new(); + hash_b.update(&bytes_2); + let b = hash_b.finalize(); + + let mut hash_ab = Hasher::new(); + hash_ab.update(&bytes_1); + hash_ab.update(&bytes_2); + let ab = hash_ab.finalize(); + + let mut reconstructed = Hasher::new_with_initial_len(a, bytes_1.len() as u64); + let hash_b_reconstructed = Hasher::new_with_initial_len(b, bytes_2.len() as u64); + + reconstructed.combine(&hash_b_reconstructed); + + reconstructed.finalize() == ab + } + } +} diff --git a/vendor/crc32fast/src/specialized/aarch64.rs b/vendor/crc32fast/src/specialized/aarch64.rs new file mode 100644 index 000000000..49de6b056 --- /dev/null +++ b/vendor/crc32fast/src/specialized/aarch64.rs @@ -0,0 +1,88 @@ +use std::arch::aarch64 as arch; + +#[derive(Clone)] +pub struct State { + state: u32, +} + +impl State { + pub fn new(state: u32) -> Option { + if std::arch::is_aarch64_feature_detected!("crc") { + // SAFETY: The conditions above ensure that all + // required instructions are supported by the CPU. + Some(Self { state }) + } else { + None + } + } + + pub fn update(&mut self, buf: &[u8]) { + // SAFETY: The `State::new` constructor ensures that all + // required instructions are supported by the CPU. + self.state = unsafe { calculate(self.state, buf) } + } + + pub fn finalize(self) -> u32 { + self.state + } + + pub fn reset(&mut self) { + self.state = 0; + } + + pub fn combine(&mut self, other: u32, amount: u64) { + self.state = ::combine::combine(self.state, other, amount); + } +} + +// target_feature is necessary to allow rustc to inline the crc32* wrappers +#[target_feature(enable = "crc")] +pub unsafe fn calculate(crc: u32, data: &[u8]) -> u32 { + let mut c32 = !crc; + let (pre_quad, quads, post_quad) = data.align_to::(); + + c32 = pre_quad.iter().fold(c32, |acc, &b| arch::__crc32b(acc, b)); + + // unrolling increases performance by a lot + let mut quad_iter = quads.chunks_exact(8); + for chunk in &mut quad_iter { + c32 = arch::__crc32d(c32, chunk[0]); + c32 = arch::__crc32d(c32, chunk[1]); + c32 = arch::__crc32d(c32, chunk[2]); + c32 = arch::__crc32d(c32, chunk[3]); + c32 = arch::__crc32d(c32, chunk[4]); + c32 = arch::__crc32d(c32, chunk[5]); + c32 = arch::__crc32d(c32, chunk[6]); + c32 = arch::__crc32d(c32, chunk[7]); + } + c32 = quad_iter + .remainder() + .iter() + .fold(c32, |acc, &q| arch::__crc32d(acc, q)); + + c32 = post_quad.iter().fold(c32, |acc, &b| arch::__crc32b(acc, b)); + + !c32 +} + +#[cfg(test)] +mod test { + quickcheck! { + fn check_against_baseline(init: u32, chunks: Vec<(Vec, usize)>) -> bool { + let mut baseline = super::super::super::baseline::State::new(init); + let mut aarch64 = super::State::new(init).expect("not supported"); + for (chunk, mut offset) in chunks { + // simulate random alignments by offsetting the slice by up to 15 bytes + offset &= 0xF; + if chunk.len() <= offset { + baseline.update(&chunk); + aarch64.update(&chunk); + } else { + baseline.update(&chunk[offset..]); + aarch64.update(&chunk[offset..]); + } + } + aarch64.finalize() == baseline.finalize() + } + } +} diff --git a/vendor/crc32fast/src/specialized/mod.rs b/vendor/crc32fast/src/specialized/mod.rs new file mode 100644 index 000000000..525a42c85 --- /dev/null +++ b/vendor/crc32fast/src/specialized/mod.rs @@ -0,0 +1,37 @@ +cfg_if! { + if #[cfg(all( + crc32fast_stdarchx86, + target_feature = "sse2", + any(target_arch = "x86", target_arch = "x86_64") + ))] { + mod pclmulqdq; + pub use self::pclmulqdq::State; + } else if #[cfg(all(feature = "nightly", target_arch = "aarch64"))] { + mod aarch64; + pub use self::aarch64::State; + } else { + #[derive(Clone)] + pub enum State {} + impl State { + pub fn new(_: u32) -> Option { + None + } + + pub fn update(&mut self, _buf: &[u8]) { + match *self {} + } + + pub fn finalize(self) -> u32 { + match self{} + } + + pub fn reset(&mut self) { + match *self {} + } + + pub fn combine(&mut self, _other: u32, _amount: u64) { + match *self {} + } + } + } +} diff --git a/vendor/crc32fast/src/specialized/pclmulqdq.rs b/vendor/crc32fast/src/specialized/pclmulqdq.rs new file mode 100644 index 000000000..84a60cab1 --- /dev/null +++ b/vendor/crc32fast/src/specialized/pclmulqdq.rs @@ -0,0 +1,225 @@ +#[cfg(target_arch = "x86")] +use core::arch::x86 as arch; +#[cfg(target_arch = "x86_64")] +use core::arch::x86_64 as arch; + +#[derive(Clone)] +pub struct State { + state: u32, +} + +impl State { + #[cfg(not(feature = "std"))] + pub fn new(state: u32) -> Option { + if cfg!(target_feature = "pclmulqdq") + && cfg!(target_feature = "sse2") + && cfg!(target_feature = "sse4.1") + { + // SAFETY: The conditions above ensure that all + // required instructions are supported by the CPU. + Some(Self { state }) + } else { + None + } + } + + #[cfg(feature = "std")] + pub fn new(state: u32) -> Option { + if is_x86_feature_detected!("pclmulqdq") + && is_x86_feature_detected!("sse2") + && is_x86_feature_detected!("sse4.1") + { + // SAFETY: The conditions above ensure that all + // required instructions are supported by the CPU. + Some(Self { state }) + } else { + None + } + } + + pub fn update(&mut self, buf: &[u8]) { + // SAFETY: The `State::new` constructor ensures that all + // required instructions are supported by the CPU. + self.state = unsafe { calculate(self.state, buf) } + } + + pub fn finalize(self) -> u32 { + self.state + } + + pub fn reset(&mut self) { + self.state = 0; + } + + pub fn combine(&mut self, other: u32, amount: u64) { + self.state = ::combine::combine(self.state, other, amount); + } +} + +const K1: i64 = 0x154442bd4; +const K2: i64 = 0x1c6e41596; +const K3: i64 = 0x1751997d0; +const K4: i64 = 0x0ccaa009e; +const K5: i64 = 0x163cd6124; +const K6: i64 = 0x1db710640; + +const P_X: i64 = 0x1DB710641; +const U_PRIME: i64 = 0x1F7011641; + +#[cfg(feature = "std")] +unsafe fn debug(s: &str, a: arch::__m128i) -> arch::__m128i { + if false { + union A { + a: arch::__m128i, + b: [u8; 16], + } + let x = A { a }.b; + print!(" {:20} | ", s); + for x in x.iter() { + print!("{:02x} ", x); + } + println!(); + } + return a; +} + +#[cfg(not(feature = "std"))] +unsafe fn debug(_s: &str, a: arch::__m128i) -> arch::__m128i { + a +} + +#[target_feature(enable = "pclmulqdq", enable = "sse2", enable = "sse4.1")] +unsafe fn calculate(crc: u32, mut data: &[u8]) -> u32 { + // In theory we can accelerate smaller chunks too, but for now just rely on + // the fallback implementation as it's too much hassle and doesn't seem too + // beneficial. + if data.len() < 128 { + return ::baseline::update_fast_16(crc, data); + } + + // Step 1: fold by 4 loop + let mut x3 = get(&mut data); + let mut x2 = get(&mut data); + let mut x1 = get(&mut data); + let mut x0 = get(&mut data); + + // fold in our initial value, part of the incremental crc checksum + x3 = arch::_mm_xor_si128(x3, arch::_mm_cvtsi32_si128(!crc as i32)); + + let k1k2 = arch::_mm_set_epi64x(K2, K1); + while data.len() >= 64 { + x3 = reduce128(x3, get(&mut data), k1k2); + x2 = reduce128(x2, get(&mut data), k1k2); + x1 = reduce128(x1, get(&mut data), k1k2); + x0 = reduce128(x0, get(&mut data), k1k2); + } + + let k3k4 = arch::_mm_set_epi64x(K4, K3); + let mut x = reduce128(x3, x2, k3k4); + x = reduce128(x, x1, k3k4); + x = reduce128(x, x0, k3k4); + + // Step 2: fold by 1 loop + while data.len() >= 16 { + x = reduce128(x, get(&mut data), k3k4); + } + + debug("128 > 64 init", x); + + // Perform step 3, reduction from 128 bits to 64 bits. This is + // significantly different from the paper and basically doesn't follow it + // at all. It's not really clear why, but implementations of this algorithm + // in Chrome/Linux diverge in the same way. It is beyond me why this is + // different than the paper, maybe the paper has like errata or something? + // Unclear. + // + // It's also not clear to me what's actually happening here and/or why, but + // algebraically what's happening is: + // + // x = (x[0:63] • K4) ^ x[64:127] // 96 bit result + // x = ((x[0:31] as u64) • K5) ^ x[32:95] // 64 bit result + // + // It's... not clear to me what's going on here. The paper itself is pretty + // vague on this part but definitely uses different constants at least. + // It's not clear to me, reading the paper, where the xor operations are + // happening or why things are shifting around. This implementation... + // appears to work though! + drop(K6); + let x = arch::_mm_xor_si128( + arch::_mm_clmulepi64_si128(x, k3k4, 0x10), + arch::_mm_srli_si128(x, 8), + ); + let x = arch::_mm_xor_si128( + arch::_mm_clmulepi64_si128( + arch::_mm_and_si128(x, arch::_mm_set_epi32(0, 0, 0, !0)), + arch::_mm_set_epi64x(0, K5), + 0x00, + ), + arch::_mm_srli_si128(x, 4), + ); + debug("128 > 64 xx", x); + + // Perform a Barrett reduction from our now 64 bits to 32 bits. The + // algorithm for this is described at the end of the paper, and note that + // this also implements the "bit reflected input" variant. + let pu = arch::_mm_set_epi64x(U_PRIME, P_X); + + // T1(x) = ⌊(R(x) % x^32)⌋ • μ + let t1 = arch::_mm_clmulepi64_si128( + arch::_mm_and_si128(x, arch::_mm_set_epi32(0, 0, 0, !0)), + pu, + 0x10, + ); + // T2(x) = ⌊(T1(x) % x^32)⌋ • P(x) + let t2 = arch::_mm_clmulepi64_si128( + arch::_mm_and_si128(t1, arch::_mm_set_epi32(0, 0, 0, !0)), + pu, + 0x00, + ); + // We're doing the bit-reflected variant, so get the upper 32-bits of the + // 64-bit result instead of the lower 32-bits. + // + // C(x) = R(x) ^ T2(x) / x^32 + let c = arch::_mm_extract_epi32(arch::_mm_xor_si128(x, t2), 1) as u32; + + if !data.is_empty() { + ::baseline::update_fast_16(!c, data) + } else { + !c + } +} + +unsafe fn reduce128(a: arch::__m128i, b: arch::__m128i, keys: arch::__m128i) -> arch::__m128i { + let t1 = arch::_mm_clmulepi64_si128(a, keys, 0x00); + let t2 = arch::_mm_clmulepi64_si128(a, keys, 0x11); + arch::_mm_xor_si128(arch::_mm_xor_si128(b, t1), t2) +} + +unsafe fn get(a: &mut &[u8]) -> arch::__m128i { + debug_assert!(a.len() >= 16); + let r = arch::_mm_loadu_si128(a.as_ptr() as *const arch::__m128i); + *a = &a[16..]; + return r; +} + +#[cfg(test)] +mod test { + quickcheck! { + fn check_against_baseline(init: u32, chunks: Vec<(Vec, usize)>) -> bool { + let mut baseline = super::super::super::baseline::State::new(init); + let mut pclmulqdq = super::State::new(init).expect("not supported"); + for (chunk, mut offset) in chunks { + // simulate random alignments by offsetting the slice by up to 15 bytes + offset &= 0xF; + if chunk.len() <= offset { + baseline.update(&chunk); + pclmulqdq.update(&chunk); + } else { + baseline.update(&chunk[offset..]); + pclmulqdq.update(&chunk[offset..]); + } + } + pclmulqdq.finalize() == baseline.finalize() + } + } +} diff --git a/vendor/crc32fast/src/table.rs b/vendor/crc32fast/src/table.rs new file mode 100644 index 000000000..78b89c321 --- /dev/null +++ b/vendor/crc32fast/src/table.rs @@ -0,0 +1,629 @@ +// NOTE: This is static instead of const to ensure that indexing into this table +// doesn't result in large memmoves when in debug mode, which can significantly +// impact performance. +pub static CRC32_TABLE: [[u32; 256]; 16] = [ + [ + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, + 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, + 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, + 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, + 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, + 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, + 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, 0x26d930ac, + 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, + 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, + 0xb6662d3d, 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, + 0x9fbfe4a5, 0xe8b8d433, 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, + 0x086d3d2d, 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, + 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, 0x4db26158, 0x3ab551ce, + 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, + 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, + 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, + 0xce61e49f, 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, + 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 0xead54739, + 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, + 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, 0xf00f9344, 0x8708a3d2, 0x1e01f268, + 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, + 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, + 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, + 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, + 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, + 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, + 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, + 0x0cb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, + 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, 0x88085ae6, + 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, + 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, + 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, + 0x47b2cf7f, 0x30b5ffe9, 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, + 0xcdd70693, 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d, + ], + [ + 0x00000000, 0x191B3141, 0x32366282, 0x2B2D53C3, 0x646CC504, 0x7D77F445, 0x565AA786, + 0x4F4196C7, 0xC8D98A08, 0xD1C2BB49, 0xFAEFE88A, 0xE3F4D9CB, 0xACB54F0C, 0xB5AE7E4D, + 0x9E832D8E, 0x87981CCF, 0x4AC21251, 0x53D92310, 0x78F470D3, 0x61EF4192, 0x2EAED755, + 0x37B5E614, 0x1C98B5D7, 0x05838496, 0x821B9859, 0x9B00A918, 0xB02DFADB, 0xA936CB9A, + 0xE6775D5D, 0xFF6C6C1C, 0xD4413FDF, 0xCD5A0E9E, 0x958424A2, 0x8C9F15E3, 0xA7B24620, + 0xBEA97761, 0xF1E8E1A6, 0xE8F3D0E7, 0xC3DE8324, 0xDAC5B265, 0x5D5DAEAA, 0x44469FEB, + 0x6F6BCC28, 0x7670FD69, 0x39316BAE, 0x202A5AEF, 0x0B07092C, 0x121C386D, 0xDF4636F3, + 0xC65D07B2, 0xED705471, 0xF46B6530, 0xBB2AF3F7, 0xA231C2B6, 0x891C9175, 0x9007A034, + 0x179FBCFB, 0x0E848DBA, 0x25A9DE79, 0x3CB2EF38, 0x73F379FF, 0x6AE848BE, 0x41C51B7D, + 0x58DE2A3C, 0xF0794F05, 0xE9627E44, 0xC24F2D87, 0xDB541CC6, 0x94158A01, 0x8D0EBB40, + 0xA623E883, 0xBF38D9C2, 0x38A0C50D, 0x21BBF44C, 0x0A96A78F, 0x138D96CE, 0x5CCC0009, + 0x45D73148, 0x6EFA628B, 0x77E153CA, 0xBABB5D54, 0xA3A06C15, 0x888D3FD6, 0x91960E97, + 0xDED79850, 0xC7CCA911, 0xECE1FAD2, 0xF5FACB93, 0x7262D75C, 0x6B79E61D, 0x4054B5DE, + 0x594F849F, 0x160E1258, 0x0F152319, 0x243870DA, 0x3D23419B, 0x65FD6BA7, 0x7CE65AE6, + 0x57CB0925, 0x4ED03864, 0x0191AEA3, 0x188A9FE2, 0x33A7CC21, 0x2ABCFD60, 0xAD24E1AF, + 0xB43FD0EE, 0x9F12832D, 0x8609B26C, 0xC94824AB, 0xD05315EA, 0xFB7E4629, 0xE2657768, + 0x2F3F79F6, 0x362448B7, 0x1D091B74, 0x04122A35, 0x4B53BCF2, 0x52488DB3, 0x7965DE70, + 0x607EEF31, 0xE7E6F3FE, 0xFEFDC2BF, 0xD5D0917C, 0xCCCBA03D, 0x838A36FA, 0x9A9107BB, + 0xB1BC5478, 0xA8A76539, 0x3B83984B, 0x2298A90A, 0x09B5FAC9, 0x10AECB88, 0x5FEF5D4F, + 0x46F46C0E, 0x6DD93FCD, 0x74C20E8C, 0xF35A1243, 0xEA412302, 0xC16C70C1, 0xD8774180, + 0x9736D747, 0x8E2DE606, 0xA500B5C5, 0xBC1B8484, 0x71418A1A, 0x685ABB5B, 0x4377E898, + 0x5A6CD9D9, 0x152D4F1E, 0x0C367E5F, 0x271B2D9C, 0x3E001CDD, 0xB9980012, 0xA0833153, + 0x8BAE6290, 0x92B553D1, 0xDDF4C516, 0xC4EFF457, 0xEFC2A794, 0xF6D996D5, 0xAE07BCE9, + 0xB71C8DA8, 0x9C31DE6B, 0x852AEF2A, 0xCA6B79ED, 0xD37048AC, 0xF85D1B6F, 0xE1462A2E, + 0x66DE36E1, 0x7FC507A0, 0x54E85463, 0x4DF36522, 0x02B2F3E5, 0x1BA9C2A4, 0x30849167, + 0x299FA026, 0xE4C5AEB8, 0xFDDE9FF9, 0xD6F3CC3A, 0xCFE8FD7B, 0x80A96BBC, 0x99B25AFD, + 0xB29F093E, 0xAB84387F, 0x2C1C24B0, 0x350715F1, 0x1E2A4632, 0x07317773, 0x4870E1B4, + 0x516BD0F5, 0x7A468336, 0x635DB277, 0xCBFAD74E, 0xD2E1E60F, 0xF9CCB5CC, 0xE0D7848D, + 0xAF96124A, 0xB68D230B, 0x9DA070C8, 0x84BB4189, 0x03235D46, 0x1A386C07, 0x31153FC4, + 0x280E0E85, 0x674F9842, 0x7E54A903, 0x5579FAC0, 0x4C62CB81, 0x8138C51F, 0x9823F45E, + 0xB30EA79D, 0xAA1596DC, 0xE554001B, 0xFC4F315A, 0xD7626299, 0xCE7953D8, 0x49E14F17, + 0x50FA7E56, 0x7BD72D95, 0x62CC1CD4, 0x2D8D8A13, 0x3496BB52, 0x1FBBE891, 0x06A0D9D0, + 0x5E7EF3EC, 0x4765C2AD, 0x6C48916E, 0x7553A02F, 0x3A1236E8, 0x230907A9, 0x0824546A, + 0x113F652B, 0x96A779E4, 0x8FBC48A5, 0xA4911B66, 0xBD8A2A27, 0xF2CBBCE0, 0xEBD08DA1, + 0xC0FDDE62, 0xD9E6EF23, 0x14BCE1BD, 0x0DA7D0FC, 0x268A833F, 0x3F91B27E, 0x70D024B9, + 0x69CB15F8, 0x42E6463B, 0x5BFD777A, 0xDC656BB5, 0xC57E5AF4, 0xEE530937, 0xF7483876, + 0xB809AEB1, 0xA1129FF0, 0x8A3FCC33, 0x9324FD72, + ], + [ + 0x00000000, 0x01C26A37, 0x0384D46E, 0x0246BE59, 0x0709A8DC, 0x06CBC2EB, 0x048D7CB2, + 0x054F1685, 0x0E1351B8, 0x0FD13B8F, 0x0D9785D6, 0x0C55EFE1, 0x091AF964, 0x08D89353, + 0x0A9E2D0A, 0x0B5C473D, 0x1C26A370, 0x1DE4C947, 0x1FA2771E, 0x1E601D29, 0x1B2F0BAC, + 0x1AED619B, 0x18ABDFC2, 0x1969B5F5, 0x1235F2C8, 0x13F798FF, 0x11B126A6, 0x10734C91, + 0x153C5A14, 0x14FE3023, 0x16B88E7A, 0x177AE44D, 0x384D46E0, 0x398F2CD7, 0x3BC9928E, + 0x3A0BF8B9, 0x3F44EE3C, 0x3E86840B, 0x3CC03A52, 0x3D025065, 0x365E1758, 0x379C7D6F, + 0x35DAC336, 0x3418A901, 0x3157BF84, 0x3095D5B3, 0x32D36BEA, 0x331101DD, 0x246BE590, + 0x25A98FA7, 0x27EF31FE, 0x262D5BC9, 0x23624D4C, 0x22A0277B, 0x20E69922, 0x2124F315, + 0x2A78B428, 0x2BBADE1F, 0x29FC6046, 0x283E0A71, 0x2D711CF4, 0x2CB376C3, 0x2EF5C89A, + 0x2F37A2AD, 0x709A8DC0, 0x7158E7F7, 0x731E59AE, 0x72DC3399, 0x7793251C, 0x76514F2B, + 0x7417F172, 0x75D59B45, 0x7E89DC78, 0x7F4BB64F, 0x7D0D0816, 0x7CCF6221, 0x798074A4, + 0x78421E93, 0x7A04A0CA, 0x7BC6CAFD, 0x6CBC2EB0, 0x6D7E4487, 0x6F38FADE, 0x6EFA90E9, + 0x6BB5866C, 0x6A77EC5B, 0x68315202, 0x69F33835, 0x62AF7F08, 0x636D153F, 0x612BAB66, + 0x60E9C151, 0x65A6D7D4, 0x6464BDE3, 0x662203BA, 0x67E0698D, 0x48D7CB20, 0x4915A117, + 0x4B531F4E, 0x4A917579, 0x4FDE63FC, 0x4E1C09CB, 0x4C5AB792, 0x4D98DDA5, 0x46C49A98, + 0x4706F0AF, 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