From 64d98f8ee037282c35007b64c2649055c56af1db Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Wed, 17 Apr 2024 14:19:03 +0200 Subject: Merging upstream version 1.68.2+dfsg1. Signed-off-by: Daniel Baumann --- vendor/packed_simd_2/.cargo-checksum.json | 2 +- vendor/packed_simd_2/Cargo.toml | 43 +-- vendor/packed_simd_2/README.md | 25 +- vendor/packed_simd_2/build.rs | 3 +- .../ci/docker/wasm32-unknown-unknown/Dockerfile | 9 +- vendor/packed_simd_2/contributing.md | 2 +- .../perf-guide/src/target-feature/rustflags.md | 6 +- vendor/packed_simd_2/rustfmt.toml | 4 +- vendor/packed_simd_2/src/api.rs | 4 +- vendor/packed_simd_2/src/api/cast/v128.rs | 297 ++++++++++++++++++--- vendor/packed_simd_2/src/api/cast/v16.rs | 63 ++++- vendor/packed_simd_2/src/api/cast/v256.rs | 297 ++++++++++++++++++--- vendor/packed_simd_2/src/api/cast/v32.rs | 126 ++++++++- vendor/packed_simd_2/src/api/cast/v512.rs | 205 +++++++++++--- vendor/packed_simd_2/src/api/cast/v64.rs | 201 ++++++++++++-- vendor/packed_simd_2/src/api/cmp/partial_eq.rs | 4 +- vendor/packed_simd_2/src/api/cmp/partial_ord.rs | 8 +- vendor/packed_simd_2/src/api/fmt/binary.rs | 4 +- vendor/packed_simd_2/src/api/fmt/debug.rs | 4 +- vendor/packed_simd_2/src/api/fmt/lower_hex.rs | 4 +- vendor/packed_simd_2/src/api/fmt/octal.rs | 4 +- vendor/packed_simd_2/src/api/fmt/upper_hex.rs | 4 +- vendor/packed_simd_2/src/api/into_bits.rs | 4 +- .../src/api/into_bits/arch_specific.rs | 272 +++++++++++++++---- vendor/packed_simd_2/src/api/into_bits/macros.rs | 2 +- vendor/packed_simd_2/src/api/into_bits/v128.rs | 232 +++++++++++++++- vendor/packed_simd_2/src/api/into_bits/v256.rs | 231 +++++++++++++++- vendor/packed_simd_2/src/api/into_bits/v512.rs | 231 +++++++++++++++- vendor/packed_simd_2/src/api/math/float/consts.rs | 36 +-- vendor/packed_simd_2/src/api/ops/scalar_shifts.rs | 7 +- vendor/packed_simd_2/src/api/ops/vector_rotates.rs | 2 + vendor/packed_simd_2/src/api/ops/vector_shifts.rs | 7 +- vendor/packed_simd_2/src/api/ptr/gather_scatter.rs | 21 +- .../src/api/reductions/float_arithmetic.rs | 8 +- .../src/api/reductions/integer_arithmetic.rs | 8 +- vendor/packed_simd_2/src/api/reductions/min_max.rs | 65 ++--- vendor/packed_simd_2/src/api/select.rs | 4 +- vendor/packed_simd_2/src/api/shuffle.rs | 54 ++-- vendor/packed_simd_2/src/api/slice/from_slice.rs | 28 +- .../packed_simd_2/src/api/slice/write_to_slice.rs | 35 +-- vendor/packed_simd_2/src/codegen.rs | 50 ++-- vendor/packed_simd_2/src/codegen/bit_manip.rs | 17 +- vendor/packed_simd_2/src/codegen/llvm.rs | 207 +++++++------- vendor/packed_simd_2/src/codegen/math.rs | 2 +- vendor/packed_simd_2/src/codegen/math/float.rs | 30 +-- vendor/packed_simd_2/src/codegen/math/float/abs.rs | 2 +- vendor/packed_simd_2/src/codegen/math/float/cos.rs | 2 +- .../packed_simd_2/src/codegen/math/float/cos_pi.rs | 2 +- vendor/packed_simd_2/src/codegen/math/float/exp.rs | 2 +- vendor/packed_simd_2/src/codegen/math/float/ln.rs | 2 +- .../packed_simd_2/src/codegen/math/float/macros.rs | 133 ++------- .../src/codegen/math/float/mul_add.rs | 2 +- .../src/codegen/math/float/mul_adde.rs | 10 +- .../packed_simd_2/src/codegen/math/float/powf.rs | 2 +- vendor/packed_simd_2/src/codegen/math/float/sin.rs | 2 +- .../src/codegen/math/float/sin_cos_pi.rs | 23 +- .../packed_simd_2/src/codegen/math/float/sin_pi.rs | 2 +- .../packed_simd_2/src/codegen/math/float/sqrt.rs | 2 +- .../packed_simd_2/src/codegen/math/float/sqrte.rs | 2 +- .../packed_simd_2/src/codegen/math/float/tanh.rs | 8 +- .../packed_simd_2/src/codegen/pointer_sized_int.rs | 24 +- vendor/packed_simd_2/src/codegen/reductions.rs | 2 +- .../packed_simd_2/src/codegen/reductions/mask.rs | 6 +- .../src/codegen/reductions/mask/aarch64.rs | 38 ++- .../src/codegen/reductions/mask/arm.rs | 26 +- .../src/codegen/reductions/mask/fallback.rs | 4 +- .../src/codegen/reductions/mask/x86.rs | 70 +++-- .../src/codegen/reductions/mask/x86/avx.rs | 10 +- .../src/codegen/reductions/mask/x86/sse.rs | 3 +- .../src/codegen/reductions/mask/x86/sse2.rs | 6 +- vendor/packed_simd_2/src/codegen/shuffle.rs | 4 +- vendor/packed_simd_2/src/codegen/shuffle1_dyn.rs | 25 +- vendor/packed_simd_2/src/codegen/swap_bytes.rs | 52 +--- vendor/packed_simd_2/src/codegen/vPtr.rs | 2 +- vendor/packed_simd_2/src/codegen/vSize.rs | 33 +-- vendor/packed_simd_2/src/lib.rs | 60 +++-- vendor/packed_simd_2/src/masks.rs | 8 +- vendor/packed_simd_2/src/testing.rs | 2 +- vendor/packed_simd_2/src/testing/macros.rs | 40 +-- vendor/packed_simd_2/src/testing/utils.rs | 34 +-- vendor/packed_simd_2/tests/endianness.rs | 10 +- 81 files changed, 2490 insertions(+), 1037 deletions(-) (limited to 'vendor/packed_simd_2') diff --git a/vendor/packed_simd_2/.cargo-checksum.json b/vendor/packed_simd_2/.cargo-checksum.json index 1ffff3edb..e235b36c3 100644 --- a/vendor/packed_simd_2/.cargo-checksum.json +++ b/vendor/packed_simd_2/.cargo-checksum.json @@ -1 +1 @@ -{"files":{"Cargo.toml":"9c95d2e7918abbed602d4bddd3e68b793c436a2e9503350575526e36b03c6195","LICENSE-APACHE":"a60eea817514531668d7e00765731449fe14d059d3249e0bc93b36de45f759f2","LICENSE-MIT":"6485b8ed310d3f0340bf1ad1f47645069ce4069dcc6bb46c7d5c6faf41de1fdb","README.md":"eda9ee8b97b83f0b3f29a2ec8b717cdcd3297a79f0163be7d9b6e1fc64359a71","bors.toml":"dee881dc69b9b7834e4eba5d95c3ed5a416d4628815a167d6a22d4cb4fb064b8","build.rs":"eb12357e953205b699ea2fd355a777af25de76ac0181cce40d3fce43547fb161","ci/all.sh":"2ae6b2445b4db83833e40b37efd0016c6b9879ee988b9b3ef94db5439a3e1606","ci/android-install-ndk.sh":"0f1746108cc30bf9b9ba45bcde7b19fc1a8bdf5b0258035b4eb8dc69b75efac4","ci/android-install-sdk.sh":"3490432022c5c8f5a115c084f7a9aca1626f96c0c87ffb62019228c4346b47e4","ci/android-sysimage.sh":"ebf4e5daa1f0fe1b2092b79f0f3f161c4c4275cb744e52352c4d81ab451e4c5a","ci/benchmark.sh":"b61d19ef6b90deba8fb79dee74c8b062d94844676293da346da87bb78a9a49a4","ci/deploy_and_run_on_ios_simulator.rs":"ec8ecf82d92072676aa47f0d1a3d021b60a7ae3531153ef12d2ff4541fc294dc","ci/docker/aarch64-linux-android/Dockerfile":"ace2e7d33c87bc0f6d3962a4a3408c04557646f7f51ab99cfbf574906796b016","ci/docker/aarch64-unknown-linux-gnu/Dockerfile":"da88c0d50f16dc08448c7fdf1fa5ed2cbe576acf9e7dd85b5b818621b2a8c702","ci/docker/arm-linux-androideabi/Dockerfile":"370e55d3330a413a3ccf677b3afb3e0ef9018a5fab263faa97ae8ac017fc2286","ci/docker/arm-unknown-linux-gnueabi/Dockerfile":"bb5f8ae890707c128652290ffc544447643bf12037ddd73c6ad6989f848cb380","ci/docker/arm-unknown-linux-gnueabihf/Dockerfile":"1afaefcbc05b740859acd4e067bc92439be6bcbe8f2e9678474fb434bcd398d9","ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile":"8282ea707a94109beed47a57574755e2d58401735904a03f85fb64c578c53b4f","ci/docker/i586-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/i686-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/mips-unknown-linux-gnu/Dockerfile":"b2ebc25797612c4f8395fe9d407725156044955bfbcf442036b7f55b43a5f9da","ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile":"b0c1692ac65bc56dd30494b1993d8e929c48cc9c4b92029b7c7592af6d4f9220","ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile":"4e9249c179300138141d0b2b7401b11897f64aed69f541f078c1db4594df2827","ci/docker/mipsel-unknown-linux-musl/Dockerfile":"3164c52b0dcbb01afa78292b15b5c43503ccf0491cf6eb801ec2bf22ae274e52","ci/docker/powerpc-unknown-linux-gnu/Dockerfile":"786f799d0b56eb54d7b6c4b00e1aed4ce81776e14e44767e083c89d014b72004","ci/docker/powerpc64-unknown-linux-gnu/Dockerfile":"e8bc363837cd9c2d8b22402acb8c1c329efc11ba5d12170603d2fe2eae9da059","ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile":"47998d45b781d797b9e6085ebe898d90de0c952b54537a8db4e8d7503eb032d9","ci/docker/s390x-unknown-linux-gnu/Dockerfile":"93fb44df3d7fd31ead158570667c97b5076a05c3d968af4a84bc13819a8f2db8","ci/docker/sparc64-unknown-linux-gnu/Dockerfile":"da1c39a3ff1fe22e41395fa7c8934e90b4c1788e551b9aec6e38bfd94effc437","ci/docker/thumbv7neon-linux-androideabi/Dockerfile":"c2decd5591bd7a09378901bef629cd944acf052eb55e4f35b79eb9cb4d62246a","ci/docker/thumbv7neon-unknown-linux-gnueabihf/Dockerfile":"51955a8bf3c4d440f47382af6f5426ebff94ab01a04da36175babda9a057740f","ci/docker/wasm32-unknown-unknown/Dockerfile":"3e5f294bc1e004aa599086c2af49d6f3e7459fa250f5fbdd60cf67d53db78758","ci/docker/x86_64-linux-android/Dockerfile":"685040273cf350d5509e580ac451555efa19790c8723ca2af066adadc6880ad2","ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile":"44b6203d9290bfdc53d81219f0937e1110847a23dd982ec8c4de388354f01536","ci/docker/x86_64-unknown-linux-gnu/Dockerfile":"7f4e3ca5fa288ea70edb4d1f75309708cd30b192e2e4444e61c4d5b3b58f89cf","ci/dox.sh":"434e9611c52e389312d2b03564adf09429f10cc76fe66a8644adb104903b87b7","ci/linux-s390x.sh":"d6b732d7795b4ba131326aff893bca6228a7d2eb0e9402f135705413dbbe0dce","ci/linux-sparc64.sh":"c92966838b1ab7ad3b7a344833ee726aba6b647cf5952e56f0ad1ba420b13325","ci/lld-shim.rs":"3d7f71ec23a49e2b67f694a0168786f9a954dda15f5a138815d966643fd3fcc3","ci/max_line_width.sh":"0a1518bba4c9ecaa55694cb2e9930d0e19c265baabf73143f17f9cf285aaa5bb","ci/run-docker.sh":"92e036390ad9b0d16f109579df1b5ced2e72e9afea40c7d011400ebd3a2a90de","ci/run.sh":"41dd6a60efaaeae9661a01370cce98b631f78392859a0cf68c946c0a16edf5f7","ci/run_examples.sh":"d1a23c6c35374a0678ba5114b9b8fefd8be0a79e774872a8bf0898d1baca18d0","ci/runtest-android.rs":"145a8e9799a5223975061fe7e586ade5669ee4877a7d7a4cf6b4ab48e8e36c7c","ci/setup_benchmarks.sh":"fae3960023f6f3d1388cd2ad22fdbab4b075f1f29dd4292d7994a20783beb6cf","ci/test-runner-linux":"c8aa6025cff5306f4f31d0c61dc5f9d4dd5a1d189ab613ef8d4c367c694d9ccd","contributing.md":"2cc8c9c560ae17867e69b06d09b758dbf7bc39eb774ada50a743724b10acc0a2","perf-guide/book.toml":"115a98284126c6b180178b44713314cc494f08a71662ee2ce15cf67f17a51064","perf-guide/src/SUMMARY.md":"3e03bffc991fdc2050f3d51842d72d9d21ea6abab56a3baf3b2d5973a78b89e1","perf-guide/src/ascii.css":"29afb08833b2fe2250f0412e1fa1161a2432a0820a14953c87124407417c741a","perf-guide/src/bound_checks.md":"5e4991ff58a183ef0cd9fdc1feb4cd12d083b44bdf87393bbb0927808ef3ce7d","perf-guide/src/float-math/approx.md":"8c09032fa2d795a0c5db1775826c850d28eb2627846d0965c60ee72de63735ad","perf-guide/src/float-math/fma.md":"311076ba4b741d604a82e74b83a8d7e8c318fcbd7f64c4392d1cf5af95c60243","perf-guide/src/float-math/fp.md":"04153e775ab6e4f0d7837bcc515230d327b04edfa34c84ce9c9e10ebaeef2be8","perf-guide/src/float-math/svml.md":"0798873b8eedaeda5fed62dc91645b57c20775a02d3cd74d8bd06958f1516506","perf-guide/src/introduction.md":"9f5a19e9e6751f25d2daad39891a0cc600974527ec4c8305843f9618910671bd","perf-guide/src/prof/linux.md":"447731eb5de7d69166728fdbc5ecb0c0c9db678ea493b45a592d67dd002184c0","perf-guide/src/prof/mca.md":"f56d54f3d20e7aa4d32052186e8237b03d65971eb5d112802b442570ff11d344","perf-guide/src/prof/profiling.md":"8a650c0fd6ede0964789bb6577557eeef1d8226a896788602ce61528e260e43c","perf-guide/src/target-feature/attribute.md":"615f88dca0a707b6c416fa605435dd6e1fb5361cc639429cbf68cd87624bd78b","perf-guide/src/target-feature/features.md":"17077760ff24c006b606dd21889c53d87228f4311f3ba3a574f9afdeacd86165","perf-guide/src/target-feature/inlining.md":"7ed1d7068d8173a00d84c16cfe5871cd68b9f04f8d0cca2d01ebc84957ebf2f6","perf-guide/src/target-feature/practice.md":"c4b371842e0086df178488fec97f20def8f0c62ee588bcd25fd948b9b1fa227e","perf-guide/src/target-feature/runtime.md":"835425f5ee597fb3e51d36e725a81ebee29f4561231d19563cd4da81dbb1cfcb","perf-guide/src/target-feature/rustflags.md":"ab49712e9293a65d74d540ba4784fcb57ff1119ec05a575d895c071f1a620f64","perf-guide/src/vert-hor-ops.md":"c6211c0ee91e60552ec592d89d9d957eedc21dee3cbd89e1ad6765ea06a27471","rust-toolchain":"2a3b62b53ddb9f167b63d22202a360811ba78df015021f704d01ee9abad4169c","rustfmt.toml":"de6101d0670bad65fb3b337d56957d2a024e017e5ab146ec784d77312daaf8ff","src/api.rs":"9de8e5f6f3f2874a184f918b5d281d1e8a1965525d3fff432c9bcba01b94ebe5","src/api/bit_manip.rs":"c47a4d0f7451f7e35d07715e4f39a472e07457fd456fdb726864a4f6887252a3","src/api/bitmask.rs":"6d2beefd62ee5d9c8eb060bee6abc641616bf828c99f82abf97b21bf004e894b","src/api/cast.rs":"03b94a3d316ac7b7be7068810044911e965e889a0ace7bae762749ca74a92747","src/api/cast/macros.rs":"b0a14d0c83ad2ebb7a275180f6d9e3f2bc312ba57a7d3d6c39fad4e0f20f9408","src/api/cast/v128.rs":"2107ea6a426a0fe37a0aa6a03a579ff0bdeb5a1599ea76e2d81734a82f41276d","src/api/cast/v16.rs":"d785cf93b8e61200c9ae1c32b9f5e9d9518e87c261c56bcaf92f2e47b0009eb4","src/api/cast/v256.rs":"b81fcfd367a5de532d922dedf18579e53666facef7957c0e1bc827825e500ae6","src/api/cast/v32.rs":"2aac9ec0a67a97328ba908b13a1ff98da3dcd7781910d592d31f9207cbd9a7d2","src/api/cast/v512.rs":"33b33de818f8d4eccc982bc2f3951a8b3d03e9762ec02789b3df82e3f5ed3fc3","src/api/cast/v64.rs":"ec878917d52a8c952633251b3a938a2cbe0a63fee6d12c15840d9f1343d1f394","src/api/cmp.rs":"357c3a2a09c6d4611c32dd7fa95be2fae933d513e229026ec9b44451a77b884e","src/api/cmp/eq.rs":"60f70f355bae4cb5b17db53204cacc3890f70670611c17df638d4c04f7cc8075","src/api/cmp/ord.rs":"589f7234761c294fa5df8f525bc4acd5a47cdb602207d524a0d4e19804cd9695","src/api/cmp/partial_eq.rs":"3ed23d2a930b0f9750c3a5309da766b03dc4f9c4d375b42ad3c50fe732693d15","src/api/cmp/partial_ord.rs":"e16b11805c94048acd058c93994b5bc74bb187f8d7e3b86a87df60e1601467f9","src/api/cmp/vertical.rs":"de3d62f38eba817299aa16f1e1939954c9a447e316509397465c2830852ba053","src/api/default.rs":"67bf21c134127d12a7028c8b88a57f0ceee8ccbd74976da8ca74eb9f16a174d5","src/api/fmt.rs":"67fb804bb86b6cd77cf8cd492b5733ce437071b66fe3297278b8a6552c325dda","src/api/fmt/binary.rs":"35cb5c266197d6224d598fb3d286e5fe48ef0c01ed356c2ff6fe9ba946f96a92","src/api/fmt/debug.rs":"aa18eea443bf353fea3db8b1a025132bbcaf91e747ecfa43b8d9fce9af395a0c","src/api/fmt/lower_hex.rs":"69d5be366631af309f214e8031c8c20267fcc27a695eac6f45c6bc1df72a67e6","src/api/fmt/octal.rs":"9eb11ba3d990213f3c7f1ec25edba7ce997cb1320e16d308c83498ba6b9bfbd9","src/api/fmt/upper_hex.rs":"a4637d085b7bb20e759ce58e08435b510a563ba3dd468af2b03560fdc5511562","src/api/from.rs":"2e599d8329cb05eaf06224cc441355c4b7b51254fc19256619333be8c149d444","src/api/from/from_array.rs":"dd3fc64fb17d6184bb60343f8da26a05edf0e5f3c14caf55d49fa15e21d948dc","src/api/from/from_vector.rs":"9764371aa9e6005aace74dea14f59e5611a095b7cf42707940924749282c52f0","src/api/hash.rs":"5076ece87969592c876486f5b1ea8affbeaec379d1a14a30859e0aa5592019de","src/api/into_bits.rs":"82297f0697d67b5a015e904e7e6e7b2a7066ba825bc54b94b4ff3e22d7a1eefb","src/api/into_bits/arch_specific.rs":"4acab22af90112072a2608fafc66fccf18cbf2e641b72af28404d30833cfe5c6","src/api/into_bits/macros.rs":"d762406de25aedff88d460dec7a80dc8e825a2a419d53218ce007efa6a1d3e04","src/api/into_bits/v128.rs":"3c502b9ce85bfcc727d6f053d49030b0ba9f46bd8e9fa5aa109382a2033f9f87","src/api/into_bits/v16.rs":"f4f4f61ba88aa51b158ec56ca3dce234349aea0daf2b3029a14ab5125d1e41e5","src/api/into_bits/v256.rs":"c24c3676707a0feb868dabe00766d74deab176794f905f79056337198c7cf790","src/api/into_bits/v32.rs":"905ba683d342fa32f4202b80bb46530807bd0a5b588f6c2e8c9f475223c47775","src/api/into_bits/v512.rs":"7cd89005215a9326eed8a742125dcbf981cba1aca72a313478eabf3df71b1160","src/api/into_bits/v64.rs":"d6238022ccff7b92e55b3f6017fc269acb6f36330a6d7e8fb389853a0f1b6478","src/api/math.rs":"8b2a2fc651917a850539f993aa0b9e5bf4da67b11685285b8de8cdca311719ec","src/api/math/float.rs":"969a75cdb3743c5ac7cde653d1a7f659ac65f2a5afb004c9928a7b34b79c3e39","src/api/math/float/abs.rs":"5b6b2701e2e11135b7ce58a05052ea8120e10e4702c95d046b9d21b827b26bf8","src/api/math/float/consts.rs":"78acba000d3fa527111300b6327c1932de9c4c1e02d4174e1a5615c01463d38c","src/api/math/float/cos.rs":"4c2dd7173728ef189314f1576c9486e03be21b7da98843b2f9011282a7979e31","src/api/math/float/exp.rs":"7c6d5f1e304f498a01cfa23b92380c815d7da0ad94eae3483783bc377d287eef","src/api/math/float/ln.rs":"54c7583f3df793b39ff57534fade27b41bb992439e5dc178252f5ca3190a3e54","src/api/math/float/mul_add.rs":"62cac77660d20159276d4c9ef066eb90c81cbddb808e8e157182c607625ad2eb","src/api/math/float/mul_adde.rs":"bae056ee9f3a70df39ec3c3b2f6437c65303888a7b843ef1a5bcf1f5aca0e602","src/api/math/float/powf.rs":"9ddb938984b36d39d82a82f862f80df8f7fb013f1d222d45698d41d88472f568","src/api/math/float/recpre.rs":"589225794ff1dbf31158dff660e6d4509ecc8befbb57c633900dea5ac0b840d6","src/api/math/float/rsqrte.rs":"a32abdcc318d7ccc8448231f54d75b884b7cbeb03a7d595713ab6243036f4dbf","src/api/math/float/sin.rs":"cbd3622b7df74f19691743001c8cf747a201f8977ad90542fee915f37dcd1e49","src/api/math/float/sqrt.rs":"0c66d5d63fb08e4d99c6b82a8828e41173aff1ac9fa1a2764a11fac217ccf2ac","src/api/math/float/sqrte.rs":"731e1c9f321b662accdd27dacb3aac2e8043b7aecb2f2161dde733bd9f025362","src/api/math/float/tanh.rs":"e57940434cc05981b086f0f3b92d32caceb38d67b90aebce5d3ed8e07c80538f","src/api/minimal.rs":"1f22bcc528555444e76de569ec0ae2029b9ae9d04805efeafa93369c8098036b","src/api/minimal/iuf.rs":"819cff26d3e196f807645bcc1d79eb27d9f175edb89910f2274d52a1e913cd11","src/api/minimal/mask.rs":"0cae10ae1fc65f5070e686c0c79bfba27b86b33d6c399367bd4848fb367dcec4","src/api/minimal/ptr.rs":"f65ebf21866a863485344432d9a7a9b7418f7fad5fdf841a4e2fa56ec0766ad0","src/api/ops.rs":"3e273b277a0f3019d42c3c59ca94a5afd4885d5ae6d2182e5089bbeec9de42ee","src/api/ops/scalar_arithmetic.rs":"d2d5ad897a59dd0787544f927e0e7ca4072c3e58b0f4a2324083312b0d5a21d7","src/api/ops/scalar_bitwise.rs":"482204e459ca6be79568e1c9f70adbe2d2151412ddf122fb2161be8ebb51c40c","src/api/ops/scalar_mask_bitwise.rs":"c250f52042e37b22d57256c80d4604104cfd2fbe2a2e127c676267270ca5d350","src/api/ops/scalar_shifts.rs":"987f8fdebeedc16e3d77c1b732e7826ef70633c541d16dfa290845d5c6289150","src/api/ops/vector_arithmetic.rs":"ddca15d09ddeef502c2ed66117a62300ca65d87e959e8b622d767bdf1c307910","src/api/ops/vector_bitwise.rs":"b3968f7005b649edcc22a54e2379b14d5ee19045f2e784029805781ae043b5ee","src/api/ops/vector_float_min_max.rs":"76bf8cb607e2c442923c1da1061a6b80d742d607408033c2a3761161114cf2a0","src/api/ops/vector_int_min_max.rs":"a378789c6ff9b32a51fbd0a97ffd36ed102cd1fe6a067d2b02017c1df342def6","src/api/ops/vector_mask_bitwise.rs":"5052d18517d765415d40327e6e8e55a312daaca0a5e2aec959bfa54b1675f9c8","src/api/ops/vector_neg.rs":"5c62f6b0221983cdbd23cd0a3af3672e6ba1255f0dfe8b19aae6fbd6503e231b","src/api/ops/vector_rotates.rs":"03cbe8a400fd7c688e4ee771a990a6754f2031b1a59b19ae81158b21471167e5","src/api/ops/vector_shifts.rs":"9bf69d0087268f61009e39aea52e03a90f378910206b6a28e8393178b6a5d0e0","src/api/ptr.rs":"8a793251bed6130dcfb2f1519ceaa18b751bbb15875928d0fb6deb5a5e07523a","src/api/ptr/gather_scatter.rs":"138b02b0fa1fdd785b95fc7048488be7e3ef277e0bc6ac5affb26af6a11d41a6","src/api/reductions.rs":"ae5baca81352ecd44526d6c30c0a1feeda475ec73ddd3c3ec6b14e944e5448ee","src/api/reductions/bitwise.rs":"8bf910ae226188bd15fc7e125f058cd2566b6186fcd0cd8fd020f352c39ce139","src/api/reductions/float_arithmetic.rs":"3997125f87c7bac07fffda3a1d814e0e6c77ca83099546a9e2fb8dc92231129f","src/api/reductions/integer_arithmetic.rs":"47471da1c5f859489680bb5d34ced3d3aa20081c16053a3af121a4496fcb57bf","src/api/reductions/mask.rs":"db83327a950e33a317f37fd33ca4e20c347fb415975ec024f3e23da8509425af","src/api/reductions/min_max.rs":"d40ccad10220ae5982785015bef92e4b0749583c2b060cad0aa4f92d99491c3b","src/api/select.rs":"a98e2ccf9fc6bdeed32d337c8675bc96c2fbe2cc34fbf149ad6047fb8e749774","src/api/shuffle.rs":"da58200790868c09659819322a489929a5b6e56c596ed07e6a44293ea02e7d09","src/api/shuffle1_dyn.rs":"bfea5a91905b31444e9ef7ca6eddb7a9606b7e22d3f71bb842eb2795a0346620","src/api/slice.rs":"ee87484e8af329547b9a5d4f2a69e8bed6ea10bbd96270d706083843d4eea2ac","src/api/slice/from_slice.rs":"53691dc9958dec4180004a42d140552b405e8cd875caa282e89af378dd63c8bc","src/api/slice/write_to_slice.rs":"3dd2e511af43dc6fa911dd0b12f6f00323e0acd1202a01365db400557d52a89b","src/api/swap_bytes.rs":"4a6792a2e49a77475e1b237592b4b2804dbddb79c474331acd0dd71b36934259","src/codegen.rs":"a29d38fa0a85eaf787fb49989e625bf64effd5f39c126fbb2a24be206d2a3917","src/codegen/bit_manip.rs":"17ecebcff1f080e712fea5eb51602a73f4201ed56a198220342c8eb55bb92692","src/codegen/llvm.rs":"b1f24237f61b7c5ddb8d47f3943aab79a95ce0e75af87ab2d1c88d842faffd39","src/codegen/math.rs":"35f96e37a78fcf0cdb02146b7f27a45108fe06a37fc2a54d8851ce131a326178","src/codegen/math/float.rs":"843b06adc2467377bd1184fd7bacb0fc10714918d29e433a9a7bffe46ed3c9d9","src/codegen/math/float/abs.rs":"f56e2b4b8055ea861c1f5cbc6b6e1d8e7e5af163b62c13574ddee4e09513bfbc","src/codegen/math/float/cos.rs":"ef3b511a24d23045b310315e80348a9b7fedb576fc2de52d74290616a0abeb2a","src/codegen/math/float/cos_pi.rs":"4e7631a5d73dac21531e09ef1802d1180f8997509c2c8fa9f67f322194263a97","src/codegen/math/float/exp.rs":"61b691598c41b5622f24e4320c1bdd08701e612a516438bdddcc728fc3405c8c","src/codegen/math/float/ln.rs":"46b718b1ba8c9d99e1ad40f53d20dfde08a3063ca7bd2a9fdd6698e060da687e","src/codegen/math/float/macros.rs":"dd42135fff13f9aca4fd3a1a4e14c7e6c31aadc6d817d63b0d2fb9e62e062744","src/codegen/math/float/mul_add.rs":"a37bf764345d4b1714f97e83897b7cf0855fc2811704bcbc0012db91825339e1","src/codegen/math/float/mul_adde.rs":"c75702bfcb361de45964a93caf959a695ef2376bd069227600b8c6872665c755","src/codegen/math/float/powf.rs":"642346e982bc4c39203de0864d2149c4179cd7b21cf67a2951687932b4675872","src/codegen/math/float/sin.rs":"9d68164c90cdca6a85155040cdac42e27342ebe0b925273ef1593df721af4258","src/codegen/math/float/sin_cos_pi.rs":"9be02ad48585a1e8d99129382fbffbaed47852f15459256a708850b6b7a75405","src/codegen/math/float/sin_pi.rs":"9890347905b4d4a3c7341c3eb06406e46e60582bcf6960688bd727e5dadc6c57","src/codegen/math/float/sqrt.rs":"e3c60dcfb0c6d2fc62adabcc931b2d4040b83cab294dea36443fb4b89eb79e34","src/codegen/math/float/sqrte.rs":"f0f4ef9eb475ae41bcc7ec6a95ad744ba6b36925faa8b2c2814004396d196b63","src/codegen/math/float/tanh.rs":"1c2c7431162ab248ee23e557e92c8b401875fb7b597ccfbba8f37b48f724de20","src/codegen/pointer_sized_int.rs":"a70697169c28218b56fd2e8d5353f2e00671d1150d0c8cef77d613bdfacd84cb","src/codegen/reductions.rs":"645e2514746d01387ddd07f0aa4ffd8430cc9ab428d4fb13773ea319fa25dd95","src/codegen/reductions/mask.rs":"8f1afe6aabf096a3278e1fc3a30f736e04aa8b9ce96373cee22162d18cfe2702","src/codegen/reductions/mask/aarch64.rs":"cba6e17603d39795dcfe8339b6b7d8714c3e162a1f0a635979f037aa24fe4206","src/codegen/reductions/mask/arm.rs":"9447904818aa2c7c25d0963eead452a639a11ca7dbd6d21eedbfcaade07a0f33","src/codegen/reductions/mask/fallback.rs":"7a0ef9f7fd03ae318b495b95e121350cd61caffc5cc6ee17fabf130d5d933453","src/codegen/reductions/mask/fallback_impl.rs":"76547f396e55ef403327c77c314cf8db8c7a5c9b9819bfb925abeacf130249e5","src/codegen/reductions/mask/x86.rs":"4c0457b6276f9809223590092a4c77e73812330326cdabd28df06820de10a310","src/codegen/reductions/mask/x86/avx.rs":"b4913d87844c522903641cbbf10db4551addb1ce5e9e78278e21612fa65c733b","src/codegen/reductions/mask/x86/avx2.rs":"677aed3f056285285daa3adff8bc65e739630b4424defa6d9665e160f027507e","src/codegen/reductions/mask/x86/sse.rs":"5a827c6f8e1074e324f6e4c778942badb6c09d747a7142de01cadec1240b3428","src/codegen/reductions/mask/x86/sse2.rs":"bc38e6c31cb4b3d62147eba6cac264e519e2a48e0f7ce9010cfa9ef0cf0ec9fd","src/codegen/shuffle.rs":"99a0b52c2470097b028af134221099baba383446a01c7dc3ae560209880bcdb7","src/codegen/shuffle1_dyn.rs":"fbc7d3d2e287543ab476a9a9314a5fbabdddd33bc463fc4bd22aa95631fcb996","src/codegen/swap_bytes.rs":"1d6cdc716eadddc92b4fd506b2445a821caa8dc00860447de09d7ebd69c2087f","src/codegen/v128.rs":"94226b31ec403d18d9d2fe06713f147c9c79e9b5f9105089088266313f843185","src/codegen/v16.rs":"ddec4ffb66b6f7aaffb9a1780c5ddba82557abd74f45073d335047e04cf74924","src/codegen/v256.rs":"6b63917f0444118d6b1595bff2045e59b97c4d24012bd575f69f1f0efc5a0241","src/codegen/v32.rs":"3477b3c5540aed86e61e2f5807dd31db947413cec9181c587d93ed6ec74f0eba","src/codegen/v512.rs":"5854f99d3aabc4cd42b28a20d9ce447756dc2ba024a409a69b6a8ae1f1842fc5","src/codegen/v64.rs":"e9e89caebfe63d10c0cbca61e4dfdba3b7e02ee0989170f80beed23237ddd950","src/codegen/vPtr.rs":"711c753a08d53a2879c4fb87a0762c46ce4e34c22f0ca88d2e4c557a0f679969","src/codegen/vSize.rs":"eeee9858749aa82142b27bc120d1989bb74a6b82e1e4efbbeaccc9634dc9acfc","src/lib.rs":"891d5369911c53caf422f3dbff2b413907ca11365baa5ed5828a7f0601270dac","src/masks.rs":"be05e923ac58fe6eb61311561b5583cd306574f206dc09fe8e3c7de3dd0c1433","src/sealed.rs":"ae7fdeaf5d84cd7710ed730ca72ca7eaba93df6cb0acb183e5c0a7327acf197f","src/testing.rs":"1d3a7862ef625e235a5734ad7204e68d350f902c0695182b1f08a0552432416e","src/testing/macros.rs":"6378856d7a40ba5ec5c7c0dad6327d79f0c77266921c24296d10aed6c68e9b98","src/testing/utils.rs":"5ec6a47b836f364ec6dede19750a19eaac704162327d03041eb0f007d5f8d75c","src/v128.rs":"16cf9a8e7156b899ee9b9cd3f2dba9d13ec63289bea8c3ee9ae2e43ad9510288","src/v16.rs":"cb6465cf1e00bf530183af1819b9fe3d7eec978f8765d5e85d9b58a39a4b4045","src/v256.rs":"fe235017da18c7f3c361831c60e3173ad304d8ea1e95d64ebebc79da2d708511","src/v32.rs":"145d347855bac59b2de6508f9e594654e6c330423af9edc0e2ac8f4d1abdf45e","src/v512.rs":"f372f277f3e62eb5c945bb1c460333fdb17b6974fcc876633788ff53bded9599","src/v64.rs":"0b8079881b71575e3414be0b7f8f7eaba65281ba6732f2b2f61f73e95b6f48f7","src/vPtr.rs":"8b3e433d487180bb4304ff71245ecad90f0010f43e139a72027b672abe58facc","src/vSize.rs":"eda5aa020706cbf94d15bada41a0c2a35fc8f3f37cb7c2cd6f34d201399a495e","tests/endianness.rs":"7db22078f31fe1421fc2d21f2e6b9df5eb0bdc99c10f6985d3a74c0df8f205dc"},"package":"3278e0492f961fd4ae70909f56b2723a7e8d01a228427294e19cdfdebda89a17"} \ No newline at end of file +{"files":{"Cargo.toml":"dc595f9306276711bb230de128e7714dc266448740f3a53341aacf0106f00b77","LICENSE-APACHE":"a60eea817514531668d7e00765731449fe14d059d3249e0bc93b36de45f759f2","LICENSE-MIT":"6485b8ed310d3f0340bf1ad1f47645069ce4069dcc6bb46c7d5c6faf41de1fdb","README.md":"fa4dd64f66972217d35b7653338c9e2011ccd8f3008ae7c0103272d4287f9b1d","bors.toml":"dee881dc69b9b7834e4eba5d95c3ed5a416d4628815a167d6a22d4cb4fb064b8","build.rs":"019ed29c43989782d8eec3a961654cfc172d7a7898da4eca8f654700af7e1988","ci/all.sh":"2ae6b2445b4db83833e40b37efd0016c6b9879ee988b9b3ef94db5439a3e1606","ci/android-install-ndk.sh":"0f1746108cc30bf9b9ba45bcde7b19fc1a8bdf5b0258035b4eb8dc69b75efac4","ci/android-install-sdk.sh":"3490432022c5c8f5a115c084f7a9aca1626f96c0c87ffb62019228c4346b47e4","ci/android-sysimage.sh":"ebf4e5daa1f0fe1b2092b79f0f3f161c4c4275cb744e52352c4d81ab451e4c5a","ci/benchmark.sh":"b61d19ef6b90deba8fb79dee74c8b062d94844676293da346da87bb78a9a49a4","ci/deploy_and_run_on_ios_simulator.rs":"ec8ecf82d92072676aa47f0d1a3d021b60a7ae3531153ef12d2ff4541fc294dc","ci/docker/aarch64-linux-android/Dockerfile":"ace2e7d33c87bc0f6d3962a4a3408c04557646f7f51ab99cfbf574906796b016","ci/docker/aarch64-unknown-linux-gnu/Dockerfile":"da88c0d50f16dc08448c7fdf1fa5ed2cbe576acf9e7dd85b5b818621b2a8c702","ci/docker/arm-linux-androideabi/Dockerfile":"370e55d3330a413a3ccf677b3afb3e0ef9018a5fab263faa97ae8ac017fc2286","ci/docker/arm-unknown-linux-gnueabi/Dockerfile":"bb5f8ae890707c128652290ffc544447643bf12037ddd73c6ad6989f848cb380","ci/docker/arm-unknown-linux-gnueabihf/Dockerfile":"1afaefcbc05b740859acd4e067bc92439be6bcbe8f2e9678474fb434bcd398d9","ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile":"8282ea707a94109beed47a57574755e2d58401735904a03f85fb64c578c53b4f","ci/docker/i586-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/i686-unknown-linux-gnu/Dockerfile":"49792922269f371bd29da4727e9085101b27be67a6b97755d0196c63317f7abb","ci/docker/mips-unknown-linux-gnu/Dockerfile":"b2ebc25797612c4f8395fe9d407725156044955bfbcf442036b7f55b43a5f9da","ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile":"b0c1692ac65bc56dd30494b1993d8e929c48cc9c4b92029b7c7592af6d4f9220","ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile":"4e9249c179300138141d0b2b7401b11897f64aed69f541f078c1db4594df2827","ci/docker/mipsel-unknown-linux-musl/Dockerfile":"3164c52b0dcbb01afa78292b15b5c43503ccf0491cf6eb801ec2bf22ae274e52","ci/docker/powerpc-unknown-linux-gnu/Dockerfile":"786f799d0b56eb54d7b6c4b00e1aed4ce81776e14e44767e083c89d014b72004","ci/docker/powerpc64-unknown-linux-gnu/Dockerfile":"e8bc363837cd9c2d8b22402acb8c1c329efc11ba5d12170603d2fe2eae9da059","ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile":"47998d45b781d797b9e6085ebe898d90de0c952b54537a8db4e8d7503eb032d9","ci/docker/s390x-unknown-linux-gnu/Dockerfile":"93fb44df3d7fd31ead158570667c97b5076a05c3d968af4a84bc13819a8f2db8","ci/docker/sparc64-unknown-linux-gnu/Dockerfile":"da1c39a3ff1fe22e41395fa7c8934e90b4c1788e551b9aec6e38bfd94effc437","ci/docker/thumbv7neon-linux-androideabi/Dockerfile":"c2decd5591bd7a09378901bef629cd944acf052eb55e4f35b79eb9cb4d62246a","ci/docker/thumbv7neon-unknown-linux-gnueabihf/Dockerfile":"51955a8bf3c4d440f47382af6f5426ebff94ab01a04da36175babda9a057740f","ci/docker/wasm32-unknown-unknown/Dockerfile":"5a022299f56730cf8c432a07391e95e199cfa36dc8da2a96c9d185c8de93e913","ci/docker/x86_64-linux-android/Dockerfile":"685040273cf350d5509e580ac451555efa19790c8723ca2af066adadc6880ad2","ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile":"44b6203d9290bfdc53d81219f0937e1110847a23dd982ec8c4de388354f01536","ci/docker/x86_64-unknown-linux-gnu/Dockerfile":"7f4e3ca5fa288ea70edb4d1f75309708cd30b192e2e4444e61c4d5b3b58f89cf","ci/dox.sh":"434e9611c52e389312d2b03564adf09429f10cc76fe66a8644adb104903b87b7","ci/linux-s390x.sh":"d6b732d7795b4ba131326aff893bca6228a7d2eb0e9402f135705413dbbe0dce","ci/linux-sparc64.sh":"c92966838b1ab7ad3b7a344833ee726aba6b647cf5952e56f0ad1ba420b13325","ci/lld-shim.rs":"3d7f71ec23a49e2b67f694a0168786f9a954dda15f5a138815d966643fd3fcc3","ci/max_line_width.sh":"0a1518bba4c9ecaa55694cb2e9930d0e19c265baabf73143f17f9cf285aaa5bb","ci/run-docker.sh":"92e036390ad9b0d16f109579df1b5ced2e72e9afea40c7d011400ebd3a2a90de","ci/run.sh":"41dd6a60efaaeae9661a01370cce98b631f78392859a0cf68c946c0a16edf5f7","ci/run_examples.sh":"d1a23c6c35374a0678ba5114b9b8fefd8be0a79e774872a8bf0898d1baca18d0","ci/runtest-android.rs":"145a8e9799a5223975061fe7e586ade5669ee4877a7d7a4cf6b4ab48e8e36c7c","ci/setup_benchmarks.sh":"fae3960023f6f3d1388cd2ad22fdbab4b075f1f29dd4292d7994a20783beb6cf","ci/test-runner-linux":"c8aa6025cff5306f4f31d0c61dc5f9d4dd5a1d189ab613ef8d4c367c694d9ccd","contributing.md":"2d2629310ad4d464c482bdbb5819f0d6ce223c576aeef2cdce6a1f6857085ea5","perf-guide/book.toml":"115a98284126c6b180178b44713314cc494f08a71662ee2ce15cf67f17a51064","perf-guide/src/SUMMARY.md":"3e03bffc991fdc2050f3d51842d72d9d21ea6abab56a3baf3b2d5973a78b89e1","perf-guide/src/ascii.css":"29afb08833b2fe2250f0412e1fa1161a2432a0820a14953c87124407417c741a","perf-guide/src/bound_checks.md":"5e4991ff58a183ef0cd9fdc1feb4cd12d083b44bdf87393bbb0927808ef3ce7d","perf-guide/src/float-math/approx.md":"8c09032fa2d795a0c5db1775826c850d28eb2627846d0965c60ee72de63735ad","perf-guide/src/float-math/fma.md":"311076ba4b741d604a82e74b83a8d7e8c318fcbd7f64c4392d1cf5af95c60243","perf-guide/src/float-math/fp.md":"04153e775ab6e4f0d7837bcc515230d327b04edfa34c84ce9c9e10ebaeef2be8","perf-guide/src/float-math/svml.md":"0798873b8eedaeda5fed62dc91645b57c20775a02d3cd74d8bd06958f1516506","perf-guide/src/introduction.md":"9f5a19e9e6751f25d2daad39891a0cc600974527ec4c8305843f9618910671bd","perf-guide/src/prof/linux.md":"447731eb5de7d69166728fdbc5ecb0c0c9db678ea493b45a592d67dd002184c0","perf-guide/src/prof/mca.md":"f56d54f3d20e7aa4d32052186e8237b03d65971eb5d112802b442570ff11d344","perf-guide/src/prof/profiling.md":"8a650c0fd6ede0964789bb6577557eeef1d8226a896788602ce61528e260e43c","perf-guide/src/target-feature/attribute.md":"615f88dca0a707b6c416fa605435dd6e1fb5361cc639429cbf68cd87624bd78b","perf-guide/src/target-feature/features.md":"17077760ff24c006b606dd21889c53d87228f4311f3ba3a574f9afdeacd86165","perf-guide/src/target-feature/inlining.md":"7ed1d7068d8173a00d84c16cfe5871cd68b9f04f8d0cca2d01ebc84957ebf2f6","perf-guide/src/target-feature/practice.md":"c4b371842e0086df178488fec97f20def8f0c62ee588bcd25fd948b9b1fa227e","perf-guide/src/target-feature/runtime.md":"835425f5ee597fb3e51d36e725a81ebee29f4561231d19563cd4da81dbb1cfcb","perf-guide/src/target-feature/rustflags.md":"01197acf6f0adec8db32b8591811f69cecb6555a2b05dc5d5ec27d0e3f7b065e","perf-guide/src/vert-hor-ops.md":"c6211c0ee91e60552ec592d89d9d957eedc21dee3cbd89e1ad6765ea06a27471","rust-toolchain":"2a3b62b53ddb9f167b63d22202a360811ba78df015021f704d01ee9abad4169c","rustfmt.toml":"d99a43f3f8ef9e425cf01c333fba9f0051f888f5d87ab4e8f63c2f7d0fe6620f","src/api.rs":"45508c6c0241519fc01a7f00c9105554c24c312c4e46900ef9c75139ea438305","src/api/bit_manip.rs":"c47a4d0f7451f7e35d07715e4f39a472e07457fd456fdb726864a4f6887252a3","src/api/bitmask.rs":"6d2beefd62ee5d9c8eb060bee6abc641616bf828c99f82abf97b21bf004e894b","src/api/cast.rs":"03b94a3d316ac7b7be7068810044911e965e889a0ace7bae762749ca74a92747","src/api/cast/macros.rs":"b0a14d0c83ad2ebb7a275180f6d9e3f2bc312ba57a7d3d6c39fad4e0f20f9408","src/api/cast/v128.rs":"edd0994efac4379dff26e178423a52dbb3ffeb38b1fc97cae975d744c00b4fb6","src/api/cast/v16.rs":"96bd98c2d21b0663abe6c0ab33005b1fa693f3db7ee6795351391343863484da","src/api/cast/v256.rs":"8c31fe91f5e78ef737dfba6979cc1240210cb094a89d284fe459bf8a991ca24b","src/api/cast/v32.rs":"a99a79dd84d2a5e6adf9db98705675915bd03fd1287d489c7fe38e84d7e4a086","src/api/cast/v512.rs":"c0dd526f41ed7b8a71c3743d91267554ec0a0c75834ccc2e3ecb0ef3004af642","src/api/cast/v64.rs":"6572fdba2a1241a6cd666d3f0cce3306cd2cb7e5e236172e59d5d4351c8a88af","src/api/cmp.rs":"357c3a2a09c6d4611c32dd7fa95be2fae933d513e229026ec9b44451a77b884e","src/api/cmp/eq.rs":"60f70f355bae4cb5b17db53204cacc3890f70670611c17df638d4c04f7cc8075","src/api/cmp/ord.rs":"589f7234761c294fa5df8f525bc4acd5a47cdb602207d524a0d4e19804cd9695","src/api/cmp/partial_eq.rs":"902ccb8aa01fd5738b30ba0b712669c21d4801958907e03bad23432c7dba0198","src/api/cmp/partial_ord.rs":"9db0c37d7434cdfc62d8d66912e972fa3d8c115ab2af051a6f45e414bd3e4f1c","src/api/cmp/vertical.rs":"de3d62f38eba817299aa16f1e1939954c9a447e316509397465c2830852ba053","src/api/default.rs":"67bf21c134127d12a7028c8b88a57f0ceee8ccbd74976da8ca74eb9f16a174d5","src/api/fmt.rs":"67fb804bb86b6cd77cf8cd492b5733ce437071b66fe3297278b8a6552c325dda","src/api/fmt/binary.rs":"02b2b287f7404f8a983813cf70c87108c8da3835578b63ab303116885f609413","src/api/fmt/debug.rs":"56e1c3bdc092747344fffaafff9da7163ee7827857f6fb7cb1c9923eca4f6fa0","src/api/fmt/lower_hex.rs":"558fd592f7f485712fb051509cecc7174a21e6bf62e5ce64766e75afc97bb8e1","src/api/fmt/octal.rs":"3b2e70877a4f368c7704f8e254236c014c365c74d93371c1feb5f030e6c66422","src/api/fmt/upper_hex.rs":"2a442f666bc80e22d41f903f881238fe114dd49344c3ed69849250e853cafc5d","src/api/from.rs":"2e599d8329cb05eaf06224cc441355c4b7b51254fc19256619333be8c149d444","src/api/from/from_array.rs":"dd3fc64fb17d6184bb60343f8da26a05edf0e5f3c14caf55d49fa15e21d948dc","src/api/from/from_vector.rs":"9764371aa9e6005aace74dea14f59e5611a095b7cf42707940924749282c52f0","src/api/hash.rs":"5076ece87969592c876486f5b1ea8affbeaec379d1a14a30859e0aa5592019de","src/api/into_bits.rs":"1ee15923352786b9ab4a31fa506762297116b18cfdb8e72853abc8ad001651d2","src/api/into_bits/arch_specific.rs":"e7445021f3908326bfee758835e5fc5ad56aa1baa77fc1c58abe4350c66c670a","src/api/into_bits/macros.rs":"bb4fe99be2af6a21d805efab44c8e4e61a7b2adb42a65504a0cf26d13efdadcd","src/api/into_bits/v128.rs":"145a44922b09a5ca5b62d88a461d327d399a997a15db4b11d7b17e554a9fa4c0","src/api/into_bits/v16.rs":"f4f4f61ba88aa51b158ec56ca3dce234349aea0daf2b3029a14ab5125d1e41e5","src/api/into_bits/v256.rs":"8cea9c5d9809f11323cb7cdc53b83df593fd17caf926251e412ae9777bed547f","src/api/into_bits/v32.rs":"905ba683d342fa32f4202b80bb46530807bd0a5b588f6c2e8c9f475223c47775","src/api/into_bits/v512.rs":"e25afa1fbf088a5d58e7d75d197b6cd4c56637ea28542ba18e46a451f29d04e7","src/api/into_bits/v64.rs":"d6238022ccff7b92e55b3f6017fc269acb6f36330a6d7e8fb389853a0f1b6478","src/api/math.rs":"8b2a2fc651917a850539f993aa0b9e5bf4da67b11685285b8de8cdca311719ec","src/api/math/float.rs":"969a75cdb3743c5ac7cde653d1a7f659ac65f2a5afb004c9928a7b34b79c3e39","src/api/math/float/abs.rs":"5b6b2701e2e11135b7ce58a05052ea8120e10e4702c95d046b9d21b827b26bf8","src/api/math/float/consts.rs":"6302c9261da4291d144d5bb53493cdd073498feb40955fb6860ea3c4d06c978a","src/api/math/float/cos.rs":"4c2dd7173728ef189314f1576c9486e03be21b7da98843b2f9011282a7979e31","src/api/math/float/exp.rs":"7c6d5f1e304f498a01cfa23b92380c815d7da0ad94eae3483783bc377d287eef","src/api/math/float/ln.rs":"54c7583f3df793b39ff57534fade27b41bb992439e5dc178252f5ca3190a3e54","src/api/math/float/mul_add.rs":"62cac77660d20159276d4c9ef066eb90c81cbddb808e8e157182c607625ad2eb","src/api/math/float/mul_adde.rs":"bae056ee9f3a70df39ec3c3b2f6437c65303888a7b843ef1a5bcf1f5aca0e602","src/api/math/float/powf.rs":"9ddb938984b36d39d82a82f862f80df8f7fb013f1d222d45698d41d88472f568","src/api/math/float/recpre.rs":"589225794ff1dbf31158dff660e6d4509ecc8befbb57c633900dea5ac0b840d6","src/api/math/float/rsqrte.rs":"a32abdcc318d7ccc8448231f54d75b884b7cbeb03a7d595713ab6243036f4dbf","src/api/math/float/sin.rs":"cbd3622b7df74f19691743001c8cf747a201f8977ad90542fee915f37dcd1e49","src/api/math/float/sqrt.rs":"0c66d5d63fb08e4d99c6b82a8828e41173aff1ac9fa1a2764a11fac217ccf2ac","src/api/math/float/sqrte.rs":"731e1c9f321b662accdd27dacb3aac2e8043b7aecb2f2161dde733bd9f025362","src/api/math/float/tanh.rs":"e57940434cc05981b086f0f3b92d32caceb38d67b90aebce5d3ed8e07c80538f","src/api/minimal.rs":"1f22bcc528555444e76de569ec0ae2029b9ae9d04805efeafa93369c8098036b","src/api/minimal/iuf.rs":"819cff26d3e196f807645bcc1d79eb27d9f175edb89910f2274d52a1e913cd11","src/api/minimal/mask.rs":"0cae10ae1fc65f5070e686c0c79bfba27b86b33d6c399367bd4848fb367dcec4","src/api/minimal/ptr.rs":"f65ebf21866a863485344432d9a7a9b7418f7fad5fdf841a4e2fa56ec0766ad0","src/api/ops.rs":"3e273b277a0f3019d42c3c59ca94a5afd4885d5ae6d2182e5089bbeec9de42ee","src/api/ops/scalar_arithmetic.rs":"d2d5ad897a59dd0787544f927e0e7ca4072c3e58b0f4a2324083312b0d5a21d7","src/api/ops/scalar_bitwise.rs":"482204e459ca6be79568e1c9f70adbe2d2151412ddf122fb2161be8ebb51c40c","src/api/ops/scalar_mask_bitwise.rs":"c250f52042e37b22d57256c80d4604104cfd2fbe2a2e127c676267270ca5d350","src/api/ops/scalar_shifts.rs":"c4773d435c3f9da4454327e6fbb2b5b41a1c0ebb1cca7372e69dc7a344a1b6e4","src/api/ops/vector_arithmetic.rs":"ddca15d09ddeef502c2ed66117a62300ca65d87e959e8b622d767bdf1c307910","src/api/ops/vector_bitwise.rs":"b3968f7005b649edcc22a54e2379b14d5ee19045f2e784029805781ae043b5ee","src/api/ops/vector_float_min_max.rs":"76bf8cb607e2c442923c1da1061a6b80d742d607408033c2a3761161114cf2a0","src/api/ops/vector_int_min_max.rs":"a378789c6ff9b32a51fbd0a97ffd36ed102cd1fe6a067d2b02017c1df342def6","src/api/ops/vector_mask_bitwise.rs":"5052d18517d765415d40327e6e8e55a312daaca0a5e2aec959bfa54b1675f9c8","src/api/ops/vector_neg.rs":"5c62f6b0221983cdbd23cd0a3af3672e6ba1255f0dfe8b19aae6fbd6503e231b","src/api/ops/vector_rotates.rs":"ee319eaaa449dc50ea8ef05b89d38519c6faa6753dfdce432ea7bb8520e4e8e7","src/api/ops/vector_shifts.rs":"e510be14127c0ffd58a2573a39701da3557d66bedec09837ac8bbd44d579da00","src/api/ptr.rs":"8a793251bed6130dcfb2f1519ceaa18b751bbb15875928d0fb6deb5a5e07523a","src/api/ptr/gather_scatter.rs":"3d614f9d5b4ca201a9f7e46af4405e1d2c28ecee1620297c23b52e37b92cc0ea","src/api/reductions.rs":"ae5baca81352ecd44526d6c30c0a1feeda475ec73ddd3c3ec6b14e944e5448ee","src/api/reductions/bitwise.rs":"8bf910ae226188bd15fc7e125f058cd2566b6186fcd0cd8fd020f352c39ce139","src/api/reductions/float_arithmetic.rs":"47a5679896db2cbb56c31372fe42143da015b6beae7db5d2f3a0309ddf427ae1","src/api/reductions/integer_arithmetic.rs":"c2df3cf7493cca4174f2c65aea422a3d20d8a23af03f8d57cef72c19fee8f20d","src/api/reductions/mask.rs":"db83327a950e33a317f37fd33ca4e20c347fb415975ec024f3e23da8509425af","src/api/reductions/min_max.rs":"6af8c9aa45c69961b1b6fc205395f4767d4421869fb105fb3d563c5605fc13cd","src/api/select.rs":"6b07e7e8026df561f7307221a896f0fbb272536f41b9109040ac094c24c69331","src/api/shuffle.rs":"26458aec2557bfab41b7765f72aefbff3a7ee08cdc689981a81f133f58ee368b","src/api/shuffle1_dyn.rs":"bfea5a91905b31444e9ef7ca6eddb7a9606b7e22d3f71bb842eb2795a0346620","src/api/slice.rs":"ee87484e8af329547b9a5d4f2a69e8bed6ea10bbd96270d706083843d4eea2ac","src/api/slice/from_slice.rs":"9b6f01ace2d12ef45c84608bb7aad3a122e2cc319b2d99170fc332a568b8de63","src/api/slice/write_to_slice.rs":"244b6bd6ccffa6e5a195f8b1abc66d94251b6d16b2ec3fe4d76d32caec68261e","src/api/swap_bytes.rs":"4a6792a2e49a77475e1b237592b4b2804dbddb79c474331acd0dd71b36934259","src/codegen.rs":"db4f232fb9f5728db310b87dc8c4733be48afacab1053798c06106bef9a42b05","src/codegen/bit_manip.rs":"525ea6ff7ad1e043b6f6136992166f1803ed5563b7f6fc292c1c40257d20e264","src/codegen/llvm.rs":"b4ccbc0bad90038f00fc3c158736462d01d0053df3afa00f9169e67d1a264444","src/codegen/math.rs":"dfcf02ad34e2fdfe22c3f1cc2822001cc895e65031b4d06e585e5047839febb7","src/codegen/math/float.rs":"b2f31f479c5c70a6ff9ad33872c1e65506f72882b77a2e3f9e71c42e92af9355","src/codegen/math/float/abs.rs":"d5aaadcf540bdb9b4264dca6471a255fd7bf509e763bef0239c0144a68466fea","src/codegen/math/float/cos.rs":"17f28d2900c852dca221fa9c92a9cd5fe7fd2df8d427bbc60216c749b2be013d","src/codegen/math/float/cos_pi.rs":"dbaf9f443f9846a491d4ec52210a7b5835dd593b03366e3135b05c37d70f9d6c","src/codegen/math/float/exp.rs":"d300058a4bcc7ae7976f216f81902cd73a9e603ad63880dff3bbc866c27a9f37","src/codegen/math/float/ln.rs":"c851e211e43f8256093ba75b03ae0c307c9962ee66d94f09b4dd80068190cbdf","src/codegen/math/float/macros.rs":"fc9924869ed85e4795983af228cacf23158f4f35919adce16c920ad4a3f0a009","src/codegen/math/float/mul_add.rs":"041a5b69d5991d93ef795351b17560c10faf80b78fd26ad7df42a239b32cf9de","src/codegen/math/float/mul_adde.rs":"d71d5f0f3333b62a7439b823cb7adf5340ea1555ce820fb4a3f4cb922f73f5f5","src/codegen/math/float/powf.rs":"9742c3877f1a5509ca5c9492a40884b6579ba6dd11c26b7112e63f70666b395d","src/codegen/math/float/sin.rs":"0e9868d35531566509f3a01d85d5253045eb4afa8525d8407dcc1f5f33c56036","src/codegen/math/float/sin_cos_pi.rs":"8e6b6142d7dd240cdb36669722e82ab9810a2261e86e659f7d97a942ad8b1258","src/codegen/math/float/sin_pi.rs":"bb6d39db8f921e03a301fc5206ac1a61a97def8a2cb83b87ccf189f3fc48d548","src/codegen/math/float/sqrt.rs":"e6ebb0c5f428efad1f672b9a8fe4e58534dbf1ea5a8fe092ce5ce76b52fe89cb","src/codegen/math/float/sqrte.rs":"23acfaea38d0e081a6d9021c1094e813d0cfd12c58c1eca9662aade5e625d51c","src/codegen/math/float/tanh.rs":"0b345a896c67a0c7a0055a8d8195279540d83480cada603e3271e27a5e797cb3","src/codegen/pointer_sized_int.rs":"6ca13c214b6cf7e0929dbe18e96a16fc0bb7d8799608df29c4c8115490f99e01","src/codegen/reductions.rs":"8eb18ebac76985d2aa30262a2edd8cb004230b511a765d657525f677a585c12c","src/codegen/reductions/mask.rs":"e67f35a1f4d156a4894a2d6ea5a935b4d898cf70eefb2715f5c1cc165e776c11","src/codegen/reductions/mask/aarch64.rs":"84b101c17cad1ede4eb6d38cada0ac7da239dba8cea3badd3829b967e558431f","src/codegen/reductions/mask/arm.rs":"aaa07129bd078ae7e677cf8b8e67ec9f30536606a0c7ed1baaa18fd1793bb218","src/codegen/reductions/mask/fallback.rs":"3eb9319d2c7cf19216b607b8459612c4e027b643cf11b036937d36896bf76786","src/codegen/reductions/mask/fallback_impl.rs":"76547f396e55ef403327c77c314cf8db8c7a5c9b9819bfb925abeacf130249e5","src/codegen/reductions/mask/x86.rs":"36dcd8af4ab99730a078ed113d3955f74eb1a2876e2e6d9f224e0ff462c216d1","src/codegen/reductions/mask/x86/avx.rs":"3a40868b38c86e35aefb96d7578de6322efe89d8135e0366359b54ddd06f861a","src/codegen/reductions/mask/x86/avx2.rs":"677aed3f056285285daa3adff8bc65e739630b4424defa6d9665e160f027507e","src/codegen/reductions/mask/x86/sse.rs":"8522f6ed03f6c32dd577d4298df477c08aeaaa38563706f29096e1911ed731f2","src/codegen/reductions/mask/x86/sse2.rs":"54ec56e49b0c6841eccb719e4f310d65fe767c04136b2ec20bd8b9d7d9897b9e","src/codegen/shuffle.rs":"1ec2930f4e1acc43ac30b518af298d466a79e9e75734a51c380b7810efd1a27f","src/codegen/shuffle1_dyn.rs":"3f13ca1597378758d05106bf5ff3715eee531f3cb6d88f48b9182bd6c9386b51","src/codegen/swap_bytes.rs":"c67c86e91ca3fc77539e0efcea081a3c62548cccf503963ae408f2e86f4e6a21","src/codegen/v128.rs":"94226b31ec403d18d9d2fe06713f147c9c79e9b5f9105089088266313f843185","src/codegen/v16.rs":"ddec4ffb66b6f7aaffb9a1780c5ddba82557abd74f45073d335047e04cf74924","src/codegen/v256.rs":"6b63917f0444118d6b1595bff2045e59b97c4d24012bd575f69f1f0efc5a0241","src/codegen/v32.rs":"3477b3c5540aed86e61e2f5807dd31db947413cec9181c587d93ed6ec74f0eba","src/codegen/v512.rs":"5854f99d3aabc4cd42b28a20d9ce447756dc2ba024a409a69b6a8ae1f1842fc5","src/codegen/v64.rs":"e9e89caebfe63d10c0cbca61e4dfdba3b7e02ee0989170f80beed23237ddd950","src/codegen/vPtr.rs":"f0753b405cdc865bdf8e82c6505f299ea1f96136239ebbaf7f9ce93d310764b8","src/codegen/vSize.rs":"c89f5fdeb28ac4c8272ed1816fce03d9d95308cc32bb2533bd8b20cd5ac102ac","src/lib.rs":"dee6d850ba925493380d1f0c20615c21daa1e81c352798b6b42e47a4fbd17ce2","src/masks.rs":"70fc0abe4c2907ce2a491c574e1cfb9f3423385da2e1a923a48c9c13f8ba6ed8","src/sealed.rs":"ae7fdeaf5d84cd7710ed730ca72ca7eaba93df6cb0acb183e5c0a7327acf197f","src/testing.rs":"896669c08d8c801448a4d2fadc9d633eda0fbe879d229997e2a182e31278e469","src/testing/macros.rs":"403bbc5ecb7c786fe36156df302d0c07a8122408dbb15f7474d7682224ba1106","src/testing/utils.rs":"41912a92266dfe884647fc035e4242fd746100df8e839808ae0397af3759a3c8","src/v128.rs":"16cf9a8e7156b899ee9b9cd3f2dba9d13ec63289bea8c3ee9ae2e43ad9510288","src/v16.rs":"cb6465cf1e00bf530183af1819b9fe3d7eec978f8765d5e85d9b58a39a4b4045","src/v256.rs":"fe235017da18c7f3c361831c60e3173ad304d8ea1e95d64ebebc79da2d708511","src/v32.rs":"145d347855bac59b2de6508f9e594654e6c330423af9edc0e2ac8f4d1abdf45e","src/v512.rs":"f372f277f3e62eb5c945bb1c460333fdb17b6974fcc876633788ff53bded9599","src/v64.rs":"0b8079881b71575e3414be0b7f8f7eaba65281ba6732f2b2f61f73e95b6f48f7","src/vPtr.rs":"8b3e433d487180bb4304ff71245ecad90f0010f43e139a72027b672abe58facc","src/vSize.rs":"eda5aa020706cbf94d15bada41a0c2a35fc8f3f37cb7c2cd6f34d201399a495e","tests/endianness.rs":"2783d727e8ff8789211e03120634cd3ad9f8972fc484012681b5b63cf89408a7"},"package":"a1914cd452d8fccd6f9db48147b29fd4ae05bea9dc5d9ad578509f72415de282"} \ No newline at end of file diff --git a/vendor/packed_simd_2/Cargo.toml b/vendor/packed_simd_2/Cargo.toml index 61fbb47fc..86239f96c 100644 --- a/vendor/packed_simd_2/Cargo.toml +++ b/vendor/packed_simd_2/Cargo.toml @@ -3,28 +3,37 @@ # When uploading crates to the registry Cargo will automatically # "normalize" Cargo.toml files for maximal compatibility # with all versions of Cargo and also rewrite `path` dependencies -# to registry (e.g., crates.io) dependencies +# to registry (e.g., crates.io) dependencies. # -# If you believe there's an error in this file please file an -# issue against the rust-lang/cargo repository. If you're -# editing this file be aware that the upstream Cargo.toml -# will likely look very different (and much more reasonable) +# If you are reading this file be aware that the original Cargo.toml +# will likely look very different (and much more reasonable). +# See Cargo.toml.orig for the original contents. [package] edition = "2018" name = "packed_simd_2" -version = "0.3.4" -authors = ["Gonzalo Brito Gadeschi ", "Jubilee Young "] +version = "0.3.8" build = "build.rs" description = "Portable Packed SIMD vectors" -homepage = "https://github.com/rust-lang-nursery/packed_simd" +homepage = "https://github.com/rust-lang/packed_simd" documentation = "https://docs.rs/crate/packed_simd/" -keywords = ["simd", "vector", "portability"] -categories = ["hardware-support", "concurrency", "no-std", "data-structures"] -license = "MIT/Apache-2.0" -repository = "https://github.com/rust-lang-nursery/packed_simd" +readme = "README.md" +keywords = [ + "simd", + "vector", + "portability", +] +categories = [ + "hardware-support", + "concurrency", + "no-std", + "data-structures", +] +license = "MIT OR Apache-2.0" +repository = "https://github.com/rust-lang/packed_simd" + [dependencies.cfg-if] -version = "0.1.10" +version = "1.0.0" [dependencies.core_arch] version = "0.1.5" @@ -32,6 +41,7 @@ optional = true [dependencies.libm] version = "0.1.4" + [dev-dependencies.arrayvec] version = "^0.5" default-features = false @@ -43,14 +53,17 @@ version = "^0.1.3" default = [] into_bits = [] libcore_neon = [] + [target."cfg(target_arch = \"x86_64\")".dependencies.sleef-sys] version = "0.1.2" optional = true + [target.wasm32-unknown-unknown.dev-dependencies.wasm-bindgen] -version = "=0.2.52" +version = "=0.2.73" [target.wasm32-unknown-unknown.dev-dependencies.wasm-bindgen-test] -version = "=0.3.2" +version = "=0.3.23" + [badges.appveyor] repository = "rust-lang/packed_simd" diff --git a/vendor/packed_simd_2/README.md b/vendor/packed_simd_2/README.md index 138dad85c..eb3101c33 100644 --- a/vendor/packed_simd_2/README.md +++ b/vendor/packed_simd_2/README.md @@ -1,3 +1,16 @@ +# The Crates.io Version Can No Longer Be Updated! + +The original maintainer is out of contact, and the new maintainers (the Portable SIMD Project Group) do not have the appropriate crates.io permissions to issue updates. + +We are aware that the version available on crates.io is currently broken, and will not build. + +If you need to continue to use the crate, we have published a "next version" under an alternative name. + +Adjust your `[dependencies]` section of `Cargo.toml` to be the following: +```toml +packed_simd = { version = "0.3.8", package = "packed_simd_2" } +``` + # `Simd<[T; N]>` ## Implementation of [Rust RFC #2366: `std::simd`][rfc2366] @@ -5,7 +18,7 @@ [![Travis-CI Status]][travis] [![Latest Version]][crates.io] [![docs]][master_docs] **WARNING**: this crate only supports the most recent nightly Rust toolchain -and will be superceded by [stdsimd](https://github.com/rust-lang/stdsimd). +and will be superseded by [stdsimd](https://github.com/rust-lang/stdsimd). ## Documentation @@ -133,11 +146,11 @@ dual licensed as above, without any additional terms or conditions. [Travis-CI Status]: https://travis-ci.com/rust-lang/packed_simd.svg?branch=master [appveyor]: https://ci.appveyor.com/project/gnzlbg/packed-simd [Appveyor Status]: https://ci.appveyor.com/api/projects/status/hd7v9dvr442hgdix?svg=true -[Latest Version]: https://img.shields.io/crates/v/packed_simd.svg -[crates.io]: https://crates.io/crates/packed_simd -[docs]: https://docs.rs/packed_simd/badge.svg -[docs.rs]: https://docs.rs/packed_simd/ -[master_docs]: https://rust-lang-nursery.github.io/packed_simd/packed_simd/ +[Latest Version]: https://img.shields.io/crates/v/packed_simd_2.svg +[crates.io]: https://crates.io/crates/packed_simd_2 +[docs]: https://docs.rs/packed_simd_2/badge.svg +[docs.rs]: https://docs.rs/packed_simd_2 +[master_docs]: https://rust-lang-nursery.github.io/packed_simd/packed_simd_2/ [perf_guide]: https://rust-lang-nursery.github.io/packed_simd/perf-guide/ [rfc2366]: https://github.com/rust-lang/rfcs/pull/2366 [ISPC]: https://ispc.github.io/ diff --git a/vendor/packed_simd_2/build.rs b/vendor/packed_simd_2/build.rs index 9bdc8b542..e87298a2d 100644 --- a/vendor/packed_simd_2/build.rs +++ b/vendor/packed_simd_2/build.rs @@ -1,6 +1,5 @@ fn main() { - let target = std::env::var("TARGET") - .expect("TARGET environment variable not defined"); + let target = std::env::var("TARGET").expect("TARGET environment variable not defined"); if target.contains("neon") { println!("cargo:rustc-cfg=libcore_neon"); } diff --git a/vendor/packed_simd_2/ci/docker/wasm32-unknown-unknown/Dockerfile b/vendor/packed_simd_2/ci/docker/wasm32-unknown-unknown/Dockerfile index f905cf1a3..bd97170bc 100644 --- a/vendor/packed_simd_2/ci/docker/wasm32-unknown-unknown/Dockerfile +++ b/vendor/packed_simd_2/ci/docker/wasm32-unknown-unknown/Dockerfile @@ -17,14 +17,15 @@ RUN make -C wabt -j$(nproc) ENV PATH=$PATH:/wabt/bin # Install `wasm-bindgen-test-runner` -RUN curl -L https://github.com/rustwasm/wasm-bindgen/releases/download/0.2.19/wasm-bindgen-0.2.19-x86_64-unknown-linux-musl.tar.gz \ +RUN curl -L https://github.com/rustwasm/wasm-bindgen/releases/download/0.2.73/wasm-bindgen-0.2.73-x86_64-unknown-linux-musl.tar.gz \ | tar xzf - -ENV PATH=$PATH:/wasm-bindgen-0.2.19-x86_64-unknown-linux-musl +# Keep in sync with the version on Cargo.toml. +ENV PATH=$PATH:/wasm-bindgen-0.2.73-x86_64-unknown-linux-musl ENV CARGO_TARGET_WASM32_UNKNOWN_UNKNOWN_RUNNER=wasm-bindgen-test-runner # Install `node` -RUN curl https://nodejs.org/dist/v10.8.0/node-v10.8.0-linux-x64.tar.xz | tar xJf - -ENV PATH=$PATH:/node-v10.8.0-linux-x64/bin +RUN curl https://nodejs.org/dist/v14.16.0/node-v14.16.0-linux-x64.tar.xz | tar xJf - +ENV PATH=$PATH:/node-v14.16.0-linux-x64/bin # We use a shim linker that removes `--strip-debug` when passed to LLD. While # this typically results in invalid debug information in release mode it doesn't diff --git a/vendor/packed_simd_2/contributing.md b/vendor/packed_simd_2/contributing.md index 93fa92783..79af8c199 100644 --- a/vendor/packed_simd_2/contributing.md +++ b/vendor/packed_simd_2/contributing.md @@ -35,7 +35,7 @@ If LLVM is indeed the cause, the issue will be reported upstream to the ## Submitting Pull Requests New code is submitted to the crate using GitHub's [pull request] mechanism. -You should first fork this repository, make your changes (preferrably in a new +You should first fork this repository, make your changes (preferably in a new branch), then use GitHub's web UI to create a new PR. [pull request]: https://help.github.com/articles/about-pull-requests/ diff --git a/vendor/packed_simd_2/perf-guide/src/target-feature/rustflags.md b/vendor/packed_simd_2/perf-guide/src/target-feature/rustflags.md index e2e806e08..f4c1d1304 100644 --- a/vendor/packed_simd_2/perf-guide/src/target-feature/rustflags.md +++ b/vendor/packed_simd_2/perf-guide/src/target-feature/rustflags.md @@ -15,7 +15,7 @@ There are two flags which can be used to enable specific vector extensions: - Provides the compiler with a comma-separated set of instruction extensions to enable. - **Example**: Use `-C target-features=+sse3,+avx` to enable generating instructions + **Example**: Use `-C target-feature=+sse3,+avx` to enable generating instructions for [Streaming SIMD Extensions 3](https://en.wikipedia.org/wiki/SSE3) and [Advanced Vector Extensions](https://en.wikipedia.org/wiki/Advanced_Vector_Extensions). @@ -33,9 +33,9 @@ There are two flags which can be used to enable specific vector extensions: - Note that all CPU features are independent, and will have to be enabled individually. - **Example**: Setting `-C target-features=+avx2` will _not_ enable `fma`, even though + **Example**: Setting `-C target-feature=+avx2` will _not_ enable `fma`, even though all CPUs which support AVX2 also support FMA. To enable both, one has to use - `-C target-features=+avx2,+fma` + `-C target-feature=+avx2,+fma` - Some features also depend on other features, which need to be enabled for the target instructions to be generated. diff --git a/vendor/packed_simd_2/rustfmt.toml b/vendor/packed_simd_2/rustfmt.toml index 5b400a4ce..7316518b9 100644 --- a/vendor/packed_simd_2/rustfmt.toml +++ b/vendor/packed_simd_2/rustfmt.toml @@ -1,7 +1,5 @@ -max_width = 79 +max_width = 110 use_small_heuristics = "Max" wrap_comments = true -comment_width = 79 -fn_args_density = "Compressed" edition = "2018" error_on_line_overflow = true \ No newline at end of file diff --git a/vendor/packed_simd_2/src/api.rs b/vendor/packed_simd_2/src/api.rs index 953685925..262fc4ee6 100644 --- a/vendor/packed_simd_2/src/api.rs +++ b/vendor/packed_simd_2/src/api.rs @@ -2,7 +2,7 @@ #[macro_use] mod bitmask; -crate mod cast; +pub(crate) mod cast; #[macro_use] mod cmp; #[macro_use] @@ -37,7 +37,7 @@ mod swap_bytes; mod bit_manip; #[cfg(feature = "into_bits")] -crate mod into_bits; +pub(crate) mod into_bits; macro_rules! impl_i { ([$elem_ty:ident; $elem_n:expr]: $tuple_id:ident, $mask_ty:ident diff --git a/vendor/packed_simd_2/src/api/cast/v128.rs b/vendor/packed_simd_2/src/api/cast/v128.rs index ab47ddc00..2e10b97b7 100644 --- a/vendor/packed_simd_2/src/api/cast/v128.rs +++ b/vendor/packed_simd_2/src/api/cast/v128.rs @@ -3,74 +3,297 @@ use crate::*; -impl_from_cast!( - i8x16[test_v128]: u8x16, m8x16, i16x16, u16x16, m16x16, i32x16, u32x16, f32x16, m32x16 -); -impl_from_cast!( - u8x16[test_v128]: i8x16, m8x16, i16x16, u16x16, m16x16, i32x16, u32x16, f32x16, m32x16 -); -impl_from_cast_mask!( - m8x16[test_v128]: i8x16, u8x16, i16x16, u16x16, m16x16, i32x16, u32x16, f32x16, m32x16 -); +impl_from_cast!(i8x16[test_v128]: u8x16, m8x16, i16x16, u16x16, m16x16, i32x16, u32x16, f32x16, m32x16); +impl_from_cast!(u8x16[test_v128]: i8x16, m8x16, i16x16, u16x16, m16x16, i32x16, u32x16, f32x16, m32x16); +impl_from_cast_mask!(m8x16[test_v128]: i8x16, u8x16, i16x16, u16x16, m16x16, i32x16, u32x16, f32x16, m32x16); impl_from_cast!( - i16x8[test_v128]: i8x8, u8x8, m8x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8, - i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8 + i16x8[test_v128]: i8x8, + u8x8, + m8x8, + u16x8, + m16x8, + i32x8, + u32x8, + f32x8, + m32x8, + i64x8, + u64x8, + f64x8, + m64x8, + isizex8, + usizex8, + msizex8 ); impl_from_cast!( - u16x8[test_v128]: i8x8, u8x8, m8x8, i16x8, m16x8, i32x8, u32x8, f32x8, m32x8, - i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8 + u16x8[test_v128]: i8x8, + u8x8, + m8x8, + i16x8, + m16x8, + i32x8, + u32x8, + f32x8, + m32x8, + i64x8, + u64x8, + f64x8, + m64x8, + isizex8, + usizex8, + msizex8 ); impl_from_cast_mask!( - m16x8[test_v128]: i8x8, u8x8, m8x8, i16x8, u16x8, i32x8, u32x8, f32x8, m32x8, - i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8 + m16x8[test_v128]: i8x8, + u8x8, + m8x8, + i16x8, + u16x8, + i32x8, + u32x8, + f32x8, + m32x8, + i64x8, + u64x8, + f64x8, + m64x8, + isizex8, + usizex8, + msizex8 ); impl_from_cast!( - i32x4[test_v128]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, u32x4, f32x4, m32x4, - i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4 + i32x4[test_v128]: i8x4, + u8x4, + m8x4, + i16x4, + u16x4, + m16x4, + u32x4, + f32x4, + m32x4, + i64x4, + u64x4, + f64x4, + m64x4, + i128x4, + u128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast!( - u32x4[test_v128]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, f32x4, m32x4, - i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4 + u32x4[test_v128]: i8x4, + u8x4, + m8x4, + i16x4, + u16x4, + m16x4, + i32x4, + f32x4, + m32x4, + i64x4, + u64x4, + f64x4, + m64x4, + i128x4, + u128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast!( - f32x4[test_v128]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, m32x4, - i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4 + f32x4[test_v128]: i8x4, + u8x4, + m8x4, + i16x4, + u16x4, + m16x4, + i32x4, + u32x4, + m32x4, + i64x4, + u64x4, + f64x4, + m64x4, + i128x4, + u128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast_mask!( - m32x4[test_v128]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, - i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4 + m32x4[test_v128]: i8x4, + u8x4, + m8x4, + i16x4, + u16x4, + m16x4, + i32x4, + u32x4, + f32x4, + i64x4, + u64x4, + f64x4, + m64x4, + i128x4, + u128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast!( - i64x2[test_v128]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2, - u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2 + i64x2[test_v128]: i8x2, + u8x2, + m8x2, + i16x2, + u16x2, + m16x2, + i32x2, + u32x2, + f32x2, + m32x2, + u64x2, + f64x2, + m64x2, + i128x2, + u128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); impl_from_cast!( - u64x2[test_v128]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2, - i64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2 + u64x2[test_v128]: i8x2, + u8x2, + m8x2, + i16x2, + u16x2, + m16x2, + i32x2, + u32x2, + f32x2, + m32x2, + i64x2, + f64x2, + m64x2, + i128x2, + u128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); impl_from_cast!( - f64x2[test_v128]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2, - i64x2, u64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2 + f64x2[test_v128]: i8x2, + u8x2, + m8x2, + i16x2, + u16x2, + m16x2, + i32x2, + u32x2, + f32x2, + m32x2, + i64x2, + u64x2, + m64x2, + i128x2, + u128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); impl_from_cast_mask!( - m64x2[test_v128]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2, - i64x2, u64x2, f64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2 + m64x2[test_v128]: i8x2, + u8x2, + m8x2, + i16x2, + u16x2, + m16x2, + i32x2, + u32x2, + f32x2, + m32x2, + i64x2, + u64x2, + f64x2, + i128x2, + u128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); impl_from_cast!( - isizex2[test_v128]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2, - i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, usizex2, msizex2 + isizex2[test_v128]: i8x2, + u8x2, + m8x2, + i16x2, + u16x2, + m16x2, + i32x2, + u32x2, + f32x2, + m32x2, + i64x2, + u64x2, + f64x2, + m64x2, + i128x2, + u128x2, + m128x2, + usizex2, + msizex2 ); impl_from_cast!( - usizex2[test_v128]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2, - i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, msizex2 + usizex2[test_v128]: i8x2, + u8x2, + m8x2, + i16x2, + u16x2, + m16x2, + i32x2, + u32x2, + f32x2, + m32x2, + i64x2, + u64x2, + f64x2, + m64x2, + i128x2, + u128x2, + m128x2, + isizex2, + msizex2 ); impl_from_cast_mask!( - msizex2[test_v128]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2, - i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2 + msizex2[test_v128]: i8x2, + u8x2, + m8x2, + i16x2, + u16x2, + m16x2, + i32x2, + u32x2, + f32x2, + m32x2, + i64x2, + u64x2, + f64x2, + m64x2, + i128x2, + u128x2, + m128x2, + isizex2, + usizex2 ); // FIXME[test_v128]: 64-bit single element vectors into_cast impls diff --git a/vendor/packed_simd_2/src/api/cast/v16.rs b/vendor/packed_simd_2/src/api/cast/v16.rs index cf974bb08..896febacb 100644 --- a/vendor/packed_simd_2/src/api/cast/v16.rs +++ b/vendor/packed_simd_2/src/api/cast/v16.rs @@ -4,14 +4,65 @@ use crate::*; impl_from_cast!( - i8x2[test_v16]: u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2, - i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2 + i8x2[test_v16]: u8x2, + m8x2, + i16x2, + u16x2, + m16x2, + i32x2, + u32x2, + f32x2, + m32x2, + i64x2, + u64x2, + f64x2, + m64x2, + i128x2, + u128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); impl_from_cast!( - u8x2[test_v16]: i8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2, - i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2 + u8x2[test_v16]: i8x2, + m8x2, + i16x2, + u16x2, + m16x2, + i32x2, + u32x2, + f32x2, + m32x2, + i64x2, + u64x2, + f64x2, + m64x2, + i128x2, + u128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); impl_from_cast_mask!( - m8x2[test_v16]: i8x2, u8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2, - i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2 + m8x2[test_v16]: i8x2, + u8x2, + i16x2, + u16x2, + m16x2, + i32x2, + u32x2, + f32x2, + m32x2, + i64x2, + u64x2, + f64x2, + m64x2, + i128x2, + u128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); diff --git a/vendor/packed_simd_2/src/api/cast/v256.rs b/vendor/packed_simd_2/src/api/cast/v256.rs index 9389dcb4c..fe0c835e3 100644 --- a/vendor/packed_simd_2/src/api/cast/v256.rs +++ b/vendor/packed_simd_2/src/api/cast/v256.rs @@ -7,75 +7,292 @@ impl_from_cast!(i8x32[test_v256]: u8x32, m8x32, i16x32, u16x32, m16x32); impl_from_cast!(u8x32[test_v256]: i8x32, m8x32, i16x32, u16x32, m16x32); impl_from_cast_mask!(m8x32[test_v256]: i8x32, u8x32, i16x32, u16x32, m16x32); -impl_from_cast!( - i16x16[test_v256]: i8x16, u8x16, m8x16, u16x16, m16x16, - i32x16, u32x16, f32x16, m32x16 -); -impl_from_cast!( - u16x16[test_v256]: i8x16, u8x16, m8x16, i16x16, m16x16, - i32x16, u32x16, f32x16, m32x16 -); -impl_from_cast_mask!( - m16x16[test_v256]: i8x16, u8x16, m8x16, i16x16, u16x16, - i32x16, u32x16, f32x16, m32x16 -); +impl_from_cast!(i16x16[test_v256]: i8x16, u8x16, m8x16, u16x16, m16x16, i32x16, u32x16, f32x16, m32x16); +impl_from_cast!(u16x16[test_v256]: i8x16, u8x16, m8x16, i16x16, m16x16, i32x16, u32x16, f32x16, m32x16); +impl_from_cast_mask!(m16x16[test_v256]: i8x16, u8x16, m8x16, i16x16, u16x16, i32x16, u32x16, f32x16, m32x16); impl_from_cast!( - i32x8[test_v256]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, u32x8, f32x8, m32x8, - i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8 + i32x8[test_v256]: i8x8, + u8x8, + m8x8, + i16x8, + u16x8, + m16x8, + u32x8, + f32x8, + m32x8, + i64x8, + u64x8, + f64x8, + m64x8, + isizex8, + usizex8, + msizex8 ); impl_from_cast!( - u32x8[test_v256]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, f32x8, m32x8, - i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8 + u32x8[test_v256]: i8x8, + u8x8, + m8x8, + i16x8, + u16x8, + m16x8, + i32x8, + f32x8, + m32x8, + i64x8, + u64x8, + f64x8, + m64x8, + isizex8, + usizex8, + msizex8 ); impl_from_cast!( - f32x8[test_v256]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, m32x8, - i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8 + f32x8[test_v256]: i8x8, + u8x8, + m8x8, + i16x8, + u16x8, + m16x8, + i32x8, + u32x8, + m32x8, + i64x8, + u64x8, + f64x8, + m64x8, + isizex8, + usizex8, + msizex8 ); impl_from_cast_mask!( - m32x8[test_v256]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, - i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8 + m32x8[test_v256]: i8x8, + u8x8, + m8x8, + i16x8, + u16x8, + m16x8, + i32x8, + u32x8, + f32x8, + i64x8, + u64x8, + f64x8, + m64x8, + isizex8, + usizex8, + msizex8 ); impl_from_cast!( - i64x4[test_v256]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4, - u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4 + i64x4[test_v256]: i8x4, + u8x4, + m8x4, + i16x4, + u16x4, + m16x4, + i32x4, + u32x4, + f32x4, + m32x4, + u64x4, + f64x4, + m64x4, + i128x4, + u128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast!( - u64x4[test_v256]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4, - i64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4 + u64x4[test_v256]: i8x4, + u8x4, + m8x4, + i16x4, + u16x4, + m16x4, + i32x4, + u32x4, + f32x4, + m32x4, + i64x4, + f64x4, + m64x4, + i128x4, + u128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast!( - f64x4[test_v256]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4, - i64x4, u64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4 + f64x4[test_v256]: i8x4, + u8x4, + m8x4, + i16x4, + u16x4, + m16x4, + i32x4, + u32x4, + f32x4, + m32x4, + i64x4, + u64x4, + m64x4, + i128x4, + u128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast_mask!( - m64x4[test_v256]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4, - i64x4, u64x4, f64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4 + m64x4[test_v256]: i8x4, + u8x4, + m8x4, + i16x4, + u16x4, + m16x4, + i32x4, + u32x4, + f32x4, + m32x4, + i64x4, + u64x4, + f64x4, + i128x4, + u128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast!( - i128x2[test_v256]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2, - i64x2, u64x2, f64x2, m64x2, u128x2, m128x2, isizex2, usizex2, msizex2 + i128x2[test_v256]: i8x2, + u8x2, + m8x2, + i16x2, + u16x2, + m16x2, + i32x2, + u32x2, + f32x2, + m32x2, + i64x2, + u64x2, + f64x2, + m64x2, + u128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); impl_from_cast!( - u128x2[test_v256]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2, - i64x2, u64x2, f64x2, m64x2, i128x2, m128x2, isizex2, usizex2, msizex2 + u128x2[test_v256]: i8x2, + u8x2, + m8x2, + i16x2, + u16x2, + m16x2, + i32x2, + u32x2, + f32x2, + m32x2, + i64x2, + u64x2, + f64x2, + m64x2, + i128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); impl_from_cast_mask!( - m128x2[test_v256]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2, - i64x2, u64x2, m64x2, f64x2, i128x2, u128x2, isizex2, usizex2, msizex2 + m128x2[test_v256]: i8x2, + u8x2, + m8x2, + i16x2, + u16x2, + m16x2, + i32x2, + u32x2, + f32x2, + m32x2, + i64x2, + u64x2, + m64x2, + f64x2, + i128x2, + u128x2, + isizex2, + usizex2, + msizex2 ); impl_from_cast!( - isizex4[test_v256]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4, - i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, usizex4, msizex4 + isizex4[test_v256]: i8x4, + u8x4, + m8x4, + i16x4, + u16x4, + m16x4, + i32x4, + u32x4, + f32x4, + m32x4, + i64x4, + u64x4, + f64x4, + m64x4, + i128x4, + u128x4, + m128x4, + usizex4, + msizex4 ); impl_from_cast!( - usizex4[test_v256]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4, - i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, msizex4 + usizex4[test_v256]: i8x4, + u8x4, + m8x4, + i16x4, + u16x4, + m16x4, + i32x4, + u32x4, + f32x4, + m32x4, + i64x4, + u64x4, + f64x4, + m64x4, + i128x4, + u128x4, + m128x4, + isizex4, + msizex4 ); impl_from_cast_mask!( - msizex4[test_v256]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4, - i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4 + msizex4[test_v256]: i8x4, + u8x4, + m8x4, + i16x4, + u16x4, + m16x4, + i32x4, + u32x4, + f32x4, + m32x4, + i64x4, + u64x4, + f64x4, + m64x4, + i128x4, + u128x4, + m128x4, + isizex4, + usizex4 ); diff --git a/vendor/packed_simd_2/src/api/cast/v32.rs b/vendor/packed_simd_2/src/api/cast/v32.rs index 2b254ba0c..4ad1cbf74 100644 --- a/vendor/packed_simd_2/src/api/cast/v32.rs +++ b/vendor/packed_simd_2/src/api/cast/v32.rs @@ -4,27 +4,129 @@ use crate::*; impl_from_cast!( - i8x4[test_v32]: u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4, - i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4 + i8x4[test_v32]: u8x4, + m8x4, + i16x4, + u16x4, + m16x4, + i32x4, + u32x4, + f32x4, + m32x4, + i64x4, + u64x4, + f64x4, + m64x4, + i128x4, + u128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast!( - u8x4[test_v32]: i8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4, - i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4 + u8x4[test_v32]: i8x4, + m8x4, + i16x4, + u16x4, + m16x4, + i32x4, + u32x4, + f32x4, + m32x4, + i64x4, + u64x4, + f64x4, + m64x4, + i128x4, + u128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast_mask!( - m8x4[test_v32]: i8x4, u8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4, - i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4 + m8x4[test_v32]: i8x4, + u8x4, + i16x4, + u16x4, + m16x4, + i32x4, + u32x4, + f32x4, + m32x4, + i64x4, + u64x4, + f64x4, + m64x4, + i128x4, + u128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast!( - i16x2[test_v32]: i8x2, u8x2, m8x2, u16x2, m16x2, i32x2, u32x2, f32x2, m32x2, - i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2 + i16x2[test_v32]: i8x2, + u8x2, + m8x2, + u16x2, + m16x2, + i32x2, + u32x2, + f32x2, + m32x2, + i64x2, + u64x2, + f64x2, + m64x2, + i128x2, + u128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); impl_from_cast!( - u16x2[test_v32]: i8x2, u8x2, m8x2, i16x2, m16x2, i32x2, u32x2, f32x2, m32x2, - i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2 + u16x2[test_v32]: i8x2, + u8x2, + m8x2, + i16x2, + m16x2, + i32x2, + u32x2, + f32x2, + m32x2, + i64x2, + u64x2, + f64x2, + m64x2, + i128x2, + u128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); impl_from_cast_mask!( - m16x2[test_v32]: i8x2, u8x2, m8x2, i16x2, u16x2, i32x2, u32x2, f32x2, m32x2, - i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2 + m16x2[test_v32]: i8x2, + u8x2, + m8x2, + i16x2, + u16x2, + i32x2, + u32x2, + f32x2, + m32x2, + i64x2, + u64x2, + f64x2, + m64x2, + i128x2, + u128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); diff --git a/vendor/packed_simd_2/src/api/cast/v512.rs b/vendor/packed_simd_2/src/api/cast/v512.rs index 5a10ab066..b64605045 100644 --- a/vendor/packed_simd_2/src/api/cast/v512.rs +++ b/vendor/packed_simd_2/src/api/cast/v512.rs @@ -11,58 +11,199 @@ impl_from_cast!(i16x32[test_v512]: i8x32, u8x32, m8x32, u16x32, m16x32); impl_from_cast!(u16x32[test_v512]: i8x32, u8x32, m8x32, i16x32, m16x32); impl_from_cast_mask!(m16x32[test_v512]: i8x32, u8x32, m8x32, i16x32, u16x32); -impl_from_cast!( - i32x16[test_v512]: i8x16, u8x16, m8x16, i16x16, u16x16, m16x16, u32x16, f32x16, m32x16 -); -impl_from_cast!( - u32x16[test_v512]: i8x16, u8x16, m8x16, i16x16, u16x16, m16x16, i32x16, f32x16, m32x16 -); -impl_from_cast!( - f32x16[test_v512]: i8x16, u8x16, m8x16, i16x16, u16x16, m16x16, i32x16, u32x16, m32x16 -); -impl_from_cast_mask!( - m32x16[test_v512]: i8x16, u8x16, m8x16, i16x16, u16x16, m16x16, i32x16, u32x16, f32x16 -); +impl_from_cast!(i32x16[test_v512]: i8x16, u8x16, m8x16, i16x16, u16x16, m16x16, u32x16, f32x16, m32x16); +impl_from_cast!(u32x16[test_v512]: i8x16, u8x16, m8x16, i16x16, u16x16, m16x16, i32x16, f32x16, m32x16); +impl_from_cast!(f32x16[test_v512]: i8x16, u8x16, m8x16, i16x16, u16x16, m16x16, i32x16, u32x16, m32x16); +impl_from_cast_mask!(m32x16[test_v512]: i8x16, u8x16, m8x16, i16x16, u16x16, m16x16, i32x16, u32x16, f32x16); impl_from_cast!( - i64x8[test_v512]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8, - u64x8, f64x8, m64x8, isizex8, usizex8, msizex8 + i64x8[test_v512]: i8x8, + u8x8, + m8x8, + i16x8, + u16x8, + m16x8, + i32x8, + u32x8, + f32x8, + m32x8, + u64x8, + f64x8, + m64x8, + isizex8, + usizex8, + msizex8 ); impl_from_cast!( - u64x8[test_v512]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8, - i64x8, f64x8, m64x8, isizex8, usizex8, msizex8 + u64x8[test_v512]: i8x8, + u8x8, + m8x8, + i16x8, + u16x8, + m16x8, + i32x8, + u32x8, + f32x8, + m32x8, + i64x8, + f64x8, + m64x8, + isizex8, + usizex8, + msizex8 ); impl_from_cast!( - f64x8[test_v512]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8, - i64x8, u64x8, m64x8, isizex8, usizex8, msizex8 + f64x8[test_v512]: i8x8, + u8x8, + m8x8, + i16x8, + u16x8, + m16x8, + i32x8, + u32x8, + f32x8, + m32x8, + i64x8, + u64x8, + m64x8, + isizex8, + usizex8, + msizex8 ); impl_from_cast_mask!( - m64x8[test_v512]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8, - i64x8, u64x8, f64x8, isizex8, usizex8, msizex8 + m64x8[test_v512]: i8x8, + u8x8, + m8x8, + i16x8, + u16x8, + m16x8, + i32x8, + u32x8, + f32x8, + m32x8, + i64x8, + u64x8, + f64x8, + isizex8, + usizex8, + msizex8 ); impl_from_cast!( - i128x4[test_v512]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4, - i64x4, u64x4, f64x4, m64x4, u128x4, m128x4, isizex4, usizex4, msizex4 + i128x4[test_v512]: i8x4, + u8x4, + m8x4, + i16x4, + u16x4, + m16x4, + i32x4, + u32x4, + f32x4, + m32x4, + i64x4, + u64x4, + f64x4, + m64x4, + u128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast!( - u128x4[test_v512]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4, - i64x4, u64x4, f64x4, m64x4, i128x4, m128x4, isizex4, usizex4, msizex4 + u128x4[test_v512]: i8x4, + u8x4, + m8x4, + i16x4, + u16x4, + m16x4, + i32x4, + u32x4, + f32x4, + m32x4, + i64x4, + u64x4, + f64x4, + m64x4, + i128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast_mask!( - m128x4[test_v512]: i8x4, u8x4, m8x4, i16x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4, - i64x4, u64x4, m64x4, f64x4, i128x4, u128x4, isizex4, usizex4, msizex4 + m128x4[test_v512]: i8x4, + u8x4, + m8x4, + i16x4, + u16x4, + m16x4, + i32x4, + u32x4, + f32x4, + m32x4, + i64x4, + u64x4, + m64x4, + f64x4, + i128x4, + u128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast!( - isizex8[test_v512]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8, - i64x8, u64x8, f64x8, m64x8, usizex8, msizex8 + isizex8[test_v512]: i8x8, + u8x8, + m8x8, + i16x8, + u16x8, + m16x8, + i32x8, + u32x8, + f32x8, + m32x8, + i64x8, + u64x8, + f64x8, + m64x8, + usizex8, + msizex8 ); impl_from_cast!( - usizex8[test_v512]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8, - i64x8, u64x8, f64x8, m64x8, isizex8, msizex8 + usizex8[test_v512]: i8x8, + u8x8, + m8x8, + i16x8, + u16x8, + m16x8, + i32x8, + u32x8, + f32x8, + m32x8, + i64x8, + u64x8, + f64x8, + m64x8, + isizex8, + msizex8 ); impl_from_cast_mask!( - msizex8[test_v512]: i8x8, u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8, - i64x8, u64x8, f64x8, m64x8, isizex8, usizex8 + msizex8[test_v512]: i8x8, + u8x8, + m8x8, + i16x8, + u16x8, + m16x8, + i32x8, + u32x8, + f32x8, + m32x8, + i64x8, + u64x8, + f64x8, + m64x8, + isizex8, + usizex8 ); diff --git a/vendor/packed_simd_2/src/api/cast/v64.rs b/vendor/packed_simd_2/src/api/cast/v64.rs index 192a4638a..b23d1a491 100644 --- a/vendor/packed_simd_2/src/api/cast/v64.rs +++ b/vendor/packed_simd_2/src/api/cast/v64.rs @@ -4,44 +4,205 @@ use crate::*; impl_from_cast!( - i8x8[test_v64]: u8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8, - i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8 + i8x8[test_v64]: u8x8, + m8x8, + i16x8, + u16x8, + m16x8, + i32x8, + u32x8, + f32x8, + m32x8, + i64x8, + u64x8, + f64x8, + m64x8, + isizex8, + usizex8, + msizex8 ); impl_from_cast!( - u8x8[test_v64]: i8x8, m8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8, - i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8 + u8x8[test_v64]: i8x8, + m8x8, + i16x8, + u16x8, + m16x8, + i32x8, + u32x8, + f32x8, + m32x8, + i64x8, + u64x8, + f64x8, + m64x8, + isizex8, + usizex8, + msizex8 ); impl_from_cast_mask!( - m8x8[test_v64]: i8x8, u8x8, i16x8, u16x8, m16x8, i32x8, u32x8, f32x8, m32x8, - i64x8, u64x8, f64x8, m64x8, isizex8, usizex8, msizex8 + m8x8[test_v64]: i8x8, + u8x8, + i16x8, + u16x8, + m16x8, + i32x8, + u32x8, + f32x8, + m32x8, + i64x8, + u64x8, + f64x8, + m64x8, + isizex8, + usizex8, + msizex8 ); impl_from_cast!( - i16x4[test_v64]: i8x4, u8x4, m8x4, u16x4, m16x4, i32x4, u32x4, f32x4, m32x4, - i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4 + i16x4[test_v64]: i8x4, + u8x4, + m8x4, + u16x4, + m16x4, + i32x4, + u32x4, + f32x4, + m32x4, + i64x4, + u64x4, + f64x4, + m64x4, + i128x4, + u128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast!( - u16x4[test_v64]: i8x4, u8x4, m8x4, i16x4, m16x4, i32x4, u32x4, f32x4, m32x4, - i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4 + u16x4[test_v64]: i8x4, + u8x4, + m8x4, + i16x4, + m16x4, + i32x4, + u32x4, + f32x4, + m32x4, + i64x4, + u64x4, + f64x4, + m64x4, + i128x4, + u128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast_mask!( - m16x4[test_v64]: i8x4, u8x4, m8x4, i16x4, u16x4, i32x4, u32x4, f32x4, m32x4, - i64x4, u64x4, f64x4, m64x4, i128x4, u128x4, m128x4, isizex4, usizex4, msizex4 + m16x4[test_v64]: i8x4, + u8x4, + m8x4, + i16x4, + u16x4, + i32x4, + u32x4, + f32x4, + m32x4, + i64x4, + u64x4, + f64x4, + m64x4, + i128x4, + u128x4, + m128x4, + isizex4, + usizex4, + msizex4 ); impl_from_cast!( - i32x2[test_v64]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, u32x2, f32x2, m32x2, - i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2 + i32x2[test_v64]: i8x2, + u8x2, + m8x2, + i16x2, + u16x2, + m16x2, + u32x2, + f32x2, + m32x2, + i64x2, + u64x2, + f64x2, + m64x2, + i128x2, + u128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); impl_from_cast!( - u32x2[test_v64]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, f32x2, m32x2, - i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2 + u32x2[test_v64]: i8x2, + u8x2, + m8x2, + i16x2, + u16x2, + m16x2, + i32x2, + f32x2, + m32x2, + i64x2, + u64x2, + f64x2, + m64x2, + i128x2, + u128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); impl_from_cast!( - f32x2[test_v64]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, m32x2, - i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2 + f32x2[test_v64]: i8x2, + u8x2, + m8x2, + i16x2, + u16x2, + m16x2, + i32x2, + u32x2, + m32x2, + i64x2, + u64x2, + f64x2, + m64x2, + i128x2, + u128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); impl_from_cast_mask!( - m32x2[test_v64]: i8x2, u8x2, m8x2, i16x2, u16x2, m16x2, i32x2, u32x2, f32x2, - i64x2, u64x2, f64x2, m64x2, i128x2, u128x2, m128x2, isizex2, usizex2, msizex2 + m32x2[test_v64]: i8x2, + u8x2, + m8x2, + i16x2, + u16x2, + m16x2, + i32x2, + u32x2, + f32x2, + i64x2, + u64x2, + f64x2, + m64x2, + i128x2, + u128x2, + m128x2, + isizex2, + usizex2, + msizex2 ); diff --git a/vendor/packed_simd_2/src/api/cmp/partial_eq.rs b/vendor/packed_simd_2/src/api/cmp/partial_eq.rs index 1712a0de5..d69dd4742 100644 --- a/vendor/packed_simd_2/src/api/cmp/partial_eq.rs +++ b/vendor/packed_simd_2/src/api/cmp/partial_eq.rs @@ -21,9 +21,7 @@ macro_rules! impl_cmp_partial_eq { // FIXME: https://github.com/rust-lang-nursery/rust-clippy/issues/2892 #[allow(clippy::partialeq_ne_impl)] - impl crate::cmp::PartialEq> - for LexicographicallyOrdered<$id> - { + impl crate::cmp::PartialEq> for LexicographicallyOrdered<$id> { #[inline] fn eq(&self, other: &Self) -> bool { self.0 == other.0 diff --git a/vendor/packed_simd_2/src/api/cmp/partial_ord.rs b/vendor/packed_simd_2/src/api/cmp/partial_ord.rs index a2292918b..76ed9ebe4 100644 --- a/vendor/packed_simd_2/src/api/cmp/partial_ord.rs +++ b/vendor/packed_simd_2/src/api/cmp/partial_ord.rs @@ -12,13 +12,9 @@ macro_rules! impl_cmp_partial_ord { } } - impl crate::cmp::PartialOrd> - for LexicographicallyOrdered<$id> - { + impl crate::cmp::PartialOrd> for LexicographicallyOrdered<$id> { #[inline] - fn partial_cmp( - &self, other: &Self, - ) -> Option { + fn partial_cmp(&self, other: &Self) -> Option { if PartialEq::eq(self, other) { Some(crate::cmp::Ordering::Equal) } else if PartialOrd::lt(self, other) { diff --git a/vendor/packed_simd_2/src/api/fmt/binary.rs b/vendor/packed_simd_2/src/api/fmt/binary.rs index b60769082..91c082555 100644 --- a/vendor/packed_simd_2/src/api/fmt/binary.rs +++ b/vendor/packed_simd_2/src/api/fmt/binary.rs @@ -4,9 +4,7 @@ macro_rules! impl_fmt_binary { ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => { impl crate::fmt::Binary for $id { #[allow(clippy::missing_inline_in_public_items)] - fn fmt( - &self, f: &mut crate::fmt::Formatter<'_>, - ) -> crate::fmt::Result { + fn fmt(&self, f: &mut crate::fmt::Formatter<'_>) -> crate::fmt::Result { write!(f, "{}(", stringify!($id))?; for i in 0..$elem_count { if i > 0 { diff --git a/vendor/packed_simd_2/src/api/fmt/debug.rs b/vendor/packed_simd_2/src/api/fmt/debug.rs index ad0b8a59a..1e209b3bf 100644 --- a/vendor/packed_simd_2/src/api/fmt/debug.rs +++ b/vendor/packed_simd_2/src/api/fmt/debug.rs @@ -44,9 +44,7 @@ macro_rules! impl_fmt_debug { ([$elem_ty:ty; $elem_count:expr]: $id:ident | $test_tt:tt) => { impl crate::fmt::Debug for $id { #[allow(clippy::missing_inline_in_public_items)] - fn fmt( - &self, f: &mut crate::fmt::Formatter<'_>, - ) -> crate::fmt::Result { + fn fmt(&self, f: &mut crate::fmt::Formatter<'_>) -> crate::fmt::Result { write!(f, "{}(", stringify!($id))?; for i in 0..$elem_count { if i > 0 { diff --git a/vendor/packed_simd_2/src/api/fmt/lower_hex.rs b/vendor/packed_simd_2/src/api/fmt/lower_hex.rs index 5a7aa14b5..8f11d3119 100644 --- a/vendor/packed_simd_2/src/api/fmt/lower_hex.rs +++ b/vendor/packed_simd_2/src/api/fmt/lower_hex.rs @@ -4,9 +4,7 @@ macro_rules! impl_fmt_lower_hex { ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => { impl crate::fmt::LowerHex for $id { #[allow(clippy::missing_inline_in_public_items)] - fn fmt( - &self, f: &mut crate::fmt::Formatter<'_>, - ) -> crate::fmt::Result { + fn fmt(&self, f: &mut crate::fmt::Formatter<'_>) -> crate::fmt::Result { write!(f, "{}(", stringify!($id))?; for i in 0..$elem_count { if i > 0 { diff --git a/vendor/packed_simd_2/src/api/fmt/octal.rs b/vendor/packed_simd_2/src/api/fmt/octal.rs index 83ac8abc7..e708e094c 100644 --- a/vendor/packed_simd_2/src/api/fmt/octal.rs +++ b/vendor/packed_simd_2/src/api/fmt/octal.rs @@ -4,9 +4,7 @@ macro_rules! impl_fmt_octal { ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => { impl crate::fmt::Octal for $id { #[allow(clippy::missing_inline_in_public_items)] - fn fmt( - &self, f: &mut crate::fmt::Formatter<'_>, - ) -> crate::fmt::Result { + fn fmt(&self, f: &mut crate::fmt::Formatter<'_>) -> crate::fmt::Result { write!(f, "{}(", stringify!($id))?; for i in 0..$elem_count { if i > 0 { diff --git a/vendor/packed_simd_2/src/api/fmt/upper_hex.rs b/vendor/packed_simd_2/src/api/fmt/upper_hex.rs index aa88f673a..5ad455706 100644 --- a/vendor/packed_simd_2/src/api/fmt/upper_hex.rs +++ b/vendor/packed_simd_2/src/api/fmt/upper_hex.rs @@ -4,9 +4,7 @@ macro_rules! impl_fmt_upper_hex { ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => { impl crate::fmt::UpperHex for $id { #[allow(clippy::missing_inline_in_public_items)] - fn fmt( - &self, f: &mut crate::fmt::Formatter<'_>, - ) -> crate::fmt::Result { + fn fmt(&self, f: &mut crate::fmt::Formatter<'_>) -> crate::fmt::Result { write!(f, "{}(", stringify!($id))?; for i in 0..$elem_count { if i > 0 { diff --git a/vendor/packed_simd_2/src/api/into_bits.rs b/vendor/packed_simd_2/src/api/into_bits.rs index f2cc1bae5..32b6d2ddc 100644 --- a/vendor/packed_simd_2/src/api/into_bits.rs +++ b/vendor/packed_simd_2/src/api/into_bits.rs @@ -19,9 +19,7 @@ where { #[inline] fn into_bits(self) -> U { - debug_assert!( - crate::mem::size_of::() == crate::mem::size_of::() - ); + debug_assert!(crate::mem::size_of::() == crate::mem::size_of::()); U::from_bits(self) } } diff --git a/vendor/packed_simd_2/src/api/into_bits/arch_specific.rs b/vendor/packed_simd_2/src/api/into_bits/arch_specific.rs index fee614005..bfac91557 100644 --- a/vendor/packed_simd_2/src/api/into_bits/arch_specific.rs +++ b/vendor/packed_simd_2/src/api/into_bits/arch_specific.rs @@ -84,15 +84,48 @@ macro_rules! impl_arch { // FIXME: 64-bit single element types // FIXME: arm/aarch float16x4_t missing impl_arch!( - [arm["arm"]: int8x8_t, uint8x8_t, poly8x8_t, int16x4_t, uint16x4_t, - poly16x4_t, int32x2_t, uint32x2_t, float32x2_t, int64x1_t, - uint64x1_t], - [aarch64["aarch64"]: int8x8_t, uint8x8_t, poly8x8_t, int16x4_t, uint16x4_t, - poly16x4_t, int32x2_t, uint32x2_t, float32x2_t, int64x1_t, uint64x1_t, - float64x1_t] | - from: i8x8, u8x8, m8x8, i16x4, u16x4, m16x4, i32x2, u32x2, f32x2, m32x2 | - into: i8x8, u8x8, i16x4, u16x4, i32x2, u32x2, f32x2 | - test: test_v64 + [ + arm["arm"]: int8x8_t, + uint8x8_t, + poly8x8_t, + int16x4_t, + uint16x4_t, + poly16x4_t, + int32x2_t, + uint32x2_t, + float32x2_t, + int64x1_t, + uint64x1_t + ], + [ + aarch64["aarch64"]: int8x8_t, + uint8x8_t, + poly8x8_t, + int16x4_t, + uint16x4_t, + poly16x4_t, + int32x2_t, + uint32x2_t, + float32x2_t, + int64x1_t, + uint64x1_t, + float64x1_t + ] | from: i8x8, + u8x8, + m8x8, + i16x4, + u16x4, + m16x4, + i32x2, + u32x2, + f32x2, + m32x2 | into: i8x8, + u8x8, + i16x4, + u16x4, + i32x2, + u32x2, + f32x2 | test: test_v64 ); //////////////////////////////////////////////////////////////////////////////// @@ -108,67 +141,169 @@ impl_arch!( // FIXME: ppc64 vector_unsigned___int128 missing impl_arch!( [x86["x86"]: __m128, __m128i, __m128d], - [x86_64["x86_64"]: __m128, __m128i, __m128d], - [arm["arm"]: int8x16_t, uint8x16_t, poly8x16_t, int16x8_t, uint16x8_t, - poly16x8_t, int32x4_t, uint32x4_t, float32x4_t, int64x2_t, uint64x2_t], - [aarch64["aarch64"]: int8x16_t, uint8x16_t, poly8x16_t, int16x8_t, - uint16x8_t, poly16x8_t, int32x4_t, uint32x4_t, float32x4_t, int64x2_t, - uint64x2_t, float64x2_t], - [powerpc["powerpc"]: vector_signed_char, vector_unsigned_char, - vector_signed_short, vector_unsigned_short, vector_signed_int, - vector_unsigned_int, vector_float], - [powerpc64["powerpc64"]: vector_signed_char, vector_unsigned_char, - vector_signed_short, vector_unsigned_short, vector_signed_int, - vector_unsigned_int, vector_float, vector_signed_long, - vector_unsigned_long, vector_double] | - from: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, - i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1 | - into: i8x16, u8x16, i16x8, u16x8, i32x4, u32x4, f32x4, i64x2, u64x2, f64x2, - i128x1, u128x1 | - test: test_v128 + [x86_64["x86_64"]: __m128, __m128i, __m128d], + [ + arm["arm"]: int8x16_t, + uint8x16_t, + poly8x16_t, + int16x8_t, + uint16x8_t, + poly16x8_t, + int32x4_t, + uint32x4_t, + float32x4_t, + int64x2_t, + uint64x2_t + ], + [ + aarch64["aarch64"]: int8x16_t, + uint8x16_t, + poly8x16_t, + int16x8_t, + uint16x8_t, + poly16x8_t, + int32x4_t, + uint32x4_t, + float32x4_t, + int64x2_t, + uint64x2_t, + float64x2_t + ], + [ + powerpc["powerpc"]: vector_signed_char, + vector_unsigned_char, + vector_signed_short, + vector_unsigned_short, + vector_signed_int, + vector_unsigned_int, + vector_float + ], + [ + powerpc64["powerpc64"]: vector_signed_char, + vector_unsigned_char, + vector_signed_short, + vector_unsigned_short, + vector_signed_int, + vector_unsigned_int, + vector_float, + vector_signed_long, + vector_unsigned_long, + vector_double + ] | from: i8x16, + u8x16, + m8x16, + i16x8, + u16x8, + m16x8, + i32x4, + u32x4, + f32x4, + m32x4, + i64x2, + u64x2, + f64x2, + m64x2, + i128x1, + u128x1, + m128x1 | into: i8x16, + u8x16, + i16x8, + u16x8, + i32x4, + u32x4, + f32x4, + i64x2, + u64x2, + f64x2, + i128x1, + u128x1 | test: test_v128 ); impl_arch!( [powerpc["powerpc"]: vector_bool_char], - [powerpc64["powerpc64"]: vector_bool_char] | - from: m8x16, m16x8, m32x4, m64x2, m128x1 | - into: i8x16, u8x16, i16x8, u16x8, i32x4, u32x4, f32x4, - i64x2, u64x2, f64x2, i128x1, u128x1, + [powerpc64["powerpc64"]: vector_bool_char] | from: m8x16, + m16x8, + m32x4, + m64x2, + m128x1 | into: i8x16, + u8x16, + i16x8, + u16x8, + i32x4, + u32x4, + f32x4, + i64x2, + u64x2, + f64x2, + i128x1, + u128x1, // Masks: - m8x16 | - test: test_v128 + m8x16 | test: test_v128 ); impl_arch!( [powerpc["powerpc"]: vector_bool_short], - [powerpc64["powerpc64"]: vector_bool_short] | - from: m16x8, m32x4, m64x2, m128x1 | - into: i8x16, u8x16, i16x8, u16x8, i32x4, u32x4, f32x4, - i64x2, u64x2, f64x2, i128x1, u128x1, + [powerpc64["powerpc64"]: vector_bool_short] | from: m16x8, + m32x4, + m64x2, + m128x1 | into: i8x16, + u8x16, + i16x8, + u16x8, + i32x4, + u32x4, + f32x4, + i64x2, + u64x2, + f64x2, + i128x1, + u128x1, // Masks: - m8x16, m16x8 | - test: test_v128 + m8x16, + m16x8 | test: test_v128 ); impl_arch!( [powerpc["powerpc"]: vector_bool_int], - [powerpc64["powerpc64"]: vector_bool_int] | - from: m32x4, m64x2, m128x1 | - into: i8x16, u8x16, i16x8, u16x8, i32x4, u32x4, f32x4, - i64x2, u64x2, f64x2, i128x1, u128x1, + [powerpc64["powerpc64"]: vector_bool_int] | from: m32x4, + m64x2, + m128x1 | into: i8x16, + u8x16, + i16x8, + u16x8, + i32x4, + u32x4, + f32x4, + i64x2, + u64x2, + f64x2, + i128x1, + u128x1, // Masks: - m8x16, m16x8, m32x4 | - test: test_v128 + m8x16, + m16x8, + m32x4 | test: test_v128 ); impl_arch!( - [powerpc64["powerpc64"]: vector_bool_long] | - from: m64x2, m128x1 | - into: i8x16, u8x16, i16x8, u16x8, i32x4, u32x4, f32x4, - i64x2, u64x2, f64x2, i128x1, u128x1, + [powerpc64["powerpc64"]: vector_bool_long] | from: m64x2, + m128x1 | into: i8x16, + u8x16, + i16x8, + u16x8, + i32x4, + u32x4, + f32x4, + i64x2, + u64x2, + f64x2, + i128x1, + u128x1, // Masks: - m8x16, m16x8, m32x4, m64x2 | - test: test_v128 + m8x16, + m16x8, + m32x4, + m64x2 | test: test_v128 ); //////////////////////////////////////////////////////////////////////////////// @@ -176,13 +311,34 @@ impl_arch!( impl_arch!( [x86["x86"]: __m256, __m256i, __m256d], - [x86_64["x86_64"]: __m256, __m256i, __m256d] | - from: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, - i32x8, u32x8, f32x8, m32x8, - i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2 | - into: i8x32, u8x32, i16x16, u16x16, i32x8, u32x8, f32x8, - i64x4, u64x4, f64x4, i128x2, u128x2 | - test: test_v256 + [x86_64["x86_64"]: __m256, __m256i, __m256d] | from: i8x32, + u8x32, + m8x32, + i16x16, + u16x16, + m16x16, + i32x8, + u32x8, + f32x8, + m32x8, + i64x4, + u64x4, + f64x4, + m64x4, + i128x2, + u128x2, + m128x2 | into: i8x32, + u8x32, + i16x16, + u16x16, + i32x8, + u32x8, + f32x8, + i64x4, + u64x4, + f64x4, + i128x2, + u128x2 | test: test_v256 ); //////////////////////////////////////////////////////////////////////////////// diff --git a/vendor/packed_simd_2/src/api/into_bits/macros.rs b/vendor/packed_simd_2/src/api/into_bits/macros.rs index 8cec5b004..265ab34ae 100644 --- a/vendor/packed_simd_2/src/api/into_bits/macros.rs +++ b/vendor/packed_simd_2/src/api/into_bits/macros.rs @@ -24,7 +24,7 @@ macro_rules! impl_from_bits_ { use crate::IntoBits; assert_eq!(size_of::<$id>(), size_of::<$from_ty>()); - // This is safe becasue we never create a reference to + // This is safe because we never create a reference to // uninitialized memory: let a: $from_ty = unsafe { zeroed() }; diff --git a/vendor/packed_simd_2/src/api/into_bits/v128.rs b/vendor/packed_simd_2/src/api/into_bits/v128.rs index e32cd7f9f..639c09c2c 100644 --- a/vendor/packed_simd_2/src/api/into_bits/v128.rs +++ b/vendor/packed_simd_2/src/api/into_bits/v128.rs @@ -4,25 +4,229 @@ #[allow(unused)] // wasm_bindgen_test use crate::*; -impl_from_bits!(i8x16[test_v128]: u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1); -impl_from_bits!(u8x16[test_v128]: i8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1); +impl_from_bits!( + i8x16[test_v128]: u8x16, + m8x16, + i16x8, + u16x8, + m16x8, + i32x4, + u32x4, + f32x4, + m32x4, + i64x2, + u64x2, + f64x2, + m64x2, + i128x1, + u128x1, + m128x1 +); +impl_from_bits!( + u8x16[test_v128]: i8x16, + m8x16, + i16x8, + u16x8, + m16x8, + i32x4, + u32x4, + f32x4, + m32x4, + i64x2, + u64x2, + f64x2, + m64x2, + i128x1, + u128x1, + m128x1 +); impl_from_bits!(m8x16[test_v128]: m16x8, m32x4, m64x2, m128x1); -impl_from_bits!(i16x8[test_v128]: i8x16, u8x16, m8x16, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1); -impl_from_bits!(u16x8[test_v128]: i8x16, u8x16, m8x16, i16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1); +impl_from_bits!( + i16x8[test_v128]: i8x16, + u8x16, + m8x16, + u16x8, + m16x8, + i32x4, + u32x4, + f32x4, + m32x4, + i64x2, + u64x2, + f64x2, + m64x2, + i128x1, + u128x1, + m128x1 +); +impl_from_bits!( + u16x8[test_v128]: i8x16, + u8x16, + m8x16, + i16x8, + m16x8, + i32x4, + u32x4, + f32x4, + m32x4, + i64x2, + u64x2, + f64x2, + m64x2, + i128x1, + u128x1, + m128x1 +); impl_from_bits!(m16x8[test_v128]: m32x4, m64x2, m128x1); -impl_from_bits!(i32x4[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, u32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1); -impl_from_bits!(u32x4[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1); -impl_from_bits!(f32x4[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1); +impl_from_bits!( + i32x4[test_v128]: i8x16, + u8x16, + m8x16, + i16x8, + u16x8, + m16x8, + u32x4, + f32x4, + m32x4, + i64x2, + u64x2, + f64x2, + m64x2, + i128x1, + u128x1, + m128x1 +); +impl_from_bits!( + u32x4[test_v128]: i8x16, + u8x16, + m8x16, + i16x8, + u16x8, + m16x8, + i32x4, + f32x4, + m32x4, + i64x2, + u64x2, + f64x2, + m64x2, + i128x1, + u128x1, + m128x1 +); +impl_from_bits!( + f32x4[test_v128]: i8x16, + u8x16, + m8x16, + i16x8, + u16x8, + m16x8, + i32x4, + u32x4, + m32x4, + i64x2, + u64x2, + f64x2, + m64x2, + i128x1, + u128x1, + m128x1 +); impl_from_bits!(m32x4[test_v128]: m64x2, m128x1); -impl_from_bits!(i64x2[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, u64x2, f64x2, m64x2, i128x1, u128x1, m128x1); -impl_from_bits!(u64x2[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, f64x2, m64x2, i128x1, u128x1, m128x1); -impl_from_bits!(f64x2[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, u64x2, m64x2, i128x1, u128x1, m128x1); +impl_from_bits!( + i64x2[test_v128]: i8x16, + u8x16, + m8x16, + i16x8, + u16x8, + m16x8, + i32x4, + u32x4, + f32x4, + m32x4, + u64x2, + f64x2, + m64x2, + i128x1, + u128x1, + m128x1 +); +impl_from_bits!( + u64x2[test_v128]: i8x16, + u8x16, + m8x16, + i16x8, + u16x8, + m16x8, + i32x4, + u32x4, + f32x4, + m32x4, + i64x2, + f64x2, + m64x2, + i128x1, + u128x1, + m128x1 +); +impl_from_bits!( + f64x2[test_v128]: i8x16, + u8x16, + m8x16, + i16x8, + u16x8, + m16x8, + i32x4, + u32x4, + f32x4, + m32x4, + i64x2, + u64x2, + m64x2, + i128x1, + u128x1, + m128x1 +); impl_from_bits!(m64x2[test_v128]: m128x1); -impl_from_bits!(i128x1[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, u128x1, m128x1); -impl_from_bits!(u128x1[test_v128]: i8x16, u8x16, m8x16, i16x8, u16x8, m16x8, i32x4, u32x4, f32x4, m32x4, i64x2, u64x2, f64x2, m64x2, i128x1, m128x1); -// note: m128x1 cannot be constructed from all the other masks bit patterns in here - +impl_from_bits!( + i128x1[test_v128]: i8x16, + u8x16, + m8x16, + i16x8, + u16x8, + m16x8, + i32x4, + u32x4, + f32x4, + m32x4, + i64x2, + u64x2, + f64x2, + m64x2, + u128x1, + m128x1 +); +impl_from_bits!( + u128x1[test_v128]: i8x16, + u8x16, + m8x16, + i16x8, + u16x8, + m16x8, + i32x4, + u32x4, + f32x4, + m32x4, + i64x2, + u64x2, + f64x2, + m64x2, + i128x1, + m128x1 +); +// note: m128x1 cannot be constructed from all the other masks bit patterns in +// here diff --git a/vendor/packed_simd_2/src/api/into_bits/v256.rs b/vendor/packed_simd_2/src/api/into_bits/v256.rs index c4c373e0d..e432bbbc9 100644 --- a/vendor/packed_simd_2/src/api/into_bits/v256.rs +++ b/vendor/packed_simd_2/src/api/into_bits/v256.rs @@ -4,24 +4,229 @@ #[allow(unused)] // wasm_bindgen_test use crate::*; -impl_from_bits!(i8x32[test_v256]: u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2); -impl_from_bits!(u8x32[test_v256]: i8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2); +impl_from_bits!( + i8x32[test_v256]: u8x32, + m8x32, + i16x16, + u16x16, + m16x16, + i32x8, + u32x8, + f32x8, + m32x8, + i64x4, + u64x4, + f64x4, + m64x4, + i128x2, + u128x2, + m128x2 +); +impl_from_bits!( + u8x32[test_v256]: i8x32, + m8x32, + i16x16, + u16x16, + m16x16, + i32x8, + u32x8, + f32x8, + m32x8, + i64x4, + u64x4, + f64x4, + m64x4, + i128x2, + u128x2, + m128x2 +); impl_from_bits!(m8x32[test_v256]: m16x16, m32x8, m64x4, m128x2); -impl_from_bits!(i16x16[test_v256]: i8x32, u8x32, m8x32, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2); -impl_from_bits!(u16x16[test_v256]: i8x32, u8x32, m8x32, i16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2); +impl_from_bits!( + i16x16[test_v256]: i8x32, + u8x32, + m8x32, + u16x16, + m16x16, + i32x8, + u32x8, + f32x8, + m32x8, + i64x4, + u64x4, + f64x4, + m64x4, + i128x2, + u128x2, + m128x2 +); +impl_from_bits!( + u16x16[test_v256]: i8x32, + u8x32, + m8x32, + i16x16, + m16x16, + i32x8, + u32x8, + f32x8, + m32x8, + i64x4, + u64x4, + f64x4, + m64x4, + i128x2, + u128x2, + m128x2 +); impl_from_bits!(m16x16[test_v256]: m32x8, m64x4, m128x2); -impl_from_bits!(i32x8[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, u32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2); -impl_from_bits!(u32x8[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2); -impl_from_bits!(f32x8[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2); +impl_from_bits!( + i32x8[test_v256]: i8x32, + u8x32, + m8x32, + i16x16, + u16x16, + m16x16, + u32x8, + f32x8, + m32x8, + i64x4, + u64x4, + f64x4, + m64x4, + i128x2, + u128x2, + m128x2 +); +impl_from_bits!( + u32x8[test_v256]: i8x32, + u8x32, + m8x32, + i16x16, + u16x16, + m16x16, + i32x8, + f32x8, + m32x8, + i64x4, + u64x4, + f64x4, + m64x4, + i128x2, + u128x2, + m128x2 +); +impl_from_bits!( + f32x8[test_v256]: i8x32, + u8x32, + m8x32, + i16x16, + u16x16, + m16x16, + i32x8, + u32x8, + m32x8, + i64x4, + u64x4, + f64x4, + m64x4, + i128x2, + u128x2, + m128x2 +); impl_from_bits!(m32x8[test_v256]: m64x4, m128x2); -impl_from_bits!(i64x4[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, u64x4, f64x4, m64x4, i128x2, u128x2, m128x2); -impl_from_bits!(u64x4[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, f64x4, m64x4, i128x2, u128x2, m128x2); -impl_from_bits!(f64x4[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, u64x4, m64x4, i128x2, u128x2, m128x2); +impl_from_bits!( + i64x4[test_v256]: i8x32, + u8x32, + m8x32, + i16x16, + u16x16, + m16x16, + i32x8, + u32x8, + f32x8, + m32x8, + u64x4, + f64x4, + m64x4, + i128x2, + u128x2, + m128x2 +); +impl_from_bits!( + u64x4[test_v256]: i8x32, + u8x32, + m8x32, + i16x16, + u16x16, + m16x16, + i32x8, + u32x8, + f32x8, + m32x8, + i64x4, + f64x4, + m64x4, + i128x2, + u128x2, + m128x2 +); +impl_from_bits!( + f64x4[test_v256]: i8x32, + u8x32, + m8x32, + i16x16, + u16x16, + m16x16, + i32x8, + u32x8, + f32x8, + m32x8, + i64x4, + u64x4, + m64x4, + i128x2, + u128x2, + m128x2 +); impl_from_bits!(m64x4[test_v256]: m128x2); -impl_from_bits!(i128x2[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, u128x2, m128x2); -impl_from_bits!(u128x2[test_v256]: i8x32, u8x32, m8x32, i16x16, u16x16, m16x16, i32x8, u32x8, f32x8, m32x8, i64x4, u64x4, f64x4, m64x4, i128x2, m128x2); -// note: m128x2 cannot be constructed from all the other masks bit patterns in here +impl_from_bits!( + i128x2[test_v256]: i8x32, + u8x32, + m8x32, + i16x16, + u16x16, + m16x16, + i32x8, + u32x8, + f32x8, + m32x8, + i64x4, + u64x4, + f64x4, + m64x4, + u128x2, + m128x2 +); +impl_from_bits!( + u128x2[test_v256]: i8x32, + u8x32, + m8x32, + i16x16, + u16x16, + m16x16, + i32x8, + u32x8, + f32x8, + m32x8, + i64x4, + u64x4, + f64x4, + m64x4, + i128x2, + m128x2 +); +// note: m128x2 cannot be constructed from all the other masks bit patterns in +// here diff --git a/vendor/packed_simd_2/src/api/into_bits/v512.rs b/vendor/packed_simd_2/src/api/into_bits/v512.rs index 4a771962c..f6e9bb8bf 100644 --- a/vendor/packed_simd_2/src/api/into_bits/v512.rs +++ b/vendor/packed_simd_2/src/api/into_bits/v512.rs @@ -4,24 +4,229 @@ #[allow(unused)] // wasm_bindgen_test use crate::*; -impl_from_bits!(i8x64[test_v512]: u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4); -impl_from_bits!(u8x64[test_v512]: i8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4); +impl_from_bits!( + i8x64[test_v512]: u8x64, + m8x64, + i16x32, + u16x32, + m16x32, + i32x16, + u32x16, + f32x16, + m32x16, + i64x8, + u64x8, + f64x8, + m64x8, + i128x4, + u128x4, + m128x4 +); +impl_from_bits!( + u8x64[test_v512]: i8x64, + m8x64, + i16x32, + u16x32, + m16x32, + i32x16, + u32x16, + f32x16, + m32x16, + i64x8, + u64x8, + f64x8, + m64x8, + i128x4, + u128x4, + m128x4 +); impl_from_bits!(m8x64[test_v512]: m16x32, m32x16, m64x8, m128x4); -impl_from_bits!(i16x32[test_v512]: i8x64, u8x64, m8x64, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4); -impl_from_bits!(u16x32[test_v512]: i8x64, u8x64, m8x64, i16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4); +impl_from_bits!( + i16x32[test_v512]: i8x64, + u8x64, + m8x64, + u16x32, + m16x32, + i32x16, + u32x16, + f32x16, + m32x16, + i64x8, + u64x8, + f64x8, + m64x8, + i128x4, + u128x4, + m128x4 +); +impl_from_bits!( + u16x32[test_v512]: i8x64, + u8x64, + m8x64, + i16x32, + m16x32, + i32x16, + u32x16, + f32x16, + m32x16, + i64x8, + u64x8, + f64x8, + m64x8, + i128x4, + u128x4, + m128x4 +); impl_from_bits!(m16x32[test_v512]: m32x16, m64x8, m128x4); -impl_from_bits!(i32x16[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, u32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4); -impl_from_bits!(u32x16[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4); -impl_from_bits!(f32x16[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4); +impl_from_bits!( + i32x16[test_v512]: i8x64, + u8x64, + m8x64, + i16x32, + u16x32, + m16x32, + u32x16, + f32x16, + m32x16, + i64x8, + u64x8, + f64x8, + m64x8, + i128x4, + u128x4, + m128x4 +); +impl_from_bits!( + u32x16[test_v512]: i8x64, + u8x64, + m8x64, + i16x32, + u16x32, + m16x32, + i32x16, + f32x16, + m32x16, + i64x8, + u64x8, + f64x8, + m64x8, + i128x4, + u128x4, + m128x4 +); +impl_from_bits!( + f32x16[test_v512]: i8x64, + u8x64, + m8x64, + i16x32, + u16x32, + m16x32, + i32x16, + u32x16, + m32x16, + i64x8, + u64x8, + f64x8, + m64x8, + i128x4, + u128x4, + m128x4 +); impl_from_bits!(m32x16[test_v512]: m64x8, m128x4); -impl_from_bits!(i64x8[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, u64x8, f64x8, m64x8, i128x4, u128x4, m128x4); -impl_from_bits!(u64x8[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, f64x8, m64x8, i128x4, u128x4, m128x4); -impl_from_bits!(f64x8[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, u64x8, m64x8, i128x4, u128x4, m128x4); +impl_from_bits!( + i64x8[test_v512]: i8x64, + u8x64, + m8x64, + i16x32, + u16x32, + m16x32, + i32x16, + u32x16, + f32x16, + m32x16, + u64x8, + f64x8, + m64x8, + i128x4, + u128x4, + m128x4 +); +impl_from_bits!( + u64x8[test_v512]: i8x64, + u8x64, + m8x64, + i16x32, + u16x32, + m16x32, + i32x16, + u32x16, + f32x16, + m32x16, + i64x8, + f64x8, + m64x8, + i128x4, + u128x4, + m128x4 +); +impl_from_bits!( + f64x8[test_v512]: i8x64, + u8x64, + m8x64, + i16x32, + u16x32, + m16x32, + i32x16, + u32x16, + f32x16, + m32x16, + i64x8, + u64x8, + m64x8, + i128x4, + u128x4, + m128x4 +); impl_from_bits!(m64x8[test_v512]: m128x4); -impl_from_bits!(i128x4[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, u128x4, m128x4); -impl_from_bits!(u128x4[test_v512]: i8x64, u8x64, m8x64, i16x32, u16x32, m16x32, i32x16, u32x16, f32x16, m32x16, i64x8, u64x8, f64x8, m64x8, i128x4, m128x4); -// note: m128x4 cannot be constructed from all the other masks bit patterns in here +impl_from_bits!( + i128x4[test_v512]: i8x64, + u8x64, + m8x64, + i16x32, + u16x32, + m16x32, + i32x16, + u32x16, + f32x16, + m32x16, + i64x8, + u64x8, + f64x8, + m64x8, + u128x4, + m128x4 +); +impl_from_bits!( + u128x4[test_v512]: i8x64, + u8x64, + m8x64, + i16x32, + u16x32, + m16x32, + i32x16, + u32x16, + f32x16, + m32x16, + i64x8, + u64x8, + f64x8, + m64x8, + i128x4, + m128x4 +); +// note: m128x4 cannot be constructed from all the other masks bit patterns in +// here diff --git a/vendor/packed_simd_2/src/api/math/float/consts.rs b/vendor/packed_simd_2/src/api/math/float/consts.rs index 89f93a6d6..7f41acbf1 100644 --- a/vendor/packed_simd_2/src/api/math/float/consts.rs +++ b/vendor/packed_simd_2/src/api/math/float/consts.rs @@ -8,8 +8,7 @@ macro_rules! impl_float_consts { pub const MIN: $id = $id::splat(core::$elem_ty::MIN); /// Smallest positive normal value. - pub const MIN_POSITIVE: $id = - $id::splat(core::$elem_ty::MIN_POSITIVE); + pub const MIN_POSITIVE: $id = $id::splat(core::$elem_ty::MIN_POSITIVE); /// Largest finite value. pub const MAX: $id = $id::splat(core::$elem_ty::MAX); @@ -21,50 +20,40 @@ macro_rules! impl_float_consts { pub const INFINITY: $id = $id::splat(core::$elem_ty::INFINITY); /// Negative infinity (-∞). - pub const NEG_INFINITY: $id = - $id::splat(core::$elem_ty::NEG_INFINITY); + pub const NEG_INFINITY: $id = $id::splat(core::$elem_ty::NEG_INFINITY); /// Archimedes' constant (π) pub const PI: $id = $id::splat(core::$elem_ty::consts::PI); /// π/2 - pub const FRAC_PI_2: $id = - $id::splat(core::$elem_ty::consts::FRAC_PI_2); + pub const FRAC_PI_2: $id = $id::splat(core::$elem_ty::consts::FRAC_PI_2); /// π/3 - pub const FRAC_PI_3: $id = - $id::splat(core::$elem_ty::consts::FRAC_PI_3); + pub const FRAC_PI_3: $id = $id::splat(core::$elem_ty::consts::FRAC_PI_3); /// π/4 - pub const FRAC_PI_4: $id = - $id::splat(core::$elem_ty::consts::FRAC_PI_4); + pub const FRAC_PI_4: $id = $id::splat(core::$elem_ty::consts::FRAC_PI_4); /// π/6 - pub const FRAC_PI_6: $id = - $id::splat(core::$elem_ty::consts::FRAC_PI_6); + pub const FRAC_PI_6: $id = $id::splat(core::$elem_ty::consts::FRAC_PI_6); /// π/8 - pub const FRAC_PI_8: $id = - $id::splat(core::$elem_ty::consts::FRAC_PI_8); + pub const FRAC_PI_8: $id = $id::splat(core::$elem_ty::consts::FRAC_PI_8); /// 1/π - pub const FRAC_1_PI: $id = - $id::splat(core::$elem_ty::consts::FRAC_1_PI); + pub const FRAC_1_PI: $id = $id::splat(core::$elem_ty::consts::FRAC_1_PI); /// 2/π - pub const FRAC_2_PI: $id = - $id::splat(core::$elem_ty::consts::FRAC_2_PI); + pub const FRAC_2_PI: $id = $id::splat(core::$elem_ty::consts::FRAC_2_PI); /// 2/sqrt(π) - pub const FRAC_2_SQRT_PI: $id = - $id::splat(core::$elem_ty::consts::FRAC_2_SQRT_PI); + pub const FRAC_2_SQRT_PI: $id = $id::splat(core::$elem_ty::consts::FRAC_2_SQRT_PI); /// sqrt(2) pub const SQRT_2: $id = $id::splat(core::$elem_ty::consts::SQRT_2); /// 1/sqrt(2) - pub const FRAC_1_SQRT_2: $id = - $id::splat(core::$elem_ty::consts::FRAC_1_SQRT_2); + pub const FRAC_1_SQRT_2: $id = $id::splat(core::$elem_ty::consts::FRAC_1_SQRT_2); /// Euler's number (e) pub const E: $id = $id::splat(core::$elem_ty::consts::E); @@ -73,8 +62,7 @@ macro_rules! impl_float_consts { pub const LOG2_E: $id = $id::splat(core::$elem_ty::consts::LOG2_E); /// log10(e) - pub const LOG10_E: $id = - $id::splat(core::$elem_ty::consts::LOG10_E); + pub const LOG10_E: $id = $id::splat(core::$elem_ty::consts::LOG10_E); /// ln(2) pub const LN_2: $id = $id::splat(core::$elem_ty::consts::LN_2); diff --git a/vendor/packed_simd_2/src/api/ops/scalar_shifts.rs b/vendor/packed_simd_2/src/api/ops/scalar_shifts.rs index 9c164ad56..4a7a09626 100644 --- a/vendor/packed_simd_2/src/api/ops/scalar_shifts.rs +++ b/vendor/packed_simd_2/src/api/ops/scalar_shifts.rs @@ -36,11 +36,10 @@ macro_rules! impl_ops_scalar_shifts { use super::*; #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)] #[cfg_attr(any(target_arch = "s390x", target_arch = "sparc64"), - allow(unreachable_code, - unused_variables, - unused_mut) + allow(unreachable_code, unused_variables) )] - // ^^^ FIXME: https://github.com/rust-lang/rust/issues/55344 + #[cfg(not(target_arch = "aarch64"))] + //~^ FIXME: https://github.com/rust-lang/packed_simd/issues/317 fn ops_scalar_shifts() { let z = $id::splat(0 as $elem_ty); let o = $id::splat(1 as $elem_ty); diff --git a/vendor/packed_simd_2/src/api/ops/vector_rotates.rs b/vendor/packed_simd_2/src/api/ops/vector_rotates.rs index 6c794ecf4..147fc2e37 100644 --- a/vendor/packed_simd_2/src/api/ops/vector_rotates.rs +++ b/vendor/packed_simd_2/src/api/ops/vector_rotates.rs @@ -47,6 +47,8 @@ macro_rules! impl_ops_vector_rotates { pub mod [<$id _ops_vector_rotate>] { use super::*; #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)] + #[cfg(not(target_arch = "aarch64"))] + //~^ FIXME: https://github.com/rust-lang/packed_simd/issues/317 fn rotate_ops() { let z = $id::splat(0 as $elem_ty); let o = $id::splat(1 as $elem_ty); diff --git a/vendor/packed_simd_2/src/api/ops/vector_shifts.rs b/vendor/packed_simd_2/src/api/ops/vector_shifts.rs index 22e1fbc0e..8bb5ac2fc 100644 --- a/vendor/packed_simd_2/src/api/ops/vector_shifts.rs +++ b/vendor/packed_simd_2/src/api/ops/vector_shifts.rs @@ -37,11 +37,10 @@ macro_rules! impl_ops_vector_shifts { use super::*; #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)] #[cfg_attr(any(target_arch = "s390x", target_arch = "sparc64"), - allow(unreachable_code, - unused_variables, - unused_mut) + allow(unreachable_code, unused_variables) )] - // ^^^ FIXME: https://github.com/rust-lang/rust/issues/55344 + #[cfg(not(target_arch = "aarch64"))] + //~^ FIXME: https://github.com/rust-lang/packed_simd/issues/317 fn ops_vector_shifts() { let z = $id::splat(0 as $elem_ty); let o = $id::splat(1 as $elem_ty); diff --git a/vendor/packed_simd_2/src/api/ptr/gather_scatter.rs b/vendor/packed_simd_2/src/api/ptr/gather_scatter.rs index 430435620..374482ac3 100644 --- a/vendor/packed_simd_2/src/api/ptr/gather_scatter.rs +++ b/vendor/packed_simd_2/src/api/ptr/gather_scatter.rs @@ -22,7 +22,8 @@ macro_rules! impl_ptr_read { /// pointers must be aligned to `mem::align_of::()`. #[inline] pub unsafe fn read( - self, mask: Simd<[M; $elem_count]>, + self, + mask: Simd<[M; $elem_count]>, value: Simd<[T; $elem_count]>, ) -> Simd<[T; $elem_count]> where @@ -128,10 +129,8 @@ macro_rules! impl_ptr_write { /// This method is unsafe because it dereferences raw pointers. The /// pointers must be aligned to `mem::align_of::()`. #[inline] - pub unsafe fn write( - self, mask: Simd<[M; $elem_count]>, - value: Simd<[T; $elem_count]>, - ) where + pub unsafe fn write(self, mask: Simd<[M; $elem_count]>, value: Simd<[T; $elem_count]>) + where M: sealed::Mask, [M; $elem_count]: sealed::SimdArray, { @@ -147,8 +146,8 @@ macro_rules! impl_ptr_write { use super::*; #[test] fn write() { - // fourty_two = [42, 42, 42, ...] - let fourty_two + // forty_two = [42, 42, 42, ...] + let forty_two = Simd::<[i32; $elem_count]>::splat(42_i32); // This test will write to this array @@ -166,11 +165,11 @@ macro_rules! impl_ptr_write { } // ptr = [&arr[0], &arr[1], ...] - // write `fourty_two` to all elements of `v` + // write `forty_two` to all elements of `v` { let backup = arr; unsafe { - ptr.write($mask_ty::splat(true), fourty_two) + ptr.write($mask_ty::splat(true), forty_two) }; assert_eq!(arr, [42_i32; $elem_count]); arr = backup; // arr = [0, 1, 2, ...] @@ -196,7 +195,7 @@ macro_rules! impl_ptr_write { } let backup = arr; - unsafe { ptr.write(mask, fourty_two) }; + unsafe { ptr.write(mask, forty_two) }; assert_eq!(arr, r); arr = backup; // arr = [0, 1, 2, 3, ...] } @@ -205,7 +204,7 @@ macro_rules! impl_ptr_write { { let backup = arr; unsafe { - ptr.write($mask_ty::splat(false), fourty_two) + ptr.write($mask_ty::splat(false), forty_two) }; assert_eq!(arr, backup); } diff --git a/vendor/packed_simd_2/src/api/reductions/float_arithmetic.rs b/vendor/packed_simd_2/src/api/reductions/float_arithmetic.rs index 4a47452e5..9dc8783db 100644 --- a/vendor/packed_simd_2/src/api/reductions/float_arithmetic.rs +++ b/vendor/packed_simd_2/src/api/reductions/float_arithmetic.rs @@ -144,8 +144,6 @@ macro_rules! impl_reduction_float_arithmetic { #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)] #[allow(unreachable_code)] - #[allow(unused_mut)] - // ^^^ FIXME: https://github.com/rust-lang/rust/issues/55344 fn sum_nan() { // FIXME: https://bugs.llvm.org/show_bug.cgi?id=36732 // https://github.com/rust-lang-nursery/packed_simd/issues/6 @@ -175,8 +173,6 @@ macro_rules! impl_reduction_float_arithmetic { #[cfg_attr(not(target_arch = "wasm32"), test)] #[cfg_attr(target_arch = "wasm32", wasm_bindgen_test)] #[allow(unreachable_code)] - #[allow(unused_mut)] - // ^^^ FIXME: https://github.com/rust-lang/rust/issues/55344 fn product_nan() { // FIXME: https://bugs.llvm.org/show_bug.cgi?id=36732 // https://github.com/rust-lang-nursery/packed_simd/issues/6 @@ -247,7 +243,7 @@ macro_rules! impl_reduction_float_arithmetic { tree_bits - red_bits } < 2, "vector: {:?} | simd_reduction: {:?} | \ - tree_reduction: {} | scalar_reduction: {}", +tree_reduction: {} | scalar_reduction: {}", v, simd_reduction, tree_reduction, @@ -303,7 +299,7 @@ macro_rules! impl_reduction_float_arithmetic { tree_bits - red_bits } < ulp_limit.try_into().unwrap(), "vector: {:?} | simd_reduction: {:?} | \ - tree_reduction: {} | scalar_reduction: {}", +tree_reduction: {} | scalar_reduction: {}", v, simd_reduction, tree_reduction, diff --git a/vendor/packed_simd_2/src/api/reductions/integer_arithmetic.rs b/vendor/packed_simd_2/src/api/reductions/integer_arithmetic.rs index 91dffad31..e99e6cb5d 100644 --- a/vendor/packed_simd_2/src/api/reductions/integer_arithmetic.rs +++ b/vendor/packed_simd_2/src/api/reductions/integer_arithmetic.rs @@ -18,9 +18,7 @@ macro_rules! impl_reduction_integer_arithmetic { #[cfg(not(target_arch = "aarch64"))] { use crate::llvm::simd_reduce_add_ordered; - let v: $ielem_ty = unsafe { - simd_reduce_add_ordered(self.0, 0 as $ielem_ty) - }; + let v: $ielem_ty = unsafe { simd_reduce_add_ordered(self.0, 0 as $ielem_ty) }; v as $elem_ty } #[cfg(target_arch = "aarch64")] @@ -49,9 +47,7 @@ macro_rules! impl_reduction_integer_arithmetic { #[cfg(not(target_arch = "aarch64"))] { use crate::llvm::simd_reduce_mul_ordered; - let v: $ielem_ty = unsafe { - simd_reduce_mul_ordered(self.0, 1 as $ielem_ty) - }; + let v: $ielem_ty = unsafe { simd_reduce_mul_ordered(self.0, 1 as $ielem_ty) }; v as $elem_ty } #[cfg(target_arch = "aarch64")] diff --git a/vendor/packed_simd_2/src/api/reductions/min_max.rs b/vendor/packed_simd_2/src/api/reductions/min_max.rs index c4c1400a8..a3ce13a45 100644 --- a/vendor/packed_simd_2/src/api/reductions/min_max.rs +++ b/vendor/packed_simd_2/src/api/reductions/min_max.rs @@ -123,7 +123,7 @@ macro_rules! impl_reduction_min_max { macro_rules! test_reduction_float_min_max { ([$elem_ty:ident; $elem_count:expr]: $id:ident | $test_tt:tt) => { - test_if!{ + test_if! { $test_tt: paste::item! { // Comparisons use integer casts within mantissa^1 range. @@ -160,20 +160,7 @@ macro_rules! test_reduction_float_min_max { // targets: if i == $id::lanes() - 1 && target_with_broken_last_lane_nan { - // FIXME: - // https://github.com/rust-lang-nursery/packed_simd/issues/5 - // - // If there is a NaN, the result should always - // the smallest element, but currently when the - // last element is NaN the current - // implementation incorrectly returns NaN. - // - // The targets mentioned above use different - // codegen that produces the correct result. - // - // These asserts detect if this behavior changes - assert!(v.min_element().is_nan(), - // FIXME: ^^^ should be -3. + assert_eq!(v.min_element(), -3., "[A]: nan at {} => {} | {:?}", i, v.min_element(), v); @@ -181,14 +168,17 @@ macro_rules! test_reduction_float_min_max { // up-to the `i-th` lane with `NaN`s, the result // is still always `-3.` unless all elements of // the vector are `NaN`s: - // - // This is also broken: for j in 0..i { v = v.replace(j, n); - assert!(v.min_element().is_nan(), - // FIXME: ^^^ should be -3. + if j == i-1 { + assert!(v.min_element().is_nan(), + "[B]: nan at {} => {} | {:?}", + i, v.min_element(), v); + } else { + assert_eq!(v.min_element(), -3., "[B]: nan at {} => {} | {:?}", i, v.min_element(), v); + } } // We are done here, since we were in the last @@ -203,7 +193,7 @@ macro_rules! test_reduction_float_min_max { if $id::lanes() == 1 { assert!(v.min_element().is_nan(), "[C]: all nans | v={:?} | min={} | \ - is_nan: {}", +is_nan: {}", v, v.min_element(), v.min_element().is_nan() ); @@ -235,7 +225,7 @@ macro_rules! test_reduction_float_min_max { // "i - 1" does not overflow. assert!(v.min_element().is_nan(), "[E]: all nans | v={:?} | min={} | \ - is_nan: {}", +is_nan: {}", v, v.min_element(), v.min_element().is_nan()); } else { @@ -280,21 +270,7 @@ macro_rules! test_reduction_float_min_max { // targets: if i == $id::lanes() - 1 && target_with_broken_last_lane_nan { - // FIXME: - // https://github.com/rust-lang-nursery/packed_simd/issues/5 - // - // If there is a NaN, the result should - // always the largest element, but currently - // when the last element is NaN the current - // implementation incorrectly returns NaN. - // - // The targets mentioned above use different - // codegen that produces the correct result. - // - // These asserts detect if this behavior - // changes - assert!(v.max_element().is_nan(), - // FIXME: ^^^ should be -3. + assert_eq!(v.max_element(), -3., "[A]: nan at {} => {} | {:?}", i, v.max_element(), v); @@ -302,14 +278,17 @@ macro_rules! test_reduction_float_min_max { // up-to the `i-th` lane with `NaN`s, the result // is still always `-3.` unless all elements of // the vector are `NaN`s: - // - // This is also broken: for j in 0..i { v = v.replace(j, n); - assert!(v.max_element().is_nan(), - // FIXME: ^^^ should be -3. + if j == i-1 { + assert!(v.min_element().is_nan(), + "[B]: nan at {} => {} | {:?}", + i, v.min_element(), v); + } else { + assert_eq!(v.max_element(), -3., "[B]: nan at {} => {} | {:?}", i, v.max_element(), v); + } } // We are done here, since we were in the last @@ -324,7 +303,7 @@ macro_rules! test_reduction_float_min_max { if $id::lanes() == 1 { assert!(v.max_element().is_nan(), "[C]: all nans | v={:?} | min={} | \ - is_nan: {}", +is_nan: {}", v, v.max_element(), v.max_element().is_nan()); @@ -355,7 +334,7 @@ macro_rules! test_reduction_float_min_max { // "i - 1" does not overflow. assert!(v.max_element().is_nan(), "[E]: all nans | v={:?} | max={} | \ - is_nan: {}", +is_nan: {}", v, v.max_element(), v.max_element().is_nan()); } else { @@ -377,5 +356,5 @@ macro_rules! test_reduction_float_min_max { } } } - } + }; } diff --git a/vendor/packed_simd_2/src/api/select.rs b/vendor/packed_simd_2/src/api/select.rs index 24525df56..daf629472 100644 --- a/vendor/packed_simd_2/src/api/select.rs +++ b/vendor/packed_simd_2/src/api/select.rs @@ -12,9 +12,7 @@ macro_rules! impl_select { #[inline] pub fn select(self, a: Simd, b: Simd) -> Simd where - T: sealed::SimdArray< - NT = <[$elem_ty; $elem_count] as sealed::SimdArray>::NT, - >, + T: sealed::SimdArray::NT>, { use crate::llvm::simd_select; Simd(unsafe { simd_select(self.0, a.0, b.0) }) diff --git a/vendor/packed_simd_2/src/api/shuffle.rs b/vendor/packed_simd_2/src/api/shuffle.rs index 13a7fae5f..fda29ccdd 100644 --- a/vendor/packed_simd_2/src/api/shuffle.rs +++ b/vendor/packed_simd_2/src/api/shuffle.rs @@ -27,9 +27,7 @@ /// Shuffling elements of two vectors: /// /// ``` -/// # #[macro_use] -/// # extern crate packed_simd; -/// # use packed_simd::*; +/// # use packed_simd_2::*; /// # fn main() { /// // Shuffle allows reordering the elements: /// let x = i32x4::new(1, 2, 3, 4); @@ -51,9 +49,7 @@ /// Shuffling elements of one vector: /// /// ``` -/// # #[macro_use] -/// # extern crate packed_simd; -/// # use packed_simd::*; +/// # use packed_simd_2::*; /// # fn main() { /// // Shuffle allows reordering the elements of a vector: /// let x = i32x4::new(1, 2, 3, 4); @@ -79,20 +75,18 @@ macro_rules! shuffle { ($vec0:expr, $vec1:expr, [$l0:expr, $l1:expr]) => {{ #[allow(unused_unsafe)] unsafe { - $crate::Simd($crate::__shuffle_vector2( + $crate::Simd($crate::__shuffle_vector2::<{[$l0, $l1]}, _, _>( $vec0.0, $vec1.0, - [$l0, $l1], )) } }}; ($vec0:expr, $vec1:expr, [$l0:expr, $l1:expr, $l2:expr, $l3:expr]) => {{ #[allow(unused_unsafe)] unsafe { - $crate::Simd($crate::__shuffle_vector4( + $crate::Simd($crate::__shuffle_vector4::<{[$l0, $l1, $l2, $l3]}, _, _>( $vec0.0, $vec1.0, - [$l0, $l1, $l2, $l3], )) } }}; @@ -101,10 +95,9 @@ macro_rules! shuffle { $l4:expr, $l5:expr, $l6:expr, $l7:expr]) => {{ #[allow(unused_unsafe)] unsafe { - $crate::Simd($crate::__shuffle_vector8( + $crate::Simd($crate::__shuffle_vector8::<{[$l0, $l1, $l2, $l3, $l4, $l5, $l6, $l7]}, _, _>( $vec0.0, $vec1.0, - [$l0, $l1, $l2, $l3, $l4, $l5, $l6, $l7], )) } }}; @@ -115,13 +108,14 @@ macro_rules! shuffle { $l12:expr, $l13:expr, $l14:expr, $l15:expr]) => {{ #[allow(unused_unsafe)] unsafe { - $crate::Simd($crate::__shuffle_vector16( - $vec0.0, - $vec1.0, + $crate::Simd($crate::__shuffle_vector16::<{ [ $l0, $l1, $l2, $l3, $l4, $l5, $l6, $l7, $l8, $l9, $l10, $l11, $l12, $l13, $l14, $l15, - ], + ] + }, _, _>( + $vec0.0, + $vec1.0, )) } }}; @@ -136,15 +130,16 @@ macro_rules! shuffle { $l28:expr, $l29:expr, $l30:expr, $l31:expr]) => {{ #[allow(unused_unsafe)] unsafe { - $crate::Simd($crate::__shuffle_vector32( - $vec0.0, - $vec1.0, + $crate::Simd($crate::__shuffle_vector32::<{ [ $l0, $l1, $l2, $l3, $l4, $l5, $l6, $l7, $l8, $l9, $l10, $l11, $l12, $l13, $l14, $l15, $l16, $l17, $l18, $l19, $l20, $l21, $l22, $l23, $l24, $l25, $l26, $l27, $l28, $l29, $l30, $l31, - ], + ] + }, _, _>( + $vec0.0, + $vec1.0, )) } }}; @@ -167,18 +162,17 @@ macro_rules! shuffle { $l60:expr, $l61:expr, $l62:expr, $l63:expr]) => {{ #[allow(unused_unsafe)] unsafe { - $crate::Simd($crate::__shuffle_vector64( + $crate::Simd($crate::__shuffle_vector64::<{[ + $l0, $l1, $l2, $l3, $l4, $l5, $l6, $l7, $l8, $l9, $l10, + $l11, $l12, $l13, $l14, $l15, $l16, $l17, $l18, $l19, + $l20, $l21, $l22, $l23, $l24, $l25, $l26, $l27, $l28, + $l29, $l30, $l31, $l32, $l33, $l34, $l35, $l36, $l37, + $l38, $l39, $l40, $l41, $l42, $l43, $l44, $l45, $l46, + $l47, $l48, $l49, $l50, $l51, $l52, $l53, $l54, $l55, + $l56, $l57, $l58, $l59, $l60, $l61, $l62, $l63, + ]}, _, _>( $vec0.0, $vec1.0, - [ - $l0, $l1, $l2, $l3, $l4, $l5, $l6, $l7, $l8, $l9, $l10, - $l11, $l12, $l13, $l14, $l15, $l16, $l17, $l18, $l19, - $l20, $l21, $l22, $l23, $l24, $l25, $l26, $l27, $l28, - $l29, $l30, $l31, $l32, $l33, $l34, $l35, $l36, $l37, - $l38, $l39, $l40, $l41, $l42, $l43, $l44, $l45, $l46, - $l47, $l48, $l49, $l50, $l51, $l52, $l53, $l54, $l55, - $l56, $l57, $l58, $l59, $l60, $l61, $l62, $l63, - ], )) } }}; diff --git a/vendor/packed_simd_2/src/api/slice/from_slice.rs b/vendor/packed_simd_2/src/api/slice/from_slice.rs index 25082d1e6..50f3914f7 100644 --- a/vendor/packed_simd_2/src/api/slice/from_slice.rs +++ b/vendor/packed_simd_2/src/api/slice/from_slice.rs @@ -14,11 +14,7 @@ macro_rules! impl_slice_from_slice { unsafe { assert!(slice.len() >= $elem_count); let target_ptr = slice.get_unchecked(0) as *const $elem_ty; - assert_eq!( - target_ptr - .align_offset(crate::mem::align_of::()), - 0 - ); + assert_eq!(target_ptr.align_offset(crate::mem::align_of::()), 0); Self::from_slice_aligned_unchecked(slice) } } @@ -43,15 +39,10 @@ macro_rules! impl_slice_from_slice { /// If `slice.len() < Self::lanes()` or `&slice[0]` is not aligned /// to an `align_of::()` boundary, the behavior is undefined. #[inline] - pub unsafe fn from_slice_aligned_unchecked( - slice: &[$elem_ty], - ) -> Self { + pub unsafe fn from_slice_aligned_unchecked(slice: &[$elem_ty]) -> Self { debug_assert!(slice.len() >= $elem_count); let target_ptr = slice.get_unchecked(0) as *const $elem_ty; - debug_assert_eq!( - target_ptr.align_offset(crate::mem::align_of::()), - 0 - ); + debug_assert_eq!(target_ptr.align_offset(crate::mem::align_of::()), 0); #[allow(clippy::cast_ptr_alignment)] *(target_ptr as *const Self) @@ -63,20 +54,13 @@ macro_rules! impl_slice_from_slice { /// /// If `slice.len() < Self::lanes()` the behavior is undefined. #[inline] - pub unsafe fn from_slice_unaligned_unchecked( - slice: &[$elem_ty], - ) -> Self { + pub unsafe fn from_slice_unaligned_unchecked(slice: &[$elem_ty]) -> Self { use crate::mem::size_of; debug_assert!(slice.len() >= $elem_count); - let target_ptr = - slice.get_unchecked(0) as *const $elem_ty as *const u8; + let target_ptr = slice.get_unchecked(0) as *const $elem_ty as *const u8; let mut x = Self::splat(0 as $elem_ty); let self_ptr = &mut x as *mut Self as *mut u8; - crate::ptr::copy_nonoverlapping( - target_ptr, - self_ptr, - size_of::(), - ); + crate::ptr::copy_nonoverlapping(target_ptr, self_ptr, size_of::()); x } } diff --git a/vendor/packed_simd_2/src/api/slice/write_to_slice.rs b/vendor/packed_simd_2/src/api/slice/write_to_slice.rs index b634d98b9..dd04a2634 100644 --- a/vendor/packed_simd_2/src/api/slice/write_to_slice.rs +++ b/vendor/packed_simd_2/src/api/slice/write_to_slice.rs @@ -13,13 +13,8 @@ macro_rules! impl_slice_write_to_slice { pub fn write_to_slice_aligned(self, slice: &mut [$elem_ty]) { unsafe { assert!(slice.len() >= $elem_count); - let target_ptr = - slice.get_unchecked_mut(0) as *mut $elem_ty; - assert_eq!( - target_ptr - .align_offset(crate::mem::align_of::()), - 0 - ); + let target_ptr = slice.get_unchecked_mut(0) as *mut $elem_ty; + assert_eq!(target_ptr.align_offset(crate::mem::align_of::()), 0); self.write_to_slice_aligned_unchecked(slice); } } @@ -45,18 +40,13 @@ macro_rules! impl_slice_write_to_slice { /// aligned to an `align_of::()` boundary, the behavior is /// undefined. #[inline] - pub unsafe fn write_to_slice_aligned_unchecked( - self, slice: &mut [$elem_ty], - ) { + pub unsafe fn write_to_slice_aligned_unchecked(self, slice: &mut [$elem_ty]) { debug_assert!(slice.len() >= $elem_count); let target_ptr = slice.get_unchecked_mut(0) as *mut $elem_ty; - debug_assert_eq!( - target_ptr.align_offset(crate::mem::align_of::()), - 0 - ); + debug_assert_eq!(target_ptr.align_offset(crate::mem::align_of::()), 0); - #[allow(clippy::cast_ptr_alignment)] - #[allow(clippy::cast_ptr_alignment)] + #[allow(clippy::cast_ptr_alignment)] + #[allow(clippy::cast_ptr_alignment)] #[allow(clippy::cast_ptr_alignment)] #[allow(clippy::cast_ptr_alignment)] *(target_ptr as *mut Self) = self; @@ -68,18 +58,11 @@ macro_rules! impl_slice_write_to_slice { /// /// If `slice.len() < Self::lanes()` the behavior is undefined. #[inline] - pub unsafe fn write_to_slice_unaligned_unchecked( - self, slice: &mut [$elem_ty], - ) { + pub unsafe fn write_to_slice_unaligned_unchecked(self, slice: &mut [$elem_ty]) { debug_assert!(slice.len() >= $elem_count); - let target_ptr = - slice.get_unchecked_mut(0) as *mut $elem_ty as *mut u8; + let target_ptr = slice.get_unchecked_mut(0) as *mut $elem_ty as *mut u8; let self_ptr = &self as *const Self as *const u8; - crate::ptr::copy_nonoverlapping( - self_ptr, - target_ptr, - crate::mem::size_of::(), - ); + crate::ptr::copy_nonoverlapping(self_ptr, target_ptr, crate::mem::size_of::()); } } diff --git a/vendor/packed_simd_2/src/codegen.rs b/vendor/packed_simd_2/src/codegen.rs index 9d1517e20..8a9e97148 100644 --- a/vendor/packed_simd_2/src/codegen.rs +++ b/vendor/packed_simd_2/src/codegen.rs @@ -1,19 +1,19 @@ //! Code-generation utilities -crate mod bit_manip; -crate mod llvm; -crate mod math; -crate mod reductions; -crate mod shuffle; -crate mod shuffle1_dyn; -crate mod swap_bytes; +pub(crate) mod bit_manip; +pub(crate) mod llvm; +pub(crate) mod math; +pub(crate) mod reductions; +pub(crate) mod shuffle; +pub(crate) mod shuffle1_dyn; +pub(crate) mod swap_bytes; macro_rules! impl_simd_array { ([$elem_ty:ident; $elem_count:expr]: $tuple_id:ident | $($elem_tys:ident),*) => { #[derive(Copy, Clone)] #[repr(simd)] - pub struct $tuple_id($(crate $elem_tys),*); + pub struct $tuple_id($(pub(crate) $elem_tys),*); //^^^^^^^ leaked through SimdArray impl crate::sealed::Seal for [$elem_ty; $elem_count] {} @@ -35,28 +35,28 @@ macro_rules! impl_simd_array { } } -crate mod pointer_sized_int; +pub(crate) mod pointer_sized_int; -crate mod v16; -crate use self::v16::*; +pub(crate) mod v16; +pub(crate) use self::v16::*; -crate mod v32; -crate use self::v32::*; +pub(crate) mod v32; +pub(crate) use self::v32::*; -crate mod v64; -crate use self::v64::*; +pub(crate) mod v64; +pub(crate) use self::v64::*; -crate mod v128; -crate use self::v128::*; +pub(crate) mod v128; +pub(crate) use self::v128::*; -crate mod v256; -crate use self::v256::*; +pub(crate) mod v256; +pub(crate) use self::v256::*; -crate mod v512; -crate use self::v512::*; +pub(crate) mod v512; +pub(crate) use self::v512::*; -crate mod vSize; -crate use self::vSize::*; +pub(crate) mod vSize; +pub(crate) use self::vSize::*; -crate mod vPtr; -crate use self::vPtr::*; +pub(crate) mod vPtr; +pub(crate) use self::vPtr::*; diff --git a/vendor/packed_simd_2/src/codegen/bit_manip.rs b/vendor/packed_simd_2/src/codegen/bit_manip.rs index 83c7d1987..32d8d717a 100644 --- a/vendor/packed_simd_2/src/codegen/bit_manip.rs +++ b/vendor/packed_simd_2/src/codegen/bit_manip.rs @@ -1,7 +1,7 @@ //! LLVM bit manipulation intrinsics. #[rustfmt::skip] -use crate::*; +pub(crate) use crate::*; #[allow(improper_ctypes, dead_code)] extern "C" { @@ -147,7 +147,7 @@ extern "C" { fn ctpop_u128x4(x: u128x4) -> u128x4; } -crate trait BitManip { +pub(crate) trait BitManip { fn ctpop(self) -> Self; fn ctlz(self) -> Self; fn cttz(self) -> Self; @@ -212,8 +212,7 @@ macro_rules! impl_bit_manip { fn ctpop(self) -> Self { let mut ones = self; for i in 0..Self::lanes() { - ones = ones - .replace(i, self.extract(i).count_ones() as $scalar); + ones = ones.replace(i, self.extract(i).count_ones() as $scalar); } ones } @@ -222,10 +221,7 @@ macro_rules! impl_bit_manip { fn ctlz(self) -> Self { let mut lz = self; for i in 0..Self::lanes() { - lz = lz.replace( - i, - self.extract(i).leading_zeros() as $scalar, - ); + lz = lz.replace(i, self.extract(i).leading_zeros() as $scalar); } lz } @@ -234,10 +230,7 @@ macro_rules! impl_bit_manip { fn cttz(self) -> Self { let mut tz = self; for i in 0..Self::lanes() { - tz = tz.replace( - i, - self.extract(i).trailing_zeros() as $scalar, - ); + tz = tz.replace(i, self.extract(i).trailing_zeros() as $scalar); } tz } diff --git a/vendor/packed_simd_2/src/codegen/llvm.rs b/vendor/packed_simd_2/src/codegen/llvm.rs index 93c6ce6b7..b4c09849b 100644 --- a/vendor/packed_simd_2/src/codegen/llvm.rs +++ b/vendor/packed_simd_2/src/codegen/llvm.rs @@ -7,101 +7,122 @@ use crate::sealed::Simd; // Shuffle intrinsics: expanded in users' crates, therefore public. extern "platform-intrinsic" { - // FIXME: Passing this intrinsics an `idx` array with an index that is - // out-of-bounds will produce a monomorphization-time error. - // https://github.com/rust-lang-nursery/packed_simd/issues/21 - #[rustc_args_required_const(2)] - pub fn simd_shuffle2(x: T, y: T, idx: [u32; 2]) -> U - where - T: Simd, - ::Element: Shuffle<[u32; 2], Output = U>; - - #[rustc_args_required_const(2)] - pub fn simd_shuffle4(x: T, y: T, idx: [u32; 4]) -> U - where - T: Simd, - ::Element: Shuffle<[u32; 4], Output = U>; - - #[rustc_args_required_const(2)] - pub fn simd_shuffle8(x: T, y: T, idx: [u32; 8]) -> U - where - T: Simd, - ::Element: Shuffle<[u32; 8], Output = U>; - - #[rustc_args_required_const(2)] - pub fn simd_shuffle16(x: T, y: T, idx: [u32; 16]) -> U - where - T: Simd, - ::Element: Shuffle<[u32; 16], Output = U>; - - #[rustc_args_required_const(2)] - pub fn simd_shuffle32(x: T, y: T, idx: [u32; 32]) -> U - where - T: Simd, - ::Element: Shuffle<[u32; 32], Output = U>; - - #[rustc_args_required_const(2)] - pub fn simd_shuffle64(x: T, y: T, idx: [u32; 64]) -> U - where - T: Simd, - ::Element: Shuffle<[u32; 64], Output = U>; + pub fn simd_shuffle2(x: T, y: T, idx: [u32; 2]) -> U; + pub fn simd_shuffle4(x: T, y: T, idx: [u32; 4]) -> U; + pub fn simd_shuffle8(x: T, y: T, idx: [u32; 8]) -> U; + pub fn simd_shuffle16(x: T, y: T, idx: [u32; 16]) -> U; + pub fn simd_shuffle32(x: T, y: T, idx: [u32; 32]) -> U; + pub fn simd_shuffle64(x: T, y: T, idx: [u32; 64]) -> U; } -pub use self::simd_shuffle16 as __shuffle_vector16; -pub use self::simd_shuffle2 as __shuffle_vector2; -pub use self::simd_shuffle32 as __shuffle_vector32; -pub use self::simd_shuffle4 as __shuffle_vector4; -pub use self::simd_shuffle64 as __shuffle_vector64; -pub use self::simd_shuffle8 as __shuffle_vector8; +#[allow(clippy::missing_safety_doc)] +#[inline] +pub unsafe fn __shuffle_vector2(x: T, y: T) -> U +where + T: Simd, + ::Element: Shuffle<[u32; 2], Output = U>, +{ + simd_shuffle2(x, y, IDX) +} + +#[allow(clippy::missing_safety_doc)] +#[inline] +pub unsafe fn __shuffle_vector4(x: T, y: T) -> U +where + T: Simd, + ::Element: Shuffle<[u32; 4], Output = U>, +{ + simd_shuffle4(x, y, IDX) +} + +#[allow(clippy::missing_safety_doc)] +#[inline] +pub unsafe fn __shuffle_vector8(x: T, y: T) -> U +where + T: Simd, + ::Element: Shuffle<[u32; 8], Output = U>, +{ + simd_shuffle8(x, y, IDX) +} + +#[allow(clippy::missing_safety_doc)] +#[inline] +pub unsafe fn __shuffle_vector16(x: T, y: T) -> U +where + T: Simd, + ::Element: Shuffle<[u32; 16], Output = U>, +{ + simd_shuffle16(x, y, IDX) +} + +#[allow(clippy::missing_safety_doc)] +#[inline] +pub unsafe fn __shuffle_vector32(x: T, y: T) -> U +where + T: Simd, + ::Element: Shuffle<[u32; 32], Output = U>, +{ + simd_shuffle32(x, y, IDX) +} + +#[allow(clippy::missing_safety_doc)] +#[inline] +pub unsafe fn __shuffle_vector64(x: T, y: T) -> U +where + T: Simd, + ::Element: Shuffle<[u32; 64], Output = U>, +{ + simd_shuffle64(x, y, IDX) +} extern "platform-intrinsic" { - crate fn simd_eq(x: T, y: T) -> U; - crate fn simd_ne(x: T, y: T) -> U; - crate fn simd_lt(x: T, y: T) -> U; - crate fn simd_le(x: T, y: T) -> U; - crate fn simd_gt(x: T, y: T) -> U; - crate fn simd_ge(x: T, y: T) -> U; - - crate fn simd_insert(x: T, idx: u32, val: U) -> T; - crate fn simd_extract(x: T, idx: u32) -> U; - - crate fn simd_cast(x: T) -> U; - - crate fn simd_add(x: T, y: T) -> T; - crate fn simd_sub(x: T, y: T) -> T; - crate fn simd_mul(x: T, y: T) -> T; - crate fn simd_div(x: T, y: T) -> T; - crate fn simd_rem(x: T, y: T) -> T; - crate fn simd_shl(x: T, y: T) -> T; - crate fn simd_shr(x: T, y: T) -> T; - crate fn simd_and(x: T, y: T) -> T; - crate fn simd_or(x: T, y: T) -> T; - crate fn simd_xor(x: T, y: T) -> T; - - crate fn simd_reduce_add_unordered(x: T) -> U; - crate fn simd_reduce_mul_unordered(x: T) -> U; - crate fn simd_reduce_add_ordered(x: T, acc: U) -> U; - crate fn simd_reduce_mul_ordered(x: T, acc: U) -> U; - crate fn simd_reduce_min(x: T) -> U; - crate fn simd_reduce_max(x: T) -> U; - crate fn simd_reduce_min_nanless(x: T) -> U; - crate fn simd_reduce_max_nanless(x: T) -> U; - crate fn simd_reduce_and(x: T) -> U; - crate fn simd_reduce_or(x: T) -> U; - crate fn simd_reduce_xor(x: T) -> U; - crate fn simd_reduce_all(x: T) -> bool; - crate fn simd_reduce_any(x: T) -> bool; - - crate fn simd_select(m: M, a: T, b: T) -> T; - - crate fn simd_fmin(a: T, b: T) -> T; - crate fn simd_fmax(a: T, b: T) -> T; - - crate fn simd_fsqrt(a: T) -> T; - crate fn simd_fma(a: T, b: T, c: T) -> T; - - crate fn simd_gather(value: T, pointers: P, mask: M) -> T; - crate fn simd_scatter(value: T, pointers: P, mask: M); - - crate fn simd_bitmask(value: T) -> U; + pub(crate) fn simd_eq(x: T, y: T) -> U; + pub(crate) fn simd_ne(x: T, y: T) -> U; + pub(crate) fn simd_lt(x: T, y: T) -> U; + pub(crate) fn simd_le(x: T, y: T) -> U; + pub(crate) fn simd_gt(x: T, y: T) -> U; + pub(crate) fn simd_ge(x: T, y: T) -> U; + + pub(crate) fn simd_insert(x: T, idx: u32, val: U) -> T; + pub(crate) fn simd_extract(x: T, idx: u32) -> U; + + pub(crate) fn simd_cast(x: T) -> U; + + pub(crate) fn simd_add(x: T, y: T) -> T; + pub(crate) fn simd_sub(x: T, y: T) -> T; + pub(crate) fn simd_mul(x: T, y: T) -> T; + pub(crate) fn simd_div(x: T, y: T) -> T; + pub(crate) fn simd_rem(x: T, y: T) -> T; + pub(crate) fn simd_shl(x: T, y: T) -> T; + pub(crate) fn simd_shr(x: T, y: T) -> T; + pub(crate) fn simd_and(x: T, y: T) -> T; + pub(crate) fn simd_or(x: T, y: T) -> T; + pub(crate) fn simd_xor(x: T, y: T) -> T; + + pub(crate) fn simd_reduce_add_unordered(x: T) -> U; + pub(crate) fn simd_reduce_mul_unordered(x: T) -> U; + pub(crate) fn simd_reduce_add_ordered(x: T, acc: U) -> U; + pub(crate) fn simd_reduce_mul_ordered(x: T, acc: U) -> U; + pub(crate) fn simd_reduce_min(x: T) -> U; + pub(crate) fn simd_reduce_max(x: T) -> U; + pub(crate) fn simd_reduce_min_nanless(x: T) -> U; + pub(crate) fn simd_reduce_max_nanless(x: T) -> U; + pub(crate) fn simd_reduce_and(x: T) -> U; + pub(crate) fn simd_reduce_or(x: T) -> U; + pub(crate) fn simd_reduce_xor(x: T) -> U; + pub(crate) fn simd_reduce_all(x: T) -> bool; + pub(crate) fn simd_reduce_any(x: T) -> bool; + + pub(crate) fn simd_select(m: M, a: T, b: T) -> T; + + pub(crate) fn simd_fmin(a: T, b: T) -> T; + pub(crate) fn simd_fmax(a: T, b: T) -> T; + + pub(crate) fn simd_fsqrt(a: T) -> T; + pub(crate) fn simd_fma(a: T, b: T, c: T) -> T; + + pub(crate) fn simd_gather(value: T, pointers: P, mask: M) -> T; + pub(crate) fn simd_scatter(value: T, pointers: P, mask: M); + + pub(crate) fn simd_bitmask(value: T) -> U; } diff --git a/vendor/packed_simd_2/src/codegen/math.rs b/vendor/packed_simd_2/src/codegen/math.rs index f3997c7f1..9a0ea7a4e 100644 --- a/vendor/packed_simd_2/src/codegen/math.rs +++ b/vendor/packed_simd_2/src/codegen/math.rs @@ -1,3 +1,3 @@ //! Vertical math operations -crate mod float; +pub(crate) mod float; diff --git a/vendor/packed_simd_2/src/codegen/math/float.rs b/vendor/packed_simd_2/src/codegen/math/float.rs index 3743b4990..10d21831f 100644 --- a/vendor/packed_simd_2/src/codegen/math/float.rs +++ b/vendor/packed_simd_2/src/codegen/math/float.rs @@ -2,18 +2,18 @@ #![allow(clippy::useless_transmute)] #[macro_use] -crate mod macros; -crate mod abs; -crate mod cos; -crate mod cos_pi; -crate mod exp; -crate mod ln; -crate mod mul_add; -crate mod mul_adde; -crate mod powf; -crate mod sin; -crate mod sin_cos_pi; -crate mod sin_pi; -crate mod sqrt; -crate mod sqrte; -crate mod tanh; +pub(crate) mod macros; +pub(crate) mod abs; +pub(crate) mod cos; +pub(crate) mod cos_pi; +pub(crate) mod exp; +pub(crate) mod ln; +pub(crate) mod mul_add; +pub(crate) mod mul_adde; +pub(crate) mod powf; +pub(crate) mod sin; +pub(crate) mod sin_cos_pi; +pub(crate) mod sin_pi; +pub(crate) mod sqrt; +pub(crate) mod sqrte; +pub(crate) mod tanh; diff --git a/vendor/packed_simd_2/src/codegen/math/float/abs.rs b/vendor/packed_simd_2/src/codegen/math/float/abs.rs index bc4421f61..34aacc25b 100644 --- a/vendor/packed_simd_2/src/codegen/math/float/abs.rs +++ b/vendor/packed_simd_2/src/codegen/math/float/abs.rs @@ -5,7 +5,7 @@ use crate::*; -crate trait Abs { +pub(crate) trait Abs { fn abs(self) -> Self; } diff --git a/vendor/packed_simd_2/src/codegen/math/float/cos.rs b/vendor/packed_simd_2/src/codegen/math/float/cos.rs index 50f6c16da..dec390cb7 100644 --- a/vendor/packed_simd_2/src/codegen/math/float/cos.rs +++ b/vendor/packed_simd_2/src/codegen/math/float/cos.rs @@ -5,7 +5,7 @@ use crate::*; -crate trait Cos { +pub(crate) trait Cos { fn cos(self) -> Self; } diff --git a/vendor/packed_simd_2/src/codegen/math/float/cos_pi.rs b/vendor/packed_simd_2/src/codegen/math/float/cos_pi.rs index ebff5fd1c..e283280ee 100644 --- a/vendor/packed_simd_2/src/codegen/math/float/cos_pi.rs +++ b/vendor/packed_simd_2/src/codegen/math/float/cos_pi.rs @@ -5,7 +5,7 @@ use crate::*; -crate trait CosPi { +pub(crate) trait CosPi { fn cos_pi(self) -> Self; } diff --git a/vendor/packed_simd_2/src/codegen/math/float/exp.rs b/vendor/packed_simd_2/src/codegen/math/float/exp.rs index 00d10e9fa..a7b20580e 100644 --- a/vendor/packed_simd_2/src/codegen/math/float/exp.rs +++ b/vendor/packed_simd_2/src/codegen/math/float/exp.rs @@ -5,7 +5,7 @@ use crate::*; -crate trait Exp { +pub(crate) trait Exp { fn exp(self) -> Self; } diff --git a/vendor/packed_simd_2/src/codegen/math/float/ln.rs b/vendor/packed_simd_2/src/codegen/math/float/ln.rs index 88a5a6c6c..a5e38cb40 100644 --- a/vendor/packed_simd_2/src/codegen/math/float/ln.rs +++ b/vendor/packed_simd_2/src/codegen/math/float/ln.rs @@ -5,7 +5,7 @@ use crate::*; -crate trait Ln { +pub(crate) trait Ln { fn ln(self) -> Self; } diff --git a/vendor/packed_simd_2/src/codegen/math/float/macros.rs b/vendor/packed_simd_2/src/codegen/math/float/macros.rs index 02d0ca3f5..8daee1afe 100644 --- a/vendor/packed_simd_2/src/codegen/math/float/macros.rs +++ b/vendor/packed_simd_2/src/codegen/math/float/macros.rs @@ -1,7 +1,6 @@ //! Utility macros #![allow(unused)] - macro_rules! impl_unary_ { // implementation mapping 1:1 (vec | $trait_id:ident, $trait_method:ident, $vec_id:ident, @@ -64,10 +63,8 @@ macro_rules! impl_unary_ { let mut halves = U { vec: self }.halves; - *halves.get_unchecked_mut(0) = - transmute($fun(transmute(*halves.get_unchecked(0)))); - *halves.get_unchecked_mut(1) = - transmute($fun(transmute(*halves.get_unchecked(1)))); + *halves.get_unchecked_mut(0) = transmute($fun(transmute(*halves.get_unchecked(0)))); + *halves.get_unchecked_mut(1) = transmute($fun(transmute(*halves.get_unchecked(1)))); U { halves }.vec } @@ -89,14 +86,10 @@ macro_rules! impl_unary_ { let mut quarters = U { vec: self }.quarters; - *quarters.get_unchecked_mut(0) = - transmute($fun(transmute(*quarters.get_unchecked(0)))); - *quarters.get_unchecked_mut(1) = - transmute($fun(transmute(*quarters.get_unchecked(1)))); - *quarters.get_unchecked_mut(2) = - transmute($fun(transmute(*quarters.get_unchecked(2)))); - *quarters.get_unchecked_mut(3) = - transmute($fun(transmute(*quarters.get_unchecked(3)))); + *quarters.get_unchecked_mut(0) = transmute($fun(transmute(*quarters.get_unchecked(0)))); + *quarters.get_unchecked_mut(1) = transmute($fun(transmute(*quarters.get_unchecked(1)))); + *quarters.get_unchecked_mut(2) = transmute($fun(transmute(*quarters.get_unchecked(2)))); + *quarters.get_unchecked_mut(3) = transmute($fun(transmute(*quarters.get_unchecked(3)))); U { quarters }.vec } @@ -137,43 +130,19 @@ macro_rules! gen_unary_impl_table { impl_unary_!(gen | $trait_id, $trait_method, $vid, $fun); }; ($vid:ident[$sid:ident; $sc:expr]: $fun:ident) => { - impl_unary_!( - scalar | $trait_id, - $trait_method, - $vid, - [$sid; $sc], - $fun - ); + impl_unary_!(scalar | $trait_id, $trait_method, $vid, [$sid; $sc], $fun); }; ($vid:ident[s]: $fun:ident) => { impl_unary_!(scalar | $trait_id, $trait_method, $vid, $fun); }; ($vid:ident[h => $vid_h:ident]: $fun:ident) => { - impl_unary_!( - halves | $trait_id, - $trait_method, - $vid, - $vid_h, - $fun - ); + impl_unary_!(halves | $trait_id, $trait_method, $vid, $vid_h, $fun); }; ($vid:ident[q => $vid_q:ident]: $fun:ident) => { - impl_unary_!( - quarter | $trait_id, - $trait_method, - $vid, - $vid_q, - $fun - ); + impl_unary_!(quarter | $trait_id, $trait_method, $vid, $vid_q, $fun); }; ($vid:ident[t => $vid_t:ident]: $fun:ident) => { - impl_unary_!( - twice | $trait_id, - $trait_method, - $vid, - $vid_t, - $fun - ); + impl_unary_!(twice | $trait_id, $trait_method, $vid, $vid_t, $fun); }; } }; @@ -188,11 +157,7 @@ macro_rules! impl_tertiary_ { fn $trait_method(self, y: Self, z: Self) -> Self { unsafe { use crate::mem::transmute; - transmute($fun( - transmute(self), - transmute(y), - transmute(z), - )) + transmute($fun(transmute(self), transmute(y), transmute(z))) } } } @@ -314,11 +279,8 @@ macro_rules! impl_tertiary_ { let x_twice = U { vec: [self, uninitialized()] }.twice; let y_twice = U { vec: [y, uninitialized()] }.twice; let z_twice = U { vec: [z, uninitialized()] }.twice; - let twice: $vect_id = transmute($fun( - transmute(x_twice), - transmute(y_twice), - transmute(z_twice), - )); + let twice: $vect_id = + transmute($fun(transmute(x_twice), transmute(y_twice), transmute(z_twice))); *(U { twice }.vec.get_unchecked(0)) } @@ -334,43 +296,19 @@ macro_rules! gen_tertiary_impl_table { impl_tertiary_!(vec | $trait_id, $trait_method, $vid, $fun); }; ($vid:ident[$sid:ident; $sc:expr]: $fun:ident) => { - impl_tertiary_!( - scalar | $trait_id, - $trait_method, - $vid, - [$sid; $sc], - $fun - ); + impl_tertiary_!(scalar | $trait_id, $trait_method, $vid, [$sid; $sc], $fun); }; ($vid:ident[s]: $fun:ident) => { impl_tertiary_!(scalar | $trait_id, $trait_method, $vid, $fun); }; ($vid:ident[h => $vid_h:ident]: $fun:ident) => { - impl_tertiary_!( - halves | $trait_id, - $trait_method, - $vid, - $vid_h, - $fun - ); + impl_tertiary_!(halves | $trait_id, $trait_method, $vid, $vid_h, $fun); }; ($vid:ident[q => $vid_q:ident]: $fun:ident) => { - impl_tertiary_!( - quarter | $trait_id, - $trait_method, - $vid, - $vid_q, - $fun - ); + impl_tertiary_!(quarter | $trait_id, $trait_method, $vid, $vid_q, $fun); }; ($vid:ident[t => $vid_t:ident]: $fun:ident) => { - impl_tertiary_!( - twice | $trait_id, - $trait_method, - $vid, - $vid_t, - $fun - ); + impl_tertiary_!(twice | $trait_id, $trait_method, $vid, $vid_t, $fun); }; } }; @@ -497,10 +435,7 @@ macro_rules! impl_binary_ { let x_twice = U { vec: [self, uninitialized()] }.twice; let y_twice = U { vec: [y, uninitialized()] }.twice; - let twice: $vect_id = transmute($fun( - transmute(x_twice), - transmute(y_twice), - )); + let twice: $vect_id = transmute($fun(transmute(x_twice), transmute(y_twice))); *(U { twice }.vec.get_unchecked(0)) } @@ -516,43 +451,19 @@ macro_rules! gen_binary_impl_table { impl_binary_!(vec | $trait_id, $trait_method, $vid, $fun); }; ($vid:ident[$sid:ident; $sc:expr]: $fun:ident) => { - impl_binary_!( - scalar | $trait_id, - $trait_method, - $vid, - [$sid; $sc], - $fun - ); + impl_binary_!(scalar | $trait_id, $trait_method, $vid, [$sid; $sc], $fun); }; ($vid:ident[s]: $fun:ident) => { impl_binary_!(scalar | $trait_id, $trait_method, $vid, $fun); }; ($vid:ident[h => $vid_h:ident]: $fun:ident) => { - impl_binary_!( - halves | $trait_id, - $trait_method, - $vid, - $vid_h, - $fun - ); + impl_binary_!(halves | $trait_id, $trait_method, $vid, $vid_h, $fun); }; ($vid:ident[q => $vid_q:ident]: $fun:ident) => { - impl_binary_!( - quarter | $trait_id, - $trait_method, - $vid, - $vid_q, - $fun - ); + impl_binary_!(quarter | $trait_id, $trait_method, $vid, $vid_q, $fun); }; ($vid:ident[t => $vid_t:ident]: $fun:ident) => { - impl_binary_!( - twice | $trait_id, - $trait_method, - $vid, - $vid_t, - $fun - ); + impl_binary_!(twice | $trait_id, $trait_method, $vid, $vid_t, $fun); }; } }; diff --git a/vendor/packed_simd_2/src/codegen/math/float/mul_add.rs b/vendor/packed_simd_2/src/codegen/math/float/mul_add.rs index f48a57dc4..d37f30fa8 100644 --- a/vendor/packed_simd_2/src/codegen/math/float/mul_add.rs +++ b/vendor/packed_simd_2/src/codegen/math/float/mul_add.rs @@ -4,7 +4,7 @@ use crate::*; // FIXME: 64-bit 1 element mul_add -crate trait MulAdd { +pub(crate) trait MulAdd { fn mul_add(self, y: Self, z: Self) -> Self; } diff --git a/vendor/packed_simd_2/src/codegen/math/float/mul_adde.rs b/vendor/packed_simd_2/src/codegen/math/float/mul_adde.rs index 8c41fb131..c0baeacec 100644 --- a/vendor/packed_simd_2/src/codegen/math/float/mul_adde.rs +++ b/vendor/packed_simd_2/src/codegen/math/float/mul_adde.rs @@ -3,7 +3,7 @@ use crate::*; // FIXME: 64-bit 1 element mul_adde -crate trait MulAddE { +pub(crate) trait MulAddE { fn mul_adde(self, y: Self, z: Self) -> Self; } @@ -38,13 +38,7 @@ macro_rules! impl_mul_adde { #[cfg(not(target_arch = "s390x"))] { use crate::mem::transmute; - unsafe { - transmute($fn( - transmute(self), - transmute(y), - transmute(z), - )) - } + unsafe { transmute($fn(transmute(self), transmute(y), transmute(z))) } } #[cfg(target_arch = "s390x")] { diff --git a/vendor/packed_simd_2/src/codegen/math/float/powf.rs b/vendor/packed_simd_2/src/codegen/math/float/powf.rs index bc15067d7..89ca52e96 100644 --- a/vendor/packed_simd_2/src/codegen/math/float/powf.rs +++ b/vendor/packed_simd_2/src/codegen/math/float/powf.rs @@ -5,7 +5,7 @@ use crate::*; -crate trait Powf { +pub(crate) trait Powf { fn powf(self, x: Self) -> Self; } diff --git a/vendor/packed_simd_2/src/codegen/math/float/sin.rs b/vendor/packed_simd_2/src/codegen/math/float/sin.rs index 7b014d07d..d88141590 100644 --- a/vendor/packed_simd_2/src/codegen/math/float/sin.rs +++ b/vendor/packed_simd_2/src/codegen/math/float/sin.rs @@ -5,7 +5,7 @@ use crate::*; -crate trait Sin { +pub(crate) trait Sin { fn sin(self) -> Self; } diff --git a/vendor/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs b/vendor/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs index 0f1249ec8..b283d1111 100644 --- a/vendor/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs +++ b/vendor/packed_simd_2/src/codegen/math/float/sin_cos_pi.rs @@ -5,7 +5,7 @@ use crate::*; -crate trait SinCosPi: Sized { +pub(crate) trait SinCosPi: Sized { type Output; fn sin_cos_pi(self) -> Self::Output; } @@ -85,17 +85,14 @@ macro_rules! impl_unary_t { let halves = U { vec: self }.halves; - let res_0: ($vid_h, $vid_h) = - transmute($fun(transmute(*halves.get_unchecked(0)))); - let res_1: ($vid_h, $vid_h) = - transmute($fun(transmute(*halves.get_unchecked(1)))); + let res_0: ($vid_h, $vid_h) = transmute($fun(transmute(*halves.get_unchecked(0)))); + let res_1: ($vid_h, $vid_h) = transmute($fun(transmute(*halves.get_unchecked(1)))); union R { result: ($vid, $vid), halves: ([$vid_h; 2], [$vid_h; 2]), } - R { halves: ([res_0.0, res_1.0], [res_0.1, res_1.1]) } - .result + R { halves: ([res_0.0, res_1.0], [res_0.1, res_1.1]) }.result } } } @@ -114,14 +111,10 @@ macro_rules! impl_unary_t { let quarters = U { vec: self }.quarters; - let res_0: ($vid_q, $vid_q) = - transmute($fun(transmute(*quarters.get_unchecked(0)))); - let res_1: ($vid_q, $vid_q) = - transmute($fun(transmute(*quarters.get_unchecked(1)))); - let res_2: ($vid_q, $vid_q) = - transmute($fun(transmute(*quarters.get_unchecked(2)))); - let res_3: ($vid_q, $vid_q) = - transmute($fun(transmute(*quarters.get_unchecked(3)))); + let res_0: ($vid_q, $vid_q) = transmute($fun(transmute(*quarters.get_unchecked(0)))); + let res_1: ($vid_q, $vid_q) = transmute($fun(transmute(*quarters.get_unchecked(1)))); + let res_2: ($vid_q, $vid_q) = transmute($fun(transmute(*quarters.get_unchecked(2)))); + let res_3: ($vid_q, $vid_q) = transmute($fun(transmute(*quarters.get_unchecked(3)))); union R { result: ($vid, $vid), diff --git a/vendor/packed_simd_2/src/codegen/math/float/sin_pi.rs b/vendor/packed_simd_2/src/codegen/math/float/sin_pi.rs index 72df98c93..0c8f6bb12 100644 --- a/vendor/packed_simd_2/src/codegen/math/float/sin_pi.rs +++ b/vendor/packed_simd_2/src/codegen/math/float/sin_pi.rs @@ -5,7 +5,7 @@ use crate::*; -crate trait SinPi { +pub(crate) trait SinPi { fn sin_pi(self) -> Self; } diff --git a/vendor/packed_simd_2/src/codegen/math/float/sqrt.rs b/vendor/packed_simd_2/src/codegen/math/float/sqrt.rs index 7ce31df62..67bb0a2a9 100644 --- a/vendor/packed_simd_2/src/codegen/math/float/sqrt.rs +++ b/vendor/packed_simd_2/src/codegen/math/float/sqrt.rs @@ -5,7 +5,7 @@ use crate::*; -crate trait Sqrt { +pub(crate) trait Sqrt { fn sqrt(self) -> Self; } diff --git a/vendor/packed_simd_2/src/codegen/math/float/sqrte.rs b/vendor/packed_simd_2/src/codegen/math/float/sqrte.rs index c1e379c34..58a1de1f4 100644 --- a/vendor/packed_simd_2/src/codegen/math/float/sqrte.rs +++ b/vendor/packed_simd_2/src/codegen/math/float/sqrte.rs @@ -6,7 +6,7 @@ use crate::llvm::simd_fsqrt; use crate::*; -crate trait Sqrte { +pub(crate) trait Sqrte { fn sqrte(self) -> Self; } diff --git a/vendor/packed_simd_2/src/codegen/math/float/tanh.rs b/vendor/packed_simd_2/src/codegen/math/float/tanh.rs index 5220c7d10..2c0dd3dc3 100644 --- a/vendor/packed_simd_2/src/codegen/math/float/tanh.rs +++ b/vendor/packed_simd_2/src/codegen/math/float/tanh.rs @@ -5,12 +5,11 @@ use crate::*; -crate trait Tanh { +pub(crate) trait Tanh { fn tanh(self) -> Self; } macro_rules! define_tanh { - ($name:ident, $basetype:ty, $simdtype:ty, $lanes:expr, $trait:path) => { fn $name(x: $simdtype) -> $simdtype { use core::intrinsics::transmute; @@ -31,8 +30,9 @@ macro_rules! define_tanh { }; } -// llvm does not seem to expose the hyperbolic versions of trigonometric functions; -// we thus call the classical rust versions on all of them (which stem from cmath). +// llvm does not seem to expose the hyperbolic versions of trigonometric +// functions; we thus call the classical rust versions on all of them (which +// stem from cmath). define_tanh!(f32 => tanh_v2f32, f32x2, 2); define_tanh!(f32 => tanh_v4f32, f32x4, 4); define_tanh!(f32 => tanh_v8f32, f32x8, 8); diff --git a/vendor/packed_simd_2/src/codegen/pointer_sized_int.rs b/vendor/packed_simd_2/src/codegen/pointer_sized_int.rs index 39f493d3b..55cbc297a 100644 --- a/vendor/packed_simd_2/src/codegen/pointer_sized_int.rs +++ b/vendor/packed_simd_2/src/codegen/pointer_sized_int.rs @@ -4,24 +4,24 @@ use cfg_if::cfg_if; cfg_if! { if #[cfg(target_pointer_width = "8")] { - crate type isize_ = i8; - crate type usize_ = u8; + pub(crate) type isize_ = i8; + pub(crate) type usize_ = u8; } else if #[cfg(target_pointer_width = "16")] { - crate type isize_ = i16; - crate type usize_ = u16; + pub(crate) type isize_ = i16; + pub(crate) type usize_ = u16; } else if #[cfg(target_pointer_width = "32")] { - crate type isize_ = i32; - crate type usize_ = u32; + pub(crate) type isize_ = i32; + pub(crate) type usize_ = u32; } else if #[cfg(target_pointer_width = "64")] { - crate type isize_ = i64; - crate type usize_ = u64; + pub(crate) type isize_ = i64; + pub(crate) type usize_ = u64; } else if #[cfg(target_pointer_width = "64")] { - crate type isize_ = i64; - crate type usize_ = u64; + pub(crate) type isize_ = i64; + pub(crate) type usize_ = u64; } else if #[cfg(target_pointer_width = "128")] { - crate type isize_ = i128; - crate type usize_ = u128; + pub(crate) type isize_ = i128; + pub(crate) type usize_ = u128; } else { compile_error!("unsupported target_pointer_width"); } diff --git a/vendor/packed_simd_2/src/codegen/reductions.rs b/vendor/packed_simd_2/src/codegen/reductions.rs index 7be4f5fab..302ca6d88 100644 --- a/vendor/packed_simd_2/src/codegen/reductions.rs +++ b/vendor/packed_simd_2/src/codegen/reductions.rs @@ -1 +1 @@ -crate mod mask; +pub(crate) mod mask; diff --git a/vendor/packed_simd_2/src/codegen/reductions/mask.rs b/vendor/packed_simd_2/src/codegen/reductions/mask.rs index 97260c6d4..a78bcc563 100644 --- a/vendor/packed_simd_2/src/codegen/reductions/mask.rs +++ b/vendor/packed_simd_2/src/codegen/reductions/mask.rs @@ -1,17 +1,17 @@ //! Code generation workaround for `all()` mask horizontal reduction. //! -//! Works arround [LLVM bug 36702]. +//! Works around [LLVM bug 36702]. //! //! [LLVM bug 36702]: https://bugs.llvm.org/show_bug.cgi?id=36702 #![allow(unused_macros)] use crate::*; -crate trait All: crate::marker::Sized { +pub(crate) trait All: crate::marker::Sized { unsafe fn all(self) -> bool; } -crate trait Any: crate::marker::Sized { +pub(crate) trait Any: crate::marker::Sized { unsafe fn any(self) -> bool; } diff --git a/vendor/packed_simd_2/src/codegen/reductions/mask/aarch64.rs b/vendor/packed_simd_2/src/codegen/reductions/mask/aarch64.rs index e9586eace..b2db52c89 100644 --- a/vendor/packed_simd_2/src/codegen/reductions/mask/aarch64.rs +++ b/vendor/packed_simd_2/src/codegen/reductions/mask/aarch64.rs @@ -19,7 +19,7 @@ macro_rules! aarch64_128_neon_impl { $vmax(crate::mem::transmute(self)) != 0 } } - } + }; } /// 64-bit wide vectors @@ -35,9 +35,7 @@ macro_rules! aarch64_64_neon_impl { halves: ($id, $id), vec: $vec128, } - U { - halves: (self, self), - }.vec.all() + U { halves: (self, self) }.vec.all() } } impl Any for $id { @@ -48,9 +46,7 @@ macro_rules! aarch64_64_neon_impl { halves: ($id, $id), vec: $vec128, } - U { - halves: (self, self), - }.vec.any() + U { halves: (self, self) }.vec.any() } } }; @@ -59,13 +55,27 @@ macro_rules! aarch64_64_neon_impl { /// Mask reduction implementation for `aarch64` targets macro_rules! impl_mask_reductions { // 64-bit wide masks - (m8x8) => { aarch64_64_neon_impl!(m8x8, m8x16); }; - (m16x4) => { aarch64_64_neon_impl!(m16x4, m16x8); }; - (m32x2) => { aarch64_64_neon_impl!(m32x2, m32x4); }; + (m8x8) => { + aarch64_64_neon_impl!(m8x8, m8x16); + }; + (m16x4) => { + aarch64_64_neon_impl!(m16x4, m16x8); + }; + (m32x2) => { + aarch64_64_neon_impl!(m32x2, m32x4); + }; // 128-bit wide masks - (m8x16) => { aarch64_128_neon_impl!(m8x16, vminvq_u8, vmaxvq_u8); }; - (m16x8) => { aarch64_128_neon_impl!(m16x8, vminvq_u16, vmaxvq_u16); }; - (m32x4) => { aarch64_128_neon_impl!(m32x4, vminvq_u32, vmaxvq_u32); }; + (m8x16) => { + aarch64_128_neon_impl!(m8x16, vminvq_u8, vmaxvq_u8); + }; + (m16x8) => { + aarch64_128_neon_impl!(m16x8, vminvq_u16, vmaxvq_u16); + }; + (m32x4) => { + aarch64_128_neon_impl!(m32x4, vminvq_u32, vmaxvq_u32); + }; // Fallback to LLVM's default code-generation: - ($id:ident) => { fallback_impl!($id); }; + ($id:ident) => { + fallback_impl!($id); + }; } diff --git a/vendor/packed_simd_2/src/codegen/reductions/mask/arm.rs b/vendor/packed_simd_2/src/codegen/reductions/mask/arm.rs index 1987af7a9..41c3cbc58 100644 --- a/vendor/packed_simd_2/src/codegen/reductions/mask/arm.rs +++ b/vendor/packed_simd_2/src/codegen/reductions/mask/arm.rs @@ -15,10 +15,7 @@ macro_rules! arm_128_v7_neon_impl { vec: $id, } let halves = U { vec: self }.halves; - let h: $half = transmute($vpmin( - transmute(halves.0), - transmute(halves.1), - )); + let h: $half = transmute($vpmin(transmute(halves.0), transmute(halves.1))); h.all() } } @@ -33,10 +30,7 @@ macro_rules! arm_128_v7_neon_impl { vec: $id, } let halves = U { vec: self }.halves; - let h: $half = transmute($vpmax( - transmute(halves.0), - transmute(halves.1), - )); + let h: $half = transmute($vpmax(transmute(halves.0), transmute(halves.1))); h.any() } } @@ -46,9 +40,17 @@ macro_rules! arm_128_v7_neon_impl { /// Mask reduction implementation for `arm` targets macro_rules! impl_mask_reductions { // 128-bit wide masks - (m8x16) => { arm_128_v7_neon_impl!(m8x16, m8x8, vpmin_u8, vpmax_u8); }; - (m16x8) => { arm_128_v7_neon_impl!(m16x8, m16x4, vpmin_u16, vpmax_u16); }; - (m32x4) => { arm_128_v7_neon_impl!(m32x4, m32x2, vpmin_u32, vpmax_u32); }; + (m8x16) => { + arm_128_v7_neon_impl!(m8x16, m8x8, vpmin_u8, vpmax_u8); + }; + (m16x8) => { + arm_128_v7_neon_impl!(m16x8, m16x4, vpmin_u16, vpmax_u16); + }; + (m32x4) => { + arm_128_v7_neon_impl!(m32x4, m32x2, vpmin_u32, vpmax_u32); + }; // Fallback to LLVM's default code-generation: - ($id:ident) => { fallback_impl!($id); }; + ($id:ident) => { + fallback_impl!($id); + }; } diff --git a/vendor/packed_simd_2/src/codegen/reductions/mask/fallback.rs b/vendor/packed_simd_2/src/codegen/reductions/mask/fallback.rs index 25e5c813a..4c377a687 100644 --- a/vendor/packed_simd_2/src/codegen/reductions/mask/fallback.rs +++ b/vendor/packed_simd_2/src/codegen/reductions/mask/fallback.rs @@ -2,5 +2,7 @@ /// Default mask reduction implementation macro_rules! impl_mask_reductions { - ($id:ident) => { fallback_impl!($id); }; + ($id:ident) => { + fallback_impl!($id); + }; } diff --git a/vendor/packed_simd_2/src/codegen/reductions/mask/x86.rs b/vendor/packed_simd_2/src/codegen/reductions/mask/x86.rs index bcfb1a6e1..4bf509806 100644 --- a/vendor/packed_simd_2/src/codegen/reductions/mask/x86.rs +++ b/vendor/packed_simd_2/src/codegen/reductions/mask/x86.rs @@ -114,17 +114,17 @@ macro_rules! x86_m64x4_impl { /// Fallback implementation. macro_rules! x86_intr_impl { ($id:ident) => { - impl All for $id { - #[inline] - unsafe fn all(self) -> bool { - use crate::llvm::simd_reduce_all; - simd_reduce_all(self.0) + impl All for $id { + #[inline] + unsafe fn all(self) -> bool { + use crate::llvm::simd_reduce_all; + simd_reduce_all(self.0) + } } - } impl Any for $id { #[inline] unsafe fn any(self) -> bool { - use crate::llvm::simd_reduce_any; + use crate::llvm::simd_reduce_any; simd_reduce_any(self.0) } } @@ -134,21 +134,47 @@ macro_rules! x86_intr_impl { /// Mask reduction implementation for `x86` and `x86_64` targets macro_rules! impl_mask_reductions { // 64-bit wide masks - (m8x8) => { x86_m8x8_impl!(m8x8); }; - (m16x4) => { x86_m8x8_impl!(m16x4); }; - (m32x2) => { x86_m8x8_impl!(m32x2); }; + (m8x8) => { + x86_m8x8_impl!(m8x8); + }; + (m16x4) => { + x86_m8x8_impl!(m16x4); + }; + (m32x2) => { + x86_m8x8_impl!(m32x2); + }; // 128-bit wide masks - (m8x16) => { x86_m8x16_impl!(m8x16); }; - (m16x8) => { x86_m8x16_impl!(m16x8); }; - (m32x4) => { x86_m32x4_impl!(m32x4); }; - (m64x2) => { x86_m64x2_impl!(m64x2); }; - (m128x1) => { x86_intr_impl!(m128x1); }; + (m8x16) => { + x86_m8x16_impl!(m8x16); + }; + (m16x8) => { + x86_m8x16_impl!(m16x8); + }; + (m32x4) => { + x86_m32x4_impl!(m32x4); + }; + (m64x2) => { + x86_m64x2_impl!(m64x2); + }; + (m128x1) => { + x86_intr_impl!(m128x1); + }; // 256-bit wide masks: - (m8x32) => { x86_m8x32_impl!(m8x32, m8x16); }; - (m16x16) => { x86_m8x32_impl!(m16x16, m16x8); }; - (m32x8) => { x86_m32x8_impl!(m32x8, m32x4); }; - (m64x4) => { x86_m64x4_impl!(m64x4, m64x2); }; - (m128x2) => { x86_intr_impl!(m128x2); }; + (m8x32) => { + x86_m8x32_impl!(m8x32, m8x16); + }; + (m16x16) => { + x86_m8x32_impl!(m16x16, m16x8); + }; + (m32x8) => { + x86_m32x8_impl!(m32x8, m32x4); + }; + (m64x4) => { + x86_m64x4_impl!(m64x4, m64x2); + }; + (m128x2) => { + x86_intr_impl!(m128x2); + }; (msizex2) => { cfg_if! { if #[cfg(target_pointer_width = "64")] { @@ -184,5 +210,7 @@ macro_rules! impl_mask_reductions { }; // Fallback to LLVM's default code-generation: - ($id:ident) => { fallback_impl!($id); }; + ($id:ident) => { + fallback_impl!($id); + }; } diff --git a/vendor/packed_simd_2/src/codegen/reductions/mask/x86/avx.rs b/vendor/packed_simd_2/src/codegen/reductions/mask/x86/avx.rs index d18736fb0..61f352d22 100644 --- a/vendor/packed_simd_2/src/codegen/reductions/mask/x86/avx.rs +++ b/vendor/packed_simd_2/src/codegen/reductions/mask/x86/avx.rs @@ -13,10 +13,7 @@ macro_rules! x86_m8x32_avx_impl { use crate::arch::x86::_mm256_testc_si256; #[cfg(target_arch = "x86_64")] use crate::arch::x86_64::_mm256_testc_si256; - _mm256_testc_si256( - crate::mem::transmute(self), - crate::mem::transmute($id::splat(true)), - ) != 0 + _mm256_testc_si256(crate::mem::transmute(self), crate::mem::transmute($id::splat(true))) != 0 } } impl Any for $id { @@ -27,10 +24,7 @@ macro_rules! x86_m8x32_avx_impl { use crate::arch::x86::_mm256_testz_si256; #[cfg(target_arch = "x86_64")] use crate::arch::x86_64::_mm256_testz_si256; - _mm256_testz_si256( - crate::mem::transmute(self), - crate::mem::transmute(self), - ) == 0 + _mm256_testz_si256(crate::mem::transmute(self), crate::mem::transmute(self)) == 0 } } }; diff --git a/vendor/packed_simd_2/src/codegen/reductions/mask/x86/sse.rs b/vendor/packed_simd_2/src/codegen/reductions/mask/x86/sse.rs index eb1ef7fac..e0c9aee92 100644 --- a/vendor/packed_simd_2/src/codegen/reductions/mask/x86/sse.rs +++ b/vendor/packed_simd_2/src/codegen/reductions/mask/x86/sse.rs @@ -16,8 +16,7 @@ macro_rules! x86_m32x4_sse_impl { // most significant bit of each lane of `a`. If all // bits are set, then all 4 lanes of the mask are // true. - _mm_movemask_ps(crate::mem::transmute(self)) - == 0b_1111_i32 + _mm_movemask_ps(crate::mem::transmute(self)) == 0b_1111_i32 } } impl Any for $id { diff --git a/vendor/packed_simd_2/src/codegen/reductions/mask/x86/sse2.rs b/vendor/packed_simd_2/src/codegen/reductions/mask/x86/sse2.rs index a99c606f5..bbb52fa47 100644 --- a/vendor/packed_simd_2/src/codegen/reductions/mask/x86/sse2.rs +++ b/vendor/packed_simd_2/src/codegen/reductions/mask/x86/sse2.rs @@ -16,8 +16,7 @@ macro_rules! x86_m64x2_sse2_impl { // most significant bit of each lane of `a`. If all // bits are set, then all 2 lanes of the mask are // true. - _mm_movemask_pd(crate::mem::transmute(self)) - == 0b_11_i32 + _mm_movemask_pd(crate::mem::transmute(self)) == 0b_11_i32 } } impl Any for $id { @@ -50,8 +49,7 @@ macro_rules! x86_m8x16_sse2_impl { // most significant bit of each byte of `a`. If all // bits are set, then all 16 lanes of the mask are // true. - _mm_movemask_epi8(crate::mem::transmute(self)) - == i32::from(u16::max_value()) + _mm_movemask_epi8(crate::mem::transmute(self)) == i32::from(u16::max_value()) } } impl Any for $id { diff --git a/vendor/packed_simd_2/src/codegen/shuffle.rs b/vendor/packed_simd_2/src/codegen/shuffle.rs index d92c9ee22..d3acd48f5 100644 --- a/vendor/packed_simd_2/src/codegen/shuffle.rs +++ b/vendor/packed_simd_2/src/codegen/shuffle.rs @@ -2,7 +2,7 @@ //! lanes and vector element types. use crate::masks::*; -use crate::sealed::{Shuffle, Seal}; +use crate::sealed::{Seal, Shuffle}; macro_rules! impl_shuffle { ($array:ty, $base:ty, $out:ty) => { @@ -10,7 +10,7 @@ macro_rules! impl_shuffle { impl Shuffle<$array> for $base { type Output = $out; } - } + }; } impl_shuffle! { [u32; 2], i8, crate::codegen::i8x2 } diff --git a/vendor/packed_simd_2/src/codegen/shuffle1_dyn.rs b/vendor/packed_simd_2/src/codegen/shuffle1_dyn.rs index 8d9577b26..19d457a45 100644 --- a/vendor/packed_simd_2/src/codegen/shuffle1_dyn.rs +++ b/vendor/packed_simd_2/src/codegen/shuffle1_dyn.rs @@ -16,8 +16,7 @@ macro_rules! impl_fallback { fn shuffle1_dyn(self, indices: Self::Indices) -> Self { let mut result = Self::splat(0); for i in 0..$id::lanes() { - result = result - .replace(i, self.extract(indices.extract(i) as usize)); + result = result.replace(i, self.extract(indices.extract(i) as usize)); } result } @@ -31,7 +30,7 @@ macro_rules! impl_shuffle1_dyn { if #[cfg(all( any( all(target_arch = "aarch64", target_feature = "neon"), - all(target_arch = "arm", target_feature = "v7", + all(target_arch = "doesnotexist", target_feature = "v7", target_feature = "neon") ), any(feature = "core_arch", libcore_neon) @@ -43,7 +42,7 @@ macro_rules! impl_shuffle1_dyn { fn shuffle1_dyn(self, indices: Self::Indices) -> Self { #[cfg(target_arch = "aarch64")] use crate::arch::aarch64::vtbl1_u8; - #[cfg(target_arch = "arm")] + #[cfg(target_arch = "doesnotexist")] use crate::arch::arm::vtbl1_u8; // This is safe because the binary is compiled with @@ -104,7 +103,7 @@ macro_rules! impl_shuffle1_dyn { } } } - } else if #[cfg(all(target_arch = "arm", target_feature = "v7", + } else if #[cfg(all(target_arch = "doesnotexist", target_feature = "v7", target_feature = "neon", any(feature = "core_arch", libcore_neon)))] { impl Shuffle1Dyn for u8x16 { @@ -150,16 +149,12 @@ macro_rules! impl_shuffle1_dyn { #[inline] fn shuffle1_dyn(self, indices: Self::Indices) -> Self { let indices: u8x8 = (indices * 2).cast(); - let indices: u8x16 = shuffle!( - indices, [0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7] - ); - let v = u8x16::new( - 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1 - ); + let indices: u8x16 = shuffle!(indices, [0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7]); + let v = u8x16::new(0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1); let indices = indices + v; unsafe { - let s: u8x16 =crate::mem::transmute(self); - crate::mem::transmute(s.shuffle1_dyn(indices)) + let s: u8x16 = crate::mem::transmute(self); + crate::mem::transmute(s.shuffle1_dyn(indices)) } } } @@ -268,7 +263,9 @@ macro_rules! impl_shuffle1_dyn { } } }; - ($id:ident) => { impl_fallback!($id); } + ($id:ident) => { + impl_fallback!($id); + }; } impl_shuffle1_dyn!(u8x2); diff --git a/vendor/packed_simd_2/src/codegen/swap_bytes.rs b/vendor/packed_simd_2/src/codegen/swap_bytes.rs index b435fb5da..9cf34a3e0 100644 --- a/vendor/packed_simd_2/src/codegen/swap_bytes.rs +++ b/vendor/packed_simd_2/src/codegen/swap_bytes.rs @@ -5,7 +5,7 @@ use crate::*; -crate trait SwapBytes { +pub(crate) trait SwapBytes { fn swap_bytes(self) -> Self; } @@ -15,7 +15,7 @@ macro_rules! impl_swap_bytes { impl SwapBytes for $id { #[inline] fn swap_bytes(self) -> Self { - unsafe { shuffle!(self, [1, 0]) } + shuffle!(self, [1, 0]) } } )+ @@ -119,52 +119,12 @@ macro_rules! impl_swap_bytes { impl_swap_bytes!(v16: u8x2, i8x2,); impl_swap_bytes!(v32: u8x4, i8x4, u16x2, i16x2,); // FIXME: 64-bit single element vector -impl_swap_bytes!( - v64: u8x8, - i8x8, - u16x4, - i16x4, - u32x2, - i32x2, /* u64x1, i64x1, */ -); +impl_swap_bytes!(v64: u8x8, i8x8, u16x4, i16x4, u32x2, i32x2 /* u64x1, i64x1, */,); -impl_swap_bytes!( - v128: u8x16, - i8x16, - u16x8, - i16x8, - u32x4, - i32x4, - u64x2, - i64x2, - u128x1, - i128x1, -); -impl_swap_bytes!( - v256: u8x32, - i8x32, - u16x16, - i16x16, - u32x8, - i32x8, - u64x4, - i64x4, - u128x2, - i128x2, -); +impl_swap_bytes!(v128: u8x16, i8x16, u16x8, i16x8, u32x4, i32x4, u64x2, i64x2, u128x1, i128x1,); +impl_swap_bytes!(v256: u8x32, i8x32, u16x16, i16x16, u32x8, i32x8, u64x4, i64x4, u128x2, i128x2,); -impl_swap_bytes!( - v512: u8x64, - i8x64, - u16x32, - i16x32, - u32x16, - i32x16, - u64x8, - i64x8, - u128x4, - i128x4, -); +impl_swap_bytes!(v512: u8x64, i8x64, u16x32, i16x32, u32x16, i32x16, u64x8, i64x8, u128x4, i128x4,); cfg_if! { if #[cfg(target_pointer_width = "8")] { diff --git a/vendor/packed_simd_2/src/codegen/vPtr.rs b/vendor/packed_simd_2/src/codegen/vPtr.rs index cf4765538..abd3aa877 100644 --- a/vendor/packed_simd_2/src/codegen/vPtr.rs +++ b/vendor/packed_simd_2/src/codegen/vPtr.rs @@ -5,7 +5,7 @@ macro_rules! impl_simd_ptr { | $($tys:ty),*) => { #[derive(Copy, Clone)] #[repr(simd)] - pub struct $tuple_id<$ty>($(crate $tys),*); + pub struct $tuple_id<$ty>($(pub(crate) $tys),*); //^^^^^^^ leaked through SimdArray impl<$ty> crate::sealed::Seal for [$ptr_ty; $elem_count] {} diff --git a/vendor/packed_simd_2/src/codegen/vSize.rs b/vendor/packed_simd_2/src/codegen/vSize.rs index 3911b2134..d5db03991 100644 --- a/vendor/packed_simd_2/src/codegen/vSize.rs +++ b/vendor/packed_simd_2/src/codegen/vSize.rs @@ -11,33 +11,6 @@ impl_simd_array!([isize; 4]: isizex4 | isize_, isize_, isize_, isize_); impl_simd_array!([usize; 4]: usizex4 | usize_, usize_, usize_, usize_); impl_simd_array!([msize; 4]: msizex4 | isize_, isize_, isize_, isize_); -impl_simd_array!( - [isize; 8]: isizex8 | isize_, - isize_, - isize_, - isize_, - isize_, - isize_, - isize_, - isize_ -); -impl_simd_array!( - [usize; 8]: usizex8 | usize_, - usize_, - usize_, - usize_, - usize_, - usize_, - usize_, - usize_ -); -impl_simd_array!( - [msize; 8]: msizex8 | isize_, - isize_, - isize_, - isize_, - isize_, - isize_, - isize_, - isize_ -); +impl_simd_array!([isize; 8]: isizex8 | isize_, isize_, isize_, isize_, isize_, isize_, isize_, isize_); +impl_simd_array!([usize; 8]: usizex8 | usize_, usize_, usize_, usize_, usize_, usize_, usize_, usize_); +impl_simd_array!([msize; 8]: msizex8 | isize_, isize_, isize_, isize_, isize_, isize_, isize_, isize_); diff --git a/vendor/packed_simd_2/src/lib.rs b/vendor/packed_simd_2/src/lib.rs index 4d12c9cd9..277cc818b 100644 --- a/vendor/packed_simd_2/src/lib.rs +++ b/vendor/packed_simd_2/src/lib.rs @@ -13,8 +13,8 @@ //! - [Vector types](#vector-types) //! - [Conditional operations](#conditional-operations) //! - [Conversions](#conversions) -//! - [Performance -//! guide](https://rust-lang-nursery.github.io/packed_simd/perf-guide/) +//! - [Hardware Features](#hardware-features) +//! - [Performance guide](https://rust-lang-nursery.github.io/packed_simd/perf-guide/) //! //! ## Introduction //! @@ -26,7 +26,7 @@ //! are applied to each vector lane in isolation of the others: //! //! ``` -//! # use packed_simd::*; +//! # use packed_simd_2::*; //! let a = i32x4::new(1, 2, 3, 4); //! let b = i32x4::new(5, 6, 7, 8); //! assert_eq!(a + b, i32x4::new(6, 8, 10, 12)); @@ -35,7 +35,7 @@ //! Many "horizontal" operations are also provided: //! //! ``` -//! # use packed_simd::*; +//! # use packed_simd_2::*; //! # let a = i32x4::new(1, 2, 3, 4); //! assert_eq!(a.wrapping_sum(), 10); //! ``` @@ -47,9 +47,9 @@ //! and performing a single horizontal operation at the end: //! //! ``` -//! # use packed_simd::*; +//! # use packed_simd_2::*; //! fn reduce(x: &[i32]) -> i32 { -//! assert!(x.len() % 4 == 0); +//! assert_eq!(x.len() % 4, 0); //! let mut sum = i32x4::splat(0); // [0, 0, 0, 0] //! for i in (0..x.len()).step_by(4) { //! sum += i32x4::from_slice_unaligned(&x[i..]); @@ -79,7 +79,7 @@ //! ## Basic operations //! //! ``` -//! # use packed_simd::*; +//! # use packed_simd_2::*; //! // Sets all elements to `0`: //! let a = i32x4::splat(0); //! @@ -107,7 +107,7 @@ //! to be performed: //! //! ``` -//! # use packed_simd::*; +//! # use packed_simd_2::*; //! let a = i32x4::new(1, 1, 2, 2); //! //! // Add `1` to the first two lanes of the vector. @@ -134,13 +134,13 @@ //! > of lanes as the mask. The example shows this by using [`m16x4`] instead //! > of [`m32x4`]. It is _typically_ more performant to use a mask element //! > width equal to the element width of the vectors being operated upon. -//! > This is, however, not true for 512-bit wide vectors when targetting +//! > This is, however, not true for 512-bit wide vectors when targeting //! > AVX-512, where the most efficient masks use only 1-bit per element. //! //! All vertical comparison operations returns masks: //! //! ``` -//! # use packed_simd::*; +//! # use packed_simd_2::*; //! let a = i32x4::new(1, 1, 3, 3); //! let b = i32x4::new(2, 2, 0, 0); //! @@ -168,11 +168,11 @@ //! u8x8 = m8x8::splat(true).into_bits();` is provided because all `m8x8` bit //! patterns are valid `u8x8` bit patterns. However, the opposite is not //! true, not all `u8x8` bit patterns are valid `m8x8` bit-patterns, so this -//! operation cannot be peformed safely using `x.into_bits()`; one needs to +//! operation cannot be performed safely using `x.into_bits()`; one needs to //! use `unsafe { crate::mem::transmute(x) }` for that, making sure that the //! value in the `u8x8` is a valid bit-pattern of `m8x8`. //! -//! * **numeric casts** (`as`): are peformed using [`FromCast`]/[`Cast`] +//! * **numeric casts** (`as`): are performed using [`FromCast`]/[`Cast`] //! (`x.cast()`), just like `as`: //! //! * casting integer vectors whose lane types have the same size (e.g. @@ -198,26 +198,36 @@ //! //! Numeric casts are not very "precise": sometimes lossy, sometimes value //! preserving, etc. +//! +//! ## Hardware Features +//! +//! This crate can use different hardware features based on your configured +//! `RUSTFLAGS`. For example, with no configured `RUSTFLAGS`, `u64x8` on +//! x86_64 will use SSE2 operations like `PCMPEQD`. If you configure +//! `RUSTFLAGS='-C target-feature=+avx2,+avx'` on supported x86_64 hardware +//! the same `u64x8` may use wider AVX2 operations like `VPCMPEQQ`. It is +//! important for performance and for hardware support requirements that +//! you choose an appropriate set of `target-feature` and `target-cpu` +//! options during builds. For more information, see the [Performance +//! guide](https://rust-lang-nursery.github.io/packed_simd/perf-guide/) #![feature( + adt_const_params, repr_simd, rustc_attrs, - const_fn, platform_intrinsics, stdsimd, - aarch64_target_feature, arm_target_feature, link_llvm_intrinsics, core_intrinsics, stmt_expr_attributes, - crate_visibility_modifier, custom_inner_attributes, - llvm_asm )] #![allow(non_camel_case_types, non_snake_case, // FIXME: these types are unsound in C FFI already // See https://github.com/rust-lang/rust/issues/53346 improper_ctypes_definitions, + incomplete_features, clippy::cast_possible_truncation, clippy::cast_lossless, clippy::cast_possible_wrap, @@ -228,6 +238,7 @@ // See https://github.com/rust-lang/rust-clippy/issues/3410 clippy::use_self, clippy::wrong_self_convention, + clippy::from_over_into, )] #![cfg_attr(test, feature(hashmap_internals))] #![deny(rust_2018_idioms, clippy::missing_inline_in_public_items)] @@ -250,9 +261,8 @@ use wasm_bindgen_test::*; #[allow(unused_imports)] use core::{ - /* arch (handled above), */ cmp, f32, f64, fmt, hash, hint, i128, - i16, i32, i64, i8, intrinsics, isize, iter, marker, mem, ops, ptr, slice, - u128, u16, u32, u64, u8, usize, + /* arch (handled above), */ cmp, f32, f64, fmt, hash, hint, i128, i16, i32, i64, i8, intrinsics, + isize, iter, marker, mem, ops, ptr, slice, u128, u16, u32, u64, u8, usize, }; #[macro_use] @@ -262,14 +272,14 @@ mod api; mod codegen; mod sealed; -pub use crate::sealed::{Simd as SimdVector, Shuffle, SimdArray, Mask}; +pub use crate::sealed::{Mask, Shuffle, Simd as SimdVector, SimdArray}; /// Packed SIMD vector type. /// /// # Examples /// /// ``` -/// # use packed_simd::Simd; +/// # use packed_simd_2::Simd; /// let v = Simd::<[i32; 4]>::new(0, 1, 2, 3); /// assert_eq!(v.extract(2), 2); /// ``` @@ -328,10 +338,10 @@ pub use self::api::into_bits::*; // Re-export the shuffle intrinsics required by the `shuffle!` macro. #[doc(hidden)] pub use self::codegen::llvm::{ - __shuffle_vector16, __shuffle_vector2, __shuffle_vector32, - __shuffle_vector4, __shuffle_vector64, __shuffle_vector8, + __shuffle_vector16, __shuffle_vector2, __shuffle_vector32, __shuffle_vector4, __shuffle_vector64, + __shuffle_vector8, }; -crate mod llvm { - crate use crate::codegen::llvm::*; +pub(crate) mod llvm { + pub(crate) use crate::codegen::llvm::*; } diff --git a/vendor/packed_simd_2/src/masks.rs b/vendor/packed_simd_2/src/masks.rs index aeb36d232..04534eab2 100644 --- a/vendor/packed_simd_2/src/masks.rs +++ b/vendor/packed_simd_2/src/masks.rs @@ -54,9 +54,7 @@ macro_rules! impl_mask_ty { impl PartialOrd<$id> for $id { #[inline] - fn partial_cmp( - &self, other: &Self, - ) -> Option { + fn partial_cmp(&self, other: &Self) -> Option { use crate::cmp::Ordering; if self == other { Some(Ordering::Equal) @@ -107,9 +105,7 @@ macro_rules! impl_mask_ty { impl crate::fmt::Debug for $id { #[inline] - fn fmt( - &self, fmtter: &mut crate::fmt::Formatter<'_>, - ) -> Result<(), crate::fmt::Error> { + fn fmt(&self, fmtter: &mut crate::fmt::Formatter<'_>) -> Result<(), crate::fmt::Error> { write!(fmtter, "{}({})", stringify!($id), self.0 != 0) } } diff --git a/vendor/packed_simd_2/src/testing.rs b/vendor/packed_simd_2/src/testing.rs index fcbcf9e2a..6320b2805 100644 --- a/vendor/packed_simd_2/src/testing.rs +++ b/vendor/packed_simd_2/src/testing.rs @@ -5,4 +5,4 @@ mod macros; #[cfg(test)] #[macro_use] -crate mod utils; +pub(crate) mod utils; diff --git a/vendor/packed_simd_2/src/testing/macros.rs b/vendor/packed_simd_2/src/testing/macros.rs index 6008634c7..7bc4268b9 100644 --- a/vendor/packed_simd_2/src/testing/macros.rs +++ b/vendor/packed_simd_2/src/testing/macros.rs @@ -3,26 +3,26 @@ macro_rules! test_if { ($cfg_tt:tt: $it:item) => { #[cfg(any( - // Test everything if: - // - // * tests are enabled, - // * no features about exclusively testing - // specific vector classes are enabled - all(test, not(any( - test_v16, - test_v32, - test_v64, - test_v128, - test_v256, - test_v512, - test_none, // disables all tests - ))), - // Test if: - // - // * tests are enabled - // * a particular cfg token tree returns true - all(test, $cfg_tt), - ))] + // Test everything if: + // + // * tests are enabled, + // * no features about exclusively testing + // specific vector classes are enabled + all(test, not(any( + test_v16, + test_v32, + test_v64, + test_v128, + test_v256, + test_v512, + test_none, // disables all tests + ))), + // Test if: + // + // * tests are enabled + // * a particular cfg token tree returns true + all(test, $cfg_tt), + ))] $it }; } diff --git a/vendor/packed_simd_2/src/testing/utils.rs b/vendor/packed_simd_2/src/testing/utils.rs index 21f27aae5..7d8f39573 100644 --- a/vendor/packed_simd_2/src/testing/utils.rs +++ b/vendor/packed_simd_2/src/testing/utils.rs @@ -7,16 +7,15 @@ use crate::{cmp::PartialOrd, fmt::Debug, LexicographicallyOrdered}; /// Tests PartialOrd for `a` and `b` where `a < b` is true. -pub fn test_lt( - a: LexicographicallyOrdered, b: LexicographicallyOrdered, -) where +pub fn test_lt(a: LexicographicallyOrdered, b: LexicographicallyOrdered) +where LexicographicallyOrdered: Debug + PartialOrd, { assert!(a < b, "{:?}, {:?}", a, b); assert!(b > a, "{:?}, {:?}", a, b); assert!(!(a == b), "{:?}, {:?}", a, b); - assert!(a != b, "{:?}, {:?}", a, b); + assert_ne!(a, b, "{:?}, {:?}", a, b); assert!(a <= b, "{:?}, {:?}", a, b); assert!(b >= a, "{:?}, {:?}", a, b); @@ -37,9 +36,8 @@ pub fn test_lt( } /// Tests PartialOrd for `a` and `b` where `a <= b` is true. -pub fn test_le( - a: LexicographicallyOrdered, b: LexicographicallyOrdered, -) where +pub fn test_le(a: LexicographicallyOrdered, b: LexicographicallyOrdered) +where LexicographicallyOrdered: Debug + PartialOrd, { assert!(a <= b, "{:?}, {:?}", a, b); @@ -54,14 +52,15 @@ pub fn test_le( assert!(!(a != b), "{:?}, {:?}", a, b); } else { - assert!(a != b, "{:?}, {:?}", a, b); + assert_ne!(a, b, "{:?}, {:?}", a, b); test_lt(a, b); } } /// Test PartialOrd::partial_cmp for `a` and `b` returning `Ordering` pub fn test_cmp( - a: LexicographicallyOrdered, b: LexicographicallyOrdered, + a: LexicographicallyOrdered, + b: LexicographicallyOrdered, o: Option, ) where LexicographicallyOrdered: PartialOrd + Debug, @@ -72,18 +71,8 @@ pub fn test_cmp( let mut arr_a: [T::Element; 64] = [Default::default(); 64]; let mut arr_b: [T::Element; 64] = [Default::default(); 64]; - unsafe { - crate::ptr::write_unaligned( - arr_a.as_mut_ptr() as *mut LexicographicallyOrdered, - a, - ) - } - unsafe { - crate::ptr::write_unaligned( - arr_b.as_mut_ptr() as *mut LexicographicallyOrdered, - b, - ) - } + unsafe { crate::ptr::write_unaligned(arr_a.as_mut_ptr() as *mut LexicographicallyOrdered, a) } + unsafe { crate::ptr::write_unaligned(arr_b.as_mut_ptr() as *mut LexicographicallyOrdered, b) } let expected = arr_a[0..T::LANES].partial_cmp(&arr_b[0..T::LANES]); let result = a.partial_cmp(&b); assert_eq!(expected, result, "{:?}, {:?}", a, b); @@ -134,8 +123,7 @@ macro_rules! ptr_vals { // all bits cleared let clear: <$id as sealed::Simd>::Element = crate::mem::zeroed(); // all bits set - let set: <$id as sealed::Simd>::Element = - crate::mem::transmute(-1_isize); + let set: <$id as sealed::Simd>::Element = crate::mem::transmute(-1_isize); (clear, set) } }; diff --git a/vendor/packed_simd_2/tests/endianness.rs b/vendor/packed_simd_2/tests/endianness.rs index 31fb7073a..da12c2338 100644 --- a/vendor/packed_simd_2/tests/endianness.rs +++ b/vendor/packed_simd_2/tests/endianness.rs @@ -1,7 +1,7 @@ #[cfg(target_arch = "wasm32")] use wasm_bindgen_test::*; -use packed_simd::*; +use packed_simd_2::*; use std::{mem, slice}; #[cfg_attr(not(target_arch = "wasm32"), test)] @@ -57,9 +57,7 @@ fn endian_load_and_stores() { 8, 9, 10, 11, 12, 13, 14, 15, ); let mut y: [i16; 8] = [0; 8]; - x.write_to_slice_unaligned(unsafe { - slice::from_raw_parts_mut(&mut y as *mut _ as *mut i8, 16) - }); + x.write_to_slice_unaligned(unsafe { slice::from_raw_parts_mut(&mut y as *mut _ as *mut i8, 16) }); let e: [i16; 8] = if cfg!(target_endian = "little") { [256, 770, 1284, 1798, 2312, 2826, 3340, 3854] @@ -68,9 +66,7 @@ fn endian_load_and_stores() { }; assert_eq!(y, e); - let z = i8x16::from_slice_unaligned(unsafe { - slice::from_raw_parts(&y as *const _ as *const i8, 16) - }); + let z = i8x16::from_slice_unaligned(unsafe { slice::from_raw_parts(&y as *const _ as *const i8, 16) }); assert_eq!(z, x); } -- cgit v1.2.3