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- // MIR for `main` before PreCodegen
+ // MIR for `main` after PreCodegen
fn main() -> () {
let mut _0: (); // return place in scope 0 at $DIR/issue-73223.rs:+0:11: +0:11
let _1: i32; // in scope 0 at $DIR/issue-73223.rs:+1:9: +1:14
let mut _2: std::option::Option<i32>; // in scope 0 at $DIR/issue-73223.rs:+1:23: +1:30
let _3: i32; // in scope 0 at $DIR/issue-73223.rs:+2:14: +2:15
let mut _5: (&i32, &i32); // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
let mut _6: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
let mut _7: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
let mut _10: bool; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
let mut _11: bool; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
let mut _12: i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
let _14: !; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
let mut _15: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
let _16: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
let mut _17: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
let _18: &i32; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
let mut _19: std::option::Option<std::fmt::Arguments>; // in scope 0 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
scope 1 {
debug split => _1; // in scope 1 at $DIR/issue-73223.rs:+1:9: +1:14
let _4: std::option::Option<i32>; // in scope 1 at $DIR/issue-73223.rs:+6:9: +6:14
scope 3 {
debug _prev => _4; // in scope 3 at $DIR/issue-73223.rs:+6:9: +6:14
let _8: &i32; // in scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
let _9: &i32; // in scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
let mut _20: &i32; // in scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
scope 4 {
debug left_val => _8; // in scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
debug right_val => _9; // in scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
let _13: core::panicking::AssertKind; // in scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
scope 5 {
debug kind => _13; // in scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
}
}
}
}
scope 2 {
debug v => _3; // in scope 2 at $DIR/issue-73223.rs:+2:14: +2:15
}
bb0: {
StorageLive(_1); // scope 0 at $DIR/issue-73223.rs:+1:9: +1:14
StorageLive(_2); // scope 0 at $DIR/issue-73223.rs:+1:23: +1:30
Deinit(_2); // scope 0 at $DIR/issue-73223.rs:+1:23: +1:30
((_2 as Some).0: i32) = const 1_i32; // scope 0 at $DIR/issue-73223.rs:+1:23: +1:30
discriminant(_2) = 1; // scope 0 at $DIR/issue-73223.rs:+1:23: +1:30
StorageLive(_3); // scope 0 at $DIR/issue-73223.rs:+2:14: +2:15
_3 = ((_2 as Some).0: i32); // scope 0 at $DIR/issue-73223.rs:+2:14: +2:15
_1 = _3; // scope 2 at $DIR/issue-73223.rs:+2:20: +2:21
StorageDead(_3); // scope 0 at $DIR/issue-73223.rs:+2:20: +2:21
StorageDead(_2); // scope 0 at $DIR/issue-73223.rs:+4:6: +4:7
StorageLive(_4); // scope 1 at $DIR/issue-73223.rs:+6:9: +6:14
StorageLive(_5); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageLive(_6); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
_6 = &_1; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageLive(_7); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
_20 = const main::promoted[0]; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
// mir::Constant
// + span: $SRC_DIR/core/src/macros/mod.rs:LL:COL
// + literal: Const { ty: &i32, val: Unevaluated(main, [], Some(promoted[0])) }
_7 = _20; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
Deinit(_5); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
(_5.0: &i32) = move _6; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
(_5.1: &i32) = move _7; // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageDead(_7); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageDead(_6); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageLive(_8); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
_8 = (_5.0: &i32); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageLive(_9); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
_9 = (_5.1: &i32); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageLive(_10); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageLive(_11); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageLive(_12); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
_12 = (*_8); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
_11 = Eq(move _12, const 1_i32); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageDead(_12); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
_10 = Not(move _11); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageDead(_11); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
switchInt(move _10) -> [false: bb2, otherwise: bb1]; // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
}
bb1: {
StorageLive(_13); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageLive(_14); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageLive(_15); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageLive(_16); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
_16 = _8; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
_15 = _16; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageLive(_17); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageLive(_18); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
_18 = _9; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
_17 = _18; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageLive(_19); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
Deinit(_19); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
discriminant(_19) = 0; // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
_14 = core::panicking::assert_failed::<i32, i32>(const core::panicking::AssertKind::Eq, move _15, move _17, move _19); // scope 5 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
// mir::Constant
// + span: $SRC_DIR/core/src/macros/mod.rs:LL:COL
// + literal: Const { ty: for<'r, 's, 't0> fn(core::panicking::AssertKind, &'r i32, &'s i32, Option<Arguments<'t0>>) -> ! {core::panicking::assert_failed::<i32, i32>}, val: Value(<ZST>) }
// mir::Constant
// + span: $SRC_DIR/core/src/macros/mod.rs:LL:COL
// + literal: Const { ty: core::panicking::AssertKind, val: Value(Scalar(0x00)) }
}
bb2: {
StorageDead(_10); // scope 4 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageDead(_9); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageDead(_8); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageDead(_5); // scope 3 at $SRC_DIR/core/src/macros/mod.rs:LL:COL
StorageDead(_4); // scope 1 at $DIR/issue-73223.rs:+8:1: +8:2
StorageDead(_1); // scope 0 at $DIR/issue-73223.rs:+8:1: +8:2
return; // scope 0 at $DIR/issue-73223.rs:+8:2: +8:2
}
}
|
