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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-14 19:33:30 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-14 19:33:30 +0000 |
| commit | c61e14d3a8412cd50d98aab604e607692c844c8a (patch) | |
| tree | 4925aca0e6b64c8664ea2f3fdfa99a52dc93d5da /tests/expected/lscpu | |
| parent | Adding upstream version 2.39.3. (diff) | |
| download | util-linux-c61e14d3a8412cd50d98aab604e607692c844c8a.tar.xz util-linux-c61e14d3a8412cd50d98aab604e607692c844c8a.zip | |
Adding upstream version 2.40.upstream/2.40
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'tests/expected/lscpu')
| -rw-r--r-- | tests/expected/lscpu/lscpu-rv64-linux | 19 | ||||
| -rw-r--r-- | tests/expected/lscpu/lscpu-rv64-visionfive2 | 33 |
2 files changed, 46 insertions, 6 deletions
diff --git a/tests/expected/lscpu/lscpu-rv64-linux b/tests/expected/lscpu/lscpu-rv64-linux index 22767db..d741cae 100644 --- a/tests/expected/lscpu/lscpu-rv64-linux +++ b/tests/expected/lscpu/lscpu-rv64-linux @@ -1,16 +1,23 @@ CPU(s): 2 On-line CPU(s) list: 0,1 +Model name: sifive,u74-mc +Thread(s) per core: 2 +Core(s) per socket: 1 +Socket(s): 1 +L1d cache: 64 KiB (2 instances) +L1i cache: 64 KiB (2 instances) +L2 cache: 2 MiB (1 instance) # The following is the parsable format, which can be fed to other # programs. Each different item in every column has an unique ID # starting usually from zero. -# CPU,Core,Socket,Node -,,, -,,, +# CPU,Core,Socket,Node,,L1d,L1i,L2 +0,0,0,,,0,0,0 +1,0,0,,,1,1,0 # The following is the parsable format, which can be fed to other # programs. Each different item in every column has an unique ID # starting usually from zero. -# CPU,Core,Socket,Node -,,, -,,, +# CPU,Core,Socket,Node,,L1d,L1i,L2 +0,-,-,,,0,0,0 +1,-,-,,,1,1,0 diff --git a/tests/expected/lscpu/lscpu-rv64-visionfive2 b/tests/expected/lscpu/lscpu-rv64-visionfive2 new file mode 100644 index 0000000..0b2390d --- /dev/null +++ b/tests/expected/lscpu/lscpu-rv64-visionfive2 @@ -0,0 +1,33 @@ +Byte Order: Little Endian +CPU(s): 4 +On-line CPU(s) list: 0-3 +Vendor ID: 0x489 +Model name: sifive,u74-mc +CPU family: 0x8000000000000007 +Model: 0x4210427 +Thread(s) per core: 1 +Core(s) per socket: 4 +Socket(s): 1 +L1d cache: 128 KiB (4 instances) +L1i cache: 128 KiB (4 instances) +L2 cache: 2 MiB (1 instance) +NUMA node(s): 1 +NUMA node0 CPU(s): 0-3 + +# The following is the parsable format, which can be fed to other +# programs. Each different item in every column has an unique ID +# starting usually from zero. +# CPU,Core,Socket,Node,,L1d,L1i,L2 +0,0,0,0,,0,0,0 +1,1,0,0,,1,1,0 +2,2,0,0,,2,2,0 +3,3,0,0,,3,3,0 + +# The following is the parsable format, which can be fed to other +# programs. Each different item in every column has an unique ID +# starting usually from zero. +# CPU,Core,Socket,Node,,L1d,L1i,L2 +0,3,0,0,,0,0,0 +1,1,0,0,,1,1,0 +2,2,0,0,,2,2,0 +3,4,0,0,,3,3,0 |