diff options
Diffstat (limited to 'tests/expected/lscpu/lscpu-loongarch-loongson_3a5000_hv')
| -rw-r--r-- | tests/expected/lscpu/lscpu-loongarch-loongson_3a5000_hv | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/tests/expected/lscpu/lscpu-loongarch-loongson_3a5000_hv b/tests/expected/lscpu/lscpu-loongarch-loongson_3a5000_hv new file mode 100644 index 0000000..825de7a --- /dev/null +++ b/tests/expected/lscpu/lscpu-loongarch-loongson_3a5000_hv @@ -0,0 +1,37 @@ +CPU op-mode(s): 32-bit, 64-bit +Address sizes: 48 bits physical, 48 bits virtual +Byte Order: Little Endian +CPU(s): 4 +On-line CPU(s) list: 0-3 +Model name: Loongson-3A5000-HV +CPU family: Loongson-64bit +Model: 0x11 +Thread(s) per core: 1 +Core(s) per socket: 4 +Socket(s): 1 +BogoMIPS: 5000.00 +Flags: cpucfg lam ual fpu lsx lasx complex crypto lvz +L1d cache: 256 KiB (4 instances) +L1i cache: 256 KiB (4 instances) +L2 cache: 1 MiB (4 instances) +L3 cache: 16 MiB (1 instance) +NUMA node(s): 1 +NUMA node0 CPU(s): 0-3 + +# The following is the parsable format, which can be fed to other +# programs. Each different item in every column has an unique ID +# starting usually from zero. +# CPU,Core,Socket,Node,,L1d,L1i,L2,L3 +0,0,0,0,,0,0,0,0 +1,1,0,0,,1,1,1,0 +2,2,0,0,,2,2,2,0 +3,3,0,0,,3,3,3,0 + +# The following is the parsable format, which can be fed to other +# programs. Each different item in every column has an unique ID +# starting usually from zero. +# CPU,Core,Socket,Node,,L1d,L1i,L2,L3 +0,0,0,0,,0,0,0,0 +1,1,0,0,,1,1,1,0 +2,2,0,0,,2,2,2,0 +3,3,0,0,,3,3,3,0 |