Adding upstream version 7.0.14-dfsg.upstream/7.0.14-dfsg

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

5 files changed, 206 insertions, 0 deletions

diff --git a/src/VBox/Devices/EFI/Firmware/CryptoPkg/Library/IntrinsicLib/Ia32/MathFtol.c b/src/VBox/Devices/EFI/Firmware/CryptoPkg/Library/IntrinsicLib/Ia32/MathFtol.c
new file mode 100644
index 00000000..02df0e8d
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/CryptoPkg/Library/IntrinsicLib/Ia32/MathFtol.c
@@ -0,0 +1,22 @@
+/** @file
+  64-bit Math Worker Function.
+  The 32-bit versions of C compiler generate calls to library routines
+  to handle 64-bit math. These functions use non-standard calling conventions.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/*
+ * Floating point to integer conversion.
+ */
+__declspec(naked) void _ftol2 (void)
+{
+  _asm {
+    fistp qword ptr [esp-8]
+    mov   edx, [esp-4]
+    mov   eax, [esp-8]
+    ret
+  }
+}
diff --git a/src/VBox/Devices/EFI/Firmware/CryptoPkg/Library/IntrinsicLib/Ia32/MathLShiftS64.c b/src/VBox/Devices/EFI/Firmware/CryptoPkg/Library/IntrinsicLib/Ia32/MathLShiftS64.c
new file mode 100644
index 00000000..3b1255db
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/CryptoPkg/Library/IntrinsicLib/Ia32/MathLShiftS64.c
@@ -0,0 +1,48 @@
+/** @file
+  64-bit Math Worker Function.
+  The 32-bit versions of C compiler generate calls to library routines
+  to handle 64-bit math. These functions use non-standard calling conventions.
+
+Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+/*
+ * Shifts a 64-bit signed value left by a particular number of bits.
+ */
+__declspec(naked) void __cdecl _allshl (void)
+{
+  _asm {
+    ;
+    ; Handle shifting of 64 or more bits (return 0)
+    ;
+    cmp     cl, 64
+    jae     short ReturnZero
+
+    ;
+    ; Handle shifting of between 0 and 31 bits
+    ;
+    cmp     cl, 32
+    jae     short More32
+    shld    edx, eax, cl
+    shl     eax, cl
+    ret
+
+    ;
+    ; Handle shifting of between 32 and 63 bits
+    ;
+More32:
+    mov     edx, eax
+    xor     eax, eax
+    and     cl, 31
+    shl     edx, cl
+    ret
+
+ReturnZero:
+    xor     eax,eax
+    xor     edx,edx
+    ret
+  }
+}
diff --git a/src/VBox/Devices/EFI/Firmware/CryptoPkg/Library/IntrinsicLib/Ia32/MathLShiftS64.nasm b/src/VBox/Devices/EFI/Firmware/CryptoPkg/Library/IntrinsicLib/Ia32/MathLShiftS64.nasm
new file mode 100644
index 00000000..110ffec4
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/CryptoPkg/Library/IntrinsicLib/Ia32/MathLShiftS64.nasm
@@ -0,0 +1,42 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+;   MathLShiftS64.nasm
+;
+; Abstract:
+;
+;   64-bit Math Worker Function.
+;   Shifts a 64-bit signed value left by a certain number of bits.
+;
+;------------------------------------------------------------------------------
+
+    SECTION .text
+
+global ASM_PFX(__ashldi3)
+;------------------------------------------------------------------------------
+;
+; void __cdecl __ashldi3 (void)
+;
+;------------------------------------------------------------------------------
+ASM_PFX(__ashldi3):
+    cmp cl,0x40
+    jnc ReturnZero
+    cmp cl,0x20
+    jnc More32
+    shld edx,eax,cl
+    shl eax,cl
+    ret
+More32:
+    mov edx,eax
+    xor eax,eax
+    and cl,0x1f
+    shl edx,cl
+    ret
+ReturnZero:
+    xor eax,eax
+    xor edx,edx
+    ret
diff --git a/src/VBox/Devices/EFI/Firmware/CryptoPkg/Library/IntrinsicLib/Ia32/MathRShiftU64.c b/src/VBox/Devices/EFI/Firmware/CryptoPkg/Library/IntrinsicLib/Ia32/MathRShiftU64.c
new file mode 100644
index 00000000..29497692
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/CryptoPkg/Library/IntrinsicLib/Ia32/MathRShiftU64.c
@@ -0,0 +1,51 @@
+/** @file
+  64-bit Math Worker Function.
+  The 32-bit versions of C compiler generate calls to library routines
+  to handle 64-bit math. These functions use non-standard calling conventions.
+
+Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+/*
+ * Shifts a 64-bit unsigned value right by a certain number of bits.
+ */
+__declspec(naked) void __cdecl _aullshr (void)
+{
+  _asm {
+    ;
+    ; Checking: Only handle 64bit shifting or more
+    ;
+    cmp     cl, 64
+    jae     _Exit
+
+    ;
+    ; Handle shifting between 0 and 31 bits
+    ;
+    cmp     cl, 32
+    jae     More32
+    shrd    eax, edx, cl
+    shr     edx, cl
+    ret
+
+    ;
+    ; Handle shifting of 32-63 bits
+    ;
+More32:
+    mov     eax, edx
+    xor     edx, edx
+    and     cl, 31
+    shr     eax, cl
+    ret
+
+    ;
+    ; Invalid number (less then 32bits), return 0
+    ;
+_Exit:
+    xor     eax, eax
+    xor     edx, edx
+    ret
+  }
+}
diff --git a/src/VBox/Devices/EFI/Firmware/CryptoPkg/Library/IntrinsicLib/Ia32/MathRShiftU64.nasm b/src/VBox/Devices/EFI/Firmware/CryptoPkg/Library/IntrinsicLib/Ia32/MathRShiftU64.nasm
new file mode 100644
index 00000000..2939aad4
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/CryptoPkg/Library/IntrinsicLib/Ia32/MathRShiftU64.nasm
@@ -0,0 +1,43 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+;   MathRShiftU64.nasm
+;
+; Abstract:
+;
+;   64-bit Math Worker Function.
+;   Shifts a 64-bit unsigned value right by a certain number of bits.
+;
+;------------------------------------------------------------------------------
+
+    SECTION .text
+
+;------------------------------------------------------------------------------
+;
+; void __cdecl __ashrdi3 (void)
+;
+;------------------------------------------------------------------------------
+global ASM_PFX(__ashrdi3)
+ASM_PFX(__ashrdi3):
+    cmp cl,0x40
+    jnc _Exit
+    cmp cl,0x20
+    jnc More32
+    shrd eax,edx,cl
+    shr edx,cl
+    ret
+More32:
+    mov eax,edx
+    xor edx,edx
+    and cl,0x1f
+    shr eax,cl
+    ret
+_Exit:
+    xor eax,eax
+    xor edx,edx
+    ret
+