Adding upstream version 7.0.14-dfsg.upstream/7.0.14-dfsg

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

5 files changed, 259 insertions, 0 deletions

diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/FspSecCore/Vtf0/Bin/ResetVec.ia32.raw b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/FspSecCore/Vtf0/Bin/ResetVec.ia32.raw
new file mode 100644
index 00000000..2dc9f178
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/FspSecCore/Vtf0/Bin/ResetVec.ia32.raw
diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/FspSecCore/Vtf0/Build.py b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/FspSecCore/Vtf0/Build.py
new file mode 100755
index 00000000..fb1a25a0
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/FspSecCore/Vtf0/Build.py
@@ -0,0 +1,47 @@
+## @file
+#  Automate the process of building the various reset vector types
+#
+#  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+import glob
+import os
+import subprocess
+import sys
+
+def RunCommand(commandLine):
+    #print ' '.join(commandLine)
+    return subprocess.call(commandLine)
+
+for filename in glob.glob(os.path.join('Bin', '*.raw')):
+    os.remove(filename)
+
+arch = 'ia32'
+debugType = None
+output = os.path.join('Bin', 'ResetVec')
+output += '.' + arch
+if debugType is not None:
+    output += '.' + debugType
+output += '.raw'
+commandLine = (
+    'nasm',
+    '-D', 'ARCH_%s' % arch.upper(),
+    '-D', 'DEBUG_%s' % str(debugType).upper(),
+    '-o', output,
+    'ResetVectorCode.asm',
+    )
+ret = RunCommand(commandLine)
+print '\tASM\t' + output
+if ret != 0: sys.exit(ret)
+
+commandLine = (
+    'python',
+    'Tools/FixupForRawSection.py',
+    output,
+    )
+print '\tFIXUP\t' + output
+ret = RunCommand(commandLine)
+if ret != 0: sys.exit(ret)
+
diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16 b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16
new file mode 100644
index 00000000..440d5ac1
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/FspSecCore/Vtf0/Ia16/ResetVec.asm16
@@ -0,0 +1,97 @@
+;; @file
+;  Reset Vector Data structure
+;  This structure is located at 0xFFFFFFC0
+;
+; Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;;
+
+BITS    16
+
+
+;
+; The layout of this file is fixed. The build tool makes assumption of the layout.
+;
+
+ORG     0x0
+;
+; Reserved
+;
+ReservedData:         DD 0eeeeeeeeh, 0eeeeeeeeh
+
+ ;  ORG     0x10
+ TIMES 0x10-($-$$) DB 0
+;
+; This is located at 0xFFFFFFD0h
+;
+    mov     di, "AP"
+    jmp     ApStartup
+
+ ;   ORG     0x20
+
+ TIMES 0x20-($-$$) DB 0
+
+; Pointer to the entry point of the PEI core
+; It is located at 0xFFFFFFE0, and is fixed up by some build tool
+; So if the value 8..1 appears in the final FD image, tool failure occurs.
+;
+PeiCoreEntryPoint:       DD      0x12345678
+
+;
+; This is the handler for all kinds of exceptions. Since it's for debugging
+; purpose only, nothing except a deadloop would be done here. Developers could
+; analyze the cause of the exception if a debugger had been attached.
+;
+InterruptHandler:
+    jmp     $
+    iret
+
+  ;  ORG     0x30
+ TIMES 0x30-($-$$) DB 0
+;
+; For IA32, the reset vector must be at 0xFFFFFFF0, i.e., 4G-16 byte
+; Execution starts here upon power-on/platform-reset.
+;
+ResetHandler:
+    nop
+    nop
+
+ApStartup:
+    ;
+    ; Jmp Rel16 instruction
+    ; Use machine code directly in case of the assembler optimization
+    ; SEC entry point relative address will be fixed up by some build tool.
+    ;
+    ; Typically, SEC entry point is the function _ModuleEntryPoint() defined in
+    ; SecEntry.asm
+    ;
+    DB      0x0e9
+    DW      -3
+
+  ; ORG     0x38
+
+ TIMES 0x38-($-$$) DB 0
+;
+; Ap reset vector segment address is at 0xFFFFFFF8
+; This will be fixed up by some build tool,
+; so if the value 1..8 appears in the final FD image,
+; tool failure occurs
+;
+ApSegAddress:    dd      0x12345678
+
+ ;   ORG     0x3c
+ TIMES 0x3c-($-$$) DB 0
+;
+; BFV Base is at 0xFFFFFFFC
+; This will be fixed up by some build tool,
+; so if the value 1..8 appears in the final FD image,
+; tool failure occurs.
+;
+BfvBase:     DD      0x12345678
+
+;
+; Nothing can go here, otherwise the layout of this file would change.
+;
+
+   ; END
diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/FspSecCore/Vtf0/ResetVectorCode.asm b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/FspSecCore/Vtf0/ResetVectorCode.asm
new file mode 100644
index 00000000..acd65bde
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/FspSecCore/Vtf0/ResetVectorCode.asm
@@ -0,0 +1,11 @@
+;------------------------------------------------------------------------------
+; @file
+; This file includes all other code files to assemble the reset vector code
+;
+; Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;------------------------------------------------------------------------------
+
+
+%include "Ia16/ResetVec.asm16"
diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/FspSecCore/Vtf0/Tools/FixupForRawSection.py b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/FspSecCore/Vtf0/Tools/FixupForRawSection.py
new file mode 100755
index 00000000..5ddddb6b
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/FspSecCore/Vtf0/Tools/FixupForRawSection.py
@@ -0,0 +1,104 @@
+## @file
+#  Apply fixup to VTF binary image for FFS Raw section
+#
+#  Copyright (c) 2014, Intel Corporation. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+import sys
+
+filename = sys.argv[1]
+
+if filename.lower().find('ia32') >= 0:
+    d = open(sys.argv[1], 'rb').read()
+    c = ((len(d) + 4 + 7) & ~7) - 4
+    if c > len(d):
+        c -= len(d)
+        f = open(sys.argv[1], 'wb')
+        f.write('\x90' * c)
+        f.write(d)
+        f.close()
+else:
+    from struct import pack
+
+    PAGE_PRESENT             =     0x01
+    PAGE_READ_WRITE          =     0x02
+    PAGE_USER_SUPERVISOR     =     0x04
+    PAGE_WRITE_THROUGH       =     0x08
+    PAGE_CACHE_DISABLE       =    0x010
+    PAGE_ACCESSED            =    0x020
+    PAGE_DIRTY               =    0x040
+    PAGE_PAT                 =    0x080
+    PAGE_GLOBAL              =   0x0100
+    PAGE_2M_MBO              =    0x080
+    PAGE_2M_PAT              =  0x01000
+
+    def NopAlign4k(s):
+        c = ((len(s) + 0xfff) & ~0xfff) - len(s)
+        return ('\x90' * c) + s
+
+    def PageDirectoryEntries4GbOf2MbPages(baseAddress):
+
+        s = ''
+        for i in range(0x800):
+            i = (
+                    baseAddress + long(i << 21) +
+                    PAGE_2M_MBO +
+                    PAGE_CACHE_DISABLE +
+                    PAGE_ACCESSED +
+                    PAGE_DIRTY +
+                    PAGE_READ_WRITE +
+                    PAGE_PRESENT
+                )
+            s += pack('Q', i)
+        return s
+
+    def PageDirectoryPointerTable4GbOf2MbPages(pdeBase):
+        s = ''
+        for i in range(0x200):
+            i = (
+                    pdeBase +
+                    (min(i, 3) << 12) +
+                    PAGE_CACHE_DISABLE +
+                    PAGE_ACCESSED +
+                    PAGE_READ_WRITE +
+                    PAGE_PRESENT
+                )
+            s += pack('Q', i)
+        return s
+
+    def PageMapLevel4Table4GbOf2MbPages(pdptBase):
+        s = ''
+        for i in range(0x200):
+            i = (
+                    pdptBase +
+                    (min(i, 0) << 12) +
+                    PAGE_CACHE_DISABLE +
+                    PAGE_ACCESSED +
+                    PAGE_READ_WRITE +
+                    PAGE_PRESENT
+                )
+            s += pack('Q', i)
+        return s
+
+    def First4GbPageEntries(topAddress):
+        PDE = PageDirectoryEntries4GbOf2MbPages(0L)
+        pml4tBase = topAddress - 0x1000
+        pdptBase = pml4tBase - 0x1000
+        pdeBase = pdptBase - len(PDE)
+        PDPT = PageDirectoryPointerTable4GbOf2MbPages(pdeBase)
+        PML4T = PageMapLevel4Table4GbOf2MbPages(pdptBase)
+        return PDE + PDPT + PML4T
+
+    def AlignAndAddPageTables():
+        d = open(sys.argv[1], 'rb').read()
+        code = NopAlign4k(d)
+        topAddress = 0x100000000 - len(code)
+        d = ('\x90' * 4) + First4GbPageEntries(topAddress) + code
+        f = open(sys.argv[1], 'wb')
+        f.write(d)
+        f.close()
+
+    AlignAndAddPageTables()
+