Adding upstream version 7.0.14-dfsg.upstream/7.0.14-dfsg

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

33 files changed, 3725 insertions, 0 deletions

diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/AArch64/Synchronization.S b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/AArch64/Synchronization.S
new file mode 100644
index 00000000..8c9f39f2
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/AArch64/Synchronization.S
@@ -0,0 +1,199 @@
+//  Implementation of synchronization functions for ARM architecture (AArch64)
+//
+//  Copyright (c) 2012-2015, ARM Limited. All rights reserved.
+//  Copyright (c) 2015, Linaro Limited. All rights reserved.
+//
+//  SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(InternalSyncCompareExchange16)
+GCC_ASM_EXPORT(InternalSyncCompareExchange32)
+GCC_ASM_EXPORT(InternalSyncCompareExchange64)
+GCC_ASM_EXPORT(InternalSyncIncrement)
+GCC_ASM_EXPORT(InternalSyncDecrement)
+
+/**
+  Performs an atomic compare exchange operation on a 16-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 16-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  @param  Value         A pointer to the 16-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  16-bit value used in compare operation.
+  @param  ExchangeValue 16-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+//UINT16
+//EFIAPI
+//InternalSyncCompareExchange16 (
+//  IN      volatile UINT16           *Value,
+//  IN      UINT16                    CompareValue,
+//  IN      UINT16                    ExchangeValue
+//  )
+ASM_PFX(InternalSyncCompareExchange16):
+  uxth    w1, w1
+  uxth    w2, w2
+  dmb     sy
+
+InternalSyncCompareExchange16Again:
+  ldxrh   w3, [x0]
+  cmp     w3, w1
+  bne     InternalSyncCompareExchange16Fail
+
+InternalSyncCompareExchange16Exchange:
+  stxrh   w4, w2, [x0]
+  cbnz    w4, InternalSyncCompareExchange16Again
+
+InternalSyncCompareExchange16Fail:
+  dmb     sy
+  mov     w0, w3
+  ret
+
+/**
+  Performs an atomic compare exchange operation on a 32-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 32-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  @param  Value         A pointer to the 32-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  32-bit value used in compare operation.
+  @param  ExchangeValue 32-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+//UINT32
+//EFIAPI
+//InternalSyncCompareExchange32 (
+//  IN      volatile UINT32           *Value,
+//  IN      UINT32                    CompareValue,
+//  IN      UINT32                    ExchangeValue
+//  )
+ASM_PFX(InternalSyncCompareExchange32):
+  dmb     sy
+
+InternalSyncCompareExchange32Again:
+  ldxr    w3, [x0]
+  cmp     w3, w1
+  bne     InternalSyncCompareExchange32Fail
+
+InternalSyncCompareExchange32Exchange:
+  stxr    w4, w2, [x0]
+  cbnz    w4, InternalSyncCompareExchange32Again
+
+InternalSyncCompareExchange32Fail:
+  dmb     sy
+  mov     w0, w3
+  ret
+
+/**
+  Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+  by Value.  If Value is equal to CompareValue, then Value is set to ExchangeValue and
+  CompareValue is returned.  If Value is not equal to CompareValue, then Value is returned.
+  The compare exchange operation must be performed using MP safe mechanisms.
+
+  @param  Value         A pointer to the 64-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  64-bit value used in compare operation.
+  @param  ExchangeValue 64-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+//UINT64
+//EFIAPI
+//InternalSyncCompareExchange64 (
+//  IN      volatile UINT64           *Value,
+//  IN      UINT64                    CompareValue,
+//  IN      UINT64                    ExchangeValue
+//  )
+ASM_PFX(InternalSyncCompareExchange64):
+  dmb     sy
+
+InternalSyncCompareExchange64Again:
+  ldxr    x3, [x0]
+  cmp     x3, x1
+  bne     InternalSyncCompareExchange64Fail
+
+InternalSyncCompareExchange64Exchange:
+  stxr    w4, x2, [x0]
+  cbnz    w4, InternalSyncCompareExchange64Again
+
+InternalSyncCompareExchange64Fail:
+  dmb     sy
+  mov     x0, x3
+  ret
+
+/**
+  Performs an atomic increment of an 32-bit unsigned integer.
+
+  Performs an atomic increment of the 32-bit unsigned integer specified by
+  Value and returns the incremented value. The increment operation must be
+  performed using MP safe mechanisms. The state of the return value is not
+  guaranteed to be MP safe.
+
+  @param  Value A pointer to the 32-bit value to increment.
+
+  @return The incremented value.
+
+**/
+//UINT32
+//EFIAPI
+//InternalSyncIncrement (
+//  IN      volatile UINT32           *Value
+//  )
+ASM_PFX(InternalSyncIncrement):
+  dmb     sy
+TryInternalSyncIncrement:
+  ldxr    w1, [x0]
+  add     w1, w1, #1
+  stxr    w2, w1, [x0]
+  cbnz    w2, TryInternalSyncIncrement
+  mov     w0, w1
+  dmb     sy
+  ret
+
+/**
+  Performs an atomic decrement of an 32-bit unsigned integer.
+
+  Performs an atomic decrement of the 32-bit unsigned integer specified by
+  Value and returns the decrement value. The decrement operation must be
+  performed using MP safe mechanisms. The state of the return value is not
+  guaranteed to be MP safe.
+
+  @param  Value A pointer to the 32-bit value to decrement.
+
+  @return The decrement value.
+
+**/
+//UINT32
+//EFIAPI
+//InternalSyncDecrement (
+//  IN      volatile UINT32           *Value
+//  )
+ASM_PFX(InternalSyncDecrement):
+  dmb     sy
+TryInternalSyncDecrement:
+  ldxr    w1, [x0]
+  sub     w1, w1, #1
+  stxr    w2, w1, [x0]
+  cbnz    w2, TryInternalSyncDecrement
+  mov     w0, w1
+  dmb     sy
+  ret
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/AArch64/Synchronization.asm b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/AArch64/Synchronization.asm
new file mode 100644
index 00000000..8209947f
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/AArch64/Synchronization.asm
@@ -0,0 +1,199 @@
+;  Implementation of synchronization functions for ARM architecture (AArch64)
+;
+;  Copyright (c) 2012-2015, ARM Limited. All rights reserved.
+;  Copyright (c) 2015, Linaro Limited. All rights reserved.
+;
+;  SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+;
+
+  EXPORT InternalSyncCompareExchange16
+  EXPORT InternalSyncCompareExchange32
+  EXPORT InternalSyncCompareExchange64
+  EXPORT InternalSyncIncrement
+  EXPORT InternalSyncDecrement
+  AREA BaseSynchronizationLib_LowLevel, CODE, READONLY
+
+;/**
+;  Performs an atomic compare exchange operation on a 16-bit unsigned integer.
+;
+;  Performs an atomic compare exchange operation on the 16-bit unsigned integer
+;  specified by Value.  If Value is equal to CompareValue, then Value is set to
+;  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+;  then Value is returned.  The compare exchange operation must be performed using
+;  MP safe mechanisms.
+;
+;  @param  Value         A pointer to the 16-bit value for the compare exchange
+;                        operation.
+;  @param  CompareValue  16-bit value used in compare operation.
+;  @param  ExchangeValue 16-bit value used in exchange operation.
+;
+;  @return The original *Value before exchange.
+;
+;**/
+;UINT16
+;EFIAPI
+;InternalSyncCompareExchange16 (
+;  IN      volatile UINT16           *Value,
+;  IN      UINT16                    CompareValue,
+;  IN      UINT16                    ExchangeValue
+;  )
+InternalSyncCompareExchange16
+  uxth    w1, w1
+  uxth    w2, w2
+  dmb     sy
+
+InternalSyncCompareExchange16Again
+  ldxrh   w3, [x0]
+  cmp     w3, w1
+  bne     InternalSyncCompareExchange16Fail
+
+InternalSyncCompareExchange16Exchange
+  stxrh   w4, w2, [x0]
+  cbnz    w4, InternalSyncCompareExchange16Again
+
+InternalSyncCompareExchange16Fail
+  dmb     sy
+  mov     w0, w3
+  ret
+
+;/**
+;  Performs an atomic compare exchange operation on a 32-bit unsigned integer.
+;
+;  Performs an atomic compare exchange operation on the 32-bit unsigned integer
+;  specified by Value.  If Value is equal to CompareValue, then Value is set to
+;  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+;  then Value is returned.  The compare exchange operation must be performed using
+;  MP safe mechanisms.
+;
+;  @param  Value         A pointer to the 32-bit value for the compare exchange
+;                        operation.
+;  @param  CompareValue  32-bit value used in compare operation.
+;  @param  ExchangeValue 32-bit value used in exchange operation.
+;
+;  @return The original *Value before exchange.
+;
+;**/
+;UINT32
+;EFIAPI
+;InternalSyncCompareExchange32 (
+;  IN      volatile UINT32           *Value,
+;  IN      UINT32                    CompareValue,
+;  IN      UINT32                    ExchangeValue
+;  )
+InternalSyncCompareExchange32
+  dmb     sy
+
+InternalSyncCompareExchange32Again
+  ldxr    w3, [x0]
+  cmp     w3, w1
+  bne     InternalSyncCompareExchange32Fail
+
+InternalSyncCompareExchange32Exchange
+  stxr    w4, w2, [x0]
+  cbnz    w4, InternalSyncCompareExchange32Again
+
+InternalSyncCompareExchange32Fail
+  dmb     sy
+  mov     w0, w3
+  ret
+
+;/**
+;  Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+;
+;  Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+;  by Value.  If Value is equal to CompareValue, then Value is set to ExchangeValue and
+;  CompareValue is returned.  If Value is not equal to CompareValue, then Value is returned.
+;  The compare exchange operation must be performed using MP safe mechanisms.
+;
+;  @param  Value         A pointer to the 64-bit value for the compare exchange
+;                        operation.
+;  @param  CompareValue  64-bit value used in compare operation.
+;  @param  ExchangeValue 64-bit value used in exchange operation.
+;
+;  @return The original *Value before exchange.
+;
+;**/
+;UINT64
+;EFIAPI
+;InternalSyncCompareExchange64 (
+;  IN      volatile UINT64           *Value,
+;  IN      UINT64                    CompareValue,
+;  IN      UINT64                    ExchangeValue
+;  )
+InternalSyncCompareExchange64
+  dmb     sy
+
+InternalSyncCompareExchange64Again
+  ldxr    x3, [x0]
+  cmp     x3, x1
+  bne     InternalSyncCompareExchange64Fail
+
+InternalSyncCompareExchange64Exchange
+  stxr    w4, x2, [x0]
+  cbnz    w4, InternalSyncCompareExchange64Again
+
+InternalSyncCompareExchange64Fail
+  dmb     sy
+  mov     x0, x3
+  ret
+
+;/**
+;  Performs an atomic increment of an 32-bit unsigned integer.
+;
+;  Performs an atomic increment of the 32-bit unsigned integer specified by
+;  Value and returns the incremented value. The increment operation must be
+;  performed using MP safe mechanisms. The state of the return value is not
+;  guaranteed to be MP safe.
+;
+;  @param  Value A pointer to the 32-bit value to increment.
+;
+;  @return The incremented value.
+;
+;**/
+;UINT32
+;EFIAPI
+;InternalSyncIncrement (
+;  IN      volatile UINT32           *Value
+;  )
+InternalSyncIncrement
+  dmb     sy
+TryInternalSyncIncrement
+  ldxr    w1, [x0]
+  add     w1, w1, #1
+  stxr    w2, w1, [x0]
+  cbnz    w2, TryInternalSyncIncrement
+  mov     w0, w1
+  dmb     sy
+  ret
+
+;/**
+;  Performs an atomic decrement of an 32-bit unsigned integer.
+;
+;  Performs an atomic decrement of the 32-bit unsigned integer specified by
+;  Value and returns the decrement value. The decrement operation must be
+;  performed using MP safe mechanisms. The state of the return value is not
+;  guaranteed to be MP safe.
+;
+;  @param  Value A pointer to the 32-bit value to decrement.
+;
+;  @return The decrement value.
+;
+;**/
+;UINT32
+;EFIAPI
+;InternalSyncDecrement (
+;  IN      volatile UINT32           *Value
+;  )
+InternalSyncDecrement
+  dmb     sy
+TryInternalSyncDecrement
+  ldxr    w1, [x0]
+  sub     w1, w1, #1
+  stxr    w2, w1, [x0]
+  cbnz    w2, TryInternalSyncDecrement
+  mov     w0, w1
+  dmb     sy
+  ret
+
+  END
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Arm/Synchronization.S b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Arm/Synchronization.S
new file mode 100644
index 00000000..64b24831
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Arm/Synchronization.S
@@ -0,0 +1,207 @@
+//  Implementation of synchronization functions for ARM architecture
+//
+//  Copyright (c) 2012-2015, ARM Limited. All rights reserved.
+//  Copyright (c) 2015, Linaro Limited. All rights reserved.
+//
+//  SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(InternalSyncCompareExchange16)
+GCC_ASM_EXPORT(InternalSyncCompareExchange32)
+GCC_ASM_EXPORT(InternalSyncCompareExchange64)
+GCC_ASM_EXPORT(InternalSyncIncrement)
+GCC_ASM_EXPORT(InternalSyncDecrement)
+
+/**
+  Performs an atomic compare exchange operation on a 16-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 16-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  @param  Value         A pointer to the 16-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  16-bit value used in compare operation.
+  @param  ExchangeValue 16-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+//UINT16
+//EFIAPI
+//InternalSyncCompareExchange16 (
+//  IN      volatile UINT16           *Value,
+//  IN      UINT16                    CompareValue,
+//  IN      UINT16                    ExchangeValue
+//  )
+ASM_PFX(InternalSyncCompareExchange16):
+  dmb
+
+InternalSyncCompareExchange16Again:
+  ldrexh  r3, [r0]
+  cmp     r3, r1
+  bne     InternalSyncCompareExchange16Fail
+
+InternalSyncCompareExchange16Exchange:
+  strexh  ip, r2, [r0]
+  cmp     ip, #0
+  bne     InternalSyncCompareExchange16Again
+
+InternalSyncCompareExchange16Fail:
+  dmb
+  mov     r0, r3
+  bx      lr
+
+/**
+  Performs an atomic compare exchange operation on a 32-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 32-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  @param  Value         A pointer to the 32-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  32-bit value used in compare operation.
+  @param  ExchangeValue 32-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+//UINT32
+//EFIAPI
+//InternalSyncCompareExchange32 (
+//  IN      volatile UINT32           *Value,
+//  IN      UINT32                    CompareValue,
+//  IN      UINT32                    ExchangeValue
+//  )
+ASM_PFX(InternalSyncCompareExchange32):
+  dmb
+
+InternalSyncCompareExchange32Again:
+  ldrex   r3, [r0]
+  cmp     r3, r1
+  bne     InternalSyncCompareExchange32Fail
+
+InternalSyncCompareExchange32Exchange:
+  strex   ip, r2, [r0]
+  cmp     ip, #0
+  bne     InternalSyncCompareExchange32Again
+
+InternalSyncCompareExchange32Fail:
+  dmb
+  mov     r0, r3
+  bx      lr
+
+/**
+  Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+  by Value.  If Value is equal to CompareValue, then Value is set to ExchangeValue and
+  CompareValue is returned.  If Value is not equal to CompareValue, then Value is returned.
+  The compare exchange operation must be performed using MP safe mechanisms.
+
+  @param  Value         A pointer to the 64-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  64-bit value used in compare operation.
+  @param  ExchangeValue 64-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+//UINT64
+//EFIAPI
+//InternalSyncCompareExchange64 (
+//  IN      volatile UINT64           *Value,         // r0
+//  IN      UINT64                    CompareValue,   // r2-r3
+//  IN      UINT64                    ExchangeValue   // stack
+//  )
+ASM_PFX(InternalSyncCompareExchange64):
+  push    { r4-r7 }
+  ldrd    r4, r5, [sp, #16]
+  dmb
+
+InternalSyncCompareExchange64Again:
+  ldrexd  r6, r7, [r0]
+  cmp     r6, r2
+  cmpeq   r7, r3
+  bne     InternalSyncCompareExchange64Fail
+
+InternalSyncCompareExchange64Exchange:
+  strexd  ip, r4, r5, [r0]
+  cmp     ip, #0
+  bne     InternalSyncCompareExchange64Again
+
+InternalSyncCompareExchange64Fail:
+  dmb
+  mov     r0, r6
+  mov     r1, r7
+  pop     { r4-r7 }
+  bx      lr
+
+/**
+  Performs an atomic increment of an 32-bit unsigned integer.
+
+  Performs an atomic increment of the 32-bit unsigned integer specified by
+  Value and returns the incremented value. The increment operation must be
+  performed using MP safe mechanisms. The state of the return value is not
+  guaranteed to be MP safe.
+
+  @param  Value A pointer to the 32-bit value to increment.
+
+  @return The incremented value.
+
+**/
+//UINT32
+//EFIAPI
+//InternalSyncIncrement (
+//  IN      volatile UINT32           *Value
+//  )
+ASM_PFX(InternalSyncIncrement):
+  dmb
+TryInternalSyncIncrement:
+  ldrex   r1, [r0]
+  add     r1, r1, #1
+  strex   r2, r1, [r0]
+  cmp     r2, #0
+  bne     TryInternalSyncIncrement
+  dmb
+  mov     r0, r1
+  bx      lr
+
+/**
+  Performs an atomic decrement of an 32-bit unsigned integer.
+
+  Performs an atomic decrement of the 32-bit unsigned integer specified by
+  Value and returns the decrement value. The decrement operation must be
+  performed using MP safe mechanisms. The state of the return value is not
+  guaranteed to be MP safe.
+
+  @param  Value A pointer to the 32-bit value to decrement.
+
+  @return The decrement value.
+
+**/
+//UINT32
+//EFIAPI
+//InternalSyncDecrement (
+//  IN      volatile UINT32           *Value
+//  )
+ASM_PFX(InternalSyncDecrement):
+  dmb
+TryInternalSyncDecrement:
+  ldrex   r1, [r0]
+  sub     r1, r1, #1
+  strex   r2, r1, [r0]
+  cmp     r2, #0
+  bne     TryInternalSyncDecrement
+  dmb
+  mov     r0, r1
+  bx      lr
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Arm/Synchronization.asm b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Arm/Synchronization.asm
new file mode 100644
index 00000000..62e53a0d
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Arm/Synchronization.asm
@@ -0,0 +1,208 @@
+//  Implementation of synchronization functions for ARM architecture
+//
+//  Copyright (c) 2012-2015, ARM Limited. All rights reserved.
+//  Copyright (c) 2015, Linaro Limited. All rights reserved.
+//
+//  SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//
+
+    EXPORT  InternalSyncCompareExchange16
+    EXPORT  InternalSyncCompareExchange32
+    EXPORT  InternalSyncCompareExchange64
+    EXPORT  InternalSyncIncrement
+    EXPORT  InternalSyncDecrement
+
+    AREA   ArmSynchronization, CODE, READONLY
+
+/**
+  Performs an atomic compare exchange operation on a 16-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 16-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  @param  Value         A pointer to the 16-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  16-bit value used in compare operation.
+  @param  ExchangeValue 16-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+//UINT16
+//EFIAPI
+//InternalSyncCompareExchange16 (
+//  IN      volatile UINT16           *Value,
+//  IN      UINT16                    CompareValue,
+//  IN      UINT16                    ExchangeValue
+//  )
+InternalSyncCompareExchange16
+  dmb
+
+InternalSyncCompareExchange16Again
+  ldrexh  r3, [r0]
+  cmp     r3, r1
+  bne     InternalSyncCompareExchange16Fail
+
+InternalSyncCompareExchange16Exchange
+  strexh  ip, r2, [r0]
+  cmp     ip, #0
+  bne     InternalSyncCompareExchange16Again
+
+InternalSyncCompareExchange16Fail
+  dmb
+  mov     r0, r3
+  bx      lr
+
+/**
+  Performs an atomic compare exchange operation on a 32-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 32-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  @param  Value         A pointer to the 32-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  32-bit value used in compare operation.
+  @param  ExchangeValue 32-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+//UINT32
+//EFIAPI
+//InternalSyncCompareExchange32 (
+//  IN      volatile UINT32           *Value,
+//  IN      UINT32                    CompareValue,
+//  IN      UINT32                    ExchangeValue
+//  )
+InternalSyncCompareExchange32
+  dmb
+
+InternalSyncCompareExchange32Again
+  ldrex   r3, [r0]
+  cmp     r3, r1
+  bne     InternalSyncCompareExchange32Fail
+
+InternalSyncCompareExchange32Exchange
+  strex   ip, r2, [r0]
+  cmp     ip, #0
+  bne     InternalSyncCompareExchange32Again
+
+InternalSyncCompareExchange32Fail
+  dmb
+  mov     r0, r3
+  bx      lr
+
+/**
+  Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+  by Value.  If Value is equal to CompareValue, then Value is set to ExchangeValue and
+  CompareValue is returned.  If Value is not equal to CompareValue, then Value is returned.
+  The compare exchange operation must be performed using MP safe mechanisms.
+
+  @param  Value         A pointer to the 64-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  64-bit value used in compare operation.
+  @param  ExchangeValue 64-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+//UINT64
+//EFIAPI
+//InternalSyncCompareExchange64 (
+//  IN      volatile UINT64           *Value,         // r0
+//  IN      UINT64                    CompareValue,   // r2-r3
+//  IN      UINT64                    ExchangeValue   // stack
+//  )
+InternalSyncCompareExchange64
+  push    { r4-r7 }
+  ldrd    r4, r5, [sp, #16]
+  dmb
+
+InternalSyncCompareExchange64Again
+  ldrexd  r6, r7, [r0]
+  cmp     r6, r2
+  cmpeq   r7, r3
+  bne     InternalSyncCompareExchange64Fail
+
+InternalSyncCompareExchange64Exchange
+  strexd  ip, r4, r5, [r0]
+  cmp     ip, #0
+  bne     InternalSyncCompareExchange64Again
+
+InternalSyncCompareExchange64Fail
+  dmb
+  mov     r0, r6
+  mov     r1, r7
+  pop     { r4-r7 }
+  bx      lr
+
+/**
+  Performs an atomic increment of an 32-bit unsigned integer.
+
+  Performs an atomic increment of the 32-bit unsigned integer specified by
+  Value and returns the incremented value. The increment operation must be
+  performed using MP safe mechanisms. The state of the return value is not
+  guaranteed to be MP safe.
+
+  @param  Value A pointer to the 32-bit value to increment.
+
+  @return The incremented value.
+
+**/
+//UINT32
+//EFIAPI
+//InternalSyncIncrement (
+//  IN      volatile UINT32           *Value
+//  )
+InternalSyncIncrement
+  dmb
+TryInternalSyncIncrement
+  ldrex   r1, [r0]
+  add     r1, r1, #1
+  strex   r2, r1, [r0]
+  cmp     r2, #0
+  bne     TryInternalSyncIncrement
+  dmb
+  mov     r0, r1
+  bx      lr
+
+/**
+  Performs an atomic decrement of an 32-bit unsigned integer.
+
+  Performs an atomic decrement of the 32-bit unsigned integer specified by
+  Value and returns the decrement value. The decrement operation must be
+  performed using MP safe mechanisms. The state of the return value is not
+  guaranteed to be MP safe.
+
+  @param  Value A pointer to the 32-bit value to decrement.
+
+  @return The decrement value.
+
+**/
+//UINT32
+//EFIAPI
+//InternalSyncDecrement (
+//  IN      volatile UINT32           *Value
+//  )
+InternalSyncDecrement
+  dmb
+TryInternalSyncDecrement
+  ldrex   r1, [r0]
+  sub     r1, r1, #1
+  strex   r2, r1, [r0]
+  cmp     r2, #0
+  bne     TryInternalSyncDecrement
+  dmb
+  mov     r0, r1
+  bx      lr
+
+  END
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
new file mode 100644
index 00000000..327bef03
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
@@ -0,0 +1,97 @@
+## @file
+#  Base Synchronization Library implementation.
+#
+#  Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
+#  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+#  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+#
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = BaseSynchronizationLib
+  MODULE_UNI_FILE                = BaseSynchronizationLib.uni
+  FILE_GUID                      = FC9990DF-C5FF-44cf-8799-CBB45B577F87
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = SynchronizationLib
+
+#
+#  VALID_ARCHITECTURES           = IA32 X64 EBC ARM AARCH64
+#
+[Sources]
+  BaseSynchronizationLibInternals.h
+
+[Sources.IA32]
+  Ia32/InternalGetSpinLockProperties.c | MSFT
+  Ia32/InterlockedCompareExchange64.c | MSFT
+  Ia32/InterlockedCompareExchange32.c | MSFT
+  Ia32/InterlockedCompareExchange16.c | MSFT
+  InterlockedIncrementMsc.c | MSFT
+  InterlockedDecrementMsc.c | MSFT
+  SynchronizationMsc.c | MSFT
+
+  Ia32/InterlockedCompareExchange64.nasm| INTEL
+  Ia32/InterlockedCompareExchange32.nasm| INTEL
+  Ia32/InterlockedCompareExchange16.nasm| INTEL
+  Ia32/InterlockedDecrement.nasm| INTEL
+  Ia32/InterlockedIncrement.nasm| INTEL
+  Synchronization.c | INTEL
+
+  Ia32/InternalGetSpinLockProperties.c | GCC
+  Ia32/GccInline.c | GCC
+  SynchronizationGcc.c  | GCC
+
+[Sources.X64]
+  Ia32/InternalGetSpinLockProperties.c | MSFT
+  X64/InterlockedCompareExchange64.c | MSFT
+  X64/InterlockedCompareExchange32.c | MSFT
+  X64/InterlockedCompareExchange16.c | MSFT
+  InterlockedIncrementMsc.c | MSFT
+  InterlockedDecrementMsc.c | MSFT
+  SynchronizationMsc.c | MSFT
+
+  X64/InterlockedCompareExchange64.nasm| INTEL
+  X64/InterlockedCompareExchange32.nasm| INTEL
+  X64/InterlockedCompareExchange16.nasm| INTEL
+  X64/InterlockedDecrement.nasm | INTEL
+  X64/InterlockedIncrement.nasm | INTEL
+  Synchronization.c | INTEL
+
+  Ia32/InternalGetSpinLockProperties.c | GCC
+  X64/GccInline.c | GCC
+  SynchronizationGcc.c  | GCC
+
+[Sources.EBC]
+  Synchronization.c
+  Ebc/Synchronization.c
+
+[Sources.ARM]
+  Synchronization.c
+  Arm/Synchronization.asm       | RVCT
+  Arm/Synchronization.S         | GCC
+
+[Sources.AARCH64]
+  Synchronization.c
+  AArch64/Synchronization.S     | GCC
+  AArch64/Synchronization.asm   | MSFT
+
+[Sources.RISCV64]
+  Synchronization.c
+  RiscV64/Synchronization.S
+
+[Packages]
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  PcdLib
+  TimerLib
+  DebugLib
+  BaseMemoryLib
+
+[Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout  ## SOMETIMES_CONSUMES
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.uni b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.uni
new file mode 100644
index 00000000..cae971f3
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.uni
@@ -0,0 +1,17 @@
+// /** @file

+// Base Synchronization Library implementation.

+//

+// Base Synchronization Library implementation.

+//

+// Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>

+// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>

+//

+// SPDX-License-Identifier: BSD-2-Clause-Patent

+//

+// **/

+

+

+#string STR_MODULE_ABSTRACT             #language en-US "Base Synchronization Library implementation"

+

+#string STR_MODULE_DESCRIPTION          #language en-US "Base Synchronization Library implementation."

+

diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLibInternals.h b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLibInternals.h
new file mode 100644
index 00000000..c24701e6
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLibInternals.h
@@ -0,0 +1,145 @@
+/** @file
+  Declaration of internal functions in BaseSynchronizationLib.
+
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef __BASE_SYNCHRONIZATION_LIB_INTERNALS__
+#define __BASE_SYNCHRONIZATION_LIB_INTERNALS__
+
+#include <Base.h>
+#include <Library/SynchronizationLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PcdLib.h>
+
+/**
+  Performs an atomic increment of an 32-bit unsigned integer.
+
+  Performs an atomic increment of the 32-bit unsigned integer specified by
+  Value and returns the incremented value. The increment operation must be
+  performed using MP safe mechanisms.
+
+  @param  Value A pointer to the 32-bit value to increment.
+
+  @return The incremented value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncIncrement (
+  IN      volatile UINT32           *Value
+  );
+
+
+/**
+  Performs an atomic decrement of an 32-bit unsigned integer.
+
+  Performs an atomic decrement of the 32-bit unsigned integer specified by
+  Value and returns the decrement value. The decrement operation must be
+  performed using MP safe mechanisms.
+
+  @param  Value A pointer to the 32-bit value to decrement.
+
+  @return The decrement value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncDecrement (
+  IN      volatile UINT32           *Value
+  );
+
+
+/**
+  Performs an atomic compare exchange operation on a 16-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 16-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  @param  Value         A pointer to the 16-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  A 16-bit value used in compare operation.
+  @param  ExchangeValue A 16-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT16
+EFIAPI
+InternalSyncCompareExchange16 (
+  IN      volatile UINT16           *Value,
+  IN      UINT16                    CompareValue,
+  IN      UINT16                    ExchangeValue
+  );
+
+
+/**
+  Performs an atomic compare exchange operation on a 32-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 32-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  @param  Value         A pointer to the 32-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  A 32-bit value used in compare operation.
+  @param  ExchangeValue A 32-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT32
+EFIAPI
+InternalSyncCompareExchange32 (
+  IN      volatile UINT32           *Value,
+  IN      UINT32                    CompareValue,
+  IN      UINT32                    ExchangeValue
+  );
+
+
+/**
+  Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+  by Value.  If Value is equal to CompareValue, then Value is set to ExchangeValue and
+  CompareValue is returned.  If Value is not equal to CompareValue, then Value is returned.
+  The compare exchange operation must be performed using MP safe mechanisms.
+
+  @param  Value         A pointer to the 64-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  A 64-bit value used in compare operation.
+  @param  ExchangeValue A 64-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT64
+EFIAPI
+InternalSyncCompareExchange64 (
+  IN      volatile UINT64           *Value,
+  IN      UINT64                    CompareValue,
+  IN      UINT64                    ExchangeValue
+  );
+
+/**
+  Internal function to retrieve the architecture specific spin lock alignment
+  requirements for optimal spin lock performance.
+
+  @return The architecture specific spin lock alignment.
+
+**/
+UINTN
+InternalGetSpinLockProperties (
+  VOID
+  );
+
+#endif
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ebc/Synchronization.c b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ebc/Synchronization.c
new file mode 100644
index 00000000..0c8e4f50
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ebc/Synchronization.c
@@ -0,0 +1,141 @@
+/** @file
+  Implementation of synchronization functions on EBC.
+
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+  Performs an atomic compare exchange operation on a 16-bit
+  unsigned integer.
+
+  Performs an atomic compare exchange operation on the 16-bit
+  unsigned integer specified by Value.  If Value is equal to
+  CompareValue, then Value is set to ExchangeValue and
+  CompareValue is returned.  If Value is not equal to
+  CompareValue, then Value is returned. The compare exchange
+  operation must be performed using MP safe mechanisms.
+
+  @param  Value         A pointer to the 16-bit value for the
+                        compare exchange operation.
+  @param  CompareValue  16-bit value used in compare operation.
+  @param  ExchangeValue 16-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT16
+EFIAPI
+InternalSyncCompareExchange16 (
+  IN      volatile UINT16           *Value,
+  IN      UINT16                    CompareValue,
+  IN      UINT16                    ExchangeValue
+  )
+{
+  return *Value != CompareValue ? *Value :
+           ((*Value = ExchangeValue), CompareValue);
+}
+
+/**
+  Performs an atomic compare exchange operation on a 32-bit
+  unsigned integer.
+
+  Performs an atomic compare exchange operation on the 32-bit
+  unsigned integer specified by Value.  If Value is equal to
+  CompareValue, then Value is set to ExchangeValue and
+  CompareValue is returned.  If Value is not equal to
+  CompareValue, then Value is returned. The compare exchange
+  operation must be performed using MP safe mechanisms.
+
+  @param  Value         A pointer to the 32-bit value for the
+                        compare exchange operation.
+  @param  CompareValue  32-bit value used in compare operation.
+  @param  ExchangeValue 32-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT32
+EFIAPI
+InternalSyncCompareExchange32 (
+  IN      volatile UINT32           *Value,
+  IN      UINT32                    CompareValue,
+  IN      UINT32                    ExchangeValue
+  )
+{
+  return *Value != CompareValue ? *Value :
+           ((*Value = ExchangeValue), CompareValue);
+}
+
+/**
+  Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+  by Value.  If Value is equal to CompareValue, then Value is set to ExchangeValue and
+  CompareValue is returned.  If Value is not equal to CompareValue, then Value is returned.
+  The compare exchange operation must be performed using MP safe mechanisms.
+
+  @param  Value         A pointer to the 64-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  64-bit value used in compare operation.
+  @param  ExchangeValue 64-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT64
+EFIAPI
+InternalSyncCompareExchange64 (
+  IN      volatile UINT64           *Value,
+  IN      UINT64                    CompareValue,
+  IN      UINT64                    ExchangeValue
+  )
+{
+  return *Value != CompareValue ? *Value :
+           ((*Value = ExchangeValue), CompareValue);
+}
+
+/**
+  Performs an atomic increment of an 32-bit unsigned integer.
+
+  Performs an atomic increment of the 32-bit unsigned integer specified by
+  Value and returns the incremented value. The increment operation must be
+  performed using MP safe mechanisms. The state of the return value is not
+  guaranteed to be MP safe.
+
+  @param  Value A pointer to the 32-bit value to increment.
+
+  @return The incremented value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncIncrement (
+  IN      volatile UINT32           *Value
+  )
+{
+  return ++*Value;
+}
+
+/**
+  Performs an atomic decrement of an 32-bit unsigned integer.
+
+  Performs an atomic decrement of the 32-bit unsigned integer specified by
+  Value and returns the decrement value. The decrement operation must be
+  performed using MP safe mechanisms. The state of the return value is not
+  guaranteed to be MP safe.
+
+  @param  Value A pointer to the 32-bit value to decrement.
+
+  @return The decrement value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncDecrement (
+  IN      volatile UINT32           *Value
+  )
+{
+  return --*Value;
+}
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/GccInline.c b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/GccInline.c
new file mode 100644
index 00000000..7c9f1673
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/GccInline.c
@@ -0,0 +1,201 @@
+/** @file
+  GCC inline implementation of BaseSynchronizationLib processor specific functions.
+
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+/**
+  Performs an atomic increment of an 32-bit unsigned integer.
+
+  Performs an atomic increment of the 32-bit unsigned integer specified by
+  Value and returns the incremented value. The increment operation must be
+  performed using MP safe mechanisms.
+
+  @param  Value A pointer to the 32-bit value to increment.
+
+  @return The incremented value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncIncrement (
+  IN      volatile UINT32    *Value
+  )
+{
+  UINT32  Result;
+
+  __asm__ __volatile__ (
+    "movl    $1, %%eax  \n\t"
+    "lock               \n\t"
+    "xadd    %%eax, %1  \n\t"
+    "inc     %%eax      \n\t"
+    : "=&a" (Result),         // %0
+      "+m" (*Value)           // %1
+    :                         // no inputs that aren't also outputs
+    : "memory",
+      "cc"
+    );
+
+  return Result;
+}
+
+
+/**
+  Performs an atomic decrement of an 32-bit unsigned integer.
+
+  Performs an atomic decrement of the 32-bit unsigned integer specified by
+  Value and returns the decremented value. The decrement operation must be
+  performed using MP safe mechanisms.
+
+  @param  Value A pointer to the 32-bit value to decrement.
+
+  @return The decremented value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncDecrement (
+  IN      volatile UINT32       *Value
+  )
+{
+   UINT32  Result;
+
+  __asm__ __volatile__ (
+    "movl    $-1, %%eax  \n\t"
+    "lock                \n\t"
+    "xadd    %%eax, %1   \n\t"
+    "dec     %%eax       \n\t"
+    : "=&a" (Result),          // %0
+      "+m" (*Value)            // %1
+    :                          // no inputs that aren't also outputs
+    : "memory",
+      "cc"
+    );
+
+  return Result;
+}
+
+
+/**
+  Performs an atomic compare exchange operation on a 16-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 16-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+
+  @param  Value         A pointer to the 16-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  16-bit value used in compare operation.
+  @param  ExchangeValue 16-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT16
+EFIAPI
+InternalSyncCompareExchange16 (
+  IN OUT volatile  UINT16           *Value,
+  IN      UINT16                    CompareValue,
+  IN      UINT16                    ExchangeValue
+  )
+{
+  __asm__ __volatile__ (
+    "lock                 \n\t"
+    "cmpxchgw    %2, %1   \n\t"
+    : "+a" (CompareValue),      // %0
+      "+m" (*Value)             // %1
+    : "q"  (ExchangeValue)      // %2
+    : "memory",
+      "cc"
+    );
+
+  return CompareValue;
+}
+
+
+/**
+  Performs an atomic compare exchange operation on a 32-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 32-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+
+  @param  Value         A pointer to the 32-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  32-bit value used in compare operation.
+  @param  ExchangeValue 32-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT32
+EFIAPI
+InternalSyncCompareExchange32 (
+  IN OUT volatile  UINT32           *Value,
+  IN      UINT32                    CompareValue,
+  IN      UINT32                    ExchangeValue
+  )
+{
+  __asm__ __volatile__ (
+    "lock                 \n\t"
+    "cmpxchgl    %2, %1   \n\t"
+    : "+a" (CompareValue),      // %0
+      "+m" (*Value)             // %1
+    : "q"  (ExchangeValue)      // %2
+    : "memory",
+      "cc"
+    );
+
+  return CompareValue;
+}
+
+
+/**
+  Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+  by Value.  If Value is equal to CompareValue, then Value is set to ExchangeValue and
+  CompareValue is returned.  If Value is not equal to CompareValue, then Value is returned.
+  The compare exchange operation must be performed using MP safe mechanisms.
+
+
+  @param  Value         A pointer to the 64-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  64-bit value used in compare operation.
+  @param  ExchangeValue 64-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT64
+EFIAPI
+InternalSyncCompareExchange64 (
+  IN OUT  volatile UINT64           *Value,
+  IN      UINT64                    CompareValue,
+  IN      UINT64                    ExchangeValue
+  )
+{
+  __asm__ __volatile__ (
+    "lock                   \n\t"
+    "cmpxchg8b   (%1)       \n\t"
+    : "+A"  (CompareValue)                    // %0
+    : "S"   (Value),                          // %1
+      "b"   ((UINT32) ExchangeValue),         // %2
+      "c"   ((UINT32) (ExchangeValue >> 32))  // %3
+    : "memory",
+      "cc"
+    );
+
+  return CompareValue;
+}
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange16.c b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange16.c
new file mode 100644
index 00000000..6680a551
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange16.c
@@ -0,0 +1,45 @@
+/** @file
+  InterlockedCompareExchange16 function
+
+  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+  Performs an atomic compare exchange operation on a 16-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 16-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  @param  Value         A pointer to the 16-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  16-bit value used in compare operation.
+  @param  ExchangeValue 16-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT16
+EFIAPI
+InternalSyncCompareExchange16 (
+  IN      volatile UINT16           *Value,
+  IN      UINT16                    CompareValue,
+  IN      UINT16                    ExchangeValue
+  )
+{
+  _asm {
+    mov     ecx, Value
+    mov     ax, CompareValue
+    mov     dx, ExchangeValue
+    lock    cmpxchg [ecx], dx
+  }
+}
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange16.nasm b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange16.nasm
new file mode 100644
index 00000000..487b6cba
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange16.nasm
@@ -0,0 +1,37 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+;   InterlockedCompareExchange16.Asm
+;
+; Abstract:
+;
+;   InterlockedCompareExchange16 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; InternalSyncCompareExchange16 (
+;   IN      volatile UINT16           *Value,
+;   IN      UINT16                    CompareValue,
+;   IN      UINT16                    ExchangeValue
+;   );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalSyncCompareExchange16)
+ASM_PFX(InternalSyncCompareExchange16):
+    mov     ecx, [esp + 4]
+    mov     ax, [esp + 8]
+    mov     dx, [esp + 12]
+    lock    cmpxchg [ecx], dx
+    ret
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange32.c b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange32.c
new file mode 100644
index 00000000..21b02095
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange32.c
@@ -0,0 +1,44 @@
+/** @file
+  InterlockedCompareExchange32 function
+
+  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+  Performs an atomic compare exchange operation on a 32-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 32-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  @param  Value         A pointer to the 32-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  32-bit value used in compare operation.
+  @param  ExchangeValue 32-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT32
+EFIAPI
+InternalSyncCompareExchange32 (
+  IN      volatile UINT32           *Value,
+  IN      UINT32                    CompareValue,
+  IN      UINT32                    ExchangeValue
+  )
+{
+  _asm {
+    mov     ecx, Value
+    mov     eax, CompareValue
+    mov     edx, ExchangeValue
+    lock    cmpxchg [ecx], edx
+  }
+}
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange32.nasm b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange32.nasm
new file mode 100644
index 00000000..945bdce6
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange32.nasm
@@ -0,0 +1,36 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+;   InterlockedCompareExchange32.Asm
+;
+; Abstract:
+;
+;   InterlockedCompareExchange32 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT32
+; EFIAPI
+; InternalSyncCompareExchange32 (
+;   IN      volatile UINT32           *Value,
+;   IN      UINT32                    CompareValue,
+;   IN      UINT32                    ExchangeValue
+;   );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalSyncCompareExchange32)
+ASM_PFX(InternalSyncCompareExchange32):
+    mov     ecx, [esp + 4]
+    mov     eax, [esp + 8]
+    mov     edx, [esp + 12]
+    lock    cmpxchg [ecx], edx
+    ret
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange64.c b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange64.c
new file mode 100644
index 00000000..9c0572ce
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange64.c
@@ -0,0 +1,44 @@
+/** @file
+  InterlockedCompareExchange64 function
+
+  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+
+/**
+  Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+  by Value.  If Value is equal to CompareValue, then Value is set to ExchangeValue and
+  CompareValue is returned.  If Value is not equal to CompareValue, then Value is returned.
+  The compare exchange operation must be performed using MP safe mechanisms.
+
+  @param  Value         A pointer to the 64-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  A 64-bit value used in a compare operation.
+  @param  ExchangeValue A 64-bit value used in an exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT64
+EFIAPI
+InternalSyncCompareExchange64 (
+  IN      volatile UINT64           *Value,
+  IN      UINT64                    CompareValue,
+  IN      UINT64                    ExchangeValue
+  )
+{
+  _asm {
+    mov     esi, Value
+    mov     eax, dword ptr [CompareValue + 0]
+    mov     edx, dword ptr [CompareValue + 4]
+    mov     ebx, dword ptr [ExchangeValue + 0]
+    mov     ecx, dword ptr [ExchangeValue + 4]
+    lock    cmpxchg8b   qword ptr [esi]
+  }
+}
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange64.nasm b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange64.nasm
new file mode 100644
index 00000000..44e8b5e2
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedCompareExchange64.nasm
@@ -0,0 +1,42 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+;   InterlockedCompareExchange64.Asm
+;
+; Abstract:
+;
+;   InterlockedCompareExchange64 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; InternalSyncCompareExchange64 (
+;   IN      volatile UINT64           *Value,
+;   IN      UINT64                    CompareValue,
+;   IN      UINT64                    ExchangeValue
+;   );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalSyncCompareExchange64)
+ASM_PFX(InternalSyncCompareExchange64):
+    push    esi
+    push    ebx
+    mov     esi, [esp + 12]
+    mov     eax, [esp + 16]
+    mov     edx, [esp + 20]
+    mov     ebx, [esp + 24]
+    mov     ecx, [esp + 28]
+    lock    cmpxchg8b [esi]
+    pop     ebx
+    pop     esi
+    ret
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedDecrement.nasm b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedDecrement.nasm
new file mode 100644
index 00000000..21d81e5a
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedDecrement.nasm
@@ -0,0 +1,33 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+;   InterlockedDecrement.Asm
+;
+; Abstract:
+;
+;   InterlockedDecrement function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT32
+; EFIAPI
+; InternalSyncDecrement (
+;   IN      volatile UINT32           *Value
+;   );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalSyncDecrement)
+ASM_PFX(InternalSyncDecrement):
+    mov       ecx, [esp + 4]
+    mov       eax, 0FFFFFFFFh
+    lock xadd dword [ecx], eax
+    dec       eax
+    ret
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedIncrement.nasm b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedIncrement.nasm
new file mode 100644
index 00000000..d4419153
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InterlockedIncrement.nasm
@@ -0,0 +1,34 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+;   InterlockedIncrement.Asm
+;
+; Abstract:
+;
+;   InterlockedIncrement function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT32
+; EFIAPI
+; InternalSyncIncrement (
+;   IN      volatile UINT32           *Value
+;   );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalSyncIncrement)
+ASM_PFX(InternalSyncIncrement):
+    mov       ecx, [esp + 4]
+    mov       eax, 1
+    lock xadd dword [ecx], eax
+    inc       eax
+    ret
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InternalGetSpinLockProperties.c b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InternalGetSpinLockProperties.c
new file mode 100644
index 00000000..7b0de3dc
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Ia32/InternalGetSpinLockProperties.c
@@ -0,0 +1,58 @@
+/** @file
+  Internal function to get spin lock alignment.
+
+  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseSynchronizationLibInternals.h"
+
+/**
+  Internal function to retrieve the architecture specific spin lock alignment
+  requirements for optimal spin lock performance.
+
+  @return The architecture specific spin lock alignment.
+
+**/
+UINTN
+InternalGetSpinLockProperties (
+  VOID
+  )
+{
+  UINT32  RegEax;
+  UINT32  RegEbx;
+  UINTN   FamilyId;
+  UINTN   ModelId;
+  UINTN   CacheLineSize;
+
+  //
+  // Retrieve CPUID Version Information
+  //
+  AsmCpuid (0x01, &RegEax, &RegEbx, NULL, NULL);
+  //
+  // EBX: Bits 15 - 08: CLFLUSH line size (Value * 8 = cache line size)
+  //
+  CacheLineSize = ((RegEbx >> 8) & 0xff) * 8;
+  //
+  // Retrieve CPU Family and Model
+  //
+  FamilyId = (RegEax >> 8) & 0xf;
+  ModelId  = (RegEax >> 4) & 0xf;
+  if (FamilyId == 0x0f) {
+    //
+    // In processors based on Intel NetBurst microarchitecture, use two cache lines
+    //
+    ModelId = ModelId | ((RegEax >> 12) & 0xf0);
+    if (ModelId <= 0x04 || ModelId == 0x06) {
+      CacheLineSize *= 2;
+    }
+  }
+
+  if (CacheLineSize < 32) {
+    CacheLineSize = 32;
+  }
+
+  return CacheLineSize;
+}
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/InterlockedDecrementMsc.c b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/InterlockedDecrementMsc.c
new file mode 100644
index 00000000..eef8783c
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/InterlockedDecrementMsc.c
@@ -0,0 +1,40 @@
+/** @file
+  InterlockedDecrement function
+
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+  Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
+**/
+
+long _InterlockedDecrement(
+   long * lpAddend
+);
+
+#pragma intrinsic(_InterlockedDecrement)
+
+/**
+  Performs an atomic decrement of an 32-bit unsigned integer.
+
+  Performs an atomic decrement of the 32-bit unsigned integer specified by
+  Value and returns the decrement value. The decrement operation must be
+  performed using MP safe mechanisms. The state of the return value is not
+  guaranteed to be MP safe.
+
+  @param  Value A pointer to the 32-bit value to decrement.
+
+  @return The decrement value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncDecrement (
+  IN      volatile UINT32           *Value
+  )
+{
+  return _InterlockedDecrement ((long *)(Value));
+}
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/InterlockedIncrementMsc.c b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/InterlockedIncrementMsc.c
new file mode 100644
index 00000000..ebd9349c
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/InterlockedIncrementMsc.c
@@ -0,0 +1,40 @@
+/** @file
+  InterLockedIncrement function
+
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+  Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
+**/
+
+long _InterlockedIncrement(
+   long * lpAddend
+);
+
+#pragma intrinsic(_InterlockedIncrement)
+
+/**
+  Performs an atomic increment of an 32-bit unsigned integer.
+
+  Performs an atomic increment of the 32-bit unsigned integer specified by
+  Value and returns the incremented value. The increment operation must be
+  performed using MP safe mechanisms. The state of the return value is not
+  guaranteed to be MP safe.
+
+  @param  Value A pointer to the 32-bit value to increment.
+
+  @return The incremented value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncIncrement (
+  IN      volatile UINT32           *Value
+  )
+{
+  return _InterlockedIncrement ((long *)(Value));
+}
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
new file mode 100644
index 00000000..116b7d07
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/RiscV64/Synchronization.S
@@ -0,0 +1,78 @@
+//------------------------------------------------------------------------------
+//
+// RISC-V synchronization functions.
+//
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+//------------------------------------------------------------------------------
+#include <Base.h>
+
+.data
+
+.text
+.align 3
+
+.global ASM_PFX(InternalSyncCompareExchange32)
+.global ASM_PFX(InternalSyncCompareExchange64)
+.global ASM_PFX(InternalSyncIncrement)
+.global ASM_PFX(InternalSyncDecrement)
+
+//
+// ompare and xchange a 32-bit value.
+//
+// @param a0 : Pointer to 32-bit value.
+// @param a1 : Compare value.
+// @param a2 : Exchange value.
+//
+ASM_PFX (InternalSyncCompareExchange32):
+    lr.w  a3, (a0)        // Load the value from a0 and make
+                          // the reservation of address.
+    bne   a3, a1, exit
+    sc.w  a3, a2, (a0)    // Write the value back to the address.
+    mv    a3, a1
+exit:
+    mv    a0, a3
+    ret
+
+.global ASM_PFX(InternalSyncCompareExchange64)
+
+//
+// Compare and xchange a 64-bit value.
+//
+// @param a0 : Pointer to 64-bit value.
+// @param a1 : Compare value.
+// @param a2 : Exchange value.
+//
+ASM_PFX (SyncCompareExchange64):
+    lr.d  a3, (a0)       // Load the value from a0 and make
+                         // the reservation of address.
+    bne   a3, a1, exit
+    sc.d  a3, a2, (a0)   // Write the value back to the address.
+    mv    a3, a1
+exit2:
+    mv    a0, a3
+    ret
+
+//
+// Performs an atomic increment of an 32-bit unsigned integer.
+//
+// @param a0 : Pointer to 32-bit value.
+//
+ASM_PFX (InternalSyncIncrement):
+    li  a1, 1
+    amoadd.w  a2, a1, (a0)
+    mv  a0, a2
+    ret
+
+//
+// Performs an atomic decrement of an 32-bit unsigned integer.
+//
+// @param a0 : Pointer to 32-bit value.
+//
+ASM_PFX (InternalSyncDecrement):
+    li  a1, -1
+    amoadd.w  a2, a1, (a0)
+    mv  a0, a2
+    ret
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Synchronization.c b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Synchronization.c
new file mode 100644
index 00000000..8ea2843c
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/Synchronization.c
@@ -0,0 +1,410 @@
+/** @file
+  Implementation of synchronization functions.
+
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseSynchronizationLibInternals.h"
+
+#define SPIN_LOCK_RELEASED          ((UINTN) 1)
+#define SPIN_LOCK_ACQUIRED          ((UINTN) 2)
+
+/**
+  Retrieves the architecture specific spin lock alignment requirements for
+  optimal spin lock performance.
+
+  This function retrieves the spin lock alignment requirements for optimal
+  performance on a given CPU architecture. The spin lock alignment is byte alignment.
+  It must be a power of two and is returned by this function. If there are no alignment
+  requirements, then 1 must be returned. The spin lock synchronization
+  functions must function correctly if the spin lock size and alignment values
+  returned by this function are not used at all. These values are hints to the
+  consumers of the spin lock synchronization functions to obtain optimal spin
+  lock performance.
+
+  @return The architecture specific spin lock alignment.
+
+**/
+UINTN
+EFIAPI
+GetSpinLockProperties (
+  VOID
+  )
+{
+  return 32;
+}
+
+/**
+  Initializes a spin lock to the released state and returns the spin lock.
+
+  This function initializes the spin lock specified by SpinLock to the released
+  state, and returns SpinLock. Optimal performance can be achieved by calling
+  GetSpinLockProperties() to determine the size and alignment requirements for
+  SpinLock.
+
+  If SpinLock is NULL, then ASSERT().
+
+  @param  SpinLock  A pointer to the spin lock to initialize to the released
+                    state.
+
+  @return SpinLock is in release state.
+
+**/
+SPIN_LOCK *
+EFIAPI
+InitializeSpinLock (
+  OUT      SPIN_LOCK                 *SpinLock
+  )
+{
+  ASSERT (SpinLock != NULL);
+  *SpinLock = SPIN_LOCK_RELEASED;
+  return SpinLock;
+}
+
+/**
+  Waits until a spin lock can be placed in the acquired state.
+
+  This function checks the state of the spin lock specified by SpinLock. If
+  SpinLock is in the released state, then this function places SpinLock in the
+  acquired state and returns SpinLock. Otherwise, this function waits
+  indefinitely for the spin lock to be released, and then places it in the
+  acquired state and returns SpinLock. All state transitions of SpinLock must
+  be performed using MP safe mechanisms.
+
+  If SpinLock is NULL, then ASSERT().
+  If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().
+  If PcdSpinLockTimeout is not zero, and SpinLock is can not be acquired in
+  PcdSpinLockTimeout microseconds, then ASSERT().
+
+  @param  SpinLock  A pointer to the spin lock to place in the acquired state.
+
+  @return SpinLock acquired the lock.
+
+**/
+SPIN_LOCK *
+EFIAPI
+AcquireSpinLock (
+  IN OUT  SPIN_LOCK                 *SpinLock
+  )
+{
+  UINT64  Current;
+  UINT64  Previous;
+  UINT64  Total;
+  UINT64  Start;
+  UINT64  End;
+  UINT64  Timeout;
+  INT64   Cycle;
+  INT64   Delta;
+
+  if (PcdGet32 (PcdSpinLockTimeout) == 0) {
+    while (!AcquireSpinLockOrFail (SpinLock)) {
+      CpuPause ();
+    }
+  } else if (!AcquireSpinLockOrFail (SpinLock)) {
+    //
+    // Get the current timer value
+    //
+    Current = GetPerformanceCounter();
+
+    //
+    // Initialize local variables
+    //
+    Start = 0;
+    End   = 0;
+    Total = 0;
+
+    //
+    // Retrieve the performance counter properties and compute the number of performance
+    // counter ticks required to reach the timeout
+    //
+    Timeout = DivU64x32 (
+                MultU64x32 (
+                  GetPerformanceCounterProperties (&Start, &End),
+                  PcdGet32 (PcdSpinLockTimeout)
+                  ),
+                1000000
+                );
+    Cycle = End - Start;
+    if (Cycle < 0) {
+      Cycle = -Cycle;
+    }
+    Cycle++;
+
+    while (!AcquireSpinLockOrFail (SpinLock)) {
+      CpuPause ();
+      Previous = Current;
+      Current  = GetPerformanceCounter();
+      Delta = (INT64) (Current - Previous);
+      if (Start > End) {
+        Delta = -Delta;
+      }
+      if (Delta < 0) {
+        Delta += Cycle;
+      }
+      Total += Delta;
+      ASSERT (Total < Timeout);
+    }
+  }
+  return SpinLock;
+}
+
+/**
+  Attempts to place a spin lock in the acquired state.
+
+  This function checks the state of the spin lock specified by SpinLock. If
+  SpinLock is in the released state, then this function places SpinLock in the
+  acquired state and returns TRUE. Otherwise, FALSE is returned. All state
+  transitions of SpinLock must be performed using MP safe mechanisms.
+
+  If SpinLock is NULL, then ASSERT().
+  If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().
+
+  @param  SpinLock  A pointer to the spin lock to place in the acquired state.
+
+  @retval TRUE  SpinLock was placed in the acquired state.
+  @retval FALSE SpinLock could not be acquired.
+
+**/
+BOOLEAN
+EFIAPI
+AcquireSpinLockOrFail (
+  IN OUT  SPIN_LOCK                 *SpinLock
+  )
+{
+  SPIN_LOCK    LockValue;
+
+  ASSERT (SpinLock != NULL);
+
+  LockValue = *SpinLock;
+  ASSERT (SPIN_LOCK_ACQUIRED == LockValue || SPIN_LOCK_RELEASED == LockValue);
+
+  return (BOOLEAN)(
+           InterlockedCompareExchangePointer (
+             (VOID**)SpinLock,
+             (VOID*)SPIN_LOCK_RELEASED,
+             (VOID*)SPIN_LOCK_ACQUIRED
+             ) == (VOID*)SPIN_LOCK_RELEASED
+           );
+}
+
+/**
+  Releases a spin lock.
+
+  This function places the spin lock specified by SpinLock in the release state
+  and returns SpinLock.
+
+  If SpinLock is NULL, then ASSERT().
+  If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().
+
+  @param  SpinLock  A pointer to the spin lock to release.
+
+  @return SpinLock released lock.
+
+**/
+SPIN_LOCK *
+EFIAPI
+ReleaseSpinLock (
+  IN OUT  SPIN_LOCK                 *SpinLock
+  )
+{
+  SPIN_LOCK    LockValue;
+
+  ASSERT (SpinLock != NULL);
+
+  LockValue = *SpinLock;
+  ASSERT (SPIN_LOCK_ACQUIRED == LockValue || SPIN_LOCK_RELEASED == LockValue);
+
+  *SpinLock = SPIN_LOCK_RELEASED;
+  return SpinLock;
+}
+
+/**
+  Performs an atomic increment of an 32-bit unsigned integer.
+
+  Performs an atomic increment of the 32-bit unsigned integer specified by
+  Value and returns the incremented value. The increment operation must be
+  performed using MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value A pointer to the 32-bit value to increment.
+
+  @return The incremented value.
+
+**/
+UINT32
+EFIAPI
+InterlockedIncrement (
+  IN      volatile UINT32           *Value
+  )
+{
+  ASSERT (Value != NULL);
+  return InternalSyncIncrement (Value);
+}
+
+/**
+  Performs an atomic decrement of an 32-bit unsigned integer.
+
+  Performs an atomic decrement of the 32-bit unsigned integer specified by
+  Value and returns the decremented value. The decrement operation must be
+  performed using MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value A pointer to the 32-bit value to decrement.
+
+  @return The decremented value.
+
+**/
+UINT32
+EFIAPI
+InterlockedDecrement (
+  IN      volatile UINT32           *Value
+  )
+{
+  ASSERT (Value != NULL);
+  return InternalSyncDecrement (Value);
+}
+
+/**
+  Performs an atomic compare exchange operation on a 16-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 16-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value         A pointer to the 16-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  16-bit value used in compare operation.
+  @param  ExchangeValue 16-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT16
+EFIAPI
+InterlockedCompareExchange16 (
+  IN OUT  volatile UINT16           *Value,
+  IN      UINT16                    CompareValue,
+  IN      UINT16                    ExchangeValue
+  )
+{
+  ASSERT (Value != NULL);
+  return InternalSyncCompareExchange16 (Value, CompareValue, ExchangeValue);
+}
+
+/**
+  Performs an atomic compare exchange operation on a 32-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 32-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value         A pointer to the 32-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  32-bit value used in compare operation.
+  @param  ExchangeValue 32-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT32
+EFIAPI
+InterlockedCompareExchange32 (
+  IN OUT  volatile UINT32           *Value,
+  IN      UINT32                    CompareValue,
+  IN      UINT32                    ExchangeValue
+  )
+{
+  ASSERT (Value != NULL);
+  return InternalSyncCompareExchange32 (Value, CompareValue, ExchangeValue);
+}
+
+/**
+  Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+  by Value.  If Value is equal to CompareValue, then Value is set to ExchangeValue and
+  CompareValue is returned.  If Value is not equal to CompareValue, then Value is returned.
+  The compare exchange operation must be performed using MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value         A pointer to the 64-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  64-bit value used in compare operation.
+  @param  ExchangeValue 64-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT64
+EFIAPI
+InterlockedCompareExchange64 (
+  IN OUT  volatile UINT64           *Value,
+  IN      UINT64                    CompareValue,
+  IN      UINT64                    ExchangeValue
+  )
+{
+  ASSERT (Value != NULL);
+  return InternalSyncCompareExchange64 (Value, CompareValue, ExchangeValue);
+}
+
+/**
+  Performs an atomic compare exchange operation on a pointer value.
+
+  Performs an atomic compare exchange operation on the pointer value specified
+  by Value. If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned. If Value is not equal to
+  CompareValue, then Value is returned. The compare exchange operation must be
+  performed using MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value         A pointer to the pointer value for the compare exchange
+                        operation.
+  @param  CompareValue  Pointer value used in compare operation.
+  @param  ExchangeValue Pointer value used in exchange operation.
+
+  @return The original *Value before exchange.
+**/
+VOID *
+EFIAPI
+InterlockedCompareExchangePointer (
+  IN OUT  VOID                      * volatile *Value,
+  IN      VOID                      *CompareValue,
+  IN      VOID                      *ExchangeValue
+  )
+{
+  UINT8  SizeOfValue;
+
+  SizeOfValue = sizeof (*Value);
+
+  switch (SizeOfValue) {
+    case sizeof (UINT32):
+      return (VOID*)(UINTN)InterlockedCompareExchange32 (
+                             (volatile UINT32 *)Value,
+                             (UINT32)(UINTN)CompareValue,
+                             (UINT32)(UINTN)ExchangeValue
+                             );
+    case sizeof (UINT64):
+      return (VOID*)(UINTN)InterlockedCompareExchange64 (
+                             (volatile UINT64 *)Value,
+                             (UINT64)(UINTN)CompareValue,
+                             (UINT64)(UINTN)ExchangeValue
+                             );
+    default:
+      ASSERT (FALSE);
+      return NULL;
+  }
+}
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/SynchronizationGcc.c b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/SynchronizationGcc.c
new file mode 100644
index 00000000..5ea87c17
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/SynchronizationGcc.c
@@ -0,0 +1,426 @@
+/** @file
+  Implementation of synchronization functions.
+
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseSynchronizationLibInternals.h"
+
+//
+// GCC inline assembly for Read Write Barrier
+//
+#define _ReadWriteBarrier() do { __asm__ __volatile__ ("": : : "memory"); } while(0)
+
+#define SPIN_LOCK_RELEASED          ((UINTN) 1)
+#define SPIN_LOCK_ACQUIRED          ((UINTN) 2)
+
+/**
+  Retrieves the architecture specific spin lock alignment requirements for
+  optimal spin lock performance.
+
+  This function retrieves the spin lock alignment requirements for optimal
+  performance on a given CPU architecture. The spin lock alignment is byte alignment.
+  It must be a power of two and is returned by this function. If there are no alignment
+  requirements, then 1 must be returned. The spin lock synchronization
+  functions must function correctly if the spin lock size and alignment values
+  returned by this function are not used at all. These values are hints to the
+  consumers of the spin lock synchronization functions to obtain optimal spin
+  lock performance.
+
+  @return The architecture specific spin lock alignment.
+
+**/
+UINTN
+EFIAPI
+GetSpinLockProperties (
+  VOID
+  )
+{
+  return InternalGetSpinLockProperties ();
+}
+
+/**
+  Initializes a spin lock to the released state and returns the spin lock.
+
+  This function initializes the spin lock specified by SpinLock to the released
+  state, and returns SpinLock. Optimal performance can be achieved by calling
+  GetSpinLockProperties() to determine the size and alignment requirements for
+  SpinLock.
+
+  If SpinLock is NULL, then ASSERT().
+
+  @param  SpinLock  A pointer to the spin lock to initialize to the released
+                    state.
+
+  @return SpinLock is in release state.
+
+**/
+SPIN_LOCK *
+EFIAPI
+InitializeSpinLock (
+  OUT      SPIN_LOCK                 *SpinLock
+  )
+{
+  ASSERT (SpinLock != NULL);
+
+  _ReadWriteBarrier();
+  *SpinLock = SPIN_LOCK_RELEASED;
+  _ReadWriteBarrier();
+
+  return SpinLock;
+}
+
+/**
+  Waits until a spin lock can be placed in the acquired state.
+
+  This function checks the state of the spin lock specified by SpinLock. If
+  SpinLock is in the released state, then this function places SpinLock in the
+  acquired state and returns SpinLock. Otherwise, this function waits
+  indefinitely for the spin lock to be released, and then places it in the
+  acquired state and returns SpinLock. All state transitions of SpinLock must
+  be performed using MP safe mechanisms.
+
+  If SpinLock is NULL, then ASSERT().
+  If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().
+  If PcdSpinLockTimeout is not zero, and SpinLock is can not be acquired in
+  PcdSpinLockTimeout microseconds, then ASSERT().
+
+  @param  SpinLock  A pointer to the spin lock to place in the acquired state.
+
+  @return SpinLock acquired the lock.
+
+**/
+SPIN_LOCK *
+EFIAPI
+AcquireSpinLock (
+  IN OUT  SPIN_LOCK                 *SpinLock
+  )
+{
+  UINT64  Current;
+  UINT64  Previous;
+  UINT64  Total;
+  UINT64  Start;
+  UINT64  End;
+  UINT64  Timeout;
+  INT64   Cycle;
+  INT64   Delta;
+
+  if (PcdGet32 (PcdSpinLockTimeout) == 0) {
+    while (!AcquireSpinLockOrFail (SpinLock)) {
+      CpuPause ();
+    }
+  } else if (!AcquireSpinLockOrFail (SpinLock)) {
+    //
+    // Get the current timer value
+    //
+    Current = GetPerformanceCounter();
+
+    //
+    // Initialize local variables
+    //
+    Start = 0;
+    End   = 0;
+    Total = 0;
+
+    //
+    // Retrieve the performance counter properties and compute the number of performance
+    // counter ticks required to reach the timeout
+    //
+    Timeout = DivU64x32 (
+                MultU64x32 (
+                  GetPerformanceCounterProperties (&Start, &End),
+                  PcdGet32 (PcdSpinLockTimeout)
+                  ),
+                1000000
+                );
+    Cycle = End - Start;
+    if (Cycle < 0) {
+      Cycle = -Cycle;
+    }
+    Cycle++;
+
+    while (!AcquireSpinLockOrFail (SpinLock)) {
+      CpuPause ();
+      Previous = Current;
+      Current  = GetPerformanceCounter();
+      Delta = (INT64) (Current - Previous);
+      if (Start > End) {
+        Delta = -Delta;
+      }
+      if (Delta < 0) {
+        Delta += Cycle;
+      }
+      Total += Delta;
+      ASSERT (Total < Timeout);
+    }
+  }
+  return SpinLock;
+}
+
+/**
+  Attempts to place a spin lock in the acquired state.
+
+  This function checks the state of the spin lock specified by SpinLock. If
+  SpinLock is in the released state, then this function places SpinLock in the
+  acquired state and returns TRUE. Otherwise, FALSE is returned. All state
+  transitions of SpinLock must be performed using MP safe mechanisms.
+
+  If SpinLock is NULL, then ASSERT().
+  If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().
+
+  @param  SpinLock  A pointer to the spin lock to place in the acquired state.
+
+  @retval TRUE  SpinLock was placed in the acquired state.
+  @retval FALSE SpinLock could not be acquired.
+
+**/
+BOOLEAN
+EFIAPI
+AcquireSpinLockOrFail (
+  IN OUT  SPIN_LOCK                 *SpinLock
+  )
+{
+  SPIN_LOCK   LockValue;
+  VOID        *Result;
+
+  ASSERT (SpinLock != NULL);
+
+  LockValue = *SpinLock;
+  ASSERT (LockValue == SPIN_LOCK_ACQUIRED || LockValue == SPIN_LOCK_RELEASED);
+
+  _ReadWriteBarrier ();
+  Result = InterlockedCompareExchangePointer (
+             (VOID**)SpinLock,
+             (VOID*)SPIN_LOCK_RELEASED,
+             (VOID*)SPIN_LOCK_ACQUIRED
+           );
+
+  _ReadWriteBarrier ();
+  return (BOOLEAN) (Result == (VOID*) SPIN_LOCK_RELEASED);
+}
+
+/**
+  Releases a spin lock.
+
+  This function places the spin lock specified by SpinLock in the release state
+  and returns SpinLock.
+
+  If SpinLock is NULL, then ASSERT().
+  If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().
+
+  @param  SpinLock  A pointer to the spin lock to release.
+
+  @return SpinLock released the lock.
+
+**/
+SPIN_LOCK *
+EFIAPI
+ReleaseSpinLock (
+  IN OUT  SPIN_LOCK                 *SpinLock
+  )
+{
+  SPIN_LOCK    LockValue;
+
+  ASSERT (SpinLock != NULL);
+
+  LockValue = *SpinLock;
+  ASSERT (LockValue == SPIN_LOCK_ACQUIRED || LockValue == SPIN_LOCK_RELEASED);
+
+  _ReadWriteBarrier ();
+  *SpinLock = SPIN_LOCK_RELEASED;
+  _ReadWriteBarrier ();
+
+  return SpinLock;
+}
+
+/**
+  Performs an atomic increment of an 32-bit unsigned integer.
+
+  Performs an atomic increment of the 32-bit unsigned integer specified by
+  Value and returns the incremented value. The increment operation must be
+  performed using MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value A pointer to the 32-bit value to increment.
+
+  @return The incremented value.
+
+**/
+UINT32
+EFIAPI
+InterlockedIncrement (
+  IN      volatile UINT32           *Value
+  )
+{
+  ASSERT (Value != NULL);
+  return InternalSyncIncrement (Value);
+}
+
+/**
+  Performs an atomic decrement of an 32-bit unsigned integer.
+
+  Performs an atomic decrement of the 32-bit unsigned integer specified by
+  Value and returns the decremented value. The decrement operation must be
+  performed using MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value A pointer to the 32-bit value to decrement.
+
+  @return The decremented value.
+
+**/
+UINT32
+EFIAPI
+InterlockedDecrement (
+  IN      volatile UINT32           *Value
+  )
+{
+  ASSERT (Value != NULL);
+  return InternalSyncDecrement (Value);
+}
+
+/**
+  Performs an atomic compare exchange operation on a 16-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 16-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value         A pointer to the 16-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  A 16-bit value used in compare operation.
+  @param  ExchangeValue A 16-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT16
+EFIAPI
+InterlockedCompareExchange16 (
+  IN OUT  volatile UINT16           *Value,
+  IN      UINT16                    CompareValue,
+  IN      UINT16                    ExchangeValue
+  )
+{
+  ASSERT (Value != NULL);
+  return InternalSyncCompareExchange16 (Value, CompareValue, ExchangeValue);
+}
+
+/**
+  Performs an atomic compare exchange operation on a 32-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 32-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value         A pointer to the 32-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  A 32-bit value used in compare operation.
+  @param  ExchangeValue A 32-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT32
+EFIAPI
+InterlockedCompareExchange32 (
+  IN OUT  volatile UINT32           *Value,
+  IN      UINT32                    CompareValue,
+  IN      UINT32                    ExchangeValue
+  )
+{
+  ASSERT (Value != NULL);
+  return InternalSyncCompareExchange32 (Value, CompareValue, ExchangeValue);
+}
+
+/**
+  Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+  by Value.  If Value is equal to CompareValue, then Value is set to ExchangeValue and
+  CompareValue is returned.  If Value is not equal to CompareValue, then Value is returned.
+  The compare exchange operation must be performed using MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value         A pointer to the 64-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  A 64-bit value used in a compare operation.
+  @param  ExchangeValue A 64-bit value used in an exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT64
+EFIAPI
+InterlockedCompareExchange64 (
+  IN OUT  volatile UINT64           *Value,
+  IN      UINT64                    CompareValue,
+  IN      UINT64                    ExchangeValue
+  )
+{
+  ASSERT (Value != NULL);
+  return InternalSyncCompareExchange64 (Value, CompareValue, ExchangeValue);
+}
+
+/**
+  Performs an atomic compare exchange operation on a pointer value.
+
+  Performs an atomic compare exchange operation on the pointer value specified
+  by Value. If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned. If Value is not equal to
+  CompareValue, then Value is returned. The compare exchange operation must be
+  performed using MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value         A pointer to the pointer value for the compare exchange
+                        operation.
+  @param  CompareValue  A pointer value used in a compare operation.
+  @param  ExchangeValue A pointer value used in an exchange operation.
+
+  @return The original *Value before exchange.
+**/
+VOID *
+EFIAPI
+InterlockedCompareExchangePointer (
+  IN OUT  VOID                      * volatile *Value,
+  IN      VOID                      *CompareValue,
+  IN      VOID                      *ExchangeValue
+  )
+{
+  UINT8  SizeOfValue;
+
+  SizeOfValue = sizeof (*Value);
+
+  switch (SizeOfValue) {
+    case sizeof (UINT32):
+      return (VOID*)(UINTN)InterlockedCompareExchange32 (
+                             (volatile UINT32 *)Value,
+                             (UINT32)(UINTN)CompareValue,
+                             (UINT32)(UINTN)ExchangeValue
+                             );
+    case sizeof (UINT64):
+      return (VOID*)(UINTN)InterlockedCompareExchange64 (
+                             (volatile UINT64 *)Value,
+                             (UINT64)(UINTN)CompareValue,
+                             (UINT64)(UINTN)ExchangeValue
+                             );
+    default:
+      ASSERT (FALSE);
+      return NULL;
+  }
+}
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/SynchronizationMsc.c b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/SynchronizationMsc.c
new file mode 100644
index 00000000..3e136576
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/SynchronizationMsc.c
@@ -0,0 +1,428 @@
+/** @file
+  Implementation of synchronization functions.
+
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BaseSynchronizationLibInternals.h"
+
+/**
+  Microsoft Visual Studio 7.1 Function Prototypes for read write barrier Intrinsics.
+**/
+
+void    _ReadWriteBarrier (void);
+#pragma intrinsic(_ReadWriteBarrier)
+
+
+#define SPIN_LOCK_RELEASED          ((UINTN) 1)
+#define SPIN_LOCK_ACQUIRED          ((UINTN) 2)
+
+/**
+  Retrieves the architecture specific spin lock alignment requirements for
+  optimal spin lock performance.
+
+  This function retrieves the spin lock alignment requirements for optimal
+  performance on a given CPU architecture. The spin lock alignment is byte alignment.
+  It must be a power of two and is returned by this function. If there are no alignment
+  requirements, then 1 must be returned. The spin lock synchronization
+  functions must function correctly if the spin lock size and alignment values
+  returned by this function are not used at all. These values are hints to the
+  consumers of the spin lock synchronization functions to obtain optimal spin
+  lock performance.
+
+  @return The architecture specific spin lock alignment.
+
+**/
+UINTN
+EFIAPI
+GetSpinLockProperties (
+  VOID
+  )
+{
+  return InternalGetSpinLockProperties ();
+}
+
+/**
+  Initializes a spin lock to the released state and returns the spin lock.
+
+  This function initializes the spin lock specified by SpinLock to the released
+  state, and returns SpinLock. Optimal performance can be achieved by calling
+  GetSpinLockProperties() to determine the size and alignment requirements for
+  SpinLock.
+
+  If SpinLock is NULL, then ASSERT().
+
+  @param  SpinLock  A pointer to the spin lock to initialize to the released
+                    state.
+
+  @return SpinLock is in release state.
+
+**/
+SPIN_LOCK *
+EFIAPI
+InitializeSpinLock (
+  OUT      SPIN_LOCK                 *SpinLock
+  )
+{
+  ASSERT (SpinLock != NULL);
+
+  _ReadWriteBarrier();
+  *SpinLock = SPIN_LOCK_RELEASED;
+  _ReadWriteBarrier();
+
+  return SpinLock;
+}
+
+/**
+  Waits until a spin lock can be placed in the acquired state.
+
+  This function checks the state of the spin lock specified by SpinLock. If
+  SpinLock is in the released state, then this function places SpinLock in the
+  acquired state and returns SpinLock. Otherwise, this function waits
+  indefinitely for the spin lock to be released, and then places it in the
+  acquired state and returns SpinLock. All state transitions of SpinLock must
+  be performed using MP safe mechanisms.
+
+  If SpinLock is NULL, then ASSERT().
+  If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().
+  If PcdSpinLockTimeout is not zero, and SpinLock is can not be acquired in
+  PcdSpinLockTimeout microseconds, then ASSERT().
+
+  @param  SpinLock  A pointer to the spin lock to place in the acquired state.
+
+  @return SpinLock acquired the lock.
+
+**/
+SPIN_LOCK *
+EFIAPI
+AcquireSpinLock (
+  IN OUT  SPIN_LOCK                 *SpinLock
+  )
+{
+  UINT64  Current;
+  UINT64  Previous;
+  UINT64  Total;
+  UINT64  Start;
+  UINT64  End;
+  UINT64  Timeout;
+  INT64   Cycle;
+  INT64   Delta;
+
+  if (PcdGet32 (PcdSpinLockTimeout) == 0) {
+    while (!AcquireSpinLockOrFail (SpinLock)) {
+      CpuPause ();
+    }
+  } else if (!AcquireSpinLockOrFail (SpinLock)) {
+    //
+    // Get the current timer value
+    //
+    Current = GetPerformanceCounter();
+
+    //
+    // Initialize local variables
+    //
+    Start = 0;
+    End   = 0;
+    Total = 0;
+
+    //
+    // Retrieve the performance counter properties and compute the number of performance
+    // counter ticks required to reach the timeout
+    //
+    Timeout = DivU64x32 (
+                MultU64x32 (
+                  GetPerformanceCounterProperties (&Start, &End),
+                  PcdGet32 (PcdSpinLockTimeout)
+                  ),
+                1000000
+                );
+    Cycle = End - Start;
+    if (Cycle < 0) {
+      Cycle = -Cycle;
+    }
+    Cycle++;
+
+    while (!AcquireSpinLockOrFail (SpinLock)) {
+      CpuPause ();
+      Previous = Current;
+      Current  = GetPerformanceCounter();
+      Delta = (INT64) (Current - Previous);
+      if (Start > End) {
+        Delta = -Delta;
+      }
+      if (Delta < 0) {
+        Delta += Cycle;
+      }
+      Total += Delta;
+      ASSERT (Total < Timeout);
+    }
+  }
+  return SpinLock;
+}
+
+/**
+  Attempts to place a spin lock in the acquired state.
+
+  This function checks the state of the spin lock specified by SpinLock. If
+  SpinLock is in the released state, then this function places SpinLock in the
+  acquired state and returns TRUE. Otherwise, FALSE is returned. All state
+  transitions of SpinLock must be performed using MP safe mechanisms.
+
+  If SpinLock is NULL, then ASSERT().
+  If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().
+
+  @param  SpinLock  A pointer to the spin lock to place in the acquired state.
+
+  @retval TRUE  SpinLock was placed in the acquired state.
+  @retval FALSE SpinLock could not be acquired.
+
+**/
+BOOLEAN
+EFIAPI
+AcquireSpinLockOrFail (
+  IN OUT  SPIN_LOCK                 *SpinLock
+  )
+{
+  SPIN_LOCK   LockValue;
+  VOID        *Result;
+
+  ASSERT (SpinLock != NULL);
+
+  LockValue = *SpinLock;
+  ASSERT (LockValue == SPIN_LOCK_ACQUIRED || LockValue == SPIN_LOCK_RELEASED);
+
+  _ReadWriteBarrier ();
+  Result = InterlockedCompareExchangePointer (
+             (VOID**)SpinLock,
+             (VOID*)SPIN_LOCK_RELEASED,
+             (VOID*)SPIN_LOCK_ACQUIRED
+           );
+
+  _ReadWriteBarrier ();
+  return (BOOLEAN) (Result == (VOID*) SPIN_LOCK_RELEASED);
+}
+
+/**
+  Releases a spin lock.
+
+  This function places the spin lock specified by SpinLock in the release state
+  and returns SpinLock.
+
+  If SpinLock is NULL, then ASSERT().
+  If SpinLock was not initialized with InitializeSpinLock(), then ASSERT().
+
+  @param  SpinLock  A pointer to the spin lock to release.
+
+  @return SpinLock released the lock.
+
+**/
+SPIN_LOCK *
+EFIAPI
+ReleaseSpinLock (
+  IN OUT  SPIN_LOCK                 *SpinLock
+  )
+{
+  SPIN_LOCK    LockValue;
+
+  ASSERT (SpinLock != NULL);
+
+  LockValue = *SpinLock;
+  ASSERT (LockValue == SPIN_LOCK_ACQUIRED || LockValue == SPIN_LOCK_RELEASED);
+
+  _ReadWriteBarrier ();
+  *SpinLock = SPIN_LOCK_RELEASED;
+  _ReadWriteBarrier ();
+
+  return SpinLock;
+}
+
+/**
+  Performs an atomic increment of an 32-bit unsigned integer.
+
+  Performs an atomic increment of the 32-bit unsigned integer specified by
+  Value and returns the incremented value. The increment operation must be
+  performed using MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value A pointer to the 32-bit value to increment.
+
+  @return The incremented value.
+
+**/
+UINT32
+EFIAPI
+InterlockedIncrement (
+  IN      volatile UINT32           *Value
+  )
+{
+  ASSERT (Value != NULL);
+  return InternalSyncIncrement (Value);
+}
+
+/**
+  Performs an atomic decrement of an 32-bit unsigned integer.
+
+  Performs an atomic decrement of the 32-bit unsigned integer specified by
+  Value and returns the decremented value. The decrement operation must be
+  performed using MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value A pointer to the 32-bit value to decrement.
+
+  @return The decremented value.
+
+**/
+UINT32
+EFIAPI
+InterlockedDecrement (
+  IN      volatile UINT32           *Value
+  )
+{
+  ASSERT (Value != NULL);
+  return InternalSyncDecrement (Value);
+}
+
+/**
+  Performs an atomic compare exchange operation on a 16-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 16-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value         A pointer to the 16-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  A 16-bit value used in a compare operation.
+  @param  ExchangeValue A 16-bit value used in an exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT16
+EFIAPI
+InterlockedCompareExchange16 (
+  IN OUT  volatile UINT16           *Value,
+  IN      UINT16                    CompareValue,
+  IN      UINT16                    ExchangeValue
+  )
+{
+  ASSERT (Value != NULL);
+  return InternalSyncCompareExchange16 (Value, CompareValue, ExchangeValue);
+}
+
+/**
+  Performs an atomic compare exchange operation on a 32-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 32-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value         A pointer to the 32-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  A 32-bit value used in a compare operation.
+  @param  ExchangeValue A 32-bit value used in an exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT32
+EFIAPI
+InterlockedCompareExchange32 (
+  IN OUT  volatile UINT32           *Value,
+  IN      UINT32                    CompareValue,
+  IN      UINT32                    ExchangeValue
+  )
+{
+  ASSERT (Value != NULL);
+  return InternalSyncCompareExchange32 (Value, CompareValue, ExchangeValue);
+}
+
+/**
+  Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+  by Value.  If Value is equal to CompareValue, then Value is set to ExchangeValue and
+  CompareValue is returned.  If Value is not equal to CompareValue, then Value is returned.
+  The compare exchange operation must be performed using MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value         A pointer to the 64-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  A 64-bit value used in a compare operation.
+  @param  ExchangeValue A 64-bit value used in an exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT64
+EFIAPI
+InterlockedCompareExchange64 (
+  IN OUT  volatile UINT64           *Value,
+  IN      UINT64                    CompareValue,
+  IN      UINT64                    ExchangeValue
+  )
+{
+  ASSERT (Value != NULL);
+  return InternalSyncCompareExchange64 (Value, CompareValue, ExchangeValue);
+}
+
+/**
+  Performs an atomic compare exchange operation on a pointer value.
+
+  Performs an atomic compare exchange operation on the pointer value specified
+  by Value. If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned. If Value is not equal to
+  CompareValue, then Value is returned. The compare exchange operation must be
+  performed using MP safe mechanisms.
+
+  If Value is NULL, then ASSERT().
+
+  @param  Value         A pointer to the pointer value for the compare exchange
+                        operation.
+  @param  CompareValue  A pointer value used in a compare operation.
+  @param  ExchangeValue A pointer value used in an exchange operation.
+
+  @return The original *Value before exchange.
+**/
+VOID *
+EFIAPI
+InterlockedCompareExchangePointer (
+  IN OUT  VOID                      * volatile *Value,
+  IN      VOID                      *CompareValue,
+  IN      VOID                      *ExchangeValue
+  )
+{
+  UINT8  SizeOfValue;
+
+  SizeOfValue = (UINT8) sizeof (*Value);
+
+  switch (SizeOfValue) {
+    case sizeof (UINT32):
+      return (VOID*)(UINTN)InterlockedCompareExchange32 (
+                             (volatile UINT32*)Value,
+                             (UINT32)(UINTN)CompareValue,
+                             (UINT32)(UINTN)ExchangeValue
+                             );
+    case sizeof (UINT64):
+      return (VOID*)(UINTN)InterlockedCompareExchange64 (
+                             (volatile UINT64*)Value,
+                             (UINT64)(UINTN)CompareValue,
+                             (UINT64)(UINTN)ExchangeValue
+                             );
+    default:
+      ASSERT (FALSE);
+      return NULL;
+  }
+}
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/GccInline.c b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/GccInline.c
new file mode 100644
index 00000000..ee9d6a4a
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/GccInline.c
@@ -0,0 +1,200 @@
+/** @file
+  GCC inline implementation of BaseSynchronizationLib processor specific functions.
+
+  Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+
+
+/**
+  Performs an atomic increment of an 32-bit unsigned integer.
+
+  Performs an atomic increment of the 32-bit unsigned integer specified by
+  Value and returns the incremented value. The increment operation must be
+  performed using MP safe mechanisms.
+
+  @param  Value A pointer to the 32-bit value to increment.
+
+  @return The incremented value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncIncrement (
+  IN      volatile UINT32    *Value
+  )
+{
+  UINT32  Result;
+
+  __asm__ __volatile__ (
+    "movl    $1, %%eax  \n\t"
+    "lock               \n\t"
+    "xadd    %%eax, %1  \n\t"
+    "inc     %%eax      \n\t"
+    : "=&a" (Result),         // %0
+      "+m" (*Value)           // %1
+    :                         // no inputs that aren't also outputs
+    : "memory",
+      "cc"
+    );
+
+  return Result;
+}
+
+
+/**
+  Performs an atomic decrement of an 32-bit unsigned integer.
+
+  Performs an atomic decrement of the 32-bit unsigned integer specified by
+  Value and returns the decremented value. The decrement operation must be
+  performed using MP safe mechanisms.
+
+  @param  Value A pointer to the 32-bit value to decrement.
+
+  @return The decremented value.
+
+**/
+UINT32
+EFIAPI
+InternalSyncDecrement (
+  IN      volatile UINT32       *Value
+  )
+{
+   UINT32  Result;
+
+  __asm__ __volatile__ (
+    "movl    $-1, %%eax  \n\t"
+    "lock                \n\t"
+    "xadd    %%eax, %1   \n\t"
+    "dec     %%eax       \n\t"
+    : "=&a" (Result),          // %0
+      "+m" (*Value)            // %1
+    :                          // no inputs that aren't also outputs
+    : "memory",
+      "cc"
+    );
+
+  return Result;
+}
+
+
+/**
+  Performs an atomic compare exchange operation on a 16-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 16-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+
+  @param  Value         A pointer to the 16-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  16-bit value used in compare operation.
+  @param  ExchangeValue 16-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT16
+EFIAPI
+InternalSyncCompareExchange16 (
+  IN OUT volatile  UINT16           *Value,
+  IN      UINT16                    CompareValue,
+  IN      UINT16                    ExchangeValue
+  )
+{
+  __asm__ __volatile__ (
+    "lock                 \n\t"
+    "cmpxchgw    %2, %1   \n\t"
+    : "+a" (CompareValue),      // %0
+      "+m" (*Value)             // %1
+    : "r"  (ExchangeValue)      // %2
+    : "memory",
+      "cc"
+    );
+
+  return CompareValue;
+}
+
+
+/**
+  Performs an atomic compare exchange operation on a 32-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 32-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+
+  @param  Value         A pointer to the 32-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  32-bit value used in compare operation.
+  @param  ExchangeValue 32-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT32
+EFIAPI
+InternalSyncCompareExchange32 (
+  IN OUT volatile  UINT32           *Value,
+  IN      UINT32                    CompareValue,
+  IN      UINT32                    ExchangeValue
+  )
+{
+  __asm__ __volatile__ (
+    "lock                 \n\t"
+    "cmpxchgl    %2, %1   \n\t"
+    : "+a" (CompareValue),      // %0
+      "+m" (*Value)             // %1
+    : "r"  (ExchangeValue)      // %2
+    : "memory",
+      "cc"
+    );
+
+  return CompareValue;
+}
+
+
+/**
+  Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+  by Value.  If Value is equal to CompareValue, then Value is set to ExchangeValue and
+  CompareValue is returned.  If Value is not equal to CompareValue, then Value is returned.
+  The compare exchange operation must be performed using MP safe mechanisms.
+
+
+  @param  Value         A pointer to the 64-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  64-bit value used in compare operation.
+  @param  ExchangeValue 64-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT64
+EFIAPI
+InternalSyncCompareExchange64 (
+  IN OUT  volatile UINT64           *Value,
+  IN      UINT64                    CompareValue,
+  IN      UINT64                    ExchangeValue
+  )
+{
+  __asm__ __volatile__ (
+    "lock                 \n\t"
+    "cmpxchgq    %2, %1   \n\t"
+    : "+a" (CompareValue),      // %0
+      "+m" (*Value)             // %1
+    : "r"  (ExchangeValue)      // %2
+    : "memory",
+      "cc"
+    );
+
+  return CompareValue;
+}
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange16.c b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange16.c
new file mode 100644
index 00000000..ab8e5031
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange16.c
@@ -0,0 +1,48 @@
+/** @file
+  InterlockedCompareExchange16 function
+
+  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+  Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
+**/
+
+__int16 _InterlockedCompareExchange16(
+   __int16 volatile * Destination,
+   __int16 Exchange,
+   __int16 Comperand
+);
+
+#pragma intrinsic(_InterlockedCompareExchange16)
+
+/**
+  Performs an atomic compare exchange operation on a 16-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 16-bit unsigned integer specified
+  by Value.  If Value is equal to CompareValue, then Value is set to ExchangeValue and
+  CompareValue is returned.  If Value is not equal to CompareValue, then Value is returned.
+  The compare exchange operation must be performed using MP safe mechanisms.
+
+  @param  Value         A pointer to the 16-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  16-bit value used in compare operation.
+  @param  ExchangeValue 16-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT16
+EFIAPI
+InternalSyncCompareExchange16 (
+  IN      volatile UINT16           *Value,
+  IN      UINT16                    CompareValue,
+  IN      UINT16                    ExchangeValue
+  )
+{
+  return _InterlockedCompareExchange16 (Value, ExchangeValue, CompareValue);
+}
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange16.nasm b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange16.nasm
new file mode 100644
index 00000000..6c00f62c
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange16.nasm
@@ -0,0 +1,36 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2015, Linaro Ltd. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+;   InterlockedCompareExchange16.Asm
+;
+; Abstract:
+;
+;   InterlockedCompareExchange16 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    DEFAULT REL
+    SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT16
+; EFIAPI
+; InternalSyncCompareExchange16 (
+;   IN      volatile UINT16           *Value,
+;   IN      UINT16                    CompareValue,
+;   IN      UINT16                    ExchangeValue
+;   );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalSyncCompareExchange16)
+ASM_PFX(InternalSyncCompareExchange16):
+    mov     ax, dx
+    lock    cmpxchg [rcx], r8w
+    ret
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange32.c b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange32.c
new file mode 100644
index 00000000..0b7212ca
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange32.c
@@ -0,0 +1,48 @@
+/** @file
+  InterlockedCompareExchange32 function
+
+  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+  Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
+**/
+
+long _InterlockedCompareExchange(
+   long volatile * Destination,
+   long Exchange,
+   long Comperand
+);
+
+#pragma intrinsic(_InterlockedCompareExchange)
+
+/**
+  Performs an atomic compare exchange operation on a 32-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 32-bit unsigned integer
+  specified by Value.  If Value is equal to CompareValue, then Value is set to
+  ExchangeValue and CompareValue is returned.  If Value is not equal to CompareValue,
+  then Value is returned.  The compare exchange operation must be performed using
+  MP safe mechanisms.
+
+  @param  Value         A pointer to the 32-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  32-bit value used in compare operation.
+  @param  ExchangeValue 32-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT32
+EFIAPI
+InternalSyncCompareExchange32 (
+  IN      volatile UINT32           *Value,
+  IN      UINT32                    CompareValue,
+  IN      UINT32                    ExchangeValue
+  )
+{
+  return _InterlockedCompareExchange (Value, ExchangeValue, CompareValue);
+}
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange32.nasm b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange32.nasm
new file mode 100644
index 00000000..b659fa6f
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange32.nasm
@@ -0,0 +1,35 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+;   InterlockedCompareExchange32.Asm
+;
+; Abstract:
+;
+;   InterlockedCompareExchange32 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    DEFAULT REL
+    SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT32
+; EFIAPI
+; InternalSyncCompareExchange32 (
+;   IN      volatile UINT32           *Value,
+;   IN      UINT32                    CompareValue,
+;   IN      UINT32                    ExchangeValue
+;   );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalSyncCompareExchange32)
+ASM_PFX(InternalSyncCompareExchange32):
+    mov     eax, edx
+    lock    cmpxchg [rcx], r8d
+    ret
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange64.c b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange64.c
new file mode 100644
index 00000000..f737b630
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange64.c
@@ -0,0 +1,47 @@
+/** @file
+  InterlockedCompareExchange64 function
+
+  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+/**
+  Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics.
+**/
+
+__int64 _InterlockedCompareExchange64(
+   __int64 volatile * Destination,
+   __int64 Exchange,
+   __int64 Comperand
+);
+
+#pragma intrinsic(_InterlockedCompareExchange64)
+
+/**
+  Performs an atomic compare exchange operation on a 64-bit unsigned integer.
+
+  Performs an atomic compare exchange operation on the 64-bit unsigned integer specified
+  by Value.  If Value is equal to CompareValue, then Value is set to ExchangeValue and
+  CompareValue is returned.  If Value is not equal to CompareValue, then Value is returned.
+  The compare exchange operation must be performed using MP safe mechanisms.
+
+  @param  Value         A pointer to the 64-bit value for the compare exchange
+                        operation.
+  @param  CompareValue  64-bit value used in compare operation.
+  @param  ExchangeValue 64-bit value used in exchange operation.
+
+  @return The original *Value before exchange.
+
+**/
+UINT64
+EFIAPI
+InternalSyncCompareExchange64 (
+  IN      volatile UINT64           *Value,
+  IN      UINT64                    CompareValue,
+  IN      UINT64                    ExchangeValue
+  )
+{
+  return _InterlockedCompareExchange64 (Value, ExchangeValue, CompareValue);
+}
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange64.nasm b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange64.nasm
new file mode 100644
index 00000000..91194da2
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedCompareExchange64.nasm
@@ -0,0 +1,35 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+;   InterlockedCompareExchange64.Asm
+;
+; Abstract:
+;
+;   InterlockedCompareExchange64 function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    DEFAULT REL
+    SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; InternalSyncCompareExchange64 (
+;   IN      volatile UINT64           *Value,
+;   IN      UINT64                    CompareValue,
+;   IN      UINT64                    ExchangeValue
+;   );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalSyncCompareExchange64)
+ASM_PFX(InternalSyncCompareExchange64):
+    mov     rax, rdx
+    lock    cmpxchg [rcx], r8
+    ret
+
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedDecrement.nasm b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedDecrement.nasm
new file mode 100644
index 00000000..d36d9b00
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedDecrement.nasm
@@ -0,0 +1,33 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+;   InterlockedDecrement.Asm
+;
+; Abstract:
+;
+;   InterlockedDecrement function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    DEFAULT REL
+    SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT32
+; EFIAPI
+; InternalSyncDecrement (
+;   IN      volatile UINT32           *Value
+;   );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalSyncDecrement)
+ASM_PFX(InternalSyncDecrement):
+    mov       eax, 0FFFFFFFFh
+    lock xadd dword [rcx], eax
+    dec       eax
+    ret
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedIncrement.nasm b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedIncrement.nasm
new file mode 100644
index 00000000..fd046958
--- /dev/null
+++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseSynchronizationLib/X64/InterlockedIncrement.nasm
@@ -0,0 +1,34 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+;   InterlockedIncrement.Asm
+;
+; Abstract:
+;
+;   InterlockedIncrement function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+    DEFAULT REL
+    SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT32
+; EFIAPI
+; InternalSyncIncrement (
+;   IN      volatile UINT32           *Value
+;   );
+;------------------------------------------------------------------------------
+global ASM_PFX(InternalSyncIncrement)
+ASM_PFX(InternalSyncIncrement):
+    mov       eax, 1
+    lock xadd dword [rcx], eax
+    inc       eax
+    ret
+