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+;; @file
+; X86 (and AMD64) Local APIC registers (VMM,++).
+;
+; Automatically generated by various.sed. DO NOT EDIT!
+;
+
+;
+; Copyright (C) 2010-2023 Oracle and/or its affiliates.
+;
+; This file is part of VirtualBox base platform packages, as
+; available from https://www.virtualbox.org.
+;
+; This program is free software; you can redistribute it and/or
+; modify it under the terms of the GNU General Public License
+; as published by the Free Software Foundation, in version 3 of the
+; License.
+;
+; This program is distributed in the hope that it will be useful, but
+; WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+; General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, see <https://www.gnu.org/licenses>.
+;
+; The contents of this file may alternatively be used under the terms
+; of the Common Development and Distribution License Version 1.0
+; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
+; in the VirtualBox distribution, in which case the provisions of the
+; CDDL are applicable instead of those of the GPL.
+;
+; You may elect to license modified versions of this file under the
+; terms and conditions of either the GPL or the CDDL or both.
+;
+; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
+;
+
+%ifndef VBOX_INCLUDED_apic_h
+%define VBOX_INCLUDED_apic_h
+%ifndef RT_WITHOUT_PRAGMA_ONCE
+%endif
+%define APIC_REG_VERSION 0x0030
+%define APIC_REG_VERSION_GET_VER(u32) (u32 & 0xff)
+%define APIC_REG_VERSION_GET_MAX_LVT(u32) ((u32 & 0xff0000) >> 16)
+%define APIC_REG_LVT_LINT0 0x0350
+%define APIC_REG_LVT_LINT1 0x0360
+%define APIC_REG_LVT_ERR 0x0370
+%define APIC_REG_LVT_PC 0x0340
+%define APIC_REG_LVT_THMR 0x0330
+%define APIC_REG_LVT_CMCI 0x02F0
+%define APIC_REG_EILVT0 0x0500
+%define APIC_REG_EILVT1 0x0510
+%define APIC_REG_EILVT2 0x0520
+%define APIC_REG_EILVT3 0x0530
+%define APIC_REG_LVT_MODE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
+%define APIC_REG_LVT_MODE_FIXED 0
+%define APIC_REG_LVT_MODE_NMI RT_BIT(10)
+%define APIC_REG_LVT_MODE_EXTINT (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
+%define APIC_REG_LVT_PIN_POLARIY RT_BIT(13)
+%define APIC_REG_LVT_REMOTE_IRR RT_BIT(14)
+%define APIC_REG_LVT_LEVEL_TRIGGER RT_BIT(15)
+%define APIC_REG_LVT_MASKED RT_BIT(16)
+%define XAPIC_HARDWARE_VERSION_P4 0x14
+%define XAPIC_MAX_LVT_ENTRIES_P4 6
+%define XAPIC_APIC_ID_BIT_COUNT_P4 8
+%define XAPIC_HARDWARE_VERSION_P6 0x10
+%define XAPIC_MAX_LVT_ENTRIES_P6 4
+%define XAPIC_APIC_ID_BIT_COUNT_P6 4
+%define XAPIC_ILLEGAL_VECTOR_START 0
+%define XAPIC_ILLEGAL_VECTOR_END 15
+%define XAPIC_RSVD_VECTOR_START 16
+%define XAPIC_RSVD_VECTOR_END 31
+ %define XAPIC_ESR_SEND_CHKSUM_ERROR_P6 RT_BIT(0)
+ %define XAPIC_ESR_RECV_CHKSUM_ERROR_P6 RT_BIT(1)
+ %define XAPIC_ESR_SEND_ACCEPT_ERROR_P6 RT_BIT(2)
+ %define XAPIC_ESR_RECV_ACCEPT_ERROR_P6 RT_BIT(3)
+%define XAPIC_ESR_REDIRECTABLE_IPI RT_BIT(4)
+%define XAPIC_ESR_SEND_ILLEGAL_VECTOR RT_BIT(5)
+%define XAPIC_ESR_RECV_ILLEGAL_VECTOR RT_BIT(6)
+%define XAPIC_ESR_ILLEGAL_REG_ADDRESS RT_BIT(7)
+%define XAPIC_ESR_WO_VALID 0x0
+%define XAPIC_TPR_VALID 0xff
+%define XAPIC_TPR_TP 0xf0
+%define XAPIC_TPR_TP_SUBCLASS 0x0f
+%define XAPIC_TPR_GET_TP(a_Tpr) ((a_Tpr) & XAPIC_TPR_TP)
+%define XAPIC_TPR_GET_TP_SUBCLASS(a_Tpr) ((a_Tpr) & XAPIC_TPR_TP_SUBCLASS)
+%define XAPIC_PPR_VALID 0xff
+%define XAPIC_PPR_PP 0xf0
+%define XAPIC_PPR_PP_SUBCLASS 0x0f
+%define XAPIC_PPR_GET_PP(a_Ppr) ((a_Ppr) & XAPIC_PPR_PP)
+%define XAPIC_PPR_GET_PP_SUBCLASS(a_Ppr) ((a_Ppr) & XAPIC_PPR_PP_SUBCLASS)
+%define XAPIC_TIMER_MODE_ONESHOT 0
+%define XAPIC_TIMER_MODE_PERIODIC 1
+%define XAPIC_TIMER_MODE_TSC_DEADLINE 2
+%define XAPIC_LVT_VECTOR 0xff
+%define XAPIC_LVT_GET_VECTOR(a_Lvt) ((a_Lvt) & XAPIC_LVT_VECTOR)
+%define XAPIC_LVT_MASK RT_BIT(16)
+%define XAPIC_LVT_IS_MASKED(a_Lvt) RT_BOOL((a_Lvt) & XAPIC_LVT_MASK)
+%define XAPIC_LVT_TIMER_MODE RT_BIT(17)
+%define XAPIC_LVT_TIMER_TSCDEADLINE RT_BIT(18)
+%define XAPIC_LVT_GET_TIMER_MODE(a_Lvt) (XAPICTIMERMODE)(((a_Lvt) >> 17) & 3)
+%define XAPIC_LVT_DELIVERY_MODE (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
+%define XAPIC_LVT_GET_DELIVERY_MODE(a_Lvt) (XAPICDELIVERYMODE)(((a_Lvt) >> 8) & 7)
+%define XAPIC_LVT_DELIVERY_STATUS RT_BIT(12)
+%define XAPIC_LVT_TRIGGER_MODE RT_BIT(15)
+%define XAPIC_LVT_GET_TRIGGER_MODE(a_Lvt) (XAPICTRIGGERMODE)(((a_Lvt) >> 15) & 1)
+%define XAPIC_LVT_REMOTE_IRR RT_BIT(14)
+%define XAPIC_LVT_GET_REMOTE_IRR(a_Lvt) (((a_Lvt) >> 14) & 1)
+%define XAPIC_LVT_POLARITY RT_BIT(13)
+%define XAPIC_LVT_GET_POLARITY(a_Lvt) (((a_Lvt) >> 13) & 1)
+%define XAPIC_LVT_COMMON_VALID (XAPIC_LVT_VECTOR | XAPIC_LVT_DELIVERY_STATUS | XAPIC_LVT_MASK)
+%define XAPIC_LVT_CMCI_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)
+%define XAPIC_LVT_TIMER_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_TIMER_MODE | XAPIC_LVT_TIMER_TSCDEADLINE)
+%define XAPIC_LVT_THERMAL_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)
+%define XAPIC_LVT_PERF_VALID (XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE)
+%define XAPIC_LVT_LINT_VALID ( XAPIC_LVT_COMMON_VALID | XAPIC_LVT_DELIVERY_MODE | XAPIC_LVT_DELIVERY_STATUS \
+ | XAPIC_LVT_POLARITY | XAPIC_LVT_REMOTE_IRR | XAPIC_LVT_TRIGGER_MODE)
+%define XAPIC_LVT_ERROR_VALID (XAPIC_LVT_COMMON_VALID)
+%define XAPIC_SVR_VECTOR 0xff
+%define XAPIC_SVR_SOFTWARE_ENABLE RT_BIT(8)
+%define XAPIC_SVR_SUPRESS_EOI_BROADCAST RT_BIT(12)
+ %define XAPIC_SVR_VALID_P4 (XAPIC_SVR_VECTOR | XAPIC_SVR_SOFTWARE_ENABLE)
+%define XAPIC_DFR_VALID 0xf0000000
+%define XAPIC_DFR_RSVD_MB1 0x0fffffff
+%define XAPIC_DFR_MODEL 0xf
+%define XAPIC_DFR_GET_MODEL(a_uReg) (((a_uReg) >> 28) & XAPIC_DFR_MODEL)
+%define XAPIC_LDR_VALID 0xff000000
+%define X2APIC_LDR_CLUSTER_ID 0xffff0000
+%define X2APIC_LDR_GET_CLUSTER_ID(a_uReg) ((a_uReg) & X2APIC_LDR_CLUSTER_ID)
+%define X2APIC_LDR_LOGICAL_ID 0x0000ffff
+%define XAPIC_LDR_FLAT_LOGICAL_ID 0xff
+%define XAPIC_LDR_CLUSTERED_CLUSTER_ID 0xf0
+%define XAPIC_LDR_CLUSTERED_LOGICAL_ID 0x0f
+%define XAPIC_LDR_CLUSTERED_GET_CLUSTER_ID(a_uReg) ((a_uReg) & XAPIC_LDR_CLUSTERED_CLUSTER_ID)
+%define XAPIC_EOI_WO_VALID 0x0
+%define XAPIC_TIMER_ICR_VALID 0xffffffff
+%define XAPIC_TIMER_DCR_VALID (RT_BIT(0) | RT_BIT(1) | RT_BIT(3))
+%define XAPIC_SELF_IPI_VALID 0xff
+%define XAPIC_SELF_IPI_VECTOR 0xff
+%define XAPIC_SELF_IPI_GET_VECTOR(a_uReg) ((a_uReg) & XAPIC_SELF_IPI_VECTOR)
+%define XAPIC_ICR_LO_VECTOR 0xff
+%define XAPIC_ICR_LO_GET_VECTOR(a_uIcr) ((a_uIcr) & XAPIC_ICR_LO_VECTOR)
+%define XAPIC_ICR_LO_DELIVERY_MODE (RT_BIT(8) | RT_BIT(9) | RT_BIT(10))
+%define XAPIC_ICR_LO_DEST_MODE RT_BIT(11)
+%define XAPIC_ICR_LO_DELIVERY_STATUS RT_BIT(12)
+%define XAPIC_ICR_LO_LEVEL RT_BIT(14)
+%define XAPIC_ICR_TRIGGER_MODE RT_BIT(15)
+%define XAPIC_ICR_LO_DEST_SHORTHAND (RT_BIT(18) | RT_BIT(19))
+%define XAPIC_ICR_LO_WR_VALID ( XAPIC_ICR_LO_VECTOR | XAPIC_ICR_LO_DELIVERY_MODE | XAPIC_ICR_LO_DEST_MODE \
+ | XAPIC_ICR_LO_LEVEL | XAPIC_ICR_TRIGGER_MODE | XAPIC_ICR_LO_DEST_SHORTHAND)
+%define XAPIC_ICR_HI_DEST 0xff000000
+%define XAPIC_ICR_HI_GET_DEST(a_u32IcrHi) (((a_u32IcrHi) >> 24) & XAPIC_ICR_HI_DEST)
+%define XAPIC_ICR_HI_WR_VALID XAPIC_ICR_HI_DEST
+%define X2APIC_ID_BROADCAST_MASK 0xffffffff
+ %define XAPIC_ID_BROADCAST_MASK_P4 0xff
+%define X2APIC_GET_XAPIC_OFF(a_uMsr) ((((a_uMsr) - MSR_IA32_X2APIC_START) << 4) & 0xff0)
+%define XAPIC_GET_X2APIC_MSR(a_offReg) ((((a_offReg) & 0xff0) >> 4) | MSR_IA32_X2APIC_START)
+%define XAPIC_OFF_ID 0x020
+%define XAPIC_OFF_VERSION 0x030
+%define XAPIC_OFF_TPR 0x080
+%define XAPIC_OFF_APR 0x090
+%define XAPIC_OFF_PPR 0x0A0
+%define XAPIC_OFF_EOI 0x0B0
+%define XAPIC_OFF_RRD 0x0C0
+%define XAPIC_OFF_LDR 0x0D0
+%define XAPIC_OFF_DFR 0x0E0
+%define XAPIC_OFF_SVR 0x0F0
+%define XAPIC_OFF_ISR0 0x100
+%define XAPIC_OFF_ISR1 0x110
+%define XAPIC_OFF_ISR2 0x120
+%define XAPIC_OFF_ISR3 0x130
+%define XAPIC_OFF_ISR4 0x140
+%define XAPIC_OFF_ISR5 0x150
+%define XAPIC_OFF_ISR6 0x160
+%define XAPIC_OFF_ISR7 0x170
+%define XAPIC_OFF_TMR0 0x180
+%define XAPIC_OFF_TMR1 0x190
+%define XAPIC_OFF_TMR2 0x1A0
+%define XAPIC_OFF_TMR3 0x1B0
+%define XAPIC_OFF_TMR4 0x1C0
+%define XAPIC_OFF_TMR5 0x1D0
+%define XAPIC_OFF_TMR6 0x1E0
+%define XAPIC_OFF_TMR7 0x1F0
+%define XAPIC_OFF_IRR0 0x200
+%define XAPIC_OFF_IRR1 0x210
+%define XAPIC_OFF_IRR2 0x220
+%define XAPIC_OFF_IRR3 0x230
+%define XAPIC_OFF_IRR4 0x240
+%define XAPIC_OFF_IRR5 0x250
+%define XAPIC_OFF_IRR6 0x260
+%define XAPIC_OFF_IRR7 0x270
+%define XAPIC_OFF_ESR 0x280
+%define XAPIC_OFF_LVT_CMCI 0x2F0
+%define XAPIC_OFF_ICR_LO 0x300
+%define XAPIC_OFF_ICR_HI 0x310
+%define XAPIC_OFF_LVT_TIMER 0x320
+%define XAPIC_OFF_LVT_THERMAL 0x330
+%define XAPIC_OFF_LVT_PERF 0x340
+%define XAPIC_OFF_LVT_LINT0 0x350
+%define XAPIC_OFF_LVT_LINT1 0x360
+%define XAPIC_OFF_LVT_ERROR 0x370
+%define XAPIC_OFF_TIMER_ICR 0x380
+%define XAPIC_OFF_TIMER_CCR 0x390
+%define XAPIC_OFF_TIMER_DCR 0x3E0
+%define X2APIC_OFF_SELF_IPI 0x3F0
+%define XAPIC_OFF_LVT_START XAPIC_OFF_LVT_TIMER
+%define XAPIC_OFF_LVT_END XAPIC_OFF_LVT_ERROR
+%define XAPIC_OFF_LVT_EXT_START XAPIC_OFF_LVT_CMCI
+%define XAPIC_OFF_LVT_EXT_END XAPIC_OFF_LVT_CMCI
+%define XAPIC_OFF_END 0x3F0
+%ifdef IPRT_INCLUDED_asm_amd64_x86_h
+%endif
+%endif