diff options
Diffstat (limited to 'src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include')
16 files changed, 1684 insertions, 0 deletions
diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/FspEas.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/FspEas.h new file mode 100644 index 00000000..d9268290 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/FspEas.h @@ -0,0 +1,18 @@ +/** @file + Intel FSP definition from Intel Firmware Support Package External + Architecture Specification v2.0. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_EAS_H_ +#define _FSP_EAS_H_ + +#include <Uefi/UefiBaseType.h> +#include <Guid/GuidHobFspEas.h> +#include <Guid/FspHeaderFile.h> +#include <FspEas/FspApi.h> + +#endif diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/FspEas/FspApi.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/FspEas/FspApi.h new file mode 100644 index 00000000..eb9ce861 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -0,0 +1,485 @@ +/** @file + Intel FSP API definition from Intel Firmware Support Package External + Architecture Specification v2.0 - v2.2 + + Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_API_H_ +#define _FSP_API_H_ + +#include <Pi/PiStatusCode.h> + +/// +/// FSP Reset Status code +/// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code +/// @{ +#define FSP_STATUS_RESET_REQUIRED_COLD 0x40000001 +#define FSP_STATUS_RESET_REQUIRED_WARM 0x40000002 +#define FSP_STATUS_RESET_REQUIRED_3 0x40000003 +#define FSP_STATUS_RESET_REQUIRED_4 0x40000004 +#define FSP_STATUS_RESET_REQUIRED_5 0x40000005 +#define FSP_STATUS_RESET_REQUIRED_6 0x40000006 +#define FSP_STATUS_RESET_REQUIRED_7 0x40000007 +#define FSP_STATUS_RESET_REQUIRED_8 0x40000008 +/// @} + +/// +/// FSP Event related definition. +/// +#define FSP_EVENT_CODE 0xF5000000 +#define FSP_POST_CODE (FSP_EVENT_CODE | 0x00F80000) + +/* + FSP may optionally include the capability of generating events messages to aid in the debugging of firmware issues. + These events fall under three catagories: Error, Progress, and Debug. The event reporting mechanism follows the + status code services described in section 6 and 7 of the PI Specification v1.7 Volume 3. + + @param[in] Type Indicates the type of event being reported. + See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_TYPE. + @param[in] Value Describes the current status of a hardware or software entity. + This includes information about the class and subclass that is used to classify the entity as well as an operation. + For progress events, the operation is the current activity. For error events, it is the exception. + For debug events, it is not defined at this time. + See MdePkg/Include/Pi/PiStatusCode.h for the definition of EFI_STATUS_CODE_VALUE. + @param[in] Instance The enumeration of a hardware or software entity within the system. + A system may contain multiple entities that match a class/subclass pairing. The instance differentiates between them. + An instance of 0 indicates that instance information is unavailable, not meaningful, or not relevant. + Valid instance numbers start with 1. + @param[in] *CallerId This parameter can be used to identify the sub-module within the FSP generating the event. + This parameter may be NULL. + @param[in] *Data This optional parameter may be used to pass additional data. The contents can have event-specific data. + For example, the FSP provides a EFI_STATUS_CODE_STRING_DATA instance to this parameter when sending debug messages. + This parameter is NULL when no additional data is provided. + + @retval EFI_SUCCESS The event was handled successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_DEVICE_ERROR The event handler failed. +*/ +typedef +EFI_STATUS +(EFIAPI *FSP_EVENT_HANDLER) ( + IN EFI_STATUS_CODE_TYPE Type, + IN EFI_STATUS_CODE_VALUE Value, + IN UINT32 Instance, + IN OPTIONAL EFI_GUID *CallerId, + IN OPTIONAL EFI_STATUS_CODE_DATA *Data + ); + +/* + Handler for FSP-T debug log messages, provided by the bootloader. + + @param[in] DebugMessage A pointer to the debug message to be written to the log. + @param[in] MessageLength Number of bytes to written to the debug log. + + @retval UINT32 The return value indicates the number of bytes actually written to + the debug log. If the return value is less than MessageLength, + an error occurred. +*/ +typedef +UINT32 +(EFIAPI *FSP_DEBUG_HANDLER) ( + IN CHAR8* DebugMessage, + IN UINT32 MessageLength + ); + +#pragma pack(1) +/// +/// FSP_UPD_HEADER Configuration. +/// +typedef struct { + /// + /// UPD Region Signature. This signature will be + /// "XXXXXX_T" for FSP-T + /// "XXXXXX_M" for FSP-M + /// "XXXXXX_S" for FSP-S + /// Where XXXXXX is an unique signature + /// + UINT64 Signature; + /// + /// Revision of the Data structure. + /// For FSP spec 2.0/2.1 value is 1. + /// For FSP spec 2.2 value is 2. + /// + UINT8 Revision; + UINT8 Reserved[23]; +} FSP_UPD_HEADER; + +/// +/// FSPT_ARCH_UPD Configuration. +/// +typedef struct { + /// + /// Revision Revision of the structure is 1 for this version of the specification. + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Length Length of the structure in bytes. The current value for this field is 32. + /// + UINT32 Length; + /// + /// FspDebugHandler Optional debug handler for the bootloader to receive debug messages + /// occurring during FSP execution. + /// + FSP_DEBUG_HANDLER FspDebugHandler; + UINT8 Reserved1[20]; +} FSPT_ARCH_UPD; + +/// +/// FSPM_ARCH_UPD Configuration. +/// +typedef struct { + /// + /// Revision of the structure. For FSP v2.0 value is 1. + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Pointer to the non-volatile storage (NVS) data buffer. + /// If it is NULL it indicates the NVS data is not available. + /// + VOID *NvsBufferPtr; + /// + /// Pointer to the temporary stack base address to be + /// consumed inside FspMemoryInit() API. + /// + VOID *StackBase; + /// + /// Temporary stack size to be consumed inside + /// FspMemoryInit() API. + /// + UINT32 StackSize; + /// + /// Size of memory to be reserved by FSP below "top + /// of low usable memory" for bootloader usage. + /// + UINT32 BootLoaderTolumSize; + /// + /// Current boot mode. + /// + UINT32 BootMode; + /// + /// Optional event handler for the bootloader to be informed of events occurring during FSP execution. + /// This value is only valid if Revision is >= 2. + /// + FSP_EVENT_HANDLER *FspEventHandler; + UINT8 Reserved1[4]; +} FSPM_ARCH_UPD; + +typedef struct { + /// + /// Revision Revision of the structure is 1 for this version of the specification. + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Length Length of the structure in bytes. The current value for this field is 32. + /// + UINT32 Length; + /// + /// FspEventHandler Optional event handler for the bootloader to be informed of events + /// occurring during FSP execution. + /// + FSP_EVENT_HANDLER FspEventHandler; + /// + /// A FSP binary may optionally implement multi-phase silicon initialization, + /// This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER + /// is non-zero. + /// To enable multi-phase silicon initialization, the bootloader must set + /// EnableMultiPhaseSiliconInit to a non-zero value. + /// + UINT8 EnableMultiPhaseSiliconInit; + UINT8 Reserved1[19]; +} FSPS_ARCH_UPD; + +/// +/// FSPT_UPD_COMMON Configuration. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; +} FSPT_UPD_COMMON; + +/// +/// FSPT_UPD_COMMON Configuration for FSP spec. 2.2 and above. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; + + /// + /// FSPT_ARCH_UPD Configuration. + /// + FSPT_ARCH_UPD FsptArchUpd; +} FSPT_UPD_COMMON_FSP22; + +/// +/// FSPM_UPD_COMMON Configuration. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; + /// + /// FSPM_ARCH_UPD Configuration. + /// + FSPM_ARCH_UPD FspmArchUpd; +} FSPM_UPD_COMMON; + +/// +/// FSPS_UPD_COMMON Configuration. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; +} FSPS_UPD_COMMON; + +/// +/// FSPS_UPD_COMMON Configuration for FSP spec. 2.2 and above. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; + + /// + /// FSPS_ARCH_UPD Configuration. + /// + FSPS_ARCH_UPD FspsArchUpd; +} FSPS_UPD_COMMON_FSP22; + +/// +/// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE. +/// +typedef enum { + /// + /// This stage is notified when the bootloader completes the + /// PCI enumeration and the resource allocation for the + /// PCI devices is complete. + /// + EnumInitPhaseAfterPciEnumeration = 0x20, + /// + /// This stage is notified just before the bootloader hand-off + /// to the OS loader. + /// + EnumInitPhaseReadyToBoot = 0x40, + /// + /// This stage is notified just before the firmware/Preboot + /// environment transfers management of all system resources + /// to the OS or next level execution environment. + /// + EnumInitPhaseEndOfFirmware = 0xF0 +} FSP_INIT_PHASE; + +/// +/// Definition of NOTIFY_PHASE_PARAMS. +/// +typedef struct { + /// + /// Notification phase used for NotifyPhase API + /// + FSP_INIT_PHASE Phase; +} NOTIFY_PHASE_PARAMS; + +/// +/// Action definition for FspMultiPhaseSiInit API +/// +typedef enum { + EnumMultiPhaseGetNumberOfPhases = 0x0, + EnumMultiPhaseExecutePhase = 0x1 +} FSP_MULTI_PHASE_ACTION; + +/// +/// Data structure returned by FSP when bootloader calling +/// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases) +/// +typedef struct { + UINT32 NumberOfPhases; + UINT32 PhasesExecuted; +} FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS; + +/// +/// FspMultiPhaseSiInit function parameter. +/// +/// For action 0 (EnumMultiPhaseGetNumberOfPhases): +/// - PhaseIndex must be 0. +/// - MultiPhaseParamPtr should point to an instance of FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS. +/// +/// For action 1 (EnumMultiPhaseExecutePhase): +/// - PhaseIndex will be the phase that will be executed by FSP. +/// - MultiPhaseParamPtr shall be NULL. +/// +typedef struct { + IN FSP_MULTI_PHASE_ACTION MultiPhaseAction; + IN UINT32 PhaseIndex; + IN OUT VOID *MultiPhaseParamPtr; +} FSP_MULTI_PHASE_PARAMS; + +#pragma pack() + +/** + This FSP API is called soon after coming out of reset and before memory and stack is + available. This FSP API will load the microcode update, enable code caching for the + region specified by the boot loader and also setup a temporary stack to be used until + main memory is initialized. + + A hardcoded stack can be set up with the following values, and the "esp" register + initialized to point to this hardcoded stack. + 1. The return address where the FSP will return control after setting up a temporary + stack. + 2. A pointer to the input parameter structure + + However, since the stack is in ROM and not writeable, this FSP API cannot be called + using the "call" instruction, but needs to be jumped to. + + @param[in] FsptUpdDataPtr Pointer to the FSPT_UPD data structure. + + @retval EFI_SUCCESS Temporary RAM was initialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR Temp RAM initialization failed. + + If this function is successful, the FSP initializes the ECX and EDX registers to point to + a temporary but writeable memory range available to the boot loader and returns with + FSP_SUCCESS in register EAX. Register ECX points to the start of this temporary + memory range and EDX points to the end of the range. Boot loader is free to use the + whole range described. Typically the boot loader can reload the ESP register to point + to the end of this returned range so that it can be used as a standard stack. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_TEMP_RAM_INIT) ( + IN VOID *FsptUpdDataPtr + ); + +/** + This FSP API is used to notify the FSP about the different phases in the boot process. + This allows the FSP to take appropriate actions as needed during different initialization + phases. The phases will be platform dependent and will be documented with the FSP + release. The current FSP supports two notify phases: + Post PCI enumeration + Ready To Boot + + @param[in] NotifyPhaseParamPtr Address pointer to the NOTIFY_PHASE_PRAMS + + @retval EFI_SUCCESS The notification was handled successfully. + @retval EFI_UNSUPPORTED The notification was not called in the proper order. + @retval EFI_INVALID_PARAMETER The notification code is invalid. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_NOTIFY_PHASE) ( + IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr + ); + +/** + This FSP API is called after TempRamInit and initializes the memory. + This FSP API accepts a pointer to a data structure that will be platform dependent + and defined for each FSP binary. This will be documented in Integration guide with + each FSP release. + After FspMemInit completes its execution, it passes the pointer to the HobList and + returns to the boot loader from where it was called. BootLoader is responsible to + migrate its stack and data to Memory. + FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to + complete the silicon initialization and provides bootloader an opportunity to get + control after system memory is available and before the temporary RAM is torn down. + + @param[in] FspmUpdDataPtr Pointer to the FSPM_UPD data structure. + @param[out] HobListPtr Pointer to receive the address of the HOB list. + + @retval EFI_SUCCESS FSP execution environment was initialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR FSP initialization failed. + @retval EFI_OUT_OF_RESOURCES Stack range requested by FSP is not met. + @retval FSP_STATUS_RESET_REQUIREDx A reset is reuired. These status codes will not be returned during S3. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_MEMORY_INIT) ( + IN VOID *FspmUpdDataPtr, + OUT VOID **HobListPtr + ); + + +/** + This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary + memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure + that will be platform dependent and defined for each FSP binary. This will be + documented in Integration Guide. + FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to + complete the silicon initialization and provides bootloader an opportunity to get + control after system memory is available and before the temporary RAM is torn down. + + @param[in] TempRamExitParamPtr Pointer to the Temp Ram Exit parameters structure. + This structure is normally defined in the Integration Guide. + And if it is not defined in the Integration Guide, pass NULL. + + @retval EFI_SUCCESS FSP execution environment was initialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR FSP initialization failed. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_TEMP_RAM_EXIT) ( + IN VOID *TempRamExitParamPtr + ); + + +/** + This FSP API is called after TempRamExit API. + FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the + silicon initialization. + + @param[in] FspsUpdDataPtr Pointer to the FSPS_UPD data structure. + If NULL, FSP will use the default parameters. + + @retval EFI_SUCCESS FSP execution environment was initialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR FSP initialization failed. + @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_SILICON_INIT) ( + IN VOID *FspsUpdDataPtr + ); + +/** + This FSP API is expected to be called after FspSiliconInit but before FspNotifyPhase. + This FSP API provides multi-phase silicon initialization; which brings greater modularity + beyond the existing FspSiliconInit() API. Increased modularity is achieved by adding an + extra API to FSP-S. This allows the bootloader to add board specific initialization steps + throughout the SiliconInit flow as needed. + + @param[in,out] FSP_MULTI_PHASE_PARAMS For action - EnumMultiPhaseGetNumberOfPhases: + FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr will contain + how many phases supported by FSP. + For action - EnumMultiPhaseExecutePhase: + FSP_MULTI_PHASE_PARAMS->MultiPhaseParamPtr shall be NULL. + @retval EFI_SUCCESS FSP execution environment was initialized successfully. + @retval EFI_INVALID_PARAMETER Input parameters are invalid. + @retval EFI_UNSUPPORTED The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR FSP initialization failed. + @retval FSP_STATUS_RESET_REQUIREDx A reset is required. These status codes will not be returned during S3. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_MULTI_PHASE_SI_INIT) ( + IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr +); + +#endif diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/FspGlobalData.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/FspGlobalData.h new file mode 100644 index 00000000..2ff4c0ea --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/FspGlobalData.h @@ -0,0 +1,78 @@ +/** @file + + Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_GLOBAL_DATA_H_ +#define _FSP_GLOBAL_DATA_H_ + +#include <FspEas.h> + +#define FSP_IN_API_MODE 0 +#define FSP_IN_DISPATCH_MODE 1 + +#pragma pack(1) + +typedef enum { + TempRamInitApiIndex, + FspInitApiIndex, + NotifyPhaseApiIndex, + FspMemoryInitApiIndex, + TempRamExitApiIndex, + FspSiliconInitApiIndex, + FspMultiPhaseSiInitApiIndex, + FspApiIndexMax +} FSP_API_INDEX; + +typedef struct { + VOID *DataPtr; + UINT32 MicrocodeRegionBase; + UINT32 MicrocodeRegionSize; + UINT32 CodeRegionBase; + UINT32 CodeRegionSize; +} FSP_PLAT_DATA; + +#define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D') +#define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F') +#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF + +typedef struct { + UINT32 Signature; + UINT8 Version; + UINT8 Reserved1[3]; + UINT32 CoreStack; + UINT32 StatusCode; + UINT32 Reserved2[8]; + FSP_PLAT_DATA PlatformData; + FSP_INFO_HEADER *FspInfoHeader; + VOID *UpdDataPtr; + VOID *TempRamInitUpdPtr; + VOID *MemoryInitUpdPtr; + VOID *SiliconInitUpdPtr; + UINT8 ApiIdx; + /// + /// 0: FSP in API mode; 1: FSP in DISPATCH mode + /// + UINT8 FspMode; + UINT8 OnSeparateStack; + UINT8 Reserved3; + UINT32 NumberOfPhases; + UINT32 PhasesExecuted; + /// + /// To store function parameters pointer + /// so it can be retrieved after stack switched. + /// + VOID *FunctionParameterPtr; + UINT8 Reserved4[16]; + UINT32 PerfSig; + UINT16 PerfLen; + UINT16 Reserved5; + UINT32 PerfIdx; + UINT64 PerfData[32]; +} FSP_GLOBAL_DATA; + +#pragma pack() + +#endif diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/FspMeasurePointId.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/FspMeasurePointId.h new file mode 100644 index 00000000..2092543f --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/FspMeasurePointId.h @@ -0,0 +1,56 @@ +/** @file + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_MEASURE_POINT_ID_H_ +#define _FSP_MEASURE_POINT_ID_H_ + +// +// 0xD0 - 0xEF are reserved for FSP common measure point +// +#define FSP_PERF_ID_MRC_INIT_ENTRY 0xD0 +#define FSP_PERF_ID_MRC_INIT_EXIT (FSP_PERF_ID_MRC_INIT_ENTRY + 1) + +#define FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY 0xD8 +#define FSP_PERF_ID_SYSTEM_AGENT_INIT_EXIT (FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY + 1) + +#define FSP_PERF_ID_PCH_INIT_ENTRY 0xDA +#define FSP_PERF_ID_PCH_INIT_EXIT (FSP_PERF_ID_PCH_INIT_ENTRY + 1) + +#define FSP_PERF_ID_CPU_INIT_ENTRY 0xE0 +#define FSP_PERF_ID_CPU_INIT_EXIT (FSP_PERF_ID_CPU_INIT_ENTRY + 1) + +#define FSP_PERF_ID_GFX_INIT_ENTRY 0xE8 +#define FSP_PERF_ID_GFX_INIT_EXIT (FSP_PERF_ID_GFX_INIT_ENTRY + 1) + +#define FSP_PERF_ID_ME_INIT_ENTRY 0xEA +#define FSP_PERF_ID_ME_INIT_EXIT (FSP_PERF_ID_ME_INIT_ENTRY + 1) + +// +// 0xF0 - 0xFF are reserved for FSP API +// +#define FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY 0xF0 +#define FSP_PERF_ID_API_TEMP_RAM_INIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY + 1) + +#define FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY 0xF2 +#define FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY + 1) + +#define FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY 0xF4 +#define FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY + 1) + +#define FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY 0xF6 +#define FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY + 1) + +#define FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY 0xF8 +#define FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + 1) + +#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY 0xFA +#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_EXIT (FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY + 1) + +#define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY 0xFC +#define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_EXIT (FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY + 1) + +#endif diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/FspStatusCode.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/FspStatusCode.h new file mode 100644 index 00000000..1c0954c5 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/FspStatusCode.h @@ -0,0 +1,40 @@ +/** @file + Intel FSP status code definition + + Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_STATUS_CODE_H_ +#define _FSP_STATUS_CODE_H_ + +// +// FSP API - 4 BITS +// +#define FSP_STATUS_CODE_TEMP_RAM_INIT 0xF000 +#define FSP_STATUS_CODE_MEMORY_INIT 0xD000 +#define FSP_STATUS_CODE_TEMP_RAM_EXIT 0xB000 +#define FSP_STATUS_CODE_SILICON_INIT 0x9000 +#define FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION 0x6000 +#define FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION 0x4000 +#define FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION 0x2000 + +// +// MODULE - 4 BITS +// +#define FSP_STATUS_CODE_GFX_PEIM 0x0700 +#define FSP_STATUS_CODE_COMMON_CODE 0x0800 +#define FSP_STATUS_CODE_SILICON_COMMON_CODE 0x0900 +#define FSP_STATUS_CODE_SYSTEM_AGENT 0x0A00 +#define FSP_STATUS_CODE_PCH 0x0B00 +#define FSP_STATUS_CODE_CPU 0x0C00 +#define FSP_STATUS_CODE_MRC 0x0D00 +#define FSP_STATUS_CODE_ME_BIOS 0x0E00 +// +// Individual Codes - 1 BYTE +// +#define FSP_STATUS_CODE_API_ENTRY 0x0000 +#define FSP_STATUS_CODE_API_EXIT 0x007F + +#endif diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h new file mode 100644 index 00000000..24e20125 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Guid/FspHeaderFile.h @@ -0,0 +1,204 @@ +/** @file + Intel FSP Header File definition from Intel Firmware Support Package External + Architecture Specification v2.0 and above. + + Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __FSP_HEADER_FILE_H__ +#define __FSP_HEADER_FILE_H__ + +#define FSP_HEADER_REVISION_3 3 + +#define FSPE_HEADER_REVISION_1 1 +#define FSPP_HEADER_REVISION_1 1 + +/// +/// Fixed FSP header offset in the FSP image +/// +#define FSP_INFO_HEADER_OFF 0x94 + +#define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x + +#define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H') + +#pragma pack(1) + +/// +/// FSP Information Header as described in FSP v2.0 Spec section 5.1.1. +/// +typedef struct { + /// + /// Byte 0x00: Signature ('FSPH') for the FSP Information Header. + /// + UINT32 Signature; + /// + /// Byte 0x04: Length of the FSP Information Header. + /// + UINT32 HeaderLength; + /// + /// Byte 0x08: Reserved. + /// + UINT8 Reserved1[2]; + /// + /// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format. + /// + UINT8 SpecVersion; + /// + /// Byte 0x0B: Revision of the FSP Information Header. + /// + UINT8 HeaderRevision; + /// + /// Byte 0x0C: Revision of the FSP binary. + /// + UINT32 ImageRevision; + /// + /// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration. + /// + CHAR8 ImageId[8]; + /// + /// Byte 0x18: Size of the entire FSP binary. + /// + UINT32 ImageSize; + /// + /// Byte 0x1C: FSP binary preferred base address. + /// + UINT32 ImageBase; + /// + /// Byte 0x20: Attribute for the FSP binary. + /// + UINT16 ImageAttribute; + /// + /// Byte 0x22: Attributes of the FSP Component. + /// + UINT16 ComponentAttribute; + /// + /// Byte 0x24: Offset of the FSP configuration region. + /// + UINT32 CfgRegionOffset; + /// + /// Byte 0x28: Size of the FSP configuration region. + /// + UINT32 CfgRegionSize; + /// + /// Byte 0x2C: Reserved2. + /// + UINT32 Reserved2; + /// + /// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized. + /// + UINT32 TempRamInitEntryOffset; + /// + /// Byte 0x34: Reserved3. + /// + UINT32 Reserved3; + /// + /// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process. + /// + UINT32 NotifyPhaseEntryOffset; + /// + /// Byte 0x3C: The offset for the API to initialize the memory. + /// + UINT32 FspMemoryInitEntryOffset; + /// + /// Byte 0x40: The offset for the API to tear down temporary RAM. + /// + UINT32 TempRamExitEntryOffset; + /// + /// Byte 0x44: The offset for the API to initialize the CPU and chipset. + /// + UINT32 FspSiliconInitEntryOffset; + /// + /// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization. + /// This value is only valid if FSP HeaderRevision is >= 5. + /// If the value is set to 0x00000000, then this API is not available in this component. + /// + UINT32 FspMultiPhaseSiInitEntryOffset; +} FSP_INFO_HEADER; + +/// +/// Signature of the FSP Extended Header +/// +#define FSP_INFO_EXTENDED_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'E') + +/// +/// FSP Information Extended Header as described in FSP v2.0 Spec section 5.1.2. +/// +typedef struct { + /// + /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header. + /// + UINT32 Signature; + /// + /// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data. + /// + UINT32 Length; + /// + /// Byte 0x08: FSP producer defined revision of the table. + /// + UINT8 Revision; + /// + /// Byte 0x09: Reserved for future use. + /// + UINT8 Reserved; + /// + /// Byte 0x0A: FSP producer identification string + /// + CHAR8 FspProducerId[6]; + /// + /// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions. + /// + UINT32 FspProducerRevision; + /// + /// Byte 0x14: Size of the FSP producer defined data (n) in bytes. + /// + UINT32 FspProducerDataSize; + /// + /// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize. + /// +} FSP_INFO_EXTENDED_HEADER; + +// +// A generic table search algorithm for additional tables can be implemented with a +// signature search algorithm until a terminator signature 'FSPP' is found. +// +#define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P') +#define FSP_PATCH_TABLE_SIGNATURE FSP_FSPP_SIGNATURE + +/// +/// FSP Patch Table as described in FSP v2.0 Spec section 5.1.5. +/// +typedef struct { + /// + /// Byte 0x00: FSP Patch Table Signature "FSPP". + /// + UINT32 Signature; + /// + /// Byte 0x04: Size including the PatchData. + /// + UINT16 HeaderLength; + /// + /// Byte 0x06: Revision is set to 0x01. + /// + UINT8 HeaderRevision; + /// + /// Byte 0x07: Reserved for future use. + /// + UINT8 Reserved; + /// + /// Byte 0x08: Number of entries to Patch. + /// + UINT32 PatchEntryNum; + /// + /// Byte 0x0C: Patch Data. + /// +//UINT32 PatchData[]; +} FSP_PATCH_TABLE; + +#pragma pack() + +extern EFI_GUID gFspHeaderFileGuid; + +#endif diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h new file mode 100644 index 00000000..631eef36 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Guid/GuidHobFspEas.h @@ -0,0 +1,17 @@ +/** @file + Intel FSP Hob Guid definition from Intel Firmware Support Package External + Architecture Specification v2.0. + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __GUID_HOB_FSP_EAS_GUID__ +#define __GUID_HOB_FSP_EAS_GUID__ + +extern EFI_GUID gFspBootLoaderTolumHobGuid; +extern EFI_GUID gFspReservedMemoryResourceHobGuid; +extern EFI_GUID gFspNonVolatileStorageHobGuid; + +#endif diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h new file mode 100644 index 00000000..c2a4e678 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/CacheAsRamLib.h @@ -0,0 +1,24 @@ +/** @file + + Copyright (c) 2014, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CACHE_AS_RAM_LIB_H_ +#define _CACHE_AS_RAM_LIB_H_ + +/** + This function disable CAR. + + @param[in] DisableCar TRUE means use INVD, FALSE means use WBINVD + +**/ +VOID +EFIAPI +DisableCacheAsRam ( + IN BOOLEAN DisableCar + ); + +#endif + diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/CacheLib.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/CacheLib.h new file mode 100644 index 00000000..7548b7e1 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/CacheLib.h @@ -0,0 +1,56 @@ +/** @file + + Copyright (c) 2014, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _CACHE_LIB_H_ +#define _CACHE_LIB_H_ + +// +// EFI_MEMORY_CACHE_TYPE +// +typedef INT32 EFI_MEMORY_CACHE_TYPE; + +#define EFI_CACHE_UNCACHEABLE 0 +#define EFI_CACHE_WRITECOMBINING 1 +#define EFI_CACHE_WRITETHROUGH 4 +#define EFI_CACHE_WRITEPROTECTED 5 +#define EFI_CACHE_WRITEBACK 6 + +/** + Reset all the MTRRs to a known state. + + @retval EFI_SUCCESS All MTRRs have been reset successfully. + +**/ +EFI_STATUS +EFIAPI +ResetCacheAttributes ( + VOID + ); + +/** + Given the memory range and cache type, programs the MTRRs. + + @param[in] MemoryAddress Base Address of Memory to program MTRR. + @param[in] MemoryLength Length of Memory to program MTRR. + @param[in] MemoryCacheType Cache Type. + + @retval EFI_SUCCESS Mtrr are set successfully. + @retval EFI_LOAD_ERROR No empty MTRRs to use. + @retval EFI_INVALID_PARAMETER The input parameter is not valid. + @retval others An error occurs when setting MTTR. + +**/ +EFI_STATUS +EFIAPI +SetCacheAttributes ( + IN EFI_PHYSICAL_ADDRESS MemoryAddress, + IN UINT64 MemoryLength, + IN EFI_MEMORY_CACHE_TYPE MemoryCacheType + ); + +#endif + diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/DebugDeviceLib.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/DebugDeviceLib.h new file mode 100644 index 00000000..f8611909 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/DebugDeviceLib.h @@ -0,0 +1,23 @@ +/** @file + + Copyright (c) 2014, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __DEBUG_DEVICE_LIB_H__ +#define __DEBUG_DEVICE_LIB_H__ + +/** + Returns the debug print device enable state. + + @return Debug print device enable state. + +**/ +UINT8 +EFIAPI +GetDebugPrintDeviceEnable ( + VOID + ); + +#endif diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/FspCommonLib.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/FspCommonLib.h new file mode 100644 index 00000000..dfc87ae6 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/FspCommonLib.h @@ -0,0 +1,308 @@ +/** @file + + Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_COMMON_LIB_H_ +#define _FSP_COMMON_LIB_H_ + +#include <FspGlobalData.h> +#include <FspMeasurePointId.h> + +/** + This function sets the FSP global data pointer. + + @param[in] FspData Fsp global data pointer. + +**/ +VOID +EFIAPI +SetFspGlobalDataPointer ( + IN FSP_GLOBAL_DATA *FspData + ); + +/** + This function gets the FSP global data pointer. + +**/ +FSP_GLOBAL_DATA * +EFIAPI +GetFspGlobalDataPointer ( + VOID + ); + +/** + This function gets back the FSP API first parameter passed by the bootloader. + + @retval ApiParameter FSP API first parameter passed by the bootloader. +**/ +UINT32 +EFIAPI +GetFspApiParameter ( + VOID + ); + +/** + This function gets back the FSP API second parameter passed by the bootloader. + + @retval ApiParameter FSP API second parameter passed by the bootloader. +**/ +UINT32 +EFIAPI +GetFspApiParameter2 ( + VOID + ); + +/** + This function returns the FSP entry stack pointer from address of the first API parameter. + + @retval FSP entry stack pointer. +**/ +VOID* +EFIAPI +GetFspEntryStack ( + VOID + ); + +/** + This function sets the FSP API parameter in the stack. + + @param[in] Value New parameter value. + +**/ +VOID +EFIAPI +SetFspApiParameter ( + IN UINT32 Value + ); + +/** + This function set the API status code returned to the BootLoader. + + @param[in] ReturnStatus Status code to return. + +**/ +VOID +EFIAPI +SetFspApiReturnStatus ( + IN UINT32 ReturnStatus + ); + +/** + This function sets the context switching stack to a new stack frame. + + @param[in] NewStackTop New core stack to be set. + +**/ +VOID +EFIAPI +SetFspCoreStackPointer ( + IN VOID *NewStackTop + ); + +/** + This function sets the platform specific data pointer. + + @param[in] PlatformData Fsp platform specific data pointer. + +**/ +VOID +EFIAPI +SetFspPlatformDataPointer ( + IN VOID *PlatformData + ); + +/** + This function gets the platform specific data pointer. + + @param[in] PlatformData Fsp platform specific data pointer. + +**/ +VOID * +EFIAPI +GetFspPlatformDataPointer ( + VOID + ); + +/** + This function sets the UPD data pointer. + + @param[in] UpdDataPtr UPD data pointer. +**/ +VOID +EFIAPI +SetFspUpdDataPointer ( + IN VOID *UpdDataPtr + ); + +/** + This function gets the UPD data pointer. + + @return UpdDataPtr UPD data pointer. +**/ +VOID * +EFIAPI +GetFspUpdDataPointer ( + VOID + ); + +/** + This function sets the memory init UPD data pointer. + + @param[in] MemoryInitUpdPtr memory init UPD data pointer. +**/ +VOID +EFIAPI +SetFspMemoryInitUpdDataPointer ( + IN VOID *MemoryInitUpdPtr + ); + +/** + This function gets the memory init UPD data pointer. + + @return memory init UPD data pointer. +**/ +VOID * +EFIAPI +GetFspMemoryInitUpdDataPointer ( + VOID + ); + +/** + This function sets the silicon init UPD data pointer. + + @param[in] SiliconInitUpdPtr silicon init UPD data pointer. +**/ +VOID +EFIAPI +SetFspSiliconInitUpdDataPointer ( + IN VOID *SiliconInitUpdPtr + ); + +/** + This function gets the silicon init UPD data pointer. + + @return silicon init UPD data pointer. +**/ +VOID * +EFIAPI +GetFspSiliconInitUpdDataPointer ( + VOID + ); + +/** + Set FSP measurement point timestamp. + + @param[in] Id Measurement point ID. + + @return performance timestamp. +**/ +UINT64 +EFIAPI +SetFspMeasurePoint ( + IN UINT8 Id + ); + +/** + This function gets the FSP info header pointer. + + @retval FspInfoHeader FSP info header pointer +**/ +FSP_INFO_HEADER * +EFIAPI +GetFspInfoHeader ( + VOID + ); + +/** + This function sets the FSP info header pointer. + + @param[in] FspInfoHeader FSP info header pointer +**/ +VOID +EFIAPI +SetFspInfoHeader ( + FSP_INFO_HEADER *FspInfoHeader + ); + +/** + This function gets the FSP info header pointer from the API context. + + @retval FspInfoHeader FSP info header pointer +**/ +FSP_INFO_HEADER * +EFIAPI +GetFspInfoHeaderFromApiContext ( + VOID + ); + +/** + This function gets the CfgRegion data pointer. + + @return CfgRegion data pointer. +**/ +VOID * +EFIAPI +GetFspCfgRegionDataPointer ( + VOID + ); + +/** + This function gets FSP API calling mode. + + @retval API calling mode +**/ +UINT8 +EFIAPI +GetFspApiCallingIndex ( + VOID + ); + +/** + This function sets FSP API calling mode. + + @param[in] Index API calling index +**/ +VOID +EFIAPI +SetFspApiCallingIndex ( + UINT8 Index + ); + +/** + This function gets FSP Phase StatusCode. + + @retval StatusCode +**/ +UINT32 +EFIAPI +GetPhaseStatusCode ( + VOID + ); + + +/** + This function sets FSP Phase StatusCode. + + @param[in] Mode Phase StatusCode +**/ +VOID +EFIAPI +SetPhaseStatusCode ( + UINT32 StatusCode + ); + +/** + This function updates the return status of the FSP API with requested reset type and returns to Boot Loader. + + @param[in] FspResetType Reset type that needs to returned as API return status + +**/ +VOID +EFIAPI +FspApiReturnStatusReset ( + IN UINT32 FspResetType + ); +#endif diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/FspPlatformLib.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/FspPlatformLib.h new file mode 100644 index 00000000..680416b4 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/FspPlatformLib.h @@ -0,0 +1,125 @@ +/** @file + + Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_PLATFORM_LIB_H_ +#define _FSP_PLATFORM_LIB_H_ + +/** + Get system memory resource descriptor by owner. + + @param[in] OwnerGuid resource owner guid +**/ +EFI_HOB_RESOURCE_DESCRIPTOR * +EFIAPI +FspGetResourceDescriptorByOwner ( + IN EFI_GUID *OwnerGuid + ); + +/** + Get system memory from HOB. + + @param[in,out] LowMemoryLength less than 4G memory length + @param[in,out] HighMemoryLength greater than 4G memory length +**/ +VOID +EFIAPI +FspGetSystemMemorySize ( + IN OUT UINT64 *LowMemoryLength, + IN OUT UINT64 *HighMemoryLength + ); + + +/** + Set a new stack frame for the continuation function. + +**/ +VOID +EFIAPI +FspSetNewStackFrame ( + VOID + ); + +/** + This function transfer control back to BootLoader after FspSiliconInit. + +**/ +VOID +EFIAPI +FspSiliconInitDone ( + VOID + ); + +/** + This function returns control to BootLoader after MemoryInitApi. + + @param[in,out] HobListPtr The address of HobList pointer. +**/ +VOID +EFIAPI +FspMemoryInitDone ( + IN OUT VOID **HobListPtr + ); + +/** + This function returns control to BootLoader after TempRamExitApi. + +**/ +VOID +EFIAPI +FspTempRamExitDone ( + VOID + ); + +/** + This function handle NotifyPhase API call from the BootLoader. + It gives control back to the BootLoader after it is handled. If the + Notification code is a ReadyToBoot event, this function will return + and FSP continues the remaining execution until it reaches the DxeIpl. + +**/ +VOID +EFIAPI +FspWaitForNotify ( + VOID + ); + +/** + This function transfer control back to BootLoader after FspSiliconInit. + + @param[in] Status return status for the FspSiliconInit. +**/ +VOID +EFIAPI +FspSiliconInitDone2 ( + IN EFI_STATUS Status + ); + +/** + This function returns control to BootLoader after MemoryInitApi. + + @param[in] Status return status for the MemoryInitApi. + @param[in,out] HobListPtr The address of HobList pointer. +**/ +VOID +EFIAPI +FspMemoryInitDone2 ( + IN EFI_STATUS Status, + IN OUT VOID **HobListPtr + ); + +/** + This function returns control to BootLoader after TempRamExitApi. + + @param[in] Status return status for the TempRamExitApi. +**/ +VOID +EFIAPI +FspTempRamExitDone2 ( + IN EFI_STATUS Status + ); + +#endif diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h new file mode 100644 index 00000000..d6ecbd47 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/FspSecPlatformLib.h @@ -0,0 +1,96 @@ +/** @file + + Copyright (c) 2015 - 2020, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_SEC_PLATFORM_LIB_H_ +#define _FSP_SEC_PLATFORM_LIB_H_ + +/** + This function performs platform level initialization. + + This function must be in ASM file, because stack is not established yet. + This function is optional. If a library instance does not provide this function, the default empty one will be used. + + The callee should not use XMM6/XMM7. + The return address is saved in MM7. + + @retval in saved in EAX - 0 means platform initialization success. + other means platform initialization fail. +**/ +UINT32 +EFIAPI +SecPlatformInit ( + VOID + ); + +/** + This function loads Microcode. + + This function must be in ASM file, because stack is not established yet. + This function is optional. If a library instance does not provide this function, the default one will be used. + + The callee should not use XMM6/XMM7. + The return address is saved in MM7. + + @param[in] FsptUpdDataPtr Address pointer to the FSPT_UPD data structure. It is saved in ESP. + + @retval in saved in EAX - 0 means Microcode is loaded successfully. + other means Microcode is not loaded successfully. +**/ +UINT32 +EFIAPI +LoadMicrocode ( + IN VOID *FsptUpdDataPtr + ); + +/** + This function initializes the CAR. + + This function must be in ASM file, because stack is not established yet. + + The callee should not use XMM6/XMM7. + The return address is saved in MM7. + + @param[in] FsptUpdDataPtr Address pointer to the FSPT_UPD data structure. It is saved in ESP. + + @retval in saved in EAX - 0 means CAR initialization success. + other means CAR initialization fail. +**/ +UINT32 +EFIAPI +SecCarInit ( + IN VOID *FsptUpdDataPtr + ); + +/** + This function check the signature of UPD. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + +**/ +EFI_STATUS +EFIAPI +FspUpdSignatureCheck ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ); + +/** + This function handles FspMultiPhaseSiInitApi. + + @param[in] ApiIdx Internal index of the FSP API. + @param[in] ApiParam Parameter of the FSP API. + +**/ +EFI_STATUS +EFIAPI +FspMultiPhaseSiInitApiHandler ( + IN UINT32 ApiIdx, + IN VOID *ApiParam + ); + +#endif diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h new file mode 100644 index 00000000..259a5760 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Library/FspSwitchStackLib.h @@ -0,0 +1,55 @@ +/** @file + + Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR> + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_SWITCH_STACK_LIB_H_ +#define _FSP_SWITCH_STACK_LIB_H_ + +/** + + This function will switch the current stack to the previous saved stack. + Before calling the previous stack has to be set in FSP_GLOBAL_DATA.CoreStack. + EIP + FLAGS 16 bit FLAGS 16 bit + EDI + ESI + EBP + ESP + EBX + EDX + ECX + EAX + DWORD IDT base1 + StackPointer: DWORD IDT base2 + + @return ReturnKey After switching to the saved stack, + this value will be saved in eax before returning. + + +**/ +UINT32 +EFIAPI +Pei2LoaderSwitchStack ( + VOID + ); + +/** + + This function is equivalent to Pei2LoaderSwitchStack () but just indicates + the stack after switched is FSP stack. + + @return ReturnKey After switching to the saved stack, + this value will be saved in eax before returning. + + +**/ +UINT32 +EFIAPI +Loader2PeiSwitchStack ( + VOID + ); + +#endif diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h new file mode 100644 index 00000000..e3c62a94 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Ppi/FspmArchConfigPpi.h @@ -0,0 +1,47 @@ +/** @file + Header file for FSP-M Arch Config PPI for Dispatch mode + + Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSPM_ARCH_CONFIG_PPI_H_ +#define _FSPM_ARCH_CONFIG_PPI_H_ + +#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1 + +/// +/// Global ID for the FSPM_ARCH_CONFIG_PPI. +/// +#define FSPM_ARCH_CONFIG_GUID \ + { \ + 0x824d5a3a, 0xaf92, 0x4c0c, { 0x9f, 0x19, 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb } \ + } + +/// +/// This PPI provides FSP-M Arch Config PPI. +/// +typedef struct { + /// + /// Revision of the structure + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Pointer to the non-volatile storage (NVS) data buffer. + /// If it is NULL it indicates the NVS data is not available. + /// + VOID *NvsBufferPtr; + /// + /// Size of memory to be reserved by FSP below "top + /// of low usable memory" for bootloader usage. + /// + UINT32 BootLoaderTolumSize; + UINT8 Reserved1[4]; +} FSPM_ARCH_CONFIG_PPI; + +extern EFI_GUID gFspmArchConfigPpiGuid; + +#endif // _FSPM_ARCH_CONFIG_PPI_H_ diff --git a/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h new file mode 100644 index 00000000..ed3a1c19 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/IntelFsp2Pkg/Include/Ppi/TempRamExitPpi.h @@ -0,0 +1,52 @@ +/** @file + This file defines the Silicon Temp Ram Exit PPI which implements the + required programming steps for disabling temporary memory. + +Copyright (c) 2019, Intel Corporation. All rights reserved.<BR> +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_TEMP_RAM_EXIT_PPI_H_ +#define _FSP_TEMP_RAM_EXIT_PPI_H_ + +/// +/// Global ID for the FSP_TEMP_RAM_EXIT_PPI. +/// +#define FSP_TEMP_RAM_EXIT_GUID \ + { \ + 0xbc1cfbdb, 0x7e50, 0x42be, { 0xb4, 0x87, 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52 } \ + } + +// +// Forward declaration for the FSP_TEMP_RAM_EXIT_PPI. +// +typedef struct _FSP_TEMP_RAM_EXIT_PPI FSP_TEMP_RAM_EXIT_PPI; + +/** + Silicon function for disabling temporary memory. + @param[in] TempRamExitParamPtr - Pointer to the TempRamExit parameters structure. + This structure is normally defined in the Integration + Guide. If it is not defined in the Integration Guide, + pass NULL. + @retval EFI_SUCCESS - FSP execution environment was initialized successfully. + @retval EFI_INVALID_PARAMETER - Input parameters are invalid. + @retval EFI_UNSUPPORTED - The FSP calling conditions were not met. + @retval EFI_DEVICE_ERROR - Temporary memory exit. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_TEMP_RAM_EXIT) ( + IN VOID *TempRamExitParamPtr + ); + +/// +/// This PPI provides function to disable temporary memory. +/// +struct _FSP_TEMP_RAM_EXIT_PPI { + FSP_TEMP_RAM_EXIT TempRamExit; +}; + +extern EFI_GUID gFspTempRamExitPpiGuid; + +#endif // _FSP_TEMP_RAM_EXIT_PPI_H_ |