diff options
Diffstat (limited to 'src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseLib/Ia32/DisableCache.nasm')
-rw-r--r-- | src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseLib/Ia32/DisableCache.nasm | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseLib/Ia32/DisableCache.nasm b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseLib/Ia32/DisableCache.nasm new file mode 100644 index 00000000..ce83bf41 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/MdePkg/Library/BaseLib/Ia32/DisableCache.nasm @@ -0,0 +1,36 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR> +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; DisableCache.Asm +; +; Abstract: +; +; Set the CD bit of CR0 to 1, clear the NW bit of CR0 to 0, and flush all caches with a +; WBINVD instruction. +; +; Notes: +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; VOID +; EFIAPI +; AsmDisableCache ( +; VOID +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(AsmDisableCache) +ASM_PFX(AsmDisableCache): + mov eax, cr0 + bts eax, 30 + btr eax, 29 + mov cr0, eax + wbinvd + ret + |