diff options
Diffstat (limited to 'src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector')
8 files changed, 716 insertions, 0 deletions
diff --git a/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia16/Real16ToFlat32.asm b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia16/Real16ToFlat32.asm new file mode 100644 index 00000000..9868dc4d --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia16/Real16ToFlat32.asm @@ -0,0 +1,137 @@ +;------------------------------------------------------------------------------ +; @file +; Transition from 16 bit real mode into 32 bit flat protected mode +; +; Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019, Citrix Systems, Inc. +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;------------------------------------------------------------------------------ + +%define SEC_DEFAULT_CR0 0x00000023 +%define SEC_DEFAULT_CR4 0x640 + +BITS 16 + +; +; Modified: EAX, EBX +; +; @param[out] DS Selector allowing flat access to all addresses +; @param[out] ES Selector allowing flat access to all addresses +; @param[out] FS Selector allowing flat access to all addresses +; @param[out] GS Selector allowing flat access to all addresses +; @param[out] SS Selector allowing flat access to all addresses +; +TransitionFromReal16To32BitFlat: + + debugShowPostCode POSTCODE_16BIT_MODE + + cli + + mov bx, 0xf000 + mov ds, bx + + mov bx, ADDR16_OF(gdtr) + +o32 lgdt [cs:bx] + + mov eax, SEC_DEFAULT_CR0 + mov cr0, eax + + jmp LINEAR_CODE_SEL:dword ADDR_OF(jumpTo32BitAndLandHere) +BITS 32 +jumpTo32BitAndLandHere: + + mov eax, SEC_DEFAULT_CR4 + mov cr4, eax + + debugShowPostCode POSTCODE_32BIT_MODE + + mov ax, LINEAR_SEL + mov ds, ax + mov es, ax + mov fs, ax + mov gs, ax + mov ss, ax + + ; parameter for Flat32SearchForBfvBase + xor eax, eax ; Start searching from top of 4GB for BfvBase + + OneTimeCallRet TransitionFromReal16To32BitFlat + +ALIGN 2 + +gdtr: + dw GDT_END - GDT_BASE - 1 ; GDT limit + dd ADDR_OF(GDT_BASE) + +ALIGN 16 + +; +; Macros for GDT entries +; + +%define PRESENT_FLAG(p) (p << 7) +%define DPL(dpl) (dpl << 5) +%define SYSTEM_FLAG(s) (s << 4) +%define DESC_TYPE(t) (t) + +; Type: data, expand-up, writable, accessed +%define DATA32_TYPE 3 + +; Type: execute, readable, expand-up, accessed +%define CODE32_TYPE 0xb + +; Type: execute, readable, expand-up, accessed +%define CODE64_TYPE 0xb + +%define GRANULARITY_FLAG(g) (g << 7) +%define DEFAULT_SIZE32(d) (d << 6) +%define CODE64_FLAG(l) (l << 5) +%define UPPER_LIMIT(l) (l) + +; +; The Global Descriptor Table (GDT) +; + +GDT_BASE: +; null descriptor +NULL_SEL equ $-GDT_BASE + DW 0 ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB 0 ; sys flag, dpl, type + DB 0 ; limit 19:16, flags + DB 0 ; base 31:24 + +; linear data segment descriptor +LINEAR_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(DATA32_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIMIT(0xf) + DB 0 ; base 31:24 + +; linear code segment descriptor +LINEAR_CODE_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(1)|CODE64_FLAG(0)|UPPER_LIMIT(0xf) + DB 0 ; base 31:24 + +%ifdef ARCH_X64 +; linear code (64-bit) segment descriptor +LINEAR_CODE64_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE64_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(1)|UPPER_LIMIT(0xf) + DB 0 ; base 31:24 +%endif + +GDT_END: + diff --git a/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia16/ResetVectorVtf0.asm b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia16/ResetVectorVtf0.asm new file mode 100644 index 00000000..e06c4a0f --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia16/ResetVectorVtf0.asm @@ -0,0 +1,79 @@ +;------------------------------------------------------------------------------ +; @file +; First code executed by processor after resetting. +; +; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019, Citrix Systems, Inc. +; +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;------------------------------------------------------------------------------ + +BITS 16 + +ALIGN 16 + +; +; Pad the image size to 4k when page tables are in VTF0 +; +; If the VTF0 image has page tables built in, then we need to make +; sure the end of VTF0 is 4k above where the page tables end. +; +; This is required so the page tables will be 4k aligned when VTF0 is +; located just below 0x100000000 (4GB) in the firmware device. +; +%ifdef ALIGN_TOP_TO_4K_FOR_PAGING + TIMES (0x1000 - ($ - EndOfPageTables) - (fourGigabytes - xenPVHEntryPoint)) DB 0 +%endif + +BITS 32 +xenPVHEntryPoint: +; +; Entry point to use when running as a Xen PVH guest. (0xffffffd0) +; +; Description of the expected state of the machine when this entry point is +; used can be found at: +; https://xenbits.xenproject.org/docs/unstable/misc/pvh.html +; + jmp xenPVHMain + +BITS 16 +ALIGN 16 + +applicationProcessorEntryPoint: +; +; Application Processors entry point +; +; GenFv generates code aligned on a 4k boundary which will jump to this +; location. (0xffffffe0) This allows the Local APIC Startup IPI to be +; used to wake up the application processors. +; + jmp EarlyApInitReal16 + +ALIGN 8 + + DD 0 + +; +; The VTF signature +; +; VTF-0 means that the VTF (Volume Top File) code does not require +; any fixups. +; +vtfSignature: + DB 'V', 'T', 'F', 0 + +ALIGN 16 + +resetVector: +; +; Reset Vector +; +; This is where the processor will begin execution +; + jmp EarlyBspInitReal16 + +ALIGN 16 + +fourGigabytes: + diff --git a/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia32/Flat32ToFlat64.asm b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia32/Flat32ToFlat64.asm new file mode 100644 index 00000000..3b05505b --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia32/Flat32ToFlat64.asm @@ -0,0 +1,68 @@ +;------------------------------------------------------------------------------ +; @file +; Transition from 32 bit flat protected mode into 64 bit flat protected mode +; +; Copyright (c) 2008 - 2018, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019, Citrix Systems, Inc. +; +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;------------------------------------------------------------------------------ + +BITS 32 + +; +; Modified: EAX, EBX, ECX, EDX, ESP +; +Transition32FlatTo64Flat: + + OneTimeCall SetCr3ForPageTables64 + + mov eax, cr4 + bts eax, 5 ; enable PAE + mov cr4, eax + + mov ecx, 0xc0000080 + rdmsr + bts eax, 8 ; set LME + wrmsr + + mov eax, cr0 + bts eax, 31 ; set PG + mov cr0, eax ; enable paging + + ; + ; backup ESP + ; + mov ebx, esp + + ; + ; recalculate delta + ; + mov esp, PVH_SPACE(16) + call .delta +.delta: + pop edx + sub edx, ADDR_OF(.delta) + + ; + ; push return addr and seg to the stack, then return far + ; + push dword LINEAR_CODE64_SEL + mov eax, ADDR_OF(jumpTo64BitAndLandHere) + add eax, edx ; add delta + push eax + retf + +BITS 64 +jumpTo64BitAndLandHere: + + ; + ; restore ESP + ; + mov esp, ebx + + debugShowPostCode POSTCODE_64BIT_MODE + + OneTimeCallRet Transition32FlatTo64Flat + diff --git a/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia32/PageTables64.asm b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia32/PageTables64.asm new file mode 100644 index 00000000..af5cc240 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia32/PageTables64.asm @@ -0,0 +1,149 @@ +;------------------------------------------------------------------------------ +; @file +; Sets the CR3 register for 64-bit paging +; +; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019, Citrix Systems, Inc. +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;------------------------------------------------------------------------------ + +BITS 32 + +%define PAGE_PRESENT 0x01 +%define PAGE_READ_WRITE 0x02 +%define PAGE_USER_SUPERVISOR 0x04 +%define PAGE_WRITE_THROUGH 0x08 +%define PAGE_CACHE_DISABLE 0x010 +%define PAGE_ACCESSED 0x020 +%define PAGE_DIRTY 0x040 +%define PAGE_PAT 0x080 +%define PAGE_GLOBAL 0x0100 +%define PAGE_2M_MBO 0x080 +%define PAGE_2M_PAT 0x01000 + +%define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \ + PAGE_ACCESSED + \ + PAGE_DIRTY + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT) + +%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT) + +; Check if Secure Encrypted Virtualization (SEV) feature is enabled +; +; If SEV is enabled then EAX will be at least 32 +; If SEV is disabled then EAX will be zero. +; +CheckSevFeature: + ; Check if we have a valid (0x8000_001F) CPUID leaf + mov eax, 0x80000000 + cpuid + + ; This check should fail on Intel or Non SEV AMD CPUs. In future if + ; Intel CPUs supports this CPUID leaf then we are guranteed to have exact + ; same bit definition. + cmp eax, 0x8000001f + jl NoSev + + ; Check for memory encryption feature: + ; CPUID Fn8000_001F[EAX] - Bit 1 + ; + mov eax, 0x8000001f + cpuid + bt eax, 1 + jnc NoSev + + ; Check if memory encryption is enabled + ; MSR_0xC0010131 - Bit 0 (SEV enabled) + mov ecx, 0xc0010131 + rdmsr + bt eax, 0 + jnc NoSev + + ; Get pte bit position to enable memory encryption + ; CPUID Fn8000_001F[EBX] - Bits 5:0 + ; + mov eax, ebx + and eax, 0x3f + jmp SevExit + +NoSev: + xor eax, eax + +SevExit: + OneTimeCallRet CheckSevFeature + +; +; Modified: EAX, EBX, ECX, EDX +; +SetCr3ForPageTables64: + + OneTimeCall CheckSevFeature + xor edx, edx + test eax, eax + jz SevNotActive + + ; If SEV is enabled, C-bit is always above 31 + sub eax, 32 + bts edx, eax + +SevNotActive: + + ; + ; For OVMF, build some initial page tables at + ; PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000). + ; + ; This range should match with PcdOvmfSecPageTablesSize which is + ; declared in the FDF files. + ; + ; At the end of PEI, the pages tables will be rebuilt into a + ; more permanent location by DxeIpl. + ; + + mov ecx, 6 * 0x1000 / 4 + xor eax, eax +clearPageTablesMemoryLoop: + mov dword[ecx * 4 + PT_ADDR (0) - 4], eax + loop clearPageTablesMemoryLoop + + ; + ; Top level Page Directory Pointers (1 * 512GB entry) + ; + mov dword[PT_ADDR (0)], PT_ADDR (0x1000) + PAGE_PDP_ATTR + mov dword[PT_ADDR (4)], edx + + ; + ; Next level Page Directory Pointers (4 * 1GB entries => 4GB) + ; + mov dword[PT_ADDR (0x1000)], PT_ADDR (0x2000) + PAGE_PDP_ATTR + mov dword[PT_ADDR (0x1004)], edx + mov dword[PT_ADDR (0x1008)], PT_ADDR (0x3000) + PAGE_PDP_ATTR + mov dword[PT_ADDR (0x100C)], edx + mov dword[PT_ADDR (0x1010)], PT_ADDR (0x4000) + PAGE_PDP_ATTR + mov dword[PT_ADDR (0x1014)], edx + mov dword[PT_ADDR (0x1018)], PT_ADDR (0x5000) + PAGE_PDP_ATTR + mov dword[PT_ADDR (0x101C)], edx + + ; + ; Page Table Entries (2048 * 2MB entries => 4GB) + ; + mov ecx, 0x800 +pageTableEntriesLoop: + mov eax, ecx + dec eax + shl eax, 21 + add eax, PAGE_2M_PDE_ATTR + mov [ecx * 8 + PT_ADDR (0x2000 - 8)], eax + mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx + loop pageTableEntriesLoop + + ; + ; Set CR3 now that the paging structures are available + ; + mov eax, PT_ADDR (0) + mov cr3, eax + + OneTimeCallRet SetCr3ForPageTables64 diff --git a/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia32/SearchForBfvBase.asm b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia32/SearchForBfvBase.asm new file mode 100644 index 00000000..28466431 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia32/SearchForBfvBase.asm @@ -0,0 +1,87 @@ +;------------------------------------------------------------------------------ +; @file +; Search for the Boot Firmware Volume (BFV) base address +; +; Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019, Citrix Systems, Inc. +; +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;------------------------------------------------------------------------------ + +;#define EFI_FIRMWARE_FILE_SYSTEM2_GUID \ +; { 0x8c8ce578, 0x8a3d, 0x4f1c, { 0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 } } +%define FFS_GUID_DWORD0 0x8c8ce578 +%define FFS_GUID_DWORD1 0x4f1c8a3d +%define FFS_GUID_DWORD2 0x61893599 +%define FFS_GUID_DWORD3 0xd32dc385 + +BITS 32 + +; +; Modified: EAX, EBX, ECX +; Preserved: EDI, ESP +; +; @param[in] EAX Start search from here +; @param[out] EBP Address of Boot Firmware Volume (BFV) +; +Flat32SearchForBfvBase: + + mov ecx, eax +searchingForBfvHeaderLoop: + ; + ; We check for a firmware volume at every 4KB address in the 16MB + ; just below where we started, ECX. + ; + sub eax, 0x1000 + mov ebx, ecx + sub ebx, eax + cmp ebx, 0x01000000 + ; if ECX-EAX > 16MB; jump notfound + ja searchedForBfvHeaderButNotFound + + ; + ; Check FFS GUID + ; + cmp dword [eax + 0x10], FFS_GUID_DWORD0 + jne searchingForBfvHeaderLoop + cmp dword [eax + 0x14], FFS_GUID_DWORD1 + jne searchingForBfvHeaderLoop + cmp dword [eax + 0x18], FFS_GUID_DWORD2 + jne searchingForBfvHeaderLoop + cmp dword [eax + 0x1c], FFS_GUID_DWORD3 + jne searchingForBfvHeaderLoop + + ; + ; Check FV Length + ; + cmp dword [eax + 0x24], 0 + jne searchingForBfvHeaderLoop + mov ebx, eax + add ebx, dword [eax + 0x20] + cmp ebx, ecx + jnz searchingForBfvHeaderLoop + + jmp searchedForBfvHeaderAndItWasFound + +searchedForBfvHeaderButNotFound: + ; + ; Hang if the SEC entry point was not found + ; + debugShowPostCode POSTCODE_BFV_NOT_FOUND + + ; + ; 0xbfbfbfbf in the EAX & EBP registers helps signal what failed + ; for debugging purposes. + ; + mov eax, 0xBFBFBFBF + mov ebp, eax + jmp $ + +searchedForBfvHeaderAndItWasFound: + mov ebp, eax + + debugShowPostCode POSTCODE_BFV_FOUND + + OneTimeCallRet Flat32SearchForBfvBase + diff --git a/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm new file mode 100644 index 00000000..825df9b6 --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/Ia32/XenPVHMain.asm @@ -0,0 +1,84 @@ +;------------------------------------------------------------------------------ +; @file +; An entry point use by Xen when a guest is started in PVH mode. +; +; Copyright (c) 2019, Citrix Systems, Inc. +; +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;------------------------------------------------------------------------------ + +BITS 32 + +xenPVHMain: + ; + ; 'BP' to indicate boot-strap processor + ; + mov di, 'BP' + + ; + ; Store "Start of day" struct pointer for later use + ; + mov dword[PVH_SPACE (0)], ebx + mov dword[PVH_SPACE (4)], 'XPVH' + + ; + ; calculate delta between build-addr and run position + ; + mov esp, PVH_SPACE(16) ; create a temporary stack + call .delta +.delta: + pop edx ; get addr of .delta + sub edx, ADDR_OF(.delta) ; calculate delta + + ; + ; Find address of GDT and gdtr and fix the later + ; + mov ebx, ADDR_OF(gdtr) + add ebx, edx ; add delta gdtr + mov eax, ADDR_OF(GDT_BASE) + add eax, edx ; add delta to GDT_BASE + mov dword[ebx + 2], eax ; fix GDT_BASE addr in gdtr + lgdt [ebx] + + mov eax, SEC_DEFAULT_CR0 + mov cr0, eax + + ; + ; push return addr to the stack, then return far + ; + push dword LINEAR_CODE_SEL ; segment to select + mov eax, ADDR_OF(.jmpToNewCodeSeg) ; return addr + add eax, edx ; add delta to return addr + push eax + retf +.jmpToNewCodeSeg: + + mov eax, SEC_DEFAULT_CR4 + mov cr4, eax + + mov ax, LINEAR_SEL + mov ds, ax + mov es, ax + mov fs, ax + mov gs, ax + mov ss, ax + + ; + ; ESP will be used as initial value of the EAX register + ; in Main.asm + ; + xor esp, esp + + ; + ; parameter for Flat32SearchForBfvBase + ; + mov eax, 0 ; ADDR_OF(fourGigabytes) + add eax, edx ; add delta + + ; + ; Jump to the main routine of the pre-SEC code + ; skiping the 16-bit part of the routine and + ; into the 32-bit flat mode part + ; + OneTimeCallRet TransitionFromReal16To32BitFlat diff --git a/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/XenResetVector.inf b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/XenResetVector.inf new file mode 100644 index 00000000..6ac67d6e --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/XenResetVector.inf @@ -0,0 +1,41 @@ +## @file +# Reset Vector +# +# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2019, Citrix Systems, Inc. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = XenResetVector + FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09 + MODULE_TYPE = SEC + VERSION_STRING = 1.1 + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 +# + +[Sources] + XenResetVector.nasmb + +[Packages] + OvmfPkg/OvmfPkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[BuildOptions] + *_*_IA32_NASMB_FLAGS = -I$(WORKSPACE)/UefiCpuPkg/ResetVector/Vtf0/ + *_*_X64_NASMB_FLAGS = -I$(WORKSPACE)/UefiCpuPkg/ResetVector/Vtf0/ + +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize + + gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtr + gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtrSize diff --git a/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/XenResetVector.nasmb b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/XenResetVector.nasmb new file mode 100644 index 00000000..4bceec7d --- /dev/null +++ b/src/VBox/Devices/EFI/Firmware/OvmfPkg/XenResetVector/XenResetVector.nasmb @@ -0,0 +1,71 @@ +;------------------------------------------------------------------------------ +; @file +; This file includes all other code files to assemble the reset vector code +; +; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2019, Citrix Systems, Inc. +; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;------------------------------------------------------------------------------ + +; +; If neither ARCH_IA32 nor ARCH_X64 are defined, then try to include +; Base.h to use the C pre-processor to determine the architecture. +; +%ifndef ARCH_IA32 + %ifndef ARCH_X64 + #include <Base.h> + #if defined (MDE_CPU_IA32) + %define ARCH_IA32 + #elif defined (MDE_CPU_X64) + %define ARCH_X64 + #endif + %endif +%endif + +%ifdef ARCH_IA32 + %ifdef ARCH_X64 + %error "Only one of ARCH_IA32 or ARCH_X64 can be defined." + %endif +%elifdef ARCH_X64 +%else + %error "Either ARCH_IA32 or ARCH_X64 must be defined." +%endif + +%include "CommonMacros.inc" + +%define PVH_SPACE(Offset) (FixedPcdGet32 (PcdXenPvhStartOfDayStructPtr) + (Offset)) + +%include "PostCodes.inc" + +%ifdef DEBUG_PORT80 + %include "Port80Debug.asm" +%elifdef DEBUG_SERIAL + %include "SerialDebug.asm" +%else + %include "DebugDisabled.asm" +%endif + +%include "Ia32/SearchForBfvBase.asm" +%include "Ia32/SearchForSecEntry.asm" + +%ifdef ARCH_X64 + #include <AutoGen.h> + + %if (FixedPcdGet32 (PcdOvmfSecPageTablesSize) != 0x6000) + %error "This implementation inherently depends on PcdOvmfSecPageTablesSize" + %endif + + %define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Offset)) +%include "Ia32/Flat32ToFlat64.asm" +%include "Ia32/PageTables64.asm" +%endif + +%include "Ia16/Real16ToFlat32.asm" +%include "Ia16/Init16.asm" + +%include "Main.asm" +%include "Ia32/XenPVHMain.asm" + +%include "Ia16/ResetVectorVtf0.asm" + |