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Diffstat (limited to 'src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32')
| -rw-r--r-- | src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32 | 12210 |
1 files changed, 12210 insertions, 0 deletions
diff --git a/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32 b/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32 new file mode 100644 index 00000000..2d1e7c28 --- /dev/null +++ b/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32 @@ -0,0 +1,12210 @@ +/* $Id: bs3-cpu-instr-3.c32 $ */ +/** @file + * BS3Kit - bs3-cpu-instr-3 - MMX, SSE and AVX instructions, C code template. + */ + +/* + * Copyright (C) 2007-2023 Oracle and/or its affiliates. + * + * This file is part of VirtualBox base platform packages, as + * available from https://www.virtualbox.org. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation, in version 3 of the + * License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see <https://www.gnu.org/licenses>. + * + * The contents of this file may alternatively be used under the terms + * of the Common Development and Distribution License Version 1.0 + * (CDDL), a copy of it is provided in the "COPYING.CDDL" file included + * in the VirtualBox distribution, in which case the provisions of the + * CDDL are applicable instead of those of the GPL. + * + * You may elect to license modified versions of this file under the + * terms and conditions of either the GPL or the CDDL or both. + * + * SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0 + */ + + +/********************************************************************************************************************************* +* Header Files * +*********************************************************************************************************************************/ +#include <bs3kit.h> + +#include <iprt/asm.h> +#include <iprt/asm-amd64-x86.h> + + +/********************************************************************************************************************************* +* Defined Constants And Macros * +*********************************************************************************************************************************/ +#define BS3_FNBS3FAR_PROTOTYPES_CMN(a_BaseNm) \ + extern FNBS3FAR RT_CONCAT(a_BaseNm, _c16); \ + extern FNBS3FAR RT_CONCAT(a_BaseNm, _c32); \ + extern FNBS3FAR RT_CONCAT(a_BaseNm, _c64) + + +/** Converts an execution mode (BS3_MODE_XXX) into an index into an array + * initialized by BS3CPUINSTR3_TEST1_MODES_INIT, + * BS3CPUINSTR3_TEST2_MODES_INIT, BS3CPUINSTR3_TEST3_MODES_INIT, ... . */ +#define BS3CPUINSTR3_TEST_MODES_INDEX(a_bMode) (BS3_MODE_IS_16BIT_CODE(bMode) ? 0 : BS3_MODE_IS_32BIT_CODE(bMode) ? 1 : 2) + + +/********************************************************************************************************************************* +* Structures and Typedefs * +*********************************************************************************************************************************/ +/** Instruction set type and operand width. */ +typedef enum +{ + T_INVALID, + T_MMX, + T_MMX_SSE, /**< MMX instruction, but require the SSE CPUID to work. */ + T_MMX_SSE2, /**< MMX instruction, but require the SSE2 CPUID to work. */ + T_MMX_SSSE3, /**< MMX instruction, but require the SSSE3 CPUID to work. */ + T_AXMMX, + T_AXMMX_OR_SSE, + T_SSE, + T_128BITS = T_SSE, + T_SSE2, + T_SSE3, + T_SSSE3, + T_SSE4_1, + T_SSE4_2, + T_SSE4A, + T_PCLMUL, + T_AVX_128, + T_AVX2_128, + T_AVX_PCLMUL, + T_AVX_256, + T_256BITS = T_AVX_256, + T_AVX2_256, + T_MAX +} INPUT_TYPE_T; + +/** Memory or register rm variant. */ +enum { + RM_REG = 0, + RM_MEM, + RM_MEM32, /**< Memory operand is 32 bits. Hack for movss and similar. */ + RM_MEM64 /**< Memory operand is 64 bits. Hack for movss and similar. */ +}; + +/** + * Execution environment configuration. + */ +typedef struct BS3CPUINSTR3_CONFIG_T +{ + uint16_t fCr0Mp : 1; + uint16_t fCr0Em : 1; + uint16_t fCr0Ts : 1; + uint16_t fCr4OsFxSR : 1; + uint16_t fCr4OsXSave : 1; + uint16_t fXcr0Sse : 1; + uint16_t fXcr0Avx : 1; + /** x87 exception pending (IE + something unmasked). */ + uint16_t fX87XcptPending : 1; + /** Aligned memory operands. If zero, they will be misaligned and tests w/o memory ops skipped. */ + uint16_t fAligned : 1; + uint16_t fAlignCheck : 1; + uint16_t fMxCsrMM : 1; /**< AMD only */ + uint8_t bXcptMmx; + uint8_t bXcptSse; + uint8_t bXcptAvx; +} BS3CPUINSTR3_CONFIG_T; +/** Pointer to an execution environment configuration. */ +typedef BS3CPUINSTR3_CONFIG_T const BS3_FAR *PCBS3CPUINSTR3_CONFIG_T; + +/** State saved by bs3CpuInstr3ConfigReconfigure. */ +typedef struct BS3CPUINSTR3_CONFIG_SAVED_T +{ + uint32_t uCr0; + uint32_t uCr4; + uint32_t uEfl; + uint16_t uFcw; + uint16_t uFsw; + uint32_t uMxCsr; +} BS3CPUINSTR3_CONFIG_SAVED_T; +typedef BS3CPUINSTR3_CONFIG_SAVED_T BS3_FAR *PBS3CPUINSTR3_CONFIG_SAVED_T; +typedef BS3CPUINSTR3_CONFIG_SAVED_T const BS3_FAR *PCBS3CPUINSTR3_CONFIG_SAVED_T; + + +/********************************************************************************************************************************* +* Global Variables * +*********************************************************************************************************************************/ +static bool g_afTypeSupports[T_MAX] = { false, false, false, false, false, false, false, false, false }; +static bool g_fAmdMisalignedSse = false; + +/** Size of g_pbBuf - at least three pages. */ +static uint32_t g_cbBuf; +/** Buffer of g_cbBuf size. */ +static uint8_t BS3_FAR *g_pbBuf; + +/** Exception type \#1 test configurations, 16 & 32 bytes strictly aligned. */ +static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig1[] = +{ +/* + * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to + * +AVX +AMD/SSE + * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR + * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */ + { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */ + { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */ + { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */ + { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */ + { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */ + { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */ + { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */ + { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */ + { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */ + { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */ + /* Memory misalignment and alignment checks: */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_GP, X86_XCPT_GP }, /* #10 */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_GP, X86_XCPT_GP }, /* #11 */ + { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */ + /* AMD only: */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_GP }, /* #13 */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_GP }, /* #14 */ +}; + +/** Exception type \#4 test configurations, 16 & 32 byte not strictly aligned. */ +static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig4[] = +{ +/* + * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to + * +AVX +AMD/SSE + * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR + * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */ + { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */ + { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */ + { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */ + { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */ + { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */ + { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */ + { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */ + { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */ + { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */ + { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */ + /* Memory misalignment and alignment checks: */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_GP, X86_XCPT_DB }, /* #10 */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_GP, X86_XCPT_AC }, /* #11 */ + { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */ + /* AMD only: */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #13 */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #14 */ +}; + +/** Exception type \#4 test configurations, for the SSE version of movups. */ +static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig4Unaligned[] = +{ +/* + * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to + * +AVX +AMD/SSE + * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR + * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */ + { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */ + { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */ + { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */ + { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */ + { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */ + { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */ + { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */ + { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */ + { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */ + { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */ + /* Memory misalignment and alignment checks: */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #10 */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_DB, X86_XCPT_AC }, /* #11 */ + { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */ + /* AMD only: */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #13 */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #14 */ +}; + +/** Exception type \#5 test configurations, less than 16 byte operands. */ +static const BS3CPUINSTR3_CONFIG_T g_aXcptConfig5[] = +{ +/* + * X87 SSE SSE SSE AVX AVX AVX MMX MMX+SSE MMX+AVX AMD/SSE <-- applies to + * +AVX +AMD/SSE + * CR0 CR0 CR0 CR4 CR4 XCR0 XCR0 FCW MXCSR + * MP, EM, TS, OSFXSR, OSXSAVE, SSE, AVX, ES+, fAligned, AC/AM, MM, bXcptMmx, bXcptSse, bXcptAvx */ + { 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #0 */ + { 1, 0, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #1 */ + { 0, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_DB }, /* #2 */ + { 0, 0, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_NM, X86_XCPT_NM, X86_XCPT_NM }, /* #3 */ + { 0, 1, 1, 1, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_UD, X86_XCPT_UD, X86_XCPT_NM }, /* #4 */ + { 0, 0, 0, 0, 1, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_UD, X86_XCPT_DB }, /* #5 */ + { 0, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #6 */ + { 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #7 */ + { 0, 0, 0, 1, 1, 0, 0, 0, 1, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_UD }, /* #8 */ + { 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0, X86_XCPT_MF, X86_XCPT_DB, X86_XCPT_DB }, /* #9 - pending x87 exception */ + /* Memory misalignment and alignment checks: */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #10 */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 0, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #11 */ + { 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 0, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #12 */ + /* AMD only: */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 1, X86_XCPT_DB, X86_XCPT_DB, X86_XCPT_DB }, /* #13 */ + { 0, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, X86_XCPT_AC, X86_XCPT_AC, X86_XCPT_AC }, /* #14 */ +}; + + + +/** + * Reconfigures the execution environment according to @a pConfig. + * + * Call bs3CpuInstr3ConfigRestore to undo the changes. + * + * @returns true on success, false if the configuration cannot be applied. In + * the latter case, no context changes are made. + * @param pSavedCfg Where to save state we modify. + * @param pCtx The register context to modify. + * @param pExtCtx The extended register context to modify. + * @param pConfig The configuration to apply. + * @param bMode The target mode. + */ +static bool bs3CpuInstr3ConfigReconfigure(PBS3CPUINSTR3_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx, + PCBS3CPUINSTR3_CONFIG_T pConfig, uint8_t bMode) +{ + /* + * Save context bits we may change here + */ + pSavedCfg->uCr0 = pCtx->cr0.u32; + pSavedCfg->uCr4 = pCtx->cr4.u32; + pSavedCfg->uEfl = pCtx->rflags.u32; + pSavedCfg->uFcw = Bs3ExtCtxGetFcw(pExtCtx); + pSavedCfg->uFsw = Bs3ExtCtxGetFsw(pExtCtx); + pSavedCfg->uMxCsr = Bs3ExtCtxGetMxCsr(pExtCtx); + + /* + * Can we make these changes? + */ + if (pConfig->fMxCsrMM && !g_fAmdMisalignedSse) + return false; + + /* Currently we skip pending x87 exceptions in real mode as they cannot be + caught, given that we preserve the bios int10h. */ + if (pConfig->fX87XcptPending && BS3_MODE_IS_RM_OR_V86(bMode)) + return false; + + /* + * Modify the test context. + */ + if (pConfig->fCr0Mp) + pCtx->cr0.u32 |= X86_CR0_MP; + else + pCtx->cr0.u32 &= ~X86_CR0_MP; + if (pConfig->fCr0Em) + pCtx->cr0.u32 |= X86_CR0_EM; + else + pCtx->cr0.u32 &= ~X86_CR0_EM; + if (pConfig->fCr0Ts) + pCtx->cr0.u32 |= X86_CR0_TS; + else + pCtx->cr0.u32 &= ~X86_CR0_TS; + + if (pConfig->fCr4OsFxSR) + pCtx->cr4.u32 |= X86_CR4_OSFXSR; + else + pCtx->cr4.u32 &= ~X86_CR4_OSFXSR; + /** @todo X86_CR4_OSXMMEEXCPT? */ + if (pConfig->fCr4OsXSave) + pCtx->cr4.u32 |= X86_CR4_OSXSAVE; + else + pCtx->cr4.u32 &= ~X86_CR4_OSXSAVE; + + if (pConfig->fXcr0Sse) + pExtCtx->fXcr0Saved |= XSAVE_C_SSE; + else + pExtCtx->fXcr0Saved &= ~XSAVE_C_SSE; + if (pConfig->fXcr0Avx) + pExtCtx->fXcr0Saved |= XSAVE_C_YMM; + else + pExtCtx->fXcr0Saved &= ~XSAVE_C_YMM; + + if (pConfig->fAlignCheck) + { + pCtx->rflags.u32 |= X86_EFL_AC; + pCtx->cr0.u32 |= X86_CR0_AM; + } + else + { + pCtx->rflags.u32 &= ~X86_EFL_AC; + pCtx->cr0.u32 &= ~X86_CR0_AM; + } + + if (!pConfig->fX87XcptPending) + Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw & ~(X86_FSW_ES | X86_FSW_B)); + else + { + Bs3ExtCtxSetFcw(pExtCtx, pSavedCfg->uFcw & ~X86_FCW_ZM); + Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw | X86_FSW_ZE | X86_FSW_ES | X86_FSW_B); + pCtx->cr0.u32 |= X86_CR0_NE; + } + + if (pConfig->fMxCsrMM) + Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr | X86_MXCSR_MM); + else + Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr & ~X86_MXCSR_MM); + return true; +} + + +/** + * Undoes changes made by bs3CpuInstr3ConfigReconfigure. + */ +static void bs3CpuInstr3ConfigRestore(PCBS3CPUINSTR3_CONFIG_SAVED_T pSavedCfg, PBS3REGCTX pCtx, PBS3EXTCTX pExtCtx) +{ + pCtx->cr0.u32 = pSavedCfg->uCr0; + pCtx->cr4.u32 = pSavedCfg->uCr4; + pCtx->rflags.u32 = pSavedCfg->uEfl; + pExtCtx->fXcr0Saved = pExtCtx->fXcr0Nominal; + Bs3ExtCtxSetFcw(pExtCtx, pSavedCfg->uFcw); + Bs3ExtCtxSetFsw(pExtCtx, pSavedCfg->uFsw); + Bs3ExtCtxSetMxCsr(pExtCtx, pSavedCfg->uMxCsr); +} + + +/** + * Allocates two extended CPU contexts and initializes the first one + * with random data. + * @returns First extended context, initialized with randomish data. NULL on + * failure (complained). + * @param ppExtCtx2 Where to return the 2nd context. + */ +static PBS3EXTCTX bs3CpuInstr3AllocExtCtxs(PBS3EXTCTX BS3_FAR *ppExtCtx2) +{ + /* Allocate extended context structures. */ + uint64_t fFlags; + uint16_t cb = Bs3ExtCtxGetSize(&fFlags); + PBS3EXTCTX pExtCtx1 = Bs3MemAlloc(BS3MEMKIND_TILED, cb * 2); + PBS3EXTCTX pExtCtx2 = (PBS3EXTCTX)((uint8_t BS3_FAR *)pExtCtx1 + cb); + if (pExtCtx1) + { + Bs3ExtCtxInit(pExtCtx1, cb, fFlags); + /** @todo populate with semi-random stuff. */ + + Bs3ExtCtxInit(pExtCtx2, cb, fFlags); + *ppExtCtx2 = pExtCtx2; + return pExtCtx1; + } + Bs3TestFailedF("Bs3MemAlloc(tiled,%#x)", cb * 2); + *ppExtCtx2 = NULL; + return NULL; +} + +static void bs3CpuInstr3FreeExtCtxs(PBS3EXTCTX pExtCtx1, PBS3EXTCTX BS3_FAR pExtCtx2) +{ + RT_NOREF_PV(pExtCtx2); + Bs3MemFree(pExtCtx1, pExtCtx1->cb * 2); +} + +/** + * Sets up SSE and maybe AVX. + */ +static void bs3CpuInstr3SetupSseAndAvx(PBS3REGCTX pCtx, PCBS3EXTCTX pExtCtx) +{ + /* CR0: */ + uint32_t cr0 = Bs3RegGetCr0(); + cr0 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM); + cr0 |= X86_CR0_NE; + Bs3RegSetCr0(cr0); + + /* If real mode context, the cr0 value will differ from the current one (we're in PE32 mode). */ + pCtx->cr0.u32 &= ~(X86_CR0_TS | X86_CR0_MP | X86_CR0_EM); + pCtx->cr0.u32 |= X86_CR0_NE; + + /* CR4: */ + if (pExtCtx->enmMethod != BS3EXTCTXMETHOD_ANCIENT) + { + uint32_t cr4 = Bs3RegGetCr4(); + if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE) + { + cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT | X86_CR4_OSXSAVE; + Bs3RegSetCr4(cr4); + Bs3RegSetXcr0(pExtCtx->fXcr0Nominal); + } + else if (pExtCtx->enmMethod == BS3EXTCTXMETHOD_FXSAVE) + { + cr4 |= X86_CR4_OSFXSR | X86_CR4_OSXMMEEXCPT; + Bs3RegSetCr4(cr4); + } + pCtx->cr4.u32 = cr4; + } +} + + + +/** + * Configures the buffer with electrict fences in paged modes. + * + * @returns Adjusted buffer pointer. + * @param pbBuf The buffer pointer. + * @param pcbBuf Pointer to the buffer size (input & output). + * @param bMode The testing target mode. + */ +DECLINLINE(uint8_t BS3_FAR *) bs3CpuInstr3BufSetup(uint8_t BS3_FAR *pbBuf, uint32_t *pcbBuf, uint8_t bMode) +{ + if (BS3_MODE_IS_PAGED(bMode)) + { + uint32_t cbBuf = *pcbBuf; + Bs3PagingProtectPtr(&pbBuf[0], X86_PAGE_SIZE, 0, X86_PTE_P); + Bs3PagingProtectPtr(&pbBuf[cbBuf - X86_PAGE_SIZE], X86_PAGE_SIZE, 0, X86_PTE_P); + pbBuf += X86_PAGE_SIZE; + cbBuf -= X86_PAGE_SIZE * 2; + *pcbBuf = cbBuf; + } + return pbBuf; +} + + +/** + * Undoes what bs3CpuInstr3BufSetup did. + * + * @param pbBuf The buffer pointer. + * @param cbBuf The buffer size. + * @param bMode The testing target mode. + */ +DECLINLINE(void) bs3CpuInstr3BufCleanup(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t bMode) +{ + if (BS3_MODE_IS_PAGED(bMode)) + { + Bs3PagingProtectPtr(&pbBuf[-X86_PAGE_SIZE], X86_PAGE_SIZE, X86_PTE_P, 0); + Bs3PagingProtectPtr(&pbBuf[cbBuf], X86_PAGE_SIZE, X86_PTE_P, 0); + } +} + + +/** + * Gets a buffer of a @a cbMemOp sized operand according to the given + * configuration and alignment restrictions. + * + * @returns Pointer to the buffer. + * @param pbBuf The buffer pointer. + * @param cbBuf The buffer size. + * @param cbMemOp The operand size. + * @param cbAlign The operand alignment restriction. + * @param pConfig The configuration. + */ +DECLINLINE(PRTUINT256U) bs3CpuInstr3BufForOperand(uint8_t BS3_FAR *pbBuf, uint32_t cbBuf, uint8_t cbMemOp, uint8_t cbAlign, + PCBS3CPUINSTR3_CONFIG_T pConfig) +{ + if (pConfig->fAligned) + { + if (!pConfig->fAlignCheck) + return (PRTUINT256U)&pbBuf[cbBuf - cbMemOp]; + return (PRTUINT256U)&pbBuf[cbBuf - cbMemOp - cbAlign]; + } + return (PRTUINT256U)&pbBuf[cbBuf - cbMemOp - 1]; +} + + +/** + * Determins the size of memory operands. + */ +DECLINLINE(uint8_t) bs3CpuInstr3MemOpSize(uint8_t cbOperand, uint8_t enmRm) +{ + if (enmRm <= RM_MEM) + return cbOperand; + if (enmRm == RM_MEM32) + return sizeof(uint32_t); + if (enmRm == RM_MEM64) + return sizeof(uint64_t); + BS3_ASSERT(0); + return cbOperand; +} + + +/* + * Test type #1. + */ + +typedef struct BS3CPUINSTR3_TEST1_VALUES_T +{ + RTUINT256U uSrc2; + RTUINT256U uSrc1; /**< uDstIn for MMX & SSE */ + RTUINT256U uDstOut; +} BS3CPUINSTR3_TEST1_VALUES_T; + +typedef struct BS3CPUINSTR3_TEST1_T +{ + FPFNBS3FAR pfnWorker; + uint8_t bAvxMisalignXcpt; + uint8_t enmRm; + uint8_t enmType; + uint8_t iRegDst; + uint8_t iRegSrc1; + uint8_t iRegSrc2; + uint8_t cValues; + BS3CPUINSTR3_TEST1_VALUES_T const BS3_FAR *paValues; +} BS3CPUINSTR3_TEST1_T; + +typedef struct BS3CPUINSTR3_TEST1_MODE_T +{ + BS3CPUINSTR3_TEST1_T const BS3_FAR *paTests; + unsigned cTests; +} BS3CPUINSTR3_TEST1_MODE_T; + +/** Initializer for a BS3CPUINSTR3_TEST1_MODE_T array (three entries). */ +#define BS3CPUINSTR3_TEST1_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ + { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } + + +/** + * Test type #1 worker. + */ +static uint8_t bs3CpuInstr3_WorkerTestType1(uint8_t bMode, BS3CPUINSTR3_TEST1_T const BS3_FAR *paTests, unsigned cTests, + PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs) +{ + BS3REGCTX Ctx; + BS3TRAPFRAME TrapFrame; + const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); + uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; + uint8_t BS3_FAR *pbBuf = g_pbBuf; + uint32_t cbBuf = g_cbBuf; + PBS3EXTCTX pExtCtxOut; + PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); + if (!pExtCtx) + return 0; + + /* Ensure the structures are allocated before we sample the stack pointer. */ + Bs3MemSet(&Ctx, 0, sizeof(Ctx)); + Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); + + /* + * Create test context. + */ + pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); + Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); + bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); + //Bs3TestPrintf("FTW=%#x mm1/st1=%.16Rhxs\n", pExtCtx->Ctx.x87.FTW, &pExtCtx->Ctx.x87.aRegs[1]); + + /* + * Run the tests in all rings since alignment issues may behave + * differently in ring-3 compared to ring-0. + */ + for (;;) + { + unsigned iCfg; + for (iCfg = 0; iCfg < cConfigs; iCfg++) + { + unsigned iTest; + BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; + if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) + continue; /* unsupported config */ + + /* + * Iterate the tests. + */ + for (iTest = 0; iTest < cTests; iTest++) + { + BS3CPUINSTR3_TEST1_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; + uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; + unsigned const cValues = paTests[iTest].cValues; + bool const fMmxInstr = paTests[iTest].enmType < T_SSE; + bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; + bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; + uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 + : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; + uint8_t const cbMemOp = bs3CpuInstr3MemOpSize(cbOperand, paTests[iTest].enmRm); + uint8_t const cbAlign = cbMemOp; + PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]); + uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD + : fMmxInstr ? paConfigs[iCfg].bXcptMmx + : fSseInstr ? paConfigs[iCfg].bXcptSse + : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; + uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; + unsigned iVal; + + /* If testing unaligned memory accesses, skip register-only tests. This allows + setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ + if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck)) + continue; + + /* #AC is only raised in ring-3.: */ + if (bXcptExpect == X86_XCPT_AC) + { + if (bRing != 3) + bXcptExpect = X86_XCPT_DB; + else if (fAvxInstr) + bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ + } + + Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); + + /* + * Iterate the test values and do the actual testing. + */ + for (iVal = 0; iVal < cValues; iVal++, idTestStep++) + { + uint16_t cErrors; + uint16_t uSavedFtw = 0xff; + RTUINT256U uMemOpExpect; + + /* + * Set up the context and some expectations. + */ + /* dest */ + if (paTests[iTest].iRegDst == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + Bs3MemSet(puMemOp, 0xcc, cbMemOp); + if (bXcptExpect == X86_XCPT_DB) + uMemOpExpect = paValues[iVal].uDstOut; + else + Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); + } + else if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, ~paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_ZERO); + + /* source #1 (/ destination for MMX and SSE) */ + if (paTests[iTest].iRegSrc1 == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + Bs3MemCpy(puMemOp, &paValues[iVal].uSrc1, cbMemOp); + if (paTests[iTest].iRegDst == UINT8_MAX) + BS3_ASSERT(fSseInstr); + else + uMemOpExpect = paValues[iVal].uSrc1; + } + else if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc1, paValues[iVal].uSrc1.QWords.qw0, BS3EXTCTXTOPMM_ZERO); + else if (fSseInstr) + Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1.DQWords.dqw0); + else + Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1, 32); + + /* source #2 */ + if (paTests[iTest].iRegSrc2 == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX && paTests[iTest].iRegSrc1 != UINT8_MAX); + Bs3MemCpy(puMemOp, &paValues[iVal].uSrc2, cbMemOp); + uMemOpExpect = paValues[iVal].uSrc2; + } + else if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, paValues[iVal].uSrc2.QWords.qw0, BS3EXTCTXTOPMM_ZERO); + else if (fSseInstr) + Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2.DQWords.dqw0); + else + Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2, 32); + + /* Memory pointer. */ + if (paTests[iTest].enmRm >= RM_MEM) + { + BS3_ASSERT( paTests[iTest].iRegDst == UINT8_MAX + || paTests[iTest].iRegSrc1 == UINT8_MAX + || paTests[iTest].iRegSrc2 == UINT8_MAX); + Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); + } + + /* + * Execute. + */ + Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); + + /* + * Check the result: + */ + cErrors = Bs3TestSubErrorCount(); + + if (fMmxInstr && bXcptExpect == X86_XCPT_DB) + { + uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); + Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); /* Observed on 10980xe after pxor mm1, mm2. */ + } + if (bXcptExpect == X86_XCPT_DB && paTests[iTest].iRegDst != UINT8_MAX) + { + if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegDst, paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_SET); + else if (fSseInstr) + Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut.DQWords.dqw0); + else + Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut, cbOperand); + } + Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); + + if (TrapFrame.bXcpt != bXcptExpect) + Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); + + /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ + if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) + { + if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) + Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); + TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; + } + Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, + bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, + pszMode, idTestStep); + + if ( paTests[iTest].enmRm >= RM_MEM + && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0) + Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp); + + if (cErrors != Bs3TestSubErrorCount()) + { + if (paConfigs[iCfg].fAligned) + Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)", + bRing, iCfg, iTest, iVal, bXcptExpect); + else + Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", + bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); + Bs3TestPrintf("\n"); + } + + if (uSavedFtw != 0xff) + Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); + } + } + + bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); + } + + /* + * Next ring. + */ + bRing++; + if (bRing > 3 || bMode == BS3_MODE_RM) + break; + Bs3RegCtxConvertToRingX(&Ctx, bRing); + } + + /* + * Cleanup. + */ + bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); + bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); + return 0; +} + + +/* + * PAND, VPAND, ANDPS, VANDPS, ANDPD, VANDPD. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pand_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andps_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andps_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andpd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andpd_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vandpd_YMM10_YMM8_YMM15_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_andps_andpd_pand(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x5555666677770000, 0x1111222233334444, 0x1111222233334444, 0x5555666677770000) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0x0c09d02808403294, 0x385406c840621622, 0x8000290816080282, 0x0050c020030090b9) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pand_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pand_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pand_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pand_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_andps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_andps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_andpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_andpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pand_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pand_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pand_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pand_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_andps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_andps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_andpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_andpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pand_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pand_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pand_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pand_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpand_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpand_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpand_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpand_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_andps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_andps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_andpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_andpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues }, + }; + + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * PANDN, VPANDN, ANDNPS, VANDNPS, ANDNPD, VANDNPD. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pandn_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnps_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnps_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnpd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vandnpd_YMM10_YMM8_YMM15_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_andnps_andnpd_pandn(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x0000000000008888, 0x0000000000000000, 0x0000000000000000, 0x0000000000008888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0x41002002649c4141, 0x06a01100260929c4, 0x342106a040449920, 0x9c0c205390090602) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pandn_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pandn_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pandn_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pandn_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_andnps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_andnps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_andnpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pandn_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pandn_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pandn_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pandn_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_andnps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_andnps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_andnpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pandn_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pandn_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pandn_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pandn_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpandn_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpandn_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpandn_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpandn_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_andnps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_andnps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_andnpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_andnpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vandnpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues }, + }; + + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + + +/* + * POR, VPOR, PORPS, VORPS, PORPD, VPORPD. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_por_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orps_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orps_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orpd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_orpd_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vorpd_YMM10_YMM8_YMM15_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_orps_orpd_por(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0xddddeeeeffff8888, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff8888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0x5fddfdae6dff73d5, 0xfffc9fec667b7ff7, 0xbc21effbffddfbe3, 0xdfdfedf3b38d9fff) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_por_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_por_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_por_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_por_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_orps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_orps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_orpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_orpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_por_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_por_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_por_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_por_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_orps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_orps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_orpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_orpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_por_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_por_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_por_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_por_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpor_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpor_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpor_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpor_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_orps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_orps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_orpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_orpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vorpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * PXOR, VPXOR, XORPS, VXORPS, XORPD, VXORPD. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pxor_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pxor_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pxor_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pxor_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_xorps_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_xorps_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_xorpd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vxorpd_YMM10_YMM8_YMM15_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_xorps_xorpd_pxor(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* ^ */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* ^ */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x8888888888888888, 0x8888888888888888, 0x8888888888888888, 0x8888888888888888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* ^ */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0x53d42d8665bf4141, 0xc7a89924261969d5, 0x3c21c6f3e9d5f961, 0xdf8f2dd3b08d0f46) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pxor_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pxor_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pxor_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pxor_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_xorps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_xorps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_xorpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pxor_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pxor_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pxor_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pxor_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_xorps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_xorps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_xorpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pxor_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pxor_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pxor_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pxor_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpxor_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpxor_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpxor_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpxor_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_xorps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_xorps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorps_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorps_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorps_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorps_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_xorpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_xorpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorpd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorpd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorpd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorpd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vxorpd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + + +/* + * PCMPGTB, VPCMPGTB, PCMPGTW, VPCMPGTW, PCMPGTD, VPCMPGTD, PCMPGTQ, VPCMPGTQ. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpcmpgtd_YMM10_YMM8_YMM15_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpgtq_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_XMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_YMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpcmpgtq_YMM10_YMM8_YMM15_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pcmpgtb_pcmpgtw_pcmpgtd_pcmpgtq(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* < */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x000000000000ffff, 0x0000000000000000, 0x0000000000000000, 0x000000000000ffff) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* < */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0x0000000000ff0000, 0x00ff00ff00ffffff, 0x000000ff0000ffff, 0xff000000ff00ffff) }, + }; + + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* < */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x000000000000ffff, 0x0000000000000000, 0x0000000000000000, 0x000000000000ffff) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* ^ */ RTUINT256_INIT_C(0x1eddddac77733294, 0xf95c8eec40725633, 0x3333e95bbf9962c3, 0x43d3cda0238499fd), /* modified 1st and 3rd value */ + /* = */ RTUINT256_INIT_C(0x00000000ffff0000, 0x000000000000ffff, 0xffff00000000ffff, 0xffff0000ffffffff) }, + }; + + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* < */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* < */ RTUINT256_INIT_C(0x555dddac09633294, 0xf95c8eec77725633, 0x7770e95bbf9962c3, 0x43d3cda0238499fd), /* modified 1st, 2nd and 3rd value */ + /* = */ RTUINT256_INIT_C(0xffffffff00000000, 0x00000000ffffffff, 0xffffffff00000000, 0xffffffffffffffff) }, + }; + + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* < */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* < */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* < */ RTUINT256_INIT_C(0x77ddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), /* modified 1st value */ + /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0x0000000000000000, 0xffffffffffffffff) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + + { bs3CpuInstr3_pcmpgtq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_pcmpgtq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + + { bs3CpuInstr3_pcmpgtq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_pcmpgtq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pcmpgtb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpgtb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpgtb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpgtb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpgtb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpgtb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pcmpgtw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpgtw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpgtw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpgtw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpgtw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpgtw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pcmpgtd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpgtd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpgtd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpgtd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpgtd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpgtd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpgtd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + + { bs3CpuInstr3_pcmpgtq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesQ }, + { bs3CpuInstr3_pcmpgtq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesQ }, + { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesQ }, + { bs3CpuInstr3_vpcmpgtq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesQ }, + { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesQ }, + { bs3CpuInstr3_vpcmpgtq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesQ }, + { bs3CpuInstr3_vpcmpgtq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesQ }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * PCMPEQB, VPCMPEQB, PCMPEQW, VPCMPEQW, PCMPEQD, VPCMPEQD, PCMPEQQ, VPCMPEQQ. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpcmpeqd_YMM10_YMM8_YMM15_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pcmpeqq_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_XMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_YMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpcmpeqq_YMM10_YMM8_YMM15_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pcmpeqb_pcmpeqw_pcmpeqd_pcmpeqq(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, + { RTUINT256_INIT_C(0x4dddf02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* ==*/ RTUINT256_INIT_C(0x1eddddac09dc3294, 0xf95c17ec667256e6, 0xb400e95bbf999bc3, 0x9cd3cda0230999fd), /* modified all to get some matches */ + /* = */ RTUINT256_INIT_C(0x00ff000000ff0000, 0x0000ff00ff0000ff, 0xff0000000000ff00, 0xff00000000ff0000) }, + }; + + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* ==*/ RTUINT256_INIT_C(0x1eddf02a6cdc3294, 0x3ef48eec666b5633, 0x88002fa8bf999ba2, 0x9c5ccda0238496bb), /* modified all to get some matches */ + /* = */ RTUINT256_INIT_C(0x0000ffffffff0000, 0xffff0000ffff0000, 0x0000ffff0000ffff, 0xffff00000000ffff) }, + }; + + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* ==*/ RTUINT256_INIT_C(0x4d09f02a09633294, 0x3ef417c8666b3fe6, 0x8800e95b564c9ba2, 0x9c5ce073238499fd), /* modified all to get some matches */ + /* = */ RTUINT256_INIT_C(0xffffffff00000000, 0xffffffffffffffff, 0x00000000ffffffff, 0xffffffff00000000) }, + }; + + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* ==*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* ==*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* ==*/ RTUINT256_INIT_C(0x1eddddac09633294, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x43d3cda0238499fd), /* modified 2nd and 3rd to get some matches */ + /* = */ RTUINT256_INIT_C(0x0000000000000000, 0xffffffffffffffff, 0xffffffffffffffff, 0x0000000000000000) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + + { bs3CpuInstr3_pcmpeqq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_pcmpeqq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + + { bs3CpuInstr3_pcmpeqq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_pcmpeqq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pcmpeqb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpeqb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpeqb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pcmpeqb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpeqb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpcmpeqb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pcmpeqw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpeqw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpeqw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pcmpeqw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpeqw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpcmpeqw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pcmpeqd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpeqd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpeqd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pcmpeqd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpeqd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpeqd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpcmpeqd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + + { bs3CpuInstr3_pcmpeqq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_pcmpeqq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpeqq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpeqq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpcmpeqq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * PADDB, VPADDB, PADDW, VPADDW, PADDD, VPADDD, PADDQ, VPADDQ. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddb_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddb_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddb_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddb_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddb_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddb_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddb_YMM7_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddb_YMM7_YMM2_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddw_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddw_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddw_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddw_YMM1_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddw_YMM1_YMM1_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddd_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddd_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddd_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddd_XMM2_XMM1_XMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddd_XMM2_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddd_YMM2_YMM1_YMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddd_YMM2_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpaddd_YMM10_YMM8_YMM15_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddq_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddq_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_paddq_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddq_XMM2_XMM1_XMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddq_XMM2_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddq_YMM2_YMM1_YMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpaddq_YMM2_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpaddq_YMM10_YMM8_YMM15_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_paddb_paddw_paddd_paddq(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* + */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x3232545476768888, 0xaaaacccceeee1010, 0xaaaacccceeee1010, 0x3232545476768888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0x6be6cdd6753fa569, 0x3750a5b4a6dd9519, 0x3c21180315e5fd65, 0xdf2fad13b68d2fb8) }, + }; + + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* + */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x3332555477768888, 0xaaaacccceeee1110, 0xaaaacccceeee1110, 0x3332555477768888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0x6be6cdd6763fA669, 0x3850A6B4A6DD9619, 0x3C21190315E5FE65, 0xE02FAE13B68D30B8) }, + }; + + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* + */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x3333555477768888, 0xAAAACCCCEEEF1110, 0xAAAACCCCEEEF1110, 0x3333555477768888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0x6BE7CDD6763FA669, 0x3850A6B4A6DD9619, 0x3C22190315E5FE65, 0xE030AE13B68E30B8) }, + }; + + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* + */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x3333555577768888, 0xAAAACCCCEEEF1110, 0xAAAACCCCEEEF1110, 0x3333555577768888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0x6BE7CDD6763FA669, 0x3850A6B4A6DD9619, 0x3C22190415E5FE65, 0xE030AE13B68E30B8) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_paddb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_paddb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_paddb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_paddb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpaddb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpaddb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpaddb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpaddb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_paddw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_paddw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_paddw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_paddw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpaddw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpaddw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpaddw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpaddw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_paddd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_paddd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_paddd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_paddd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpaddd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpaddd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpaddd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpaddd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + + { bs3CpuInstr3_paddq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_paddq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_paddq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_paddq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpaddq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpaddq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpaddq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpaddq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_paddb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_paddb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_paddb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_paddb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpaddb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpaddb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpaddb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpaddb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_paddw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_paddw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_paddw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_paddw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpaddw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpaddw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpaddw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpaddw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_paddd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_paddd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_paddd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_paddd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpaddd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpaddd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpaddd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpaddd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + + { bs3CpuInstr3_paddq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_paddq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_paddq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_paddq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpaddq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpaddq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpaddq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpaddq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_paddb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_paddb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_paddb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_paddb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpaddb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpaddb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpaddb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpaddb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_paddw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_paddw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_paddw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_paddw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpaddw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpaddw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpaddw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpaddw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_paddd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_paddd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_paddd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_paddd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpaddd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpaddd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpaddd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpaddd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpaddd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + + { bs3CpuInstr3_paddq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_paddq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_paddq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_paddq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpaddq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpaddq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpaddq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpaddq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpaddq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * PSUBB, VPSUBB, PSUBW, VPSUBW, PSUBD, VPSUBD, PSUBQ, VPSUBQ. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubb_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubb_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubb_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubb_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubb_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubb_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubb_YMM7_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubb_YMM7_YMM2_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubw_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubw_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubw_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubw_YMM1_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubw_YMM1_YMM1_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubd_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubd_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubd_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubd_XMM2_XMM1_XMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubd_XMM2_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubd_YMM2_YMM1_YMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubd_YMM2_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpsubd_YMM10_YMM8_YMM15_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubq_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubq_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psubq_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubq_XMM2_XMM1_XMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubq_XMM2_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubq_YMM2_YMM1_YMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpsubq_YMM10_YMM8_YMM15_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psubb_psubw_psubd_psubq(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* + */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x8888888888887878, 0x8888888888888888, 0x8888888888888888, 0x8888888888887878) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0xd1d4ed829d87bfbf, 0xbb687724da07174d, 0xd4dfbab3694dc721, 0xa777ed2d907b0342) }, + }; + + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* + */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x8888888888887778, 0x8888888888888888, 0x8888888888888888, 0x8888888888887778) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0xd1d4ed829c87bebf, 0xba687724da07164d, 0xd3dfb9b3694dc721, 0xa777ed2d907b0342) }, + }; + + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* + */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x8888888888877778, 0x8888888888888888, 0x8888888888888888, 0x8888888888877778) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0xd1d3ed829c86bebf, 0xba687724da07164d, 0xd3dfb9b3694cc721, 0xa776ed2d907b0342) }, + }; + + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesQ[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* + */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* + */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x8888888888877778, 0x8888888888888888, 0x8888888888888888, 0x8888888888877778) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* + */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0xd1d3ed819c86bebf, 0xba687723da07164d, 0xd3dfb9b3694cc721, 0xa776ed2c907b0342) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_psubb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psubb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psubb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psubb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsubb_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsubb_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsubb_YMM7_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsubb_YMM7_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_psubw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psubw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psubw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psubw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsubw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsubw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsubw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsubw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_psubd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psubd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psubd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psubd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsubd_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsubd_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsubd_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsubd_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + + { bs3CpuInstr3_psubq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_psubq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_psubq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_psubq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpsubq_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpsubq_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpsubq_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_psubb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psubb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psubb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psubb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsubb_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsubb_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsubb_YMM7_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsubb_YMM7_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_psubw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psubw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psubw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psubw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsubw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsubw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsubw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsubw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_psubd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psubd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psubd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psubd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsubd_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsubd_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsubd_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsubd_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + + { bs3CpuInstr3_psubq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_psubq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_psubq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_psubq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpsubq_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpsubq_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpsubq_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_psubb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psubb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psubb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psubb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsubb_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsubb_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsubb_YMM7_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX_256, 7, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsubb_YMM7_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 7, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_psubw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psubw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psubw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psubw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsubw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsubw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsubw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsubw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_psubd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psubd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psubd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psubd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsubd_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsubd_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsubd_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsubd_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsubd_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + + { bs3CpuInstr3_psubq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_psubq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_psubq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_psubq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpsubq_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpsubq_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpsubq_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpsubq_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + { bs3CpuInstr3_vpsubq_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesQ), s_aValuesQ }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * PMULLW, VPMULLW, PMULLD, VPMULLD. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmullw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmullw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmullw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmullw_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmullw_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmullw_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmullw_YMM1_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmullw_YMM1_YMM1_FSxBX_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulld_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulld_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulld_XMM2_XMM1_XMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulld_XMM2_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulld_YMM2_YMM1_YMM0_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulld_YMM2_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmulld_YMM10_YMM8_YMM15_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmulld_YMM10_YMM8_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmullw_pmulld(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* * */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x0b6106d488890000, 0x5c293e94a7419630, 0x5c293e94a7419630, 0x0b6106d488890000) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0x8ec59e38d5149124, 0xf3b0dc605ba6fed2, 0x8800d8b8476c9066, 0xf3d45ee00ba4b9cf) }, + }; + + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* * */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x2ea606d477780000, 0x6e5d3e9430ec9630, 0x6e5d3e9430ec9630, 0x2ea606d477780000) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0x97439e3846719124, 0x8216dc606340fed2, 0x7c2bd8b8f1c09066, 0x31915ee054fbb9cf) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pmullw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmullw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmullw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmullw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmullw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmullw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmullw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmullw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pmulld_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pmulld_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmulld_XMM2_XMM1_XMM0_icebp_c16, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmulld_XMM2_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmulld_YMM2_YMM1_YMM0_icebp_c16, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmulld_YMM2_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pmullw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmullw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmullw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmullw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmullw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmullw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmullw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmullw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pmulld_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pmulld_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmulld_XMM2_XMM1_XMM0_icebp_c32, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmulld_XMM2_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmulld_YMM2_YMM1_YMM0_icebp_c32, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmulld_YMM2_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pmullw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmullw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmullw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmullw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmullw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmullw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmullw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmullw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pmulld_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pmulld_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmulld_XMM2_XMM1_XMM0_icebp_c64, 255, RM_REG, T_AVX_128, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmulld_XMM2_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmulld_YMM2_YMM1_YMM0_icebp_c64, 255, RM_REG, T_AVX_256, 2, 1, 0, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmulld_YMM2_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 2, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmulld_YMM10_YMM8_YMM15_icebp_c64, 255, RM_REG, T_AVX_256, 10, 8, 15, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmulld_YMM10_YMM8_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 10, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * PMULHW, VPMULHW. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhw_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhw_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhw_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp); + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmulhw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* * */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0xf49ff92cffff0000, 0xf92cf49ff258f258, 0xf92cf49ff258f258, 0xf49ff92cffff0000) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0x0949021f03fd16e2, 0xfe5df57e19c81583, 0x2390fbc8ea4ad947, 0xe5990635f0e229f2) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pmulhw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pmulhw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pmulhw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * PMULHUW, VPMULHUW. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhuw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhuw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhuw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhuw_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhuw_XMM1_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhuw_XMM1_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhuw_YMM1_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhuw_YMM1_YMM1_FSxBX_icebp); + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmulhuw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* * */ RTUINT256_INIT_C(0, 0, 0, 0), + /* = */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* * */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* = */ RTUINT256_INIT_C(0x49f45f9277760000, 0x0a3d16c1258b369c, 0x0a3d16c1258b369c, 0x49f45f9277760000) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* * */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* = */ RTUINT256_INIT_C(0x0949cff503fd16e2, 0x3d510d4619c81583, 0x5fb12b7040963c0a, 0x296cb44814665aaa) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pmulhuw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhuw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhuw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhuw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pmulhuw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhuw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhuw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhuw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pmulhuw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhuw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhuw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmulhuw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhuw_XMM1_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmulhuw_YMM1_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * PSHUFB + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufb_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufb_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufb_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufb_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pshufb_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pshufb_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufb_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufb_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpshufb_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpshufb_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufb_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufb_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpshufb_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpshufb_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_pshufb(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = + { + { /*mask*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /*val*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, + { /*mask*/ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff), + /*val*/ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0000000000000000) }, + { /*mask*/ RTUINT256_INIT_C( 1, 2, 3, 0x7f7f7f7f7f7f7f7f), + /*val*/ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xffffffffffffffff) }, + { /*mask*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), + /*val*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C( 8, 10, 11, 0xeeeedddddddd0000) }, + { /*mask*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), + /*val*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x00a0002300990000) }, + }; + + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = + { + { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*val*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /*val*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, + { /*mask*/ RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), + /*val*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { /*mask*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*val*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0xaaaa999999990000, 0xccccbbbbbbbbaaaa, 0x0000ffffffffeeee, 0xeeeedddddddd0000) }, + { /*mask*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*val*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0xdd320063ac004000, 0xdd00f9005c091e00, 0x00998800d35b0000, 0x005b002300620000) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pshufb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_pshufb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_pshufb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_pshufb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pshufb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_pshufb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_pshufb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_pshufb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pshufb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_pshufb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_pshufb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_pshufb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_pshufb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_pshufb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpshufb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PUNPCKHBW + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhbw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhbw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhbw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhbw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_punpckhbw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_punpckhbw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpckhbw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpckhbw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpckhbw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpckhbw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhbw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = + { + { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), + /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1e1f2e2f3e3f4e4) }, + { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x55dd55dd66ee66ee) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9c435cd3e0cd73a0) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1b1f2b2f3b3f4b4, 0xf5b5f6b6f7b7f8b8, 0xd191d292d393d494, 0xd595d696d797d898) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x55dd55dd66ee66ee, 0x77ff77ff88008800, 0x1199119922aa22aa, 0x33bb33bb44cc44cc) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d1e09ddf0dd2aac, 0x6c09dc637332d594, 0xb48821002fe9a85b, 0x56bf4c999b62a2c3) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_punpckhbw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhbw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhbw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_punpckhbw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhbw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhbw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_punpckhbw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhbw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhbw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhbw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhbw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhbw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PUNPCKHWD + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhwd_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhwd_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhwd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhwd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_punpckhwd_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_punpckhwd_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpckhwd_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpckhwd_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpckhwd_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpckhwd_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhwd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = + { + { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), + /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2e1e2f3f4e3e4) }, + { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x5555dddd6666eeee) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9c5c43d3e073cda0) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2b1b2f3f4b3b4, 0xf5f6b5b6f7f8b7b8, 0xd1d29192d3d49394, 0xd5d69596d7d89798) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x5555dddd6666eeee, 0x7777ffff88880000, 0x111199992222aaaa, 0x3333bbbb4444cccc) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d091eddf02addac, 0x6cdc096373d53294, 0xb42188002fa8e95b, 0x564cbf999ba262c3) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_punpckhwd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhwd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhwd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_punpckhwd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhwd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhwd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_punpckhwd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhwd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhwd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhwd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhwd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhwd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PUNPCKHDQ + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhdq_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhdq_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhdq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhdq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_punpckhdq_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_punpckhdq_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpckhdq_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpckhdq_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpckhdq_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpckhdq_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhdq(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = + { + { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), + /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4e1e2e3e4) }, + { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x55556666ddddeeee) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9c5ce07343d3cda0) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4b1b2b3b4, 0xf5f6f7f8b5b6b7b8, 0xd1d2d3d491929394, 0xd5d6d7d895969798) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x55556666ddddeeee, 0x77778888ffff0000, 0x111122229999aaaa, 0x33334444bbbbcccc) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d09f02a1eddddac, 0x6cdc73d509633294, 0xb4212fa88800e95b, 0x564c9ba2bf9962c3) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_punpckhdq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhdq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_punpckhdq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhdq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_punpckhdq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhdq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckhdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhdq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhdq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhdq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PUNPCKHQDQ + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhqdq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckhqdq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_punpckhqdq_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_punpckhqdq_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpckhqdq_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpckhqdq_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpckhqdq_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpckhqdq_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhqdq(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xb1b2b3b4b5b6b7b8, 0xd1d2d3d4d5d6d7d8, 0x9192939495969798) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x5555666677778888, 0xddddeeeeffff0000, 0x1111222233334444, 0x9999aaaabbbbcccc) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x1eddddac09633294, 0xb4212fa8564c9ba2, 0x8800e95bbf9962c3) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_punpckhqdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhqdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_punpckhqdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhqdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_punpckhqdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhqdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhqdq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckhqdq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckhqdq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PUNPCKLBW + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklbw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklbw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklbw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklbw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_punpcklbw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_punpcklbw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpcklbw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpcklbw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpcklbw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpcklbw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpcklbw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = + { + { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), + /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf5e5f6e6f7e7f8e8) }, + { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x77ff77ff88008800) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x932309849699bbfd) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xe1a1e2a2e3a3e4a4, 0xe5a5e6a6e7a7e8a8, 0xc181c282c383c484, 0xc585c686c787c888) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x1199119922aa22aa, 0x33bb33bb44cc44cc, 0x55dd55dd66ee66ee, 0x77ff77ff88008800) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x3ef9f45c178ec8ec, 0x66406b723f56e633, 0x9c435cd3e0cd73a0, 0x932309849699bbfd) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_punpcklbw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpcklbw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpcklbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpcklbw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_punpcklbw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpcklbw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpcklbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpcklbw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_punpcklbw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpcklbw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpcklbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpcklbw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpcklbw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpcklbw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklbw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PUNPCKLWD + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklwd_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklwd_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklwd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklwd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_punpcklwd_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_punpcklwd_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpcklwd_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpcklwd_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpcklwd_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpcklwd_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpcklwd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = + { + { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), + /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf5f6e5e6f7f8e7e8) }, + { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x7777ffff88880000) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9309238496bb99fd) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xe1e2a1a2e3e4a3a4, 0xe5e6a5a6e7e8a7a8, 0xc1c28182c3c48384, 0xc5c68586c7c88788) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x111199992222aaaa, 0x3333bbbb4444cccc, 0x5555dddd6666eeee, 0x7777ffff88880000) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x3ef4f95c17c88eec, 0x666b40723fe65633, 0x9c5c43d3e073cda0, 0x9309238496bb99fd) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_punpcklwd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpcklwd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpcklwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpcklwd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_punpcklwd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpcklwd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpcklwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpcklwd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_punpcklwd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpcklwd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpcklwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpcklwd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpcklwd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpcklwd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklwd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PUNPCKLDQ + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckldq_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckldq_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckldq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpckldq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_punpckldq_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_punpckldq_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckldq_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckldq_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpckldq_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpckldq_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckldq_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpckldq_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpckldq_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpckldq_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckldq(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = + { + { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), + /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf5f6f7f8e5e6e7e8) }, + { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x77778888ffff0000) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x930996bb238499fd) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xe1e2e3e4a1a2a3a4, 0xe5e6e7e8a5a6a7a8, 0xc1c2c3c481828384, 0xc5c6c7c885868788) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x111122229999aaaa, 0x33334444bbbbcccc, 0x55556666ddddeeee, 0x77778888ffff0000) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x3ef417c8f95c8eec, 0x666b3fe640725633, 0x9c5ce07343d3cda0, 0x930996bb238499fd) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_punpckldq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckldq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckldq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckldq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_punpckldq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckldq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckldq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckldq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_punpckldq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckldq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_punpckldq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckldq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckldq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpckldq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpckldq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PUNPCKLQDQ + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklqdq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_punpcklqdq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_punpcklqdq_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_punpcklqdq_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpcklqdq_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpcklqdq_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpunpcklqdq_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpunpcklqdq_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpcklqdq(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xe1e2e3e4e5e6e7e8, 0xa1a2a3a4a5a6a7a8, 0xc1c2c3c4c5c6c7c8, 0x8182838485868788) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x1111222233334444, 0x9999aaaabbbbcccc, 0x5555666677778888, 0xddddeeeeffff0000) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x3ef417c8666b3fe6, 0xf95c8eec40725633, 0x9c5ce073930996bb, 0x43d3cda0238499fd) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_punpcklqdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpcklqdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_punpcklqdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpcklqdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_punpcklqdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpcklqdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpcklqdq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_punpcklqdq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpunpcklqdq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PACKSSWB + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packsswb_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packsswb_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packsswb_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packsswb_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_packsswb_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_packsswb_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpacksswb_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpacksswb_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpacksswb_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpacksswb_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpacksswb_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpacksswb_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpacksswb_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpacksswb_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packsswb(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = + { + { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), + /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x8080808080808080) }, + { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x7f7f7f808080ff00) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x808080807f807f80) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xFF820064fffe0042), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x8264fe4222808081) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x7f7f7f807f7f7f7f, 0x8080ff0080808080, 0x7f7f7f7f7f7f7f80, 0x808080808080ff00) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x7f807f7f7f7f7f7f, 0x7f807f7f80807f7f, 0x807f7f8080808080, 0x8080807f7f807f80) }, + { /*src2*/ RTUINT256_INIT_C(0x002200250079007e, 0xfffffffeff88ff7f, 0x0064003200160008, 0x0042004600880080), + /*src1*/ RTUINT256_INIT_C(0x0001000200030005, 0x0007000b000d0011, 0x00130017001d0025, 0x0029002b002f0035), + /* => */ RTUINT256_INIT_C(0x2225797efffe8880, 0x01020305070b0d11, 0x6432160842467f7f, 0x13171d25292b2f35) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_packsswb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packsswb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packsswb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packsswb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_packsswb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packsswb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packsswb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packsswb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_packsswb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packsswb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packsswb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packsswb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packsswb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packsswb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpacksswb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PACKSSDW + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packssdw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packssdw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packssdw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packssdw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_packssdw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_packssdw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackssdw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackssdw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpackssdw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpackssdw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackssdw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackssdw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpackssdw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpackssdw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packssdw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = + { + { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), + /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x8000800080008000) }, + { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C( 8, 10, 11, 0x7fff7fff80008000) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x800080007fff7fff) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xffff898400007495), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x00002222ffff9485), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x8984749522229485) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x8000800080008000, 0x8000800080008000, 0x8000800080008000, 0x8000800080008000) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x7fff7fff7fff7fff, 0x8000800080008000, 0x7fff7fff7fff7fff, 0x8000800080008000) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x7fff7fff7fff7fff, 0x7fff7fff80007fff, 0x80007fff80008000, 0x800080007fff7fff) }, + { /*src2*/ RTUINT256_INIT_C(0x0000349000002349, 0xffffa230ffffe384, 0xffff348300007ffe, 0x00008000ffff7fff), + /*src1*/ RTUINT256_INIT_C(0xffff800100007ffe, 0xffffcbaffffffffe, 0x0000643200001608, 0xffffffe0ffffffc0), + /* => */ RTUINT256_INIT_C(0x34902349a230e384, 0x80017ffecbaffffe, 0x80007ffe7fff8000, 0x64321608ffe0ffc0) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_packssdw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packssdw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packssdw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packssdw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_packssdw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packssdw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packssdw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packssdw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_packssdw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packssdw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packssdw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packssdw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packssdw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packssdw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackssdw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PACKUSWB + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packuswb_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packuswb_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packuswb_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packuswb_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_packuswb_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_packuswb_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackuswb_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackuswb_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpackuswb_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpackuswb_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackuswb_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackuswb_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpackuswb_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpackuswb_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packuswb(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64[] = + { + { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), + /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0000000000000000) }, + { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C( 8, 10, 11, 0xffffff0000000000) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x00000000ff00ff00) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xFF820064fffe0042), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x0064004222000000) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0xffffff00ffffffff, 0x0000000000000000, 0xffffffffffffff00, 0x000000000000000) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0xff00ffffffffffff, 0xff00ffff0000ffff, 0x00ffff0000000000, 0x000000ffff00ff00) }, + { /*src2*/ RTUINT256_INIT_C(0x002200250079007e, 0xfffffffeff88ff7f, 0x0064003200160008, 0x0042004600880080), + /*src1*/ RTUINT256_INIT_C(0x0001000200030005, 0x0007000b000d0011, 0x00130017001d0025, 0x0029002b002f0035), + /* => */ RTUINT256_INIT_C(0x2225797e00000000, 0x01020305070b0d11, 0x6432160842468880, 0x13171d25292b2f35) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_packuswb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packuswb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packuswb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packuswb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_packuswb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packuswb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packuswb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packuswb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_packuswb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX, 1, 1, 2, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packuswb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX, 1, 1, 255, RT_ELEMENTS(s_aValues64), s_aValues64 }, + { bs3CpuInstr3_packuswb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packuswb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packuswb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packuswb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackuswb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PACKUSDW + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packusdw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_packusdw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_packusdw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_packusdw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackusdw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackusdw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpackusdw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpackusdw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackusdw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpackusdw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpackusdw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpackusdw_YMM8_YMM9_FSxBX_icebp_c64; +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_packusdw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesOthers[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0x0000000000000000, 0xffffffffffffffff, 0x0000000000000000) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffff0000ffff, 0x0000ffff00000000, 0x00000000ffffffff) }, + { /*src2*/ RTUINT256_INIT_C(0x0000349000002349, 0xffffa230ffffe384, 0xffff348300007ffe, 0x00008000ffff7fff), + /*src1*/ RTUINT256_INIT_C(0xffff800100007ffe, 0xffffcbaffffffffe, 0x0000643200001608, 0xffffffe0ffffffc0), + /* => */ RTUINT256_INIT_C(0x3490234900000000, 0x00007ffe00000000, 0x00007ffe80000000, 0x6432160800000000) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_packusdw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packusdw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_packusdw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packusdw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_packusdw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packusdw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packusdw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_packusdw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + { bs3CpuInstr3_vpackusdw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesOthers), s_aValuesOthers }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PMAXUB - Compare unsigned byte integers and returns maximum values. + * [V]PMAXUW - Compare unsigned word integers and returns maximum values. + * [V]PMAXUD - Compare unsigned double word integers and returns maximum values. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxub_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxub_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxub_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmaxub_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmaxub_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxub_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxub_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmaxub_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmaxub_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxub_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxub_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmaxub_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmaxub_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxuw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxuw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmaxuw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmaxuw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxuw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxuw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmaxuw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmaxuw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxuw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxuw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmaxuw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmaxuw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxud_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxud_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmaxud_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmaxud_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxud_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxud_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmaxud_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmaxud_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxud_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxud_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmaxud_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmaxud_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmaxub_pmaxuw_pmaxud(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB64[] = + { + { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), + /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8) }, + { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff8888) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9cd3e0a0938499fd) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xff820064fffe0042), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0xff82fe64fffeff81) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4dddf0ac6cdc73d5, 0xf9f48eec667256e6, 0xb421e9a8bf999bc3, 0x9cd3e0a0938499fd) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0xf95c8eec666b5633, 0xb421e95bbf999ba2, 0x9c5ce073930999fd) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0xf95c8eec666b3fe6, 0xb4212fa8bf9962c3, 0x9c5ce073930996bb) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pmaxub_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pmaxub_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pmaxub_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pmaxuw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmaxuw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pmaxud_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pmaxud_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pmaxub_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pmaxub_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pmaxub_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pmaxuw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmaxuw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pmaxud_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pmaxud_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pmaxub_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pmaxub_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pmaxub_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pmaxub_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pmaxub_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pmaxub_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxub_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pmaxuw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmaxuw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmaxuw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmaxuw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxuw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pmaxud_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pmaxud_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pmaxud_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pmaxud_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxud_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PMAXSB - Compare signed byte integers and returns maximum values. + * [V]PMAXSW - Compare signed word integers and returns maximum values. + * [V]PMAXSD - Compare signed double word integers and returns maximum values. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsb_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsb_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmaxsb_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmaxsb_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsb_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsb_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmaxsb_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmaxsb_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsb_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsb_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmaxsb_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmaxsb_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmaxsw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmaxsw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmaxsw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmaxsw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmaxsw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmaxsw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaxsd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmaxsd_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmaxsd_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsd_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsd_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmaxsd_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmaxsd_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsd_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaxsd_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmaxsd_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmaxsd_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmaxsb_pmaxsw_pmaxsd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB64[] = + { + { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), + /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8) }, + { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C( 4, 6, 7, 0x5555666677770000) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x43d3e073238499fd) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xff820064fffe0042), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x00220064fffe0042) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d09f02a6c6373d5, 0x3e5c17ec66725633, 0xb4212f5b564c62c3, 0x435ce073230999fd) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b5633, 0xb4212fa8564c62c3, 0x43d3e073238499fd) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x43d3cda0238499fd) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pmaxsb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pmaxsb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pmaxsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pmaxsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pmaxsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmaxsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pmaxsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pmaxsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pmaxsb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pmaxsb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pmaxsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pmaxsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pmaxsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmaxsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pmaxsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pmaxsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pmaxsb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pmaxsb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pmaxsb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pmaxsb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpmaxsb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pmaxsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pmaxsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pmaxsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmaxsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmaxsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pmaxsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpmaxsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pmaxsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pmaxsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pmaxsd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pmaxsd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpmaxsd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PMINUB - Compare unsigned byte integers and returns minimum values. + * [V]PMINUW - Compare unsigned word integers and returns minimum values. + * [V]PMINUD - Compare unsigned double word integers and returns minimum values. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminub_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminub_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminub_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminub_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pminub_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pminub_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminub_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminub_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpminub_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpminub_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminub_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminub_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpminub_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpminub_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminuw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminuw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pminuw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pminuw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminuw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminuw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpminuw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpminuw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminuw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminuw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpminuw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpminuw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminud_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminud_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pminud_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pminud_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminud_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminud_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpminud_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpminud_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminud_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminud_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpminud_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpminud_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pminub_pminuw_pminud(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB64[] = + { + { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), + /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8) }, + { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C( 4, 6, 7, 0x5555666677770000) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x435ccd73230996bb) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xff820064fffe0042), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x00220000ff800042) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1e09dd2a09633294, 0x3e5c17c8406b3f33, 0x88002f5b564c62a2, 0x435ccd73230996bb) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0x3ef417c840723fe6, 0x88002fa8564c62c3, 0x43d3cda0238496bb) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0x3ef417c840725633, 0x8800e95b564c9ba2, 0x43d3cda0238499fd) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pminub_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pminub_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pminub_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pminub_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pminuw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pminuw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pminud_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pminud_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pminub_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pminub_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pminub_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pminub_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pminuw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pminuw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pminud_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pminud_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pminub_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pminub_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pminub_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pminub_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pminub_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pminub_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminub_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pminuw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pminuw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pminuw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pminuw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminuw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pminud_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pminud_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pminud_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pminud_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminud_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PMINSB - Compare signed byte integers and returns minimum values. + * [V]PMINSW - Compare signed word integers and returns minimum values. + * [V]PMINSD - Compare signed double word integers and returns minimum values. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsb_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsb_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pminsb_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pminsb_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsb_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsb_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpminsb_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpminsb_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsb_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsb_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpminsb_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpminsb_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pminsw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pminsw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpminsw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpminsw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpminsw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpminsw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pminsd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pminsd_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pminsd_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsd_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsd_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpminsd_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpminsd_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsd_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpminsd_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpminsd_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpminsd_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pminsb_pminsw_pminsd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB64[] = + { + { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), + /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C( 1, 2, 3, 0xf1f2f3f4f5f6f7f8), + /*src1*/ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xe1e2e3e4e5e6e7e8) }, + { /*src2*/ RTUINT256_INIT_C( 4, 5, 7, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C( 4, 6, 7, 0xddddeeeeffff8888) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0x9c5ccda0930996bb) }, + { /*src2*/ RTUINT256_INIT_C( 8, 10, 11, 0xff820064fffe0042), + /*src1*/ RTUINT256_INIT_C(12, 13, 14, 0x0022fe00ff80ff81), + /* => */ RTUINT256_INIT_C(12, 13, 14, 0xff82fe00ff80ff81) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1eddddac09dc3294, 0xf9f48ec8406b3fe6, 0x8800e9a8bf999ba2, 0x9cd3cda0938496bb) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40723fe6, 0x8800e95bbf999ba2, 0x9c5ccda0930996bb) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pminsb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pminsb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pminsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pminsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pminsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pminsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pminsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pminsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pminsb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pminsb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pminsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pminsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pminsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pminsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pminsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pminsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pminsb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pminsb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pminsb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pminsb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpminsb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pminsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pminsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB64), s_aValuesB64 }, + { bs3CpuInstr3_pminsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pminsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pminsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pminsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpminsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pminsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pminsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pminsd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pminsd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpminsd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]MOVSS - move (mem) or merge (reg) scalar single-precision floating-point value. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movss_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movss_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movss_FSxBX_XMM1_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovss_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovss_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovss_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movss_XMM11_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movss_XMM8_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movss_FSxBX_XMM11_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovss_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovss_XMM10_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovss_FSxBX_XMM9_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movss(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesR[] = + { + { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x81828384c5c6c7c8) }, + { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeee77778888) }, + { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0930996bb) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesM[] = + { + { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x00000000c5c6c7c8) }, + { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000077778888) }, + { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x00000000930996bb) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_movss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_movss_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM32, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_movss_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + + { bs3CpuInstr3_vmovss_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_vmovss_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_vmovss_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_movss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_movss_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM32, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_movss_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + + { bs3CpuInstr3_vmovss_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_vmovss_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_vmovss_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_movss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_movss_XMM11_XMM8_icebp_c64, 255, RM_REG, T_SSE, 11, 11, 8, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_movss_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_movss_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_movss_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_movss_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM32, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + + { bs3CpuInstr3_vmovss_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_vmovss_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 9, 9, 10, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_vmovss_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_vmovss_XMM10_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 10, 10, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_vmovss_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_vmovss_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); +} + + +/* + * [V]MOVSD - move (mem) or merge (reg) scalar single-precision floating-point value. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movsd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movsd_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movsd_FSxBX_XMM1_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsd_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsd_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movsd_XMM11_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movsd_XMM8_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movsd_FSxBX_XMM11_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovsd_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovsd_XMM10_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovsd_FSxBX_XMM9_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movsd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesR[] = + { + { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) }, + { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8), + /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0x81828384c5c6c7c8) }, + { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesM[] = + { + { /*src*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*dst-in*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*dst-in*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0xc1c2c3c4c5c6c7c8) }, + { /*src*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*dst-in*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x5555666677778888) }, + { /*src*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*dst-in*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x9c5ce073930996bb) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_movsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_movsd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_movsd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + + { bs3CpuInstr3_vmovsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_vmovsd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_vmovsd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_movsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_movsd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_movsd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + + { bs3CpuInstr3_vmovsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_vmovsd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_vmovsd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_movsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_movsd_XMM11_XMM8_icebp_c64, 255, RM_REG, T_SSE, 11, 11, 8, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_movsd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_movsd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_movsd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_movsd_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + + { bs3CpuInstr3_vmovsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 1, 2, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_vmovsd_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 9, 9, 10, RT_ELEMENTS(s_aValuesR), s_aValuesR }, + { bs3CpuInstr3_vmovsd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 1, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_vmovsd_XMM10_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 10, 255, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_vmovsd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + { bs3CpuInstr3_vmovsd_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesM), s_aValuesM }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); +} + + +/* + * [V]MOVLPS - Merge a low qword (two single precision floating-point values) + * from memory with the high qword from a register (SSE destination + * or VEX 2nd source). + * The store variant just stores the high qword. + * [V]MOVLPD - Same, just using double precision floating-point unit. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movlps_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movlps_FSxBX_XMM1_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movlps_XMM8_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movlps_FSxBX_XMM11_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovlps_XMM10_XMM14_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovlps_FSxBX_XMM9_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movlpd_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movlpd_FSxBX_XMM1_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovlpd_XMM1_XMM2_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovlpd_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movlpd_XMM8_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movlpd_FSxBX_XMM11_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovlpd_XMM10_XMM14_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovlpd_FSxBX_XMM9_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movlps_movlpd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesLd[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9999aaaabbbbcccc, 0x81828384c5c6c7c8) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSt[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9999aaaabbbbcccc, 0x81828384c5c6c7c8) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x8800e95bbf9962c3, 0x9c5ce073930996bb) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_movlps_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movlps_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + { bs3CpuInstr3_movlpd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movlpd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + + { bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + { bs3CpuInstr3_vmovlpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovlpd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_movlps_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movlps_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + { bs3CpuInstr3_movlpd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movlpd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + + { bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + { bs3CpuInstr3_vmovlpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovlpd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_movlps_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movlps_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movlps_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + { bs3CpuInstr3_movlps_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + { bs3CpuInstr3_movlpd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movlpd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movlpd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + { bs3CpuInstr3_movlpd_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + + { bs3CpuInstr3_vmovlps_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovlps_XMM10_XMM14_FSxBX_icebp_c64,X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 14, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovlps_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + { bs3CpuInstr3_vmovlps_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + { bs3CpuInstr3_vmovlpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovlpd_XMM10_XMM14_FSxBX_icebp_c64,X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 14, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovlpd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + { bs3CpuInstr3_vmovlpd_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); +} + + +/* + * [V]MOVHPS - Merge a high qword (two single precision floating-point values) + * from memory with the low qword from a register (SSE destination + * or VEX 2nd source). + * The store variant just stores the high qword. + * [V]MOVHPD - Same, just using double precision floating-point unit. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movhps_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movhps_FSxBX_XMM1_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovhps_XMM1_XMM2_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovhps_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movhps_XMM8_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movhps_FSxBX_XMM11_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovhps_XMM10_XMM14_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovhps_FSxBX_XMM9_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movhpd_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movhpd_FSxBX_XMM1_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovhpd_XMM1_XMM2_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovhpd_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movhpd_XMM8_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movhpd_FSxBX_XMM11_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovhpd_XMM10_XMM14_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovhpd_FSxBX_XMM9_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movhps_movhpd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesLd[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0xc1c2c3c4c5c6c7c8, 0x8182838485868788) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x5555666677778888, 0xddddeeeeffff0000) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9c5ce073930996bb, 0x43d3cda0238499fd) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSt[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*ign*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*ign*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0xd1d2d3d4d5d6d7d8) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8), + /*ign*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x1111222233334444) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*ign*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0xb4212fa8564c9ba2) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_movhps_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movhps_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + { bs3CpuInstr3_movhpd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movhpd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + + { bs3CpuInstr3_vmovhps_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovhps_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + { bs3CpuInstr3_vmovhpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovhpd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_movhps_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movhps_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + { bs3CpuInstr3_movhpd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movhpd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + + { bs3CpuInstr3_vmovhps_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovhps_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + { bs3CpuInstr3_vmovhpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovhpd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_movhps_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movhps_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movhps_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + { bs3CpuInstr3_movhps_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + { bs3CpuInstr3_movhpd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movhpd_XMM8_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_movhpd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + { bs3CpuInstr3_movhpd_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM64, T_SSE, 255, 128, 11, RT_ELEMENTS(s_aValuesSt), s_aValuesSt }, + + { bs3CpuInstr3_vmovhps_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovhps_XMM10_XMM14_FSxBX_icebp_c64,X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 14, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovhps_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + { bs3CpuInstr3_vmovhps_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + { bs3CpuInstr3_vmovhpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovhpd_XMM10_XMM14_FSxBX_icebp_c64,X86_XCPT_AC, RM_MEM64, T_AVX_128, 10, 14, 255, RT_ELEMENTS(s_aValuesLd), s_aValuesLd }, + { bs3CpuInstr3_vmovhpd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 1, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + { bs3CpuInstr3_vmovhpd_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 255, 128, 9, RT_ELEMENTS(s_aValuesSt), s_aValuesSt}, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); +} + + +/* + * [V]MOVHLPS - Move high qword in source (2) to low qword in destination, leaving + * the high qword in the destination as it was. The VEX variant + * takes the high qword from the first source operand. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movhlps_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovhlps_XMM1_XMM2_XMM3_icebp); +extern FNBS3FAR bs3CpuInstr3_movhlps_XMM8_XMM12_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovhlps_XMM10_XMM14_XMM12_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movhlps(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9192939495969798, 0xd1d2d3d4d5d6d7d8) }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x81828384c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x9999aaaabbbbcccc, 0x1111222233334444) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x8800e95bbf9962c3, 0xb4212fa8564c9ba2) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_movhlps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovhlps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_movhlps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovhlps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_movhlps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movhlps_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 12, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovhlps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovhlps_XMM10_XMM14_XMM12_icebp_c64, 255, RM_REG, T_AVX_128, 10, 14, 12, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); +} + + +/* + * [V]PAVGB - Average unsigned packed byte integers with rounding. + * [V]PAVGW - Average unsigned packed word integers with rounding. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgb_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgb_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgb_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgb_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pavgb_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pavgb_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgb_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgb_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpavgb_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpavgb_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgb_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgb_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpavgb_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpavgb_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pavgw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pavgw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pavgw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpavgw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpavgw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpavgw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpavgw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpavgw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pavgb_pavgw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8, 0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x3673e76b3ba053b5, 0x9ca853da536f4b8d, 0x9e118c828b737fb3, 0x7098d78a5b4798dc) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8, 0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x35f3e6eb3b205335, 0x9c28535a536f4b0d, 0x9e118c828af37f33, 0x7018d70a5b47985c) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pavgb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pavgb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pavgb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pavgb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pavgw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pavgw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pavgw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pavgw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pavgb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pavgb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pavgb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pavgb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pavgw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pavgw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pavgw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pavgw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pavgb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pavgb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pavgb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pavgb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pavgb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pavgb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpavgb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pavgw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pavgw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pavgw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pavgw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pavgw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pavgw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpavgw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PSIGNB - Negate/Zero/Keep the destination packed byte integers based on the sign of the corresponding source operand. + * [V]PSIGNW - Negate/Zero/Keep the destination packed word integers based on the sign of the corresponding source operand. + * [V]PSIGND - Negate/Zero/Keep the destination packed doubleword integers based on the sign of the corresponding source operand. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignb_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignb_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignb_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignb_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_psignb_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_psignb_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignb_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignb_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpsignb_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpsignb_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignb_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignb_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpsignb_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpsignb_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_psignw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_psignw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpsignw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpsignw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpsignw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpsignw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignd_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignd_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psignd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_psignd_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_psignd_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignd_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignd_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpsignd_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpsignd_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignd_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsignd_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpsignd_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpsignd_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psignb_psignw_psignd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesB[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x4f4e4d4c4b4a4948, 0x5f5e5d5c5b5a5958, 0x6f6e6d6c6b6a6968, 0x7f7e7d7c7b7a7978) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1edd23ac099d326c, 0xf9a48e14407256cd, 0x7800e9a5bf999e3d, 0xbdd333a0dd846703) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesW[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x4e4e4c4c4a4a4848, 0x5e5e5c5c5a5a5858, 0x6e6e6c6c6a6a6868, 0x7e7e7c7c7a7a7878) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1edd225409633294, 0xf95c8eec40725633, 0x7800e95bbf999d3d, 0xbc2d3260dc7c6603) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x4e4d4c4c4a494848, 0x5e5d5c5c5a595858, 0x6e6d6c6c6a696868, 0x7e7d7c7c7a797878) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x77ff16a5bf9962c3, 0xbc2c3260dc7b6603) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_psignb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psignb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psignb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psignb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_psignw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psignw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psignw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psignw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_psignd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psignd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psignd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psignd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_psignb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psignb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psignb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psignb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_psignw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psignw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psignw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psignw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_psignd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psignd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psignd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psignd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_psignb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psignb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psignb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psignb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psignb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_psignb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpsignb_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_psignw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psignw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psignw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psignw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psignw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_psignw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpsignw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_psignd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psignd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psignd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psignd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psignd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_psignd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpsignd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PHADDW - Horizontally add word sized signed integers. + * [V]PHADDD - Horizontally add doubleword sized signed integers. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_phaddw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_phaddw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vphaddw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vphaddw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vphaddw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vphaddw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddd_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddd_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_phaddd_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_phaddd_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddd_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddd_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vphaddd_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vphaddd_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddd_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddd_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vphaddd_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vphaddd_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phaddw_phaddd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x85868d8e05060d0e) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x7ccf29c41173bd81) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 9, 10, 0xa5a6adae85868d8e, 0x25262d2e05060d0e) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 13, 14, 0xe3c9f1ee7ccf29c4, 0x715b225c1173bd81) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xe5e6edeec5c6cdce, 0x65666d6e45464d4e, 0xa5a6adae85868d8e, 0x25262d2e05060d0e) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x3d33e0b156bca651, 0xfc893bf7884896a5, 0xe3c9f1ee7ccf29c4, 0x715b225c1173bd81) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64D[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x87898b8c07090b0c) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x2f66772e6758679d) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128D[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 9, 10, 0xa7a9abac87898b8c, 0x27292b2c07090b0c) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 13, 14, 0x0a6dcb4a2f66772e, 0x479a4c1e6758679d) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256D[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xe7e9ebecc7c9cbcc, 0x67696b6c47494b4c, 0xa7a9abac87898b8c, 0x27292b2c07090b0c) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0xb9e663ffa55f57ae, 0x2841104039cee51f, 0x0a6dcb4a2f66772e, 0x479a4c1e6758679d) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_phaddw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phaddw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phaddw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phaddw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphaddw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + + { bs3CpuInstr3_phaddd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D }, + { bs3CpuInstr3_phaddd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D }, + { bs3CpuInstr3_phaddd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_phaddd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphaddd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphaddd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphaddd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + { bs3CpuInstr3_vphaddd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_phaddw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phaddw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phaddw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phaddw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphaddw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + + { bs3CpuInstr3_phaddd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D }, + { bs3CpuInstr3_phaddd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D }, + { bs3CpuInstr3_phaddd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_phaddd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphaddd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphaddd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphaddd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + { bs3CpuInstr3_vphaddd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_phaddw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phaddw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phaddw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phaddw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phaddw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phaddw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphaddw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphaddw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphaddw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + + { bs3CpuInstr3_phaddd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D }, + { bs3CpuInstr3_phaddd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D }, + { bs3CpuInstr3_phaddd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_phaddd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_phaddd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_phaddd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphaddd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphaddd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphaddd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphaddd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphaddd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + { bs3CpuInstr3_vphaddd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + { bs3CpuInstr3_vphaddd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + { bs3CpuInstr3_vphaddd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PHSUBW - Horizontally subtract word sized signed integers. + * [V]PHSUBD - Horizontally subtract doubleword sized signed integers. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_phsubw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_phsubw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vphsubw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vphsubw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vphsubw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vphsubw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubd_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubd_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_phsubd_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_phsubd_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubd_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubd_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vphsubd_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vphsubd_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubd_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubd_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vphsubd_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vphsubd_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phsubw_phsubd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0202020202020202) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x441703b289cd7679) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 9, 10, 0x0202020202020202, 0x0202020202020202) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 13, 14, 0x7b874556441703b2, 0x615ba32a89cd7679) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x0202020202020202, 0x0202020202020202, 0x0202020202020202, 0x0202020202020202) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0xa32106f9d8d4d97b, 0xbecf2931959015c1, 0x7b874556441703b2, 0x615ba32a89cd7679) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64D[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0404040404040404) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 5, 6, 7, 0xf6acb648dfb0cc5d) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128D[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 9, 10, 0x0404040404040404, 0x0404040404040404) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 13, 14, 0xa22b6bfaf6acb648, 0x37987968dfb0cc5d) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256D[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x0404040404040404, 0x0404040404040404, 0x0404040404040404, 0x0404040404040404) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1fd283ab2777281e, 0xea8554e84715c747, 0xa22b6bfaf6acb648, 0x37987968dfb0cc5d) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_phsubw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phsubw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phsubw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phsubw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphsubw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + + { bs3CpuInstr3_phsubd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D }, + { bs3CpuInstr3_phsubd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D }, + { bs3CpuInstr3_phsubd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_phsubd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphsubd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphsubd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphsubd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + { bs3CpuInstr3_vphsubd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_phsubw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phsubw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phsubw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phsubw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphsubw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + + { bs3CpuInstr3_phsubd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D }, + { bs3CpuInstr3_phsubd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D }, + { bs3CpuInstr3_phsubd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_phsubd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphsubd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphsubd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphsubd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + { bs3CpuInstr3_vphsubd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_phsubw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phsubw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phsubw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phsubw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phsubw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phsubw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphsubw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphsubw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphsubw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + + { bs3CpuInstr3_phsubd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64D), s_aValues64D }, + { bs3CpuInstr3_phsubd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64D), s_aValues64D }, + { bs3CpuInstr3_phsubd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_phsubd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_phsubd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_phsubd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphsubd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphsubd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphsubd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphsubd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128D), s_aValues128D }, + { bs3CpuInstr3_vphsubd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + { bs3CpuInstr3_vphsubd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + { bs3CpuInstr3_vphsubd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + { bs3CpuInstr3_vphsubd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256D), s_aValues256D }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PHADDSW - Horizontally add and saturate word sized signed integers. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddsw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddsw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddsw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phaddsw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_phaddsw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_phaddsw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddsw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddsw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vphaddsw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vphaddsw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddsw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphaddsw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vphaddsw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vphaddsw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phaddsw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x85868d8e80008000) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x800080001173bd81) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 9, 10, 0xa5a6adae85868d8e, 0x8000800080008000) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 13, 14, 0xe3c9f1ee80008000, 0x8000225c1173bd81) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xe5e6edeec5c6cdce, 0x8000800080008000, 0xa5a6adae85868d8e, 0x8000800080008000) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x3d337fff56bc7fff, 0xfc893bf788487fff, 0xe3c9f1ee80008000, 0x8000225c1173bd81) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_phaddsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phaddsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phaddsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phaddsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphaddsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_phaddsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phaddsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phaddsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phaddsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphaddsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_phaddsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phaddsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phaddsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phaddsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phaddsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phaddsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphaddsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphaddsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphaddsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphaddsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PHSUBSW - Horizontally subtract and saturate word sized signed integers. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubsw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubsw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubsw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phsubsw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_phsubsw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_phsubsw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubsw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubsw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vphsubsw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vphsubsw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubsw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphsubsw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vphsubsw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vphsubsw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phsubsw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0x0202020202020202) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x441703b289cd8000) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 9, 10, 0x0202020202020202, 0x0202020202020202) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 13, 14, 0x7b878000441703b2, 0x615b7fff89cd8000) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x0202020202020202, 0x0202020202020202, 0x0202020202020202, 0x0202020202020202) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0xa32106f9d8d4d97b, 0xbecf2931959015c1, 0x7b878000441703b2, 0x615b7fff89cd8000) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_phsubsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phsubsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phsubsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phsubsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphsubsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_phsubsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phsubsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phsubsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phsubsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphsubsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_phsubsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phsubsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_phsubsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phsubsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phsubsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_phsubsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vphsubsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphsubsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphsubsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vphsubsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PMADDUBSW - Horizontally subtract and saturate word sized signed integers. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaddubsw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaddubsw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaddubsw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmaddubsw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmaddubsw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmaddubsw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmaddubsw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmaddubsw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmaddubsw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmaddubsw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmaddubsw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64W[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 1, 2, 3, 0xc0c5c1d9c2fdc431) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 5, 6, 7, 0x31a82e40f5bd8000) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128W[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 9, 10, 0xcb25ccb9ce5dd011, 0xc0c5c1d9c2fdc431) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 13, 14, 0xd7a00b7f6d9691bc, 0x31a82e40f5bd8000) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256W[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xebe5ee79f11df3d1, 0xd985db99ddbddff1, 0xcb25ccb9ce5dd011, 0xc0c5c1d9c2fdc431) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x10cb0e68f5e0fd9a, 0x37fed92249260ffc, 0xd7a00b7f6d9691bc, 0x31a82e40f5bd8000) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pmaddubsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_pmaddubsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_pmaddubsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_pmaddubsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pmaddubsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_pmaddubsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_pmaddubsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_pmaddubsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pmaddubsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_pmaddubsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64W), s_aValues64W }, + { bs3CpuInstr3_pmaddubsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_pmaddubsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_pmaddubsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_pmaddubsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vpmaddubsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vpmaddubsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vpmaddubsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128W), s_aValues128W }, + { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vpmaddubsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vpmaddubsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + { bs3CpuInstr3_vpmaddubsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256W), s_aValues256W }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PMULHRSW - Vertically multiply, round and scale word sized signed integers and extract the high 16-bits. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhrsw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhrsw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhrsw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmulhrsw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmulhrsw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmulhrsw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmulhrsw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmulhrsw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmulhrsw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmulhrsw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmulhrsw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x0899072e05d40489, 0x16341448126d10a1, 0x27d7256a230e20c1, 0x3d823a9437b734e9) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1293043f07fc2dc5, 0xfcbceafe33912b08, 0x4721f792d495b28f, 0xcb340c6be1c453e5) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pmulhrsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmulhrsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmulhrsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmulhrsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pmulhrsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmulhrsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmulhrsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmulhrsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pmulhrsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmulhrsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmulhrsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmulhrsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmulhrsw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmulhrsw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmulhrsw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PSADBW - Compute sum of absolute differences of packed unsigned byte integers. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psadbw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psadbw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psadbw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_psadbw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_psadbw_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_psadbw_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsadbw_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsadbw_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpsadbw_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpsadbw_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsadbw_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpsadbw_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpsadbw_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpsadbw_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_psadbw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x0000000000000200, 0x0000000000000200, 0x0000000000000200, 0x0000000000000200) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x00000000000002f6, 0x00000000000002e5, 0x0000000000000264, 0x0000000000000240) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_psadbw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_psadbw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_psadbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_psadbw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_psadbw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_psadbw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_psadbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_psadbw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_psadbw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_psadbw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_psadbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_psadbw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_psadbw_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_psadbw_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpsadbw_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PMULDQ - Multiply packed signed double word integers. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmuldq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmuldq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmuldq_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmuldq_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuldq_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuldq_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmuldq_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmuldq_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuldq_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuldq_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmuldq_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmuldq_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmuldq(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x02e97bbaf7148240, 0x0935ee3369408840, 0x118666b3e1709040, 0x1bdae53c5fa49a40) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x03fdeed546719124, 0x19c88e386340fed2, 0xea4a418ff1c09066, 0xf0e1df0254fbb9cf) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pmuldq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuldq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pmuldq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuldq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pmuldq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuldq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuldq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuldq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuldq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PMULUDQ - Multiply packed unsigned double word integers. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmuludq_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmuludq_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmuludq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmuludq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmuludq_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmuludq_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuludq_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuludq_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmuludq_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmuludq_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuludq_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmuludq_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmuludq_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmuludq_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmuludq(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xae972b6af7148240, 0x94c37dc369408840, 0x7cf3d623e1709040, 0x6728348c5fa49a40) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x03fdeed546719124, 0x19c88e386340fed2, 0x4096dd31f1c09066, 0x146678ff54fbb9cf) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pmuludq_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuludq_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuludq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuludq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pmuludq_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuludq_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuludq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuludq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pmuludq_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuludq_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuludq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuludq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuludq_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmuludq_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmuludq_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PUNPCKLPS - Unpack and interleave low packed single precision FP values. + * [V]PUNPCKLPD - Unpack and interleave low packed double precision FP values. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_unpcklps_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_unpcklps_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_unpcklps_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_unpcklps_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpcklps_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpcklps_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vunpcklps_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vunpcklps_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpcklps_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpcklps_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vunpcklps_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vunpcklps_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_unpcklpd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_unpcklpd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_unpcklpd_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_unpcklpd_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpcklpd_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpcklpd_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vunpcklpd_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vunpcklpd_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpcklpd_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpcklpd_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vunpcklpd_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vunpcklpd_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpcklps_punpcklpd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesS[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xe1e2e3e4a1a2a3a4, 0xe5e6e7e8a5a6a7a8, 0xc1c2c3c481828384, 0xc5c6c7c885868788) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x3ef417c8f95c8eec, 0x666b3fe640725633, 0x9c5ce07343d3cda0, 0x930996bb238499fd) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xe1e2e3e4e5e6e7e8, 0xa1a2a3a4a5a6a7a8, 0xc1c2c3c4c5c6c7c8, 0x8182838485868788) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x3ef417c8666b3fe6, 0xf95c8eec40725633, 0x9c5ce073930996bb, 0x43d3cda0238499fd) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_unpcklps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_unpcklps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + + { bs3CpuInstr3_unpcklpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_unpcklpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_unpcklps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_unpcklps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + + { bs3CpuInstr3_unpcklpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_unpcklpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_unpcklps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_unpcklps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_unpcklps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_unpcklps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpcklps_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + + { bs3CpuInstr3_unpcklpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_unpcklpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_unpcklpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_unpcklpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpcklpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PUNPCKHPS - Unpack and interleave low packed single precision FP values. + * [V]PUNPCKHPD - Unpack and interleave low packed double precision FP values. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_unpckhps_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_unpckhps_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_unpckhps_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_unpckhps_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpckhps_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpckhps_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vunpckhps_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vunpckhps_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpckhps_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpckhps_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vunpckhps_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vunpckhps_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_unpckhpd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_unpckhpd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_unpckhpd_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_unpckhpd_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpckhpd_XMM1_XMM2_XMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpckhpd_XMM1_XMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vunpckhpd_XMM8_XMM9_XMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vunpckhpd_XMM8_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpckhpd_YMM1_YMM2_YMM3_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vunpckhpd_YMM1_YMM2_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vunpckhpd_YMM8_YMM9_YMM10_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vunpckhpd_YMM8_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_punpckhps_punpckhpd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesS[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4b1b2b3b4, 0xf5f6f7f8b5b6b7b8, 0xd1d2d3d491929394, 0xd5d6d7d895969798) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d09f02a1eddddac, 0x6cdc73d509633294, 0xb4212fa88800e95b, 0x564c9ba2bf9962c3) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesD[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xb1b2b3b4b5b6b7b8, 0xd1d2d3d4d5d6d7d8, 0x9192939495969798) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x1eddddac09633294, 0xb4212fa8564c9ba2, 0x8800e95bbf9962c3) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_unpckhps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_unpckhps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + + { bs3CpuInstr3_unpckhpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_unpckhpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_XMM1_XMM2_XMM3_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_XMM1_XMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_YMM1_YMM2_YMM3_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_YMM1_YMM2_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_unpckhps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_unpckhps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + + { bs3CpuInstr3_unpckhpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_unpckhpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_XMM1_XMM2_XMM3_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_XMM1_XMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_YMM1_YMM2_YMM3_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_YMM1_YMM2_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_unpckhps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_unpckhps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_unpckhps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_unpckhps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + { bs3CpuInstr3_vunpckhps_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesS), s_aValuesS }, + + { bs3CpuInstr3_unpckhpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_unpckhpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_unpckhpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE, 8, 8, 9, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_unpckhpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 8, 8, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_XMM1_XMM2_XMM3_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_XMM1_XMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_XMM8_XMM9_XMM10_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_XMM8_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_YMM1_YMM2_YMM3_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_YMM1_YMM2_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_YMM8_YMM9_YMM10_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vunpckhpd_YMM8_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]SHUFPS - Shuffle two pairs of single precision floating point values. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_shufps_XMM1_XMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_shufps_XMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_shufps_XMM1_XMM2_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_shufps_XMM1_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_shufps_XMM8_XMM9_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_shufps_XMM8_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_shufps_XMM8_XMM9_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_shufps_XMM8_FSxBX_000h_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufps_XMM1_XMM2_XMM3_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufps_XMM1_XMM2_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufps_XMM1_XMM2_XMM3_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufps_XMM1_XMM2_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_vshufps_XMM8_XMM9_XMM10_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vshufps_XMM8_XMM9_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vshufps_XMM8_XMM9_XMM10_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vshufps_XMM8_XMM9_FSxBX_000h_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufps_YMM1_YMM2_YMM3_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufps_YMM1_YMM2_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufps_YMM1_YMM2_YMM3_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufps_YMM1_YMM2_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_vshufps_YMM8_YMM9_YMM10_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vshufps_YMM8_YMM9_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vshufps_YMM8_YMM9_YMM10_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vshufps_YMM8_YMM9_FSxBX_000h_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_shufps(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f1f2f3f4, 0xb1b2b3b4b1b2b3b4, 0xd1d2d3d4d1d2d3d4, 0x9192939491929394) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d09f02a4d09f02a, 0x1eddddac1eddddac, 0xb4212fa8b4212fa8, 0x8800e95b8800e95b) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xe5e6e7e8e5e6e7e8, 0xa5a6a7a8a5a6a7a8, 0xc5c6c7c8c5c6c7c8, 0x8586878885868788) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x666b3fe6666b3fe6, 0x4072563340725633, 0x930996bb930996bb, 0x238499fd238499fd) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_shufps_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufps_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufps_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_shufps_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vshufps_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufps_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufps_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufps_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_shufps_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufps_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufps_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_shufps_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vshufps_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufps_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufps_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufps_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_shufps_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufps_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufps_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufps_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufps_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_shufps_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_shufps_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_shufps_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vshufps_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufps_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufps_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufps_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufps_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufps_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufps_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufps_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufps_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]SHUFPD - Shuffle two pairs of double precision floating point values. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_shufpd_XMM1_XMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_shufpd_XMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_shufpd_XMM1_XMM2_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_shufpd_XMM1_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_shufpd_XMM8_XMM9_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_shufpd_XMM8_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_shufpd_XMM8_XMM9_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_shufpd_XMM8_FSxBX_000h_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufpd_XMM1_XMM2_XMM3_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufpd_XMM1_XMM2_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufpd_XMM1_XMM2_XMM3_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufpd_XMM1_XMM2_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_vshufpd_XMM8_XMM9_XMM10_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vshufpd_XMM8_XMM9_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vshufpd_XMM8_XMM9_XMM10_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vshufpd_XMM8_XMM9_FSxBX_000h_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufpd_YMM1_YMM2_YMM3_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufpd_YMM1_YMM2_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufpd_YMM1_YMM2_YMM3_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vshufpd_YMM1_YMM2_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_vshufpd_YMM8_YMM9_YMM10_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vshufpd_YMM8_YMM9_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vshufpd_YMM8_YMM9_YMM10_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vshufpd_YMM8_YMM9_FSxBX_000h_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_shufpd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xb1b2b3b4b5b6b7b8, 0xd1d2d3d4d5d6d7d8, 0x9192939495969798) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x1eddddac09633294, 0xb4212fa8564c9ba2, 0x8800e95bbf9962c3) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xe1e2e3e4e5e6e7e8, 0xa1a2a3a4a5a6a7a8, 0xc1c2c3c4c5c6c7c8, 0x8182838485868788) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x3ef417c8666b3fe6, 0xf95c8eec40725633, 0x9c5ce073930996bb, 0x43d3cda0238499fd) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_shufpd_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufpd_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufpd_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_shufpd_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vshufpd_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufpd_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufpd_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufpd_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_shufpd_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufpd_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufpd_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_shufpd_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vshufpd_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufpd_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufpd_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufpd_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_shufpd_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufpd_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufpd_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufpd_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_shufpd_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE2, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_shufpd_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE2, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_shufpd_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_SSE2, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_shufpd_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE2, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vshufpd_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vshufpd_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufpd_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufpd_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufpd_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufpd_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufpd_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufpd_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vshufpd_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PALIGNR - Concatenate and align source operands to the right. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_MM1_MM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_MM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_MM1_MM2_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_MM1_FSxBX_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_MM1_MM2_003h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_MM1_FSxBX_003h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_MM1_MM2_009h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_MM1_FSxBX_009h_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_XMM1_XMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_XMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_XMM1_XMM2_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_XMM1_FSxBX_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_XMM1_XMM2_003h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_XMM1_FSxBX_003h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_XMM1_XMM2_013h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_palignr_XMM1_FSxBX_013h_icebp); +extern FNBS3FAR bs3CpuInstr3_palignr_XMM8_XMM9_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_palignr_XMM8_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_palignr_XMM8_XMM9_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_palignr_XMM8_FSxBX_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_palignr_XMM8_XMM9_003h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_palignr_XMM8_FSxBX_003h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_palignr_XMM8_XMM9_013h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_palignr_XMM8_FSxBX_013h_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_003h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_003h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_013h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_013h_icebp); +extern FNBS3FAR bs3CpuInstr3_vpalignr_XMM8_XMM9_XMM10_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpalignr_XMM8_XMM9_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpalignr_XMM8_XMM9_XMM10_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpalignr_XMM8_XMM9_FSxBX_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpalignr_XMM8_XMM9_XMM10_003h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpalignr_XMM8_XMM9_FSxBX_003h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpalignr_XMM8_XMM9_XMM10_013h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpalignr_XMM8_XMM9_FSxBX_013h_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_003h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_003h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_013h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_013h_icebp); +extern FNBS3FAR bs3CpuInstr3_vpalignr_YMM8_YMM9_YMM10_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpalignr_YMM8_YMM9_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpalignr_YMM8_YMM9_YMM10_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpalignr_YMM8_YMM9_FSxBX_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpalignr_YMM8_YMM9_YMM10_003h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpalignr_YMM8_YMM9_FSxBX_003h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpalignr_YMM8_YMM9_YMM10_013h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpalignr_YMM8_YMM9_FSxBX_013h_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_palignr(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x0000000000000000, 0x0000000000000000, 0x0000000000000000, 0x0000000000000000) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64B_03[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 17, 18, 19, 0x868788c1c2c3c4c5) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 21, 22, 23, 0x8499fd9c5ce07393) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues64B_09[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 17, 18, 19, 0x0081828384858687) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 21, 22, 23, 0x0043d3cda0238499) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128B_03[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 17, 18, 0x868788d1d2d3d4d5, 0xd6d7d8c1c2c3c4c5) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 21, 22, 0x8499fdb4212fa856, 0x4c9ba29c5ce07393) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues128B_13[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 17, 18, 0x0000009192939495, 0x9697988182838485) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 21, 22, 0x0000008800e95bbf, 0x9962c343d3cda023) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256B_03[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xa6a7a8f1f2f3f4f5, 0xf6f7f8e1e2e3e4e5, 0x868788d1d2d3d4d5, 0xd6d7d8c1c2c3c4c5) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x7256334d09f02a6c, 0xdc73d53ef417c866, 0x8499fdb4212fa856, 0x4c9ba29c5ce07393) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues256B_13[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0x000000b1b2b3b4b5, 0xb6b7b8a1a2a3a4a5, 0x0000009192939495, 0x9697988182838485) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x0000001eddddac09, 0x633294f95c8eec40, 0x0000008800e95bbf, 0x9962c343d3cda023) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_palignr_MM1_MM2_0FFh_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_palignr_MM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_palignr_MM1_MM2_000h_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_palignr_MM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_palignr_MM1_MM2_003h_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64B_03), s_aValues64B_03 }, + { bs3CpuInstr3_palignr_MM1_FSxBX_003h_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64B_03), s_aValues64B_03 }, + { bs3CpuInstr3_palignr_MM1_MM2_009h_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64B_09), s_aValues64B_09 }, + { bs3CpuInstr3_palignr_MM1_FSxBX_009h_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64B_09), s_aValues64B_09 }, + + { bs3CpuInstr3_palignr_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_palignr_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_palignr_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_palignr_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_palignr_XMM1_XMM2_003h_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + { bs3CpuInstr3_palignr_XMM1_FSxBX_003h_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + { bs3CpuInstr3_palignr_XMM1_XMM2_013h_icebp_c16, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + { bs3CpuInstr3_palignr_XMM1_FSxBX_013h_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + + { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_003h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_003h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_013h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_013h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_003h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_003h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_013h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_013h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_palignr_MM1_MM2_0FFh_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_palignr_MM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_palignr_MM1_MM2_000h_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_palignr_MM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_palignr_MM1_MM2_003h_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64B_03), s_aValues64B_03 }, + { bs3CpuInstr3_palignr_MM1_FSxBX_003h_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64B_03), s_aValues64B_03 }, + { bs3CpuInstr3_palignr_MM1_MM2_009h_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64B_09), s_aValues64B_09 }, + { bs3CpuInstr3_palignr_MM1_FSxBX_009h_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64B_09), s_aValues64B_09 }, + + { bs3CpuInstr3_palignr_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_palignr_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_palignr_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_palignr_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_palignr_XMM1_XMM2_003h_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + { bs3CpuInstr3_palignr_XMM1_FSxBX_003h_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + { bs3CpuInstr3_palignr_XMM1_XMM2_013h_icebp_c32, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + { bs3CpuInstr3_palignr_XMM1_FSxBX_013h_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + + { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_003h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_003h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_013h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_013h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_003h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_003h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_013h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_013h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_palignr_MM1_MM2_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_palignr_MM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_palignr_MM1_MM2_000h_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_palignr_MM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_palignr_MM1_MM2_003h_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64B_03), s_aValues64B_03 }, + { bs3CpuInstr3_palignr_MM1_FSxBX_003h_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64B_03), s_aValues64B_03 }, + { bs3CpuInstr3_palignr_MM1_MM2_009h_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues64B_09), s_aValues64B_09 }, + { bs3CpuInstr3_palignr_MM1_FSxBX_009h_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues64B_09), s_aValues64B_09 }, + + { bs3CpuInstr3_palignr_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_palignr_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_palignr_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_palignr_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_palignr_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_palignr_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_palignr_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_palignr_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_palignr_XMM1_XMM2_003h_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + { bs3CpuInstr3_palignr_XMM1_FSxBX_003h_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + { bs3CpuInstr3_palignr_XMM8_XMM9_003h_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + { bs3CpuInstr3_palignr_XMM8_FSxBX_003h_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + + { bs3CpuInstr3_palignr_XMM1_XMM2_013h_icebp_c64, 255, RM_REG, T_SSSE3, 1, 1, 2, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + { bs3CpuInstr3_palignr_XMM1_FSxBX_013h_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 1, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + { bs3CpuInstr3_palignr_XMM8_XMM9_013h_icebp_c64, 255, RM_REG, T_SSSE3, 8, 8, 9, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + { bs3CpuInstr3_palignr_XMM8_FSxBX_013h_icebp_c64, 255, RM_MEM, T_SSSE3, 8, 8, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + + { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpalignr_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpalignr_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpalignr_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpalignr_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpalignr_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpalignr_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpalignr_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpalignr_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_003h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_003h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + { bs3CpuInstr3_vpalignr_XMM8_XMM9_XMM10_003h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + { bs3CpuInstr3_vpalignr_XMM8_XMM9_FSxBX_003h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128B_03), s_aValues128B_03 }, + { bs3CpuInstr3_vpalignr_XMM1_XMM2_XMM3_013h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + { bs3CpuInstr3_vpalignr_XMM1_XMM2_FSxBX_013h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + { bs3CpuInstr3_vpalignr_XMM8_XMM9_XMM10_013h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + { bs3CpuInstr3_vpalignr_XMM8_XMM9_FSxBX_013h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues128B_13), s_aValues128B_13 }, + + { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_003h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_003h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, + { bs3CpuInstr3_vpalignr_YMM8_YMM9_YMM10_003h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, + { bs3CpuInstr3_vpalignr_YMM8_YMM9_FSxBX_003h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256B_03), s_aValues256B_03 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_YMM3_013h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, + { bs3CpuInstr3_vpalignr_YMM1_YMM2_FSxBX_013h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, + { bs3CpuInstr3_vpalignr_YMM8_YMM9_YMM10_013h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, + { bs3CpuInstr3_vpalignr_YMM8_YMM9_FSxBX_013h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues256B_13), s_aValues256B_13 }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PBLENDW - Blend packed words based on an 8-bit immediate. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pblendw_XMM1_XMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pblendw_XMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pblendw_XMM1_XMM2_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pblendw_XMM1_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_pblendw_XMM8_XMM9_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pblendw_XMM8_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pblendw_XMM8_XMM9_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pblendw_XMM8_FSxBX_000h_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_vpblendw_XMM8_XMM9_XMM10_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpblendw_XMM8_XMM9_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpblendw_XMM8_XMM9_XMM10_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpblendw_XMM8_XMM9_FSxBX_000h_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_vpblendw_YMM8_YMM9_YMM10_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpblendw_YMM8_YMM9_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpblendw_YMM8_YMM9_YMM10_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpblendw_YMM8_YMM9_FSxBX_000h_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pblendw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pblendw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pblendw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pblendw_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pblendw_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pblendw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pblendw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pblendw_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pblendw_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pblendw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pblendw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pblendw_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pblendw_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_pblendw_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pblendw_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pblendw_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pblendw_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpblendw_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpblendw_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpblendw_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpblendw_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vpblendw_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpblendw_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpblendw_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpblendw_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpblendw_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpblendw_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpblendw_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpblendw_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]BLENDPS - Blend packed single precision floating point values based on an 8-bit immediate. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendps_XMM1_XMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendps_XMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendps_XMM1_XMM2_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendps_XMM1_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_blendps_XMM8_XMM9_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_blendps_XMM8_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_blendps_XMM8_XMM9_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_blendps_XMM8_FSxBX_000h_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_vblendps_XMM8_XMM9_XMM10_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendps_XMM8_XMM9_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendps_XMM8_XMM9_XMM10_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendps_XMM8_XMM9_FSxBX_000h_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_vblendps_YMM8_YMM9_YMM10_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendps_YMM8_YMM9_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendps_YMM8_YMM9_YMM10_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendps_YMM8_YMM9_FSxBX_000h_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_blendps(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_blendps_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_blendps_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_blendps_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_blendps_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_blendps_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_blendps_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_blendps_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_blendps_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_blendps_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_blendps_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_blendps_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_blendps_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_blendps_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_blendps_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_blendps_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_blendps_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendps_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendps_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendps_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendps_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vblendps_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendps_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendps_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendps_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendps_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendps_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendps_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendps_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]BLENDPD - Blend packed double precision floating point values based on an 8-bit immediate. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendpd_XMM1_XMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendpd_XMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendpd_XMM1_XMM2_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendpd_XMM1_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_blendpd_XMM8_XMM9_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_blendpd_XMM8_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_blendpd_XMM8_XMM9_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_blendpd_XMM8_FSxBX_000h_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_vblendpd_XMM8_XMM9_XMM10_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendpd_XMM8_XMM9_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendpd_XMM8_XMM9_XMM10_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendpd_XMM8_XMM9_FSxBX_000h_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_vblendpd_YMM8_YMM9_YMM10_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendpd_YMM8_YMM9_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendpd_YMM8_YMM9_YMM10_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendpd_YMM8_YMM9_FSxBX_000h_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_blendpd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_blendpd_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_blendpd_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_blendpd_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_blendpd_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_000h_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_blendpd_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_blendpd_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_blendpd_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_blendpd_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_000h_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_blendpd_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_blendpd_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_blendpd_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_blendpd_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_blendpd_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_blendpd_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_blendpd_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_blendpd_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendpd_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendpd_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendpd_YMM8_YMM9_YMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vblendpd_YMM8_YMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vblendpd_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendpd_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendpd_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendpd_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendpd_YMM1_YMM2_YMM3_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendpd_YMM1_YMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendpd_YMM8_YMM9_YMM10_000h_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vblendpd_YMM8_YMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]PCLMULQDQ - Carry-less multiplication of a quadword. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pclmulqdq_XMM1_XMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pclmulqdq_XMM1_XMM2_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_pclmulqdq_XMM8_XMM9_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pclmulqdq_XMM8_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pclmulqdq_XMM8_XMM9_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pclmulqdq_XMM8_FSxBX_000h_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_XMM10_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_FSxBX_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_XMM10_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_FSxBX_000h_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pclmulqdq(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 1, 2, 0x6541a5056544a512, 0x6753a7176756a740) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 5, 6, 0x5fb1fa02ce11d9e9, 0x547462ca50871166) }, + }; + static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C( 9, 10, 0x6041a0056044a012, 0x6253a2176256a240) }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ RTUINT256_INIT_C( 13, 14, 0x26d2ea34453fe24f, 0x2592f499ed1f651f) }, + }; + + static BS3CPUINSTR3_TEST1_T const s_aTests16[] = + { + { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_0FFh_icebp_c16, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_000h_icebp_c16, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests32[] = + { + { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_0FFh_icebp_c32, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_000h_icebp_c32, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_T const s_aTests64[] = + { + { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pclmulqdq_XMM8_XMM9_0FFh_icebp_c64, 255, RM_REG, T_PCLMUL, 8, 8, 9, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pclmulqdq_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_PCLMUL, 8, 8, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_pclmulqdq_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_PCLMUL, 1, 1, 2, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pclmulqdq_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_PCLMUL, 1, 1, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pclmulqdq_XMM8_XMM9_000h_icebp_c64, 255, RM_REG, T_PCLMUL, 8, 8, 9, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pclmulqdq_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM, T_PCLMUL, 8, 8, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_0FFh_icebp_c64, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_XMM10_0FFh_icebp_c64, 255, RM_REG, T_AVX_PCLMUL, 8, 9, 10, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 8, 9, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_XMM3_000h_icebp_c64, 255, RM_REG, T_AVX_PCLMUL, 1, 2, 3, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpclmulqdq_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 1, 2, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_PCLMUL, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, + }; + static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * Test type #2 - GPR <- MM/XMM/YMM, no VVVV. + */ + +typedef struct BS3CPUINSTR3_TEST2_VALUES_T +{ + RTUINT256U uMedia; + uint64_t uGpr; +} BS3CPUINSTR3_TEST2_VALUES_T; + +typedef struct BS3CPUINSTR3_TEST2_T +{ + FPFNBS3FAR pfnWorker; + uint8_t bAvxMisalignXcpt; + uint8_t enmRm; + uint8_t enmType; + uint8_t cbGpr; + uint8_t cBitsGprValMask; + bool fInvalidEncoding; + bool fGprDst; + uint8_t iGprReg; + uint8_t iMediaReg; + uint8_t cValues; + BS3CPUINSTR3_TEST2_VALUES_T const BS3_FAR *paValues; +} BS3CPUINSTR3_TEST2_T; + +typedef struct BS3CPUINSTR3_TEST2_MODE_T +{ + BS3CPUINSTR3_TEST2_T const BS3_FAR *paTests; + unsigned cTests; +} BS3CPUINSTR3_TEST2_MODE_T; + +/** Initializer for a BS3CPUINSTR3_TEST2_MODE_T array (three entries). */ +#define BS3CPUINSTR3_TEST2_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ + { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } + + +/** + * Test type #2 worker. + */ +static uint8_t bs3CpuInstr3_WorkerTestType2(uint8_t bMode, BS3CPUINSTR3_TEST2_T const BS3_FAR *paTests, unsigned cTests, + PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs) +{ + BS3REGCTX Ctx; + BS3TRAPFRAME TrapFrame; + const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); + uint8_t BS3_FAR *pbBuf = g_pbBuf; + uint32_t cbBuf = g_cbBuf; + uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; + PBS3EXTCTX pExtCtxOut; + PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); + if (!pExtCtx) + return 0; + + /* Ensure the structures are allocated before we sample the stack pointer. */ + Bs3MemSet(&Ctx, 0, sizeof(Ctx)); + Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); + + /* + * Create test context. + */ + pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); + Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); + bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); + + /* + * Run the tests in all rings since alignment issues may behave + * differently in ring-3 compared to ring-0. + */ + for (;;) + { + unsigned iCfg; + for (iCfg = 0; iCfg < cConfigs; iCfg++) + { + unsigned iTest; + BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; + if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) + continue; /* unsupported config */ + + /* + * Iterate the tests. + */ + for (iTest = 0; iTest < cTests; iTest++) + { + BS3CPUINSTR3_TEST2_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; + uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; + unsigned const cValues = paTests[iTest].cValues; + bool const fGprDst = paTests[iTest].fGprDst; + bool const fMmxInstr = paTests[iTest].enmType < T_SSE; + bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; + bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; + uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 + : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; + uint8_t const cbMemOp = bs3CpuInstr3MemOpSize(cbOperand, paTests[iTest].enmRm); + uint8_t const cbAlign = RT_MIN(cbOperand, 16); + PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]); + uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] + || paTests[iTest].fInvalidEncoding ? X86_XCPT_UD + : fMmxInstr ? paConfigs[iCfg].bXcptMmx + : fSseInstr ? paConfigs[iCfg].bXcptSse + : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; + uint64_t const fGprValMask = paTests[iTest].cBitsGprValMask == 64 ? UINT64_MAX + : RT_BIT_64(paTests[iTest].cBitsGprValMask) - 1; + uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; + unsigned iVal; + + /* If testing unaligned memory accesses, skip register-only tests. This allows + setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ + if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck)) + continue; + + /* #AC is only raised in ring-3.: */ + if (bXcptExpect == X86_XCPT_AC) + { + if (bRing != 3) + bXcptExpect = X86_XCPT_DB; + else if (fAvxInstr) + bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ + } + + Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); + + /* + * Iterate the test values and do the actual testing. + */ + for (iVal = 0; iVal < cValues; iVal++, idTestStep++) + { + uint16_t cErrors; + uint16_t uSavedFtw = 0xff; + RTUINT256U uMemOpExpect; + + /* + * Set up the context and some expectations. + */ + if (fGprDst) + { + /* dest - gpr/mem */ + if (paTests[iTest].iGprReg == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + Bs3MemSet(puMemOp, 0xcc, cbMemOp); + if (bXcptExpect != X86_XCPT_DB) + Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); + else + { + Bs3MemSet(&uMemOpExpect, 0xaa, sizeof(uMemOpExpect)); + switch (paTests[iTest].cbGpr) + { + case 1: uMemOpExpect.au8[0] = (uint8_t) (paValues[iVal].uGpr & fGprValMask); break; + case 2: uMemOpExpect.au16[0] = (uint16_t)(paValues[iVal].uGpr & fGprValMask); break; + case 4: uMemOpExpect.au32[0] = (uint32_t)(paValues[iVal].uGpr & fGprValMask); break; + case 8: uMemOpExpect.au64[0] = (paValues[iVal].uGpr & fGprValMask); break; + default: BS3_ASSERT(0); + } + } + } + else + Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, UINT64_C(0xcccccccccccccccc), + BS3_MODE_IS_64BIT_CODE(bMode) ? 8 : 4); /* we only restore 63:32 when bMode==LM64 */ + + /* source - media/mem */ + if (paTests[iTest].iMediaReg == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + BS3_ASSERT(paTests[iTest].iGprReg != UINT8_MAX); + Bs3MemCpy(puMemOp, &paValues[iVal].uMedia, cbMemOp); + uMemOpExpect = paValues[iVal].uMedia; + } + else if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaReg, paValues[iVal].uMedia.QWords.qw0, BS3EXTCTXTOPMM_ZERO); + else if (fSseInstr) + Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia.DQWords.dqw0); + else + Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia, 32); + } + else + { + /* dest - media */ + if (paTests[iTest].iMediaReg == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + Bs3MemSet(puMemOp, 0xcc, cbMemOp); + if (bXcptExpect == X86_XCPT_DB) + uMemOpExpect = paValues[iVal].uMedia; + else + Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); + } + + /* source - gpr/mem */ + if (paTests[iTest].iGprReg == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); + if (bXcptExpect == X86_XCPT_DB) + switch (paTests[iTest].cbGpr) + { + case 1: uMemOpExpect.au8[0] = (uint8_t) (paValues[iVal].uGpr & fGprValMask); break; + case 2: uMemOpExpect.au16[0] = (uint16_t)(paValues[iVal].uGpr & fGprValMask); break; + case 4: uMemOpExpect.au32[0] = (uint32_t)(paValues[iVal].uGpr & fGprValMask); break; + case 8: uMemOpExpect.au64[0] = (paValues[iVal].uGpr & fGprValMask); break; + default: BS3_ASSERT(0); + } + Bs3MemCpy(puMemOp, &uMemOpExpect, cbMemOp); + } + else + Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, paValues[iVal].uGpr & fGprValMask, paTests[iTest].cbGpr); + } + + /* Memory pointer. */ + if (paTests[iTest].enmRm >= RM_MEM) + { + BS3_ASSERT(paTests[iTest].iGprReg == UINT8_MAX || paTests[iTest].iMediaReg == UINT8_MAX); + Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); + } + + /* + * Execute. + */ + Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); + + /* + * Check the result: + */ + cErrors = Bs3TestSubErrorCount(); + + if (fMmxInstr && bXcptExpect == X86_XCPT_DB) + { + uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); + Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); + } + if (!fGprDst && bXcptExpect == X86_XCPT_DB && paTests[iTest].iMediaReg != UINT8_MAX) + { + if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaReg, paValues[iVal].uMedia.QWords.qw0, BS3EXTCTXTOPMM_SET); + else if (fSseInstr) + Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia.DQWords.dqw0); + else + Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaReg, &paValues[iVal].uMedia, 32); + } + Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); + + if (TrapFrame.bXcpt != bXcptExpect) + Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); + + if (fGprDst && bXcptExpect == X86_XCPT_DB && paTests[iTest].iGprReg != UINT8_MAX) + Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, paValues[iVal].uGpr & fGprValMask, + paTests[iTest].cbGpr >= 4 ? 8 : paTests[iTest].cbGpr); + /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ + if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) + { + if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) + Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); + TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; + } + Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, + bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, + pszMode, idTestStep); + + if ( paTests[iTest].enmRm >= RM_MEM + && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0) + Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp); + + if (cErrors != Bs3TestSubErrorCount()) + { + if (paConfigs[iCfg].fAligned) + Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)", + bRing, iCfg, iTest, iVal, bXcptExpect); + else + Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", + bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); + Bs3TestPrintf("\n"); + } + + if (uSavedFtw != 0xff) + Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); + } + } + + bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); + } + + /* + * Next ring. + */ + bRing++; + if (bRing > 3 || bMode == BS3_MODE_RM) + break; + Bs3RegCtxConvertToRingX(&Ctx, bRing); + } + + /* + * Cleanup. + */ + bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); + bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); + return 0; +} + + +/* + * PMOVMSKB, VPMOVMSKB. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovmskb_EAX_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovmskb_RAX_YMM9_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmovmskb(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffffffff) }, + { RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x00000000) }, + { RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), UINT64_C(0xffffffff) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x03000003) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x255193ab) }, + }; + + static BS3CPUINSTR3_TEST2_T const s_aTests16[] = + { + { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 4, 8, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 4, 8, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c16, 255, RM_REG, T_SSE2, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c16, 255, RM_MEM, T_SSE2, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c16, 255, RM_MEM, T_AVX_128, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c16, 255, RM_REG, T_AVX2_256, 4, 32, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c16, 255, RM_MEM, T_AVX2_256, 4, 32, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST2_T const s_aTests32[] = + { + { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 4, 8, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 4, 8, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c32, 255, RM_REG, T_SSE2, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c32, 255, RM_MEM, T_SSE2, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 4, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c32, 255, RM_MEM, T_AVX_128, 4, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c32, 255, RM_REG, T_AVX2_256, 4, 32, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c32, 255, RM_MEM, T_AVX2_256, 4, 32, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST2_T const s_aTests64[] = + { + { bs3CpuInstr3_pmovmskb_EAX_MM2_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 8, 8, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmovmskb_EAX_qword_FSxBX_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 8, 8, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmovmskb_EAX_XMM2_icebp_c64, 255, RM_REG, T_SSE2, 8, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pmovmskb_EAX_dqword_FSxBX_icebp_c64, 255, RM_MEM, T_SSE2, 8, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmovmskb_EAX_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 8, 16, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmovmskb_EAX_dqword_FSxBX_icebp_c64, 255, RM_MEM, T_AVX_128, 8, 16, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmovmskb_EAX_YMM2_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 32, false, true, 0, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmovmskb_EAX_qqword_FSxBX_icebp_c64, 255, RM_MEM, T_AVX2_256, 8, 32, true, true, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpmovmskb_RAX_YMM9_icebp_c64, 255, RM_REG, T_AVX2_256, 8, 32, false, true, 0, 9, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * [V]MOVD / [V]MOVQ - greg/mem variants only. + */ + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_MM1_EDX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_EAX_MM1_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_FSxBX_MM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movd_MM1_R9D_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movd_R10D_MM0_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_XMM1_EAX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_EAX_XMM1_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movd_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movd_XMM9_R8D_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movd_R8D_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movd_XMM9_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movd_FSxBX_XMM9_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovd_XMM1_EAX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovd_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovd_EDX_XMM1_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovd_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovd_XMM9_R9D_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovd_R8D_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovd_XMM9_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovd_FSxBX_XMM9_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_FSxBX_MM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movq_R9_MM1_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_06e_movq_MM1_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_07e_movq_FSxBX_MM1_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movq_MM1_R9_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movq_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movq_XMM9_R8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movq_R8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movq_XMM9_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movq_FSxBX_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_06e_movq_XMM1_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_06e_movq_XMM9_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_07e_movq_FSxBX_XMM1_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_07e_movq_FSxBX_XMM9_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovq_XMM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovq_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovq_XMM9_R8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovq_R8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovq_XMM9_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovq_FSxBX_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_06e_vmovq_XMM1_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_06e_vmovq_XMM9_FSxBX_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_07e_vmovq_FSxBX_XMM1_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_07e_vmovq_FSxBX_XMM9_icebp_c64; + + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movd_movq(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesRm[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f7f7f7f7f7f7f) }, + { RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x8080808080808080) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x5555666677778888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x9c5ce073930996bb) }, + }; + static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesMediaD[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) }, + { RTUINT256_INIT_C(0, 0, 0, 0x00000000ffffffff), UINT64_C(0xffffffffffffffff) }, + { RTUINT256_INIT_C(0, 0, 0, 0x000000007f7f7f7f), UINT64_C(0x7f7f7f7f7f7f7f7f) }, + { RTUINT256_INIT_C(0, 0, 0, 0x0000000080808080), UINT64_C(0x8080808080808080) }, + { RTUINT256_INIT_C(0, 0, 0, 0x0000000077778888), UINT64_C(0x5555666677778888) }, + { RTUINT256_INIT_C(0, 0, 0, 0x00000000930996bb), UINT64_C(0x9c5ce073930996bb) }, + }; + static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesMediaQ[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0) }, + { RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff), UINT64_C(0xffffffffffffffff) }, + { RTUINT256_INIT_C(0, 0, 0, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f7f7f7f7f7f7f) }, + { RTUINT256_INIT_C(0, 0, 0, 0x8080808080808080), UINT64_C(0x8080808080808080) }, + { RTUINT256_INIT_C(0, 0, 0, 0x5555666677778888), UINT64_C(0x5555666677778888) }, + { RTUINT256_INIT_C(0, 0, 0, 0x9c5ce073930996bb), UINT64_C(0x9c5ce073930996bb) }, + }; + + /* Note! Seems the 256-bit variants doesn't generate \#ACs on a 10980XE. WEIRD! */ + static BS3CPUINSTR3_TEST2_T const s_aTests16[] = + { + { bs3CpuInstr3_movd_MM1_EDX_icebp_c16, 255, RM_REG, T_MMX, 4, 32, false, false, 2, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_movd_MM1_FSxBX_icebp_c16, 255, RM_MEM32, T_MMX, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_movd_EAX_MM1_icebp_c16, 255, RM_REG, T_MMX, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_movd_FSxBX_MM1_icebp_c16, 255, RM_MEM32, T_MMX, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + + { bs3CpuInstr3_movd_XMM1_EAX_icebp_c16, 255, RM_REG, T_SSE2, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_movd_XMM1_FSxBX_icebp_c16, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_movd_EAX_XMM1_icebp_c16, 255, RM_REG, T_SSE2, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_movd_FSxBX_XMM1_icebp_c16, 255, RM_MEM32, T_SSE2, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + + { bs3CpuInstr3_vmovd_XMM1_EAX_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_vmovd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_vmovd_EDX_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_vmovd_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_movq_MM1_FSxBX_icebp_c16, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_movq_FSxBX_MM1_icebp_c16, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_movq_XMM1_FSxBX_icebp_c16, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_movq_FSxBX_XMM1_icebp_c16, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + + { bs3CpuInstr3_vmovq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_vmovq_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + }; + static BS3CPUINSTR3_TEST2_T const s_aTests32[] = + { + { bs3CpuInstr3_movd_MM1_EDX_icebp_c32, 255, RM_REG, T_MMX, 4, 32, false, false, 2, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_movd_MM1_FSxBX_icebp_c32, 255, RM_MEM32, T_MMX, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_movd_EAX_MM1_icebp_c32, 255, RM_REG, T_MMX, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_movd_FSxBX_MM1_icebp_c32, 255, RM_MEM32, T_MMX, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + + { bs3CpuInstr3_movd_XMM1_EAX_icebp_c32, 255, RM_REG, T_SSE2, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_movd_XMM1_FSxBX_icebp_c32, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_movd_EAX_XMM1_icebp_c32, 255, RM_REG, T_SSE2, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_movd_FSxBX_XMM1_icebp_c32, 255, RM_MEM32, T_SSE2, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + + { bs3CpuInstr3_vmovd_XMM1_EAX_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_vmovd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_vmovd_EDX_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_vmovd_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + + { bs3CpuInstr3_movq_MM1_FSxBX_icebp_c32, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_movq_FSxBX_MM1_icebp_c32, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + + { bs3CpuInstr3_movq_XMM1_FSxBX_icebp_c32, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_movq_FSxBX_XMM1_icebp_c32, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + + { bs3CpuInstr3_vmovq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_vmovq_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + }; + static BS3CPUINSTR3_TEST2_T const s_aTests64[] = + { + { bs3CpuInstr3_movd_MM1_EDX_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, false, 2, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_movd_MM1_R9D_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, false, 9, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_movd_MM1_FSxBX_icebp_c64, 255, RM_MEM32, T_MMX, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_movd_EAX_MM1_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_movd_R10D_MM0_icebp_c64, 255, RM_REG, T_MMX, 4, 32, false, true, 10, 0, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_movd_FSxBX_MM1_icebp_c64, 255, RM_MEM32, T_MMX, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + + { bs3CpuInstr3_movd_XMM1_EAX_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_movd_XMM9_R8D_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, false, 8, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_movd_XMM1_FSxBX_icebp_c64, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_movd_XMM9_FSxBX_icebp_c64, 255, RM_MEM32, T_SSE2, 4, 32, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_movd_EAX_XMM1_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 0, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_movd_R8D_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_movd_FSxBX_XMM1_icebp_c64, 255, RM_MEM32, T_SSE2, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + + { bs3CpuInstr3_vmovd_XMM1_EAX_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, false, 0, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_vmovd_XMM9_R9D_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, false, 9, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_vmovd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_vmovd_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaD), s_aValuesMediaD }, + { bs3CpuInstr3_vmovd_EDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_vmovd_R8D_XMM9_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_vmovd_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_vmovd_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + + { bs3CpuInstr3_movq_MM1_R9_icebp_c64, 255, RM_REG, T_MMX, 8, 64, false, false, 9, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_movq_MM1_FSxBX_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_06e_movq_MM1_FSxBX_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_movq_R9_MM1_icebp_c64, 255, RM_REG, T_MMX, 8, 64, false, true, 9, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_movq_FSxBX_MM1_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_07e_movq_FSxBX_MM1_icebp_c64, 255, RM_MEM64, T_MMX, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + + { bs3CpuInstr3_movq_XMM9_R8_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, false, 8, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_movq_XMM1_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_06e_movq_XMM1_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_movq_XMM9_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_06e_movq_XMM9_FSxBX_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_movq_R8_XMM9_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_movq_FSxBX_XMM1_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_07e_movq_FSxBX_XMM1_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_movq_FSxBX_XMM9_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_07e_movq_FSxBX_XMM9_icebp_c64, 255, RM_MEM64, T_SSE2, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + + { bs3CpuInstr3_vmovq_XMM9_R8_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, false, 8, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_vmovq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_06e_vmovq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 1, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_vmovq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_06e_vmovq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, false, 255, 9, RT_ELEMENTS(s_aValuesMediaQ), s_aValuesMediaQ }, + { bs3CpuInstr3_vmovq_R8_XMM9_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 8, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_vmovq_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_07e_vmovq_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 1, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_vmovq_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + { bs3CpuInstr3_07e_vmovq_FSxBX_XMM9_icebp_c64, X86_XCPT_AC, RM_MEM64, T_AVX_128, 8, 64, false, true, 255, 9, RT_ELEMENTS(s_aValuesRm), s_aValuesRm }, + }; + static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); +} + + +/* + * [V]PEXTRW. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pextrw_EDX_MM1_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pextrw_EDX_XMM1_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_pextrw_RDX_XMM1_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pextrw_R9D_MM1_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pextrw_R9D_XMM8_000h_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pextrw_EDX_MM1_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pextrw_EDX_XMM1_0FFh_icebp); +extern FNBS3FAR bs3CpuInstr3_pextrw_RDX_XMM1_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pextrw_R9D_MM1_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pextrw_R9D_XMM8_0FFh_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpextrw_EDX_XMM1_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_vpextrw_RDX_XMM1_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpextrw_EDX_XMM8_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpextrw_R9D_XMM8_000h_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpextrw_EDX_XMM1_0FFh_icebp); +extern FNBS3FAR bs3CpuInstr3_vpextrw_RDX_XMM1_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpextrw_EDX_XMM8_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpextrw_R9D_XMM8_0FFh_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pextrw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues00[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0x1234), /*->*/ UINT64_C(0x1234) }, + { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffff) }, + { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f) }, + { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x8080) }, + { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x8888) }, + { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x96bb) }, + }; + + static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesFF[] = + { + { RTUINT256_INIT_C(0, 0, 0x1234000000000000, 0), UINT64_C(0x1234) }, + { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffff) }, + { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f) }, + { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x8080) }, + { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x1111) }, + { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xb421) }, + }; + + static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesFF_64[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0x1234000000000000), UINT64_C(0x1234) }, + { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffff) }, + { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f) }, + { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x8080) }, + { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x5555) }, + { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x9c5c) }, + }; + + static BS3CPUINSTR3_TEST2_T const s_aTests16[] = + { + { bs3CpuInstr3_pextrw_EDX_MM1_000h_icebp_c16, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pextrw_EDX_XMM1_000h_icebp_c16, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpextrw_EDX_XMM1_000h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_pextrw_EDX_MM1_0FFh_icebp_c16, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, + { bs3CpuInstr3_pextrw_EDX_XMM1_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpextrw_EDX_XMM1_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + }; + static BS3CPUINSTR3_TEST2_T const s_aTests32[] = + { + { bs3CpuInstr3_pextrw_EDX_MM1_000h_icebp_c32, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pextrw_EDX_XMM1_000h_icebp_c32, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpextrw_EDX_XMM1_000h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_pextrw_EDX_MM1_0FFh_icebp_c32, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, + { bs3CpuInstr3_pextrw_EDX_XMM1_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpextrw_EDX_XMM1_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + }; + static BS3CPUINSTR3_TEST2_T const s_aTests64[] = + { + { bs3CpuInstr3_pextrw_EDX_MM1_000h_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pextrw_R9D_MM1_000h_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 9, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pextrw_EDX_XMM1_000h_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + /// @todo Emits the SSE4.1 0f3a variant { bs3CpuInstr3_pextrw_RDX_XMM1_000h_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pextrw_R9D_XMM8_000h_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpextrw_EDX_XMM1_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpextrw_RDX_XMM1_000h_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpextrw_R9D_XMM8_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, + + { bs3CpuInstr3_pextrw_EDX_MM1_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, + { bs3CpuInstr3_pextrw_R9D_MM1_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, false, true, 9, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, + { bs3CpuInstr3_pextrw_EDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + /// @todo Emits the SSE4.1 0f3a variant { bs3CpuInstr3_pextrw_RDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pextrw_R9D_XMM8_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpextrw_EDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpextrw_RDX_XMM1_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpextrw_R9D_XMM8_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + }; + static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); +} + + +/* + * [V]MOVMSKPS / [V]MOVMSKPD. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movmskps_EDX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movmskps_RDX_XMM1_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movmskps_R9D_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movmskps_RDX_XMM8_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovmskps_EDX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovmskps_RDX_XMM1_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovmskps_EDX_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovmskps_R9D_XMM8_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovmskps_EDX_YMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovmskps_RDX_YMM1_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovmskps_EDX_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovmskps_R9D_YMM8_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movmskpd_EDX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movmskpd_RDX_XMM1_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movmskpd_R9D_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movmskpd_RDX_XMM8_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovmskpd_EDX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovmskpd_RDX_XMM1_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovmskpd_EDX_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovmskpd_R9D_XMM8_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovmskpd_EDX_YMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovmskpd_RDX_YMM1_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovmskpd_EDX_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovmskpd_R9D_YMM8_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movmskps_movmskpd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesR32_128[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0x0) }, + { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xf) }, + { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x0) }, + { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0xf) }, + { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x0) }, + { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xb) }, + }; + + static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesR32_256[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0x00) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xff) }, + { RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x00) }, + { RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), UINT64_C(0xff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff0000, 0x1111222233334444, 0x5555666677778888), UINT64_C(0xf0) }, + { RTUINT256_INIT_C(0x9c5ce073930996bb, 0xb4212fa8564c9ba2, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xeb) }, + }; + + static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesR64_128[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), UINT64_C(0x0) }, + { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0x3) }, + { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x0) }, + { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x3) }, + { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x0) }, + { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x3) }, + }; + + static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesR64_256[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), UINT64_C(0x0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xf) }, + { RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x0) }, + { RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), UINT64_C(0xf) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff0000, 0x1111222233334444, 0x5555666677778888), UINT64_C(0xc) }, + { RTUINT256_INIT_C(0x9c5ce073930996bb, 0xb4212fa8564c9ba2, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xf) }, + }; + + static BS3CPUINSTR3_TEST2_T const s_aTests16[] = + { + { bs3CpuInstr3_movmskps_EDX_XMM1_icebp_c16, 255, RM_REG, T_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, + { bs3CpuInstr3_vmovmskps_EDX_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, + { bs3CpuInstr3_vmovmskps_EDX_YMM1_icebp_c16, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_256), s_aValuesR32_256 }, + + { bs3CpuInstr3_movmskpd_EDX_XMM1_icebp_c16, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, + { bs3CpuInstr3_vmovmskpd_EDX_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, + { bs3CpuInstr3_vmovmskpd_EDX_YMM1_icebp_c16, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_256), s_aValuesR64_256 }, + }; + static BS3CPUINSTR3_TEST2_T const s_aTests32[] = + { + { bs3CpuInstr3_movmskps_EDX_XMM1_icebp_c32, 255, RM_REG, T_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, + { bs3CpuInstr3_vmovmskps_EDX_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, + { bs3CpuInstr3_vmovmskps_EDX_YMM1_icebp_c32, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_256), s_aValuesR32_256 }, + + { bs3CpuInstr3_movmskpd_EDX_XMM1_icebp_c32, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, + { bs3CpuInstr3_vmovmskpd_EDX_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, + { bs3CpuInstr3_vmovmskpd_EDX_YMM1_icebp_c32, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_256), s_aValuesR64_256 }, + }; + static BS3CPUINSTR3_TEST2_T const s_aTests64[] = + { + { bs3CpuInstr3_movmskps_EDX_XMM1_icebp_c64, 255, RM_REG, T_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, + { bs3CpuInstr3_movmskps_R9D_XMM8_icebp_c64, 255, RM_REG, T_SSE, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, + { bs3CpuInstr3_movmskps_RDX_XMM1_icebp_c64, 255, RM_REG, T_SSE, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, + { bs3CpuInstr3_vmovmskps_EDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, + { bs3CpuInstr3_vmovmskps_RDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, + { bs3CpuInstr3_vmovmskps_R9D_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, + + { bs3CpuInstr3_vmovmskps_EDX_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_256), s_aValuesR32_256 }, + { bs3CpuInstr3_vmovmskps_RDX_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_256), s_aValuesR32_256 }, + { bs3CpuInstr3_vmovmskps_R9D_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR32_256), s_aValuesR32_256 }, + + { bs3CpuInstr3_movmskpd_EDX_XMM1_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, + { bs3CpuInstr3_movmskpd_R9D_XMM8_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, + { bs3CpuInstr3_movmskpd_RDX_XMM1_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, + { bs3CpuInstr3_vmovmskpd_EDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, + { bs3CpuInstr3_vmovmskpd_RDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, + { bs3CpuInstr3_vmovmskpd_R9D_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, + + { bs3CpuInstr3_vmovmskpd_EDX_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_256), s_aValuesR64_256 }, + { bs3CpuInstr3_vmovmskpd_RDX_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_256), s_aValuesR64_256 }, + { bs3CpuInstr3_vmovmskpd_R9D_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR64_256), s_aValuesR64_256 }, + }; + static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + + + +/* + * Test type #3 - two MM/XMM/YMM operands, no flags. + */ + +typedef struct BS3CPUINSTR3_TEST3_VALUES_T +{ + RTUINT256U uSrc; + RTUINT256U uDstOut; +} BS3CPUINSTR3_TEST3_VALUES_T; + +typedef struct BS3CPUINSTR3_TEST3_T +{ + FPFNBS3FAR pfnWorker; + uint8_t bAvxMisalignXcpt; + uint8_t enmRm; + uint8_t enmType; + uint8_t iRegDst; + uint8_t iRegSrc; + uint8_t cValues; + BS3CPUINSTR3_TEST3_VALUES_T const BS3_FAR *paValues; +} BS3CPUINSTR3_TEST3_T; + +typedef struct BS3CPUINSTR3_TEST3_MODE_T +{ + BS3CPUINSTR3_TEST3_T const BS3_FAR *paTests; + unsigned cTests; +} BS3CPUINSTR3_TEST3_MODE_T; + +/** Initializer for a BS3CPUINSTR3_TEST3_MODE_T array (three entries). */ +#define BS3CPUINSTR3_TEST3_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ + { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } + + +/** + * Test type #1 worker. + */ +static uint8_t bs3CpuInstr3_WorkerTestType3(uint8_t bMode, BS3CPUINSTR3_TEST3_T const BS3_FAR *paTests, unsigned cTests, + PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs, uint8_t cbMaxAlign) +{ + BS3REGCTX Ctx; + BS3TRAPFRAME TrapFrame; + const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); + uint8_t BS3_FAR *pbBuf = g_pbBuf; + uint32_t cbBuf = g_cbBuf; + uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; + PBS3EXTCTX pExtCtxOut; + PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); + if (!pExtCtx) + return 0; + + /* Ensure the structures are allocated before we sample the stack pointer. */ + Bs3MemSet(&Ctx, 0, sizeof(Ctx)); + Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); + + /* + * Create test context. + */ + Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); + bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); + pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); + + /* + * Run the tests in all rings since alignment issues may behave + * differently in ring-3 compared to ring-0. + */ + for (;;) + { + unsigned iCfg; + for (iCfg = 0; iCfg < cConfigs; iCfg++) + { + unsigned iTest; + BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; + if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) + continue; /* unsupported config */ + + /* + * Iterate the tests. + */ + for (iTest = 0; iTest < cTests; iTest++) + { + BS3CPUINSTR3_TEST3_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; + uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; + unsigned const cValues = paTests[iTest].cValues; + bool const fMmxInstr = paTests[iTest].enmType < T_SSE; + bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; + bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; + uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 + : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; + uint8_t const cbMemOp = cbOperand; + uint8_t const cbAlign = RT_MIN(cbOperand, !cbMaxAlign ? 16 : cbMaxAlign); + PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]); + uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD + : fMmxInstr ? paConfigs[iCfg].bXcptMmx + : fSseInstr ? paConfigs[iCfg].bXcptSse + : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; + uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; + unsigned iVal; + + /* If testing unaligned memory accesses, skip register-only tests. This allows + setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ + if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck)) + continue; + + /* #AC is only raised in ring-3.: */ + if (bXcptExpect == X86_XCPT_AC) + { + if (bRing != 3) + bXcptExpect = X86_XCPT_DB; + else if (fAvxInstr) + bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ + } + + Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); + + /* + * Iterate the test values and do the actual testing. + */ + for (iVal = 0; iVal < cValues; iVal++, idTestStep++) + { + uint16_t cErrors; + uint16_t uSavedFtw = 0xff; + RTUINT256U uMemOpExpect; + + /* + * Set up the context and some expectations. + */ + /* dest */ + if (paTests[iTest].iRegDst == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + Bs3MemSet(puMemOp, 0xcc, cbMemOp); + if (bXcptExpect == X86_XCPT_DB) + uMemOpExpect = paValues[iVal].uDstOut; + else + Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); + } + else if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc, ~paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_ZERO); + + /* source */ + if (paTests[iTest].iRegSrc == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX); + Bs3MemCpy(puMemOp, &paValues[iVal].uSrc, cbMemOp); + uMemOpExpect = paValues[iVal].uSrc; + } + else if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc, paValues[iVal].uSrc.QWords.qw0, BS3EXTCTXTOPMM_ZERO); + else if (fSseInstr) + Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc, &paValues[iVal].uSrc.DQWords.dqw0); + else + Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc, &paValues[iVal].uSrc, 32); + + /* Memory pointer. */ + if (paTests[iTest].enmRm >= RM_MEM) + { + BS3_ASSERT( paTests[iTest].iRegDst == UINT8_MAX + || paTests[iTest].iRegSrc == UINT8_MAX); + Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); + } + + /* + * Execute. + */ + Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); + + /* + * Check the result: + */ + cErrors = Bs3TestSubErrorCount(); + + if (bXcptExpect == X86_XCPT_DB && fMmxInstr) + { + uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); + Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); + } + if (bXcptExpect == X86_XCPT_DB && paTests[iTest].iRegDst != UINT8_MAX) + { + if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegDst, paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_SET); + else if (fSseInstr) + Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut.DQWords.dqw0); + else + Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut, cbOperand); + } + Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); + + if (TrapFrame.bXcpt != bXcptExpect) + Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); + + /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ + if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) + { + if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) + Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); + TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; + } + Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, + bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, + pszMode, idTestStep); + + if ( paTests[iTest].enmRm >= RM_MEM + && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0) + Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp); + + if (cErrors != Bs3TestSubErrorCount()) + { + if (paConfigs[iCfg].fAligned) + Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)", + bRing, iCfg, iTest, iVal, bXcptExpect); + else + Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", + bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); + Bs3TestPrintf("\n"); + } + + if (uSavedFtw != 0xff) + Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); + } + } + + bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); + } + + /* + * Next ring. + */ + bRing++; + if (bRing > 3 || bMode == BS3_MODE_RM) + break; + Bs3RegCtxConvertToRingX(&Ctx, bRing); + } + + /* + * Cleanup. + */ + bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); + bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); + return 0; +} + + +/* + * PSHUFW + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp); + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_pshufw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0, 0, 0, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0x5555555555555555) }, + { RTUINT256_INIT_C(0, 0, 0, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0x9c5c9c5c9c5c9c5c) }, + }; + + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0, 0, 0, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0x8888777766665555) }, + { RTUINT256_INIT_C(0, 0, 0, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0x96bb9309e0739c5c) }, + }; + + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp_c16, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp_c32, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_pshufw_MM1_MM2_0FFh_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufw_MM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufw_MM1_MM2_01Bh_icebp_c64, 255, RM_REG, T_AXMMX_OR_SSE, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_pshufw_MM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_AXMMX_OR_SSE, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/); +} + + +/* + * [V]PSHUFHW + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp); +extern FNBS3FAR bs3CpuInstr3_vpshufhw_YMM12_YMM7_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpshufhw_YMM9_YMM12_01Bh_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pshufhw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x5555555555555555, 0x1111222233334444, 0x1111111111111111, 0x5555666677778888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x4d094d094d094d09, 0x3ef417c8666b3fe6, 0xb421b421b421b421, 0x9c5ce073930996bb) }, + }; + + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x8888777766665555, 0x1111222233334444, 0x4444333322221111, 0x5555666677778888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x73d56cdcf02a4d09, 0x3ef417c8666b3fe6, 0x9ba2564c2fa8b421, 0x9c5ce073930996bb) }, + }; + + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_pshufhw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufhw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufhw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_pshufhw_XMM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshufhw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufhw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshufhw_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshufhw_YMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufhw_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshufhw_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshufhw_YMM12_YMM7_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 12, 7, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufhw_YMM9_YMM12_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 12, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/); +} + + +/* + * [V]PSHUFLW + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp); +extern FNBS3FAR bs3CpuInstr3_vpshuflw_YMM12_YMM7_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpshuflw_YMM9_YMM12_01Bh_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pshuflw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x5555666677778888, 0x1111111111111111, 0x1111222233334444, 0x5555555555555555) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef43ef43ef43ef4, 0xb4212fa8564c9ba2, 0x9c5c9c5c9c5c9c5c) }, + }; + + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x5555666677778888, 0x4444333322221111, 0x1111222233334444, 0x8888777766665555) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3fe6666b17c83ef4, 0xb4212fa8564c9ba2, 0x96bb9309e0739c5c) }, + }; + + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_pshuflw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshuflw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshuflw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_pshuflw_XMM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshuflw_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshuflw_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshuflw_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshuflw_YMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshuflw_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshuflw_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshuflw_YMM12_YMM7_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 12, 7, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshuflw_YMM9_YMM12_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 12, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/); +} + + +/* + * [V]PSHUFD + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp); + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp); +extern FNBS3FAR bs3CpuInstr3_vpshufd_YMM12_YMM7_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpshufd_YMM9_YMM12_01Bh_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pshufd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesFF[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x5555666655556666, 0x5555666655556666, 0x1111222211112222, 0x1111222211112222) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x4d09f02a4d09f02a, 0x4d09f02a4d09f02a, 0xb4212fa8b4212fa8, 0xb4212fa8b4212fa8) }, + }; + + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues1B[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x3333444411112222, 0x7777888855556666, 0x7777888855556666, 0x3333444411112222) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x666b3fe63ef417c8, 0x6cdc73d54d09f02a, 0x930996bb9c5ce073, 0x564c9ba2b4212fa8) }, + }; + + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp_c16, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp_c16, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp_c32, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp_c32, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_pshufd_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufd_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pshufd_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_SSE2, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_pshufd_XMM1_FSxBX_01Bh_icebp_c64, 255, RM_MEM, T_SSE2, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshufd_XMM1_XMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufd_XMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufd_XMM1_XMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshufd_XMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + + { bs3CpuInstr3_vpshufd_YMM1_YMM2_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufd_YMM1_FSxBX_0FFh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufd_YMM1_YMM2_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 1, 2, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshufd_YMM1_FSxBX_01Bh_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + { bs3CpuInstr3_vpshufd_YMM12_YMM7_0FFh_icebp_c64, 255, RM_REG, T_AVX2_256, 12, 7, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpshufd_YMM9_YMM12_01Bh_icebp_c64, 255, RM_REG, T_AVX2_256, 9, 12, RT_ELEMENTS(s_aValues1B), s_aValues1B }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/); +} + + +/** + * Values shared by the move functions (same input as output). + */ +static BS3CPUINSTR3_TEST3_VALUES_T const g_aMoveValues3[] = +{ + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb) }, +}; + + +/* + * MOVNTDQA - load double qword, strictly aligned, with non-temporal hint. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movntdqa_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_movntdqa_XMM10_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntdqa_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovntdqa_XMM11_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntdqa_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovntdqa_YMM12_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movntdqa(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_movntdqa_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdqa_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdqa_YMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_movntdqa_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdqa_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdqa_YMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_movntdqa_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movntdqa_XMM10_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE4_1, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdqa_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdqa_XMM11_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdqa_YMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdqa_YMM12_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX2_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/); +} + + +/* + * MOVNTDQ - store double qword, strictly aligned, with non-temporal hint. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movntdq_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movntdq_FSxBX_XMM10_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntdq_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovntdq_FSxBX_XMM10_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntdq_FSxBX_YMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovntdq_FSxBX_YMM10_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movntdq(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_movntdq_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE2, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdq_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdq_FSxBX_YMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_movntdq_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE2, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdq_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdq_FSxBX_YMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_movntdq_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE2, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movntdq_FSxBX_XMM10_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE2, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdq_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdq_FSxBX_XMM10_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdq_FSxBX_YMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntdq_FSxBX_YMM10_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/); +} + + +/* + * [V]MOVNPS / [V]MOVNTPD - load single/double precision floating-point, aligned, + * with non-temporal hint. Only difference is the unit. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movntps_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movntps_FSxBX_XMM10_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntps_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovntps_FSxBX_XMM11_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntps_FSxBX_YMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovntps_FSxBX_YMM12_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movntpd_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movntpd_FSxBX_XMM10_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntpd_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovntpd_FSxBX_XMM11_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovntpd_FSxBX_YMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovntpd_FSxBX_YMM12_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movntps_movntpd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_movntps_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntps_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntps_FSxBX_YMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_movntpd_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntpd_FSxBX_XMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntpd_FSxBX_YMM1_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_movntps_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntps_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntps_FSxBX_YMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_movntpd_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntpd_FSxBX_XMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntpd_FSxBX_YMM1_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_movntps_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movntps_FSxBX_XMM10_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntps_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntps_FSxBX_XMM11_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntps_FSxBX_YMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntps_FSxBX_YMM12_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_movntpd_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movntpd_FSxBX_XMM10_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntpd_FSxBX_XMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntpd_FSxBX_XMM11_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntpd_FSxBX_YMM1_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovntpd_FSxBX_YMM12_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/); +} + + +/* + * MOVUPS - packed single-precision floating point, unaligned. + * + * Note! We only cover one of the two register<->register variants here + * thanks to the assembler (probably the one with the smaller opcode). + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movups_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movups_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_movups_XMM8_XMM12_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movups_XMM10_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovups_XMM7_XMM14_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovups_XMM11_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovups_YMM12_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovups_YMM12_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movups_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movups_FSxBX_XMM10_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovups_FSxBX_XMM11_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovups_FSxBX_YMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovups_FSxBX_YMM12_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movups(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_movups_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movups_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movups_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovups_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovups_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_FSxBX_YMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_movups_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movups_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movups_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovups_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovups_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_FSxBX_YMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_movups_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movups_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movups_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movups_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movups_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movups_FSxBX_XMM10_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovups_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovups_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_FSxBX_YMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovups_FSxBX_YMM12_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4Unaligned, RT_ELEMENTS(g_aXcptConfig4Unaligned), 0 /*cbMaxAlign*/); +} + + +/* + * MOVUPD - packed double-precision floating point, unaligned. + * + * Note! We only cover one of the two register<->register variants here + * thanks to the assembler (probably the one with the smaller opcode). + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movupd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movupd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_movupd_XMM8_XMM12_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movupd_XMM10_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovupd_XMM7_XMM14_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovupd_XMM11_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovupd_YMM12_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovupd_YMM12_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movupd_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movupd_FSxBX_XMM10_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovupd_FSxBX_XMM11_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovupd_FSxBX_YMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovupd_FSxBX_YMM12_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movupd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_movupd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movupd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movupd_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovupd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovupd_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_FSxBX_YMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_movupd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movupd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movupd_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovupd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovupd_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_FSxBX_YMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_movupd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movupd_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movupd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movupd_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movupd_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movupd_FSxBX_XMM10_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovupd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovupd_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_FSxBX_YMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovupd_FSxBX_YMM12_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4Unaligned, RT_ELEMENTS(g_aXcptConfig4Unaligned), 0 /*cbMaxAlign*/); +} + + +/* + * [V]MOVSLDUP - Duplicate even single precision floating-point values. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movsldup_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movsldup_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_movsldup_XMM8_XMM12_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movsldup_XMM10_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsldup_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsldup_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovsldup_XMM7_XMM14_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovsldup_XMM11_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsldup_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovsldup_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovsldup_YMM12_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovsldup_YMM12_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movsldup(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0xbbbbccccbbbbcccc, 0xffff2121ffff2121, 0x3333444433334444, 0x7777888877778888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x6cdc73d56cdc73d5, 0x666b3fe6666b3fe6, 0x564c9ba2564c9ba2, 0x930996bb930996bb) }, + }; + + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_movsldup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movsldup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovsldup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovsldup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovsldup_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovsldup_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_movsldup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movsldup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovsldup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovsldup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovsldup_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovsldup_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_movsldup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movsldup_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE3, 8, 12, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movsldup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movsldup_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 10, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovsldup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovsldup_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovsldup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovsldup_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovsldup_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovsldup_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovsldup_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovsldup_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/); +} + + +/* + * [V]MOVSHDUP - Duplicate even single precision floating-point values. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movshdup_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movshdup_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_movshdup_XMM8_XMM12_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movshdup_XMM10_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovshdup_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovshdup_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovshdup_XMM7_XMM14_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovshdup_XMM11_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovshdup_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovshdup_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovshdup_YMM12_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovshdup_YMM12_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movshdup(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x9999aaaa9999aaaa, 0xddddeeeeddddeeee, 0x1111222211112222, 0x5555666655556666) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x4d09f02a4d09f02a, 0x3ef417c83ef417c8, 0xb4212fa8b4212fa8, 0x9c5ce0739c5ce073) }, + }; + + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_movshdup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movshdup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovshdup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovshdup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovshdup_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovshdup_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_movshdup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movshdup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovshdup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovshdup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovshdup_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovshdup_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_movshdup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movshdup_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE3, 8, 12, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movshdup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movshdup_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 10, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovshdup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovshdup_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovshdup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovshdup_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovshdup_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovshdup_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovshdup_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovshdup_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), 0 /*cbMaxAlign*/); +} + + +/* + * [V]MOVDDUP - Duplicate even single precision floating-point values. + * + * Similar to MOVSLDUP, but different exception class and unit size. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movddup_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movddup_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_movddup_XMM8_XMM12_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movddup_XMM10_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovddup_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovddup_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovddup_XMM7_XMM14_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovddup_XMM11_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovddup_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovddup_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovddup_YMM12_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovddup_YMM12_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movddup(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0xddddeeeeffff2121, 0xddddeeeeffff2121, 0x5555666677778888, 0x5555666677778888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x3ef417c8666b3fe6, 0x3ef417c8666b3fe6, 0x9c5ce073930996bb, 0x9c5ce073930996bb) }, + }; + + /* Note! Seems the 256-bit variants doesn't generate \#ACs on a 10980XE. WEIRD! */ + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_movddup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movddup_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovddup_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovddup_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovddup_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovddup_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_movddup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movddup_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovddup_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovddup_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovddup_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovddup_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_movddup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE3, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movddup_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE3, 8, 12, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movddup_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_movddup_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 10, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovddup_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovddup_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovddup_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovddup_XMM11_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vmovddup_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovddup_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovddup_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vmovddup_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5), 0 /*cbMaxAlign*/); +} + + +/* + * [V]MOVAPS / [V]MOVAPD + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movaps_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movaps_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_movaps_XMM8_XMM12_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movaps_XMM10_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovaps_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovaps_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovaps_XMM7_XMM14_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovaps_XMM11_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovaps_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovaps_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovaps_YMM12_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovaps_YMM12_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movapd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movapd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_movapd_XMM8_XMM12_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movapd_XMM10_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovapd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovapd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovapd_XMM7_XMM14_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovapd_XMM11_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovapd_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovapd_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovapd_YMM12_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovapd_YMM12_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movaps_movapd(uint8_t bMode) +{ + /* Note! Seems the 256-bit variants doesn't generate \#ACs on a 10980XE. WEIRD! */ + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_movaps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movaps_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movapd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movapd_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovaps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovaps_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_XMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovaps_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovaps_YMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_YMM1_FSxBX_icebp_c16, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_movaps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movaps_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movapd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movapd_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovaps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovaps_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_XMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovaps_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovaps_YMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_YMM1_FSxBX_icebp_c32, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_movaps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movaps_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movaps_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movaps_XMM10_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movapd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movapd_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movapd_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movapd_XMM10_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovaps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovaps_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovaps_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovaps_XMM11_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_XMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_XMM11_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovaps_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovaps_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovaps_YMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovaps_YMM12_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_YMM1_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovapd_YMM12_FSxBX_icebp_c64, X86_XCPT_GP, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/); +} + + +/* + * [V]MOVDQU - move unaligned packed qwords. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movdqu_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_07f_movdqu_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movdqu_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_movdqu_XMM8_XMM12_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_07f_movdqu_XMM8_XMM12_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movdqu_XMM10_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqu_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_07f_vmovdqu_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqu_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovdqu_XMM7_XMM14_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovdqu_XMM11_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqu_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_07f_vmovdqu_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqu_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovdqu_YMM12_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovdqu_YMM12_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movdqu_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movdqu_FSxBX_XMM10_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqu_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovdqu_FSxBX_XMM11_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqu_FSxBX_YMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovdqu_FSxBX_YMM12_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movdqu(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_movdqu_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_movdqu_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqu_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqu_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovdqu_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_vmovdqu_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_FSxBX_XMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovdqu_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_vmovdqu_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_FSxBX_YMM1_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_movdqu_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_movdqu_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqu_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqu_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovdqu_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_vmovdqu_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_FSxBX_XMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovdqu_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_vmovdqu_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_FSxBX_YMM1_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_movdqu_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_movdqu_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqu_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_movdqu_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqu_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqu_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqu_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqu_FSxBX_XMM10_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovdqu_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_vmovdqu_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_XMM7_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 7, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_FSxBX_XMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovdqu_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_vmovdqu_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_FSxBX_YMM1_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqu_FSxBX_YMM12_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4Unaligned, RT_ELEMENTS(g_aXcptConfig4Unaligned), 0 /*cbMaxAlign*/); +} + + +/* + * [V]MOVDQA - move aligned packed qwords. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movdqa_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_07f_movdqa_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movdqa_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_movdqa_XMM8_XMM12_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_07f_movdqa_XMM8_XMM12_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_movdqa_XMM10_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqa_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_07f_vmovdqa_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqa_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovdqa_XMM8_XMM14_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_07f_vmovdqa_XMM8_XMM14_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovdqa_XMM11_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqa_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_07f_vmovdqa_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqa_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovdqa_YMM12_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_07f_vmovdqa_YMM12_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vmovdqa_YMM12_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movdqa_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_movdqa_FSxBX_XMM10_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqa_FSxBX_XMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovdqa_FSxBX_XMM11_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovdqa_FSxBX_YMM1_icebp); +extern FNBS3FAR bs3CpuInstr3_vmovdqa_FSxBX_YMM12_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movdqa(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_movdqa_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_movdqa_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqa_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqa_FSxBX_XMM1_icebp_c16, 255, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovdqa_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_vmovdqa_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_FSxBX_XMM1_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovdqa_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_vmovdqa_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_YMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_FSxBX_YMM1_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_movdqa_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_movdqa_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqa_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqa_FSxBX_XMM1_icebp_c32, 255, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovdqa_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_vmovdqa_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_FSxBX_XMM1_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovdqa_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_vmovdqa_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_YMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_FSxBX_YMM1_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_movdqa_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_movdqa_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqa_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_movdqa_XMM8_XMM12_icebp_c64, 255, RM_REG, T_SSE, 8, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqa_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqa_XMM10_FSxBX_icebp_c64, 255, RM_MEM, T_SSE, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqa_FSxBX_XMM1_icebp_c64, 255, RM_MEM, T_SSE, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_movdqa_FSxBX_XMM10_icebp_c64, 255, RM_MEM, T_SSE, 255, 10, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovdqa_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_vmovdqa_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_XMM8_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 8, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_vmovdqa_XMM8_XMM14_icebp_c64, 255, RM_REG, T_AVX_128, 8, 14, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_XMM11_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_FSxBX_XMM1_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_FSxBX_XMM11_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 255, 11, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vmovdqa_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_vmovdqa_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_07f_vmovdqa_YMM12_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 12, 8, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_YMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_YMM12_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_FSxBX_YMM1_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 255, 1, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vmovdqa_FSxBX_YMM12_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_256, 255, 12, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig1, RT_ELEMENTS(g_aXcptConfig1), 255 /*cbMaxAlign*/); +} + + +/* + * [V]PABSB / [V]PABSW / [V]PABSD + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsb_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsb_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsb_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsb_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pabsb_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pabsb_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsb_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsb_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpabsb_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpabsb_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsb_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsb_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpabsb_YMM9_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpabsb_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsw_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsw_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pabsw_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pabsw_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpabsw_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpabsw_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsw_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsw_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpabsw_YMM9_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpabsw_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsd_MM1_MM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsd_MM1_FSxBX_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pabsd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pabsd_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pabsd_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpabsd_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpabsd_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsd_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpabsd_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpabsd_YMM9_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpabsd_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pabsb_pabsw_pabsd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesB[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0x0101010101010101, 0x0101010101010101, 0x0101010101010101, 0x0101010101010101) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x6767565645453434, 0x2323121201012121, 0x1111222233334444, 0x5555666677777878) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x4d09102a6c24732b, 0x3e0c1738666b3f1a, 0x4c212f58564c655e, 0x645c20736d096a45) }, + }; + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesW[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0x0001000100010001, 0x0001000100010001, 0x0001000100010001, 0x0001000100010001) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x6667555644453334, 0x2223111200012121, 0x1111222233334444, 0x5555666677777778) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x4d090fd66cdc73d5, 0x3ef417c8666b3fe6, 0x4bdf2fa8564c645e, 0x63a41f8d6cf76945) }, + }; + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesD[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0x0000000100000001, 0x0000000100000001, 0x0000000100000001, 0x0000000100000001) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x6666555644443334, 0x222211120000dedf, 0x1111222233334444, 0x5555666677778888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0x4bded058564c9ba2, 0x63a31f8d6cf66945) }, + }; + + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_pabsb_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pabsb_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pabsb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pabsb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pabsw_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pabsw_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pabsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pabsw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pabsd_MM1_MM2_icebp_c16, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pabsd_MM1_FSxBX_icebp_c16, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pabsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pabsd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_pabsb_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pabsb_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pabsb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pabsb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pabsw_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pabsw_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pabsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pabsw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pabsd_MM1_MM2_icebp_c32, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pabsd_MM1_FSxBX_icebp_c32, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pabsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pabsd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_pabsb_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pabsb_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pabsb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pabsb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pabsb_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSSE3, 9, 8, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_pabsb_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + { bs3CpuInstr3_vpabsb_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesB), s_aValuesB }, + + { bs3CpuInstr3_pabsw_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pabsw_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pabsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pabsw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pabsw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSSE3, 9, 8, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_pabsw_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + { bs3CpuInstr3_vpabsw_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesW), s_aValuesW }, + + { bs3CpuInstr3_pabsd_MM1_MM2_icebp_c64, 255, RM_REG, T_MMX_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pabsd_MM1_FSxBX_icebp_c64, 255, RM_MEM, T_MMX_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pabsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSSE3, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pabsd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pabsd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSSE3, 9, 8, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_pabsd_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSSE3, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + { bs3CpuInstr3_vpabsd_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesD), s_aValuesD }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS); +} + + +/* + * [V]PMOVSXBW / [V]PMOVSXBD / [V]PMOVSXBQ / [V]PMOVSXWD / [V]PMOVSXWQ / [V]PMOVSXDQ + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovsxbw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovsxbw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmovsxbw_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmovsxbw_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxbw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxbw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovsxbw_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovsxbw_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxbw_YMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxbw_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovsxbw_YMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovsxbw_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovsxbd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovsxbd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmovsxbd_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmovsxbd_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxbd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxbd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovsxbd_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovsxbd_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxbd_YMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxbd_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovsxbd_YMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovsxbd_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovsxbq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovsxbq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmovsxbq_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmovsxbq_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxbq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxbq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovsxbq_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovsxbq_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxbq_YMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxbq_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovsxbq_YMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovsxbq_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovsxwd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovsxwd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmovsxwd_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmovsxwd_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxwd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxwd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovsxwd_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovsxwd_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxwd_YMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxwd_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovsxwd_YMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovsxwd_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovsxwq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovsxwq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmovsxwq_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmovsxwq_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxwq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxwq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovsxwq_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovsxwq_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxwq_YMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxwq_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovsxwq_YMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovsxwq_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovsxdq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovsxdq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmovsxdq_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmovsxdq_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxdq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxdq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovsxdq_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovsxdq_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxdq_YMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovsxdq_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovsxdq_YMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovsxdq_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmovsxbw_pmovsxbd_pmovsxbq_pmovsxwd_pmovsxwq_pmovsxdq(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesBW[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x0011001100220022, 0x0033003300440044, 0x0055005500660066, 0x00770077ff88ff88) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0xffb40021002fffa8, 0x0056004cff9bffa2, 0xff9c005cffe00073, 0xff930009ff96ffbb) }, + }; + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesBD[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x0000005500000055, 0x0000006600000066, 0x0000007700000077, 0xffffff88ffffff88) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0xffffff9c0000005c, 0xffffffe000000073, 0xffffff9300000009, 0xffffff96ffffffbb) }, + }; + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesBQ[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x0000000000000077, 0x0000000000000077, 0xffffffffffffff88, 0xffffffffffffff88) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0xffffffffffffff93, 0x0000000000000009, 0xffffffffffffff96, 0xffffffffffffffbb) }, + }; + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesWD[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x0000111100002222, 0x0000333300004444, 0x0000555500006666, 0x00007777ffff8888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0xffffb42100002fa8, 0x0000564cffff9ba2, 0xffff9c5cffffe073, 0xffff9309ffff96bb) }, + }; + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesWQ[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x0000000000005555, 0x0000000000006666, 0x0000000000007777, 0xffffffffffff8888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0xffffffffffff9c5c, 0xffffffffffffe073, 0xffffffffffff9309, 0xffffffffffff96bb) }, + }; + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesDQ[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x0000000011112222, 0x0000000033334444, 0x0000000055556666, 0x0000000077778888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0xffffffffb4212fa8, 0x00000000564c9ba2, 0xffffffff9c5ce073, 0xffffffff930996bb) }, + }; + + /** @todo Some variants produce different results wrt. to #DB vs #AC exceptions on real hardware (i7-6700K) and in a VM. + * The exception encountered on real hardware is put in the comment, the X86_XCPT_DB is when emulating the instruction using IEM. + * Needs investigation + */ + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_pmovsxbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_pmovsxbw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + + { bs3CpuInstr3_pmovsxbd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_pmovsxbd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + + { bs3CpuInstr3_pmovsxbq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_pmovsxbq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_YMM1_FSxBX_icebp_c16, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + + { bs3CpuInstr3_pmovsxwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_pmovsxwd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + + { bs3CpuInstr3_pmovsxwq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_pmovsxwq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_YMM1_FSxBX_icebp_c16, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + + { bs3CpuInstr3_pmovsxdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_pmovsxdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_pmovsxbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_pmovsxbw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + + { bs3CpuInstr3_pmovsxbd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_pmovsxbd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + + { bs3CpuInstr3_pmovsxbq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_pmovsxbq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_YMM1_FSxBX_icebp_c32, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + + { bs3CpuInstr3_pmovsxwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_pmovsxwd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + + { bs3CpuInstr3_pmovsxwq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_pmovsxwq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_YMM1_FSxBX_icebp_c32, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + + { bs3CpuInstr3_pmovsxdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_pmovsxdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_pmovsxbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_pmovsxbw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_pmovsxbw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_pmovsxbw_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovsxbw_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + + { bs3CpuInstr3_pmovsxbd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_pmovsxbd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_pmovsxbd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_pmovsxbd_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovsxbd_YMM9_FSxBX_icebp_c64, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + + { bs3CpuInstr3_pmovsxbq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_pmovsxbq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_pmovsxbq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_pmovsxbq_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_YMM1_FSxBX_icebp_c64, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovsxbq_YMM9_FSxBX_icebp_c64, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + + { bs3CpuInstr3_pmovsxwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_pmovsxwd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_pmovsxwd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_pmovsxwd_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovsxwd_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + + { bs3CpuInstr3_pmovsxwq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_pmovsxwq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_pmovsxwq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_pmovsxwq_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_YMM1_FSxBX_icebp_c64, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovsxwq_YMM9_FSxBX_icebp_c64, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + + { bs3CpuInstr3_pmovsxdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_pmovsxdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_pmovsxdq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_pmovsxdq_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovsxdq_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5), X86_EFL_STATUS_BITS); +} + + +/* + * [V]PMOVZXBW / [V]PMOVZXBD / [V]PMOVZXBQ / [V]PMOVZXWD / [V]PMOVZXWQ / [V]PMOVZXDQ + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovzxbw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovzxbw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmovzxbw_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmovzxbw_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxbw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxbw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovzxbw_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovzxbw_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxbw_YMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxbw_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovzxbw_YMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovzxbw_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovzxbd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovzxbd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmovzxbd_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmovzxbd_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxbd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxbd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovzxbd_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovzxbd_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxbd_YMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxbd_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovzxbd_YMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovzxbd_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovzxbq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovzxbq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmovzxbq_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmovzxbq_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxbq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxbq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovzxbq_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovzxbq_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxbq_YMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxbq_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovzxbq_YMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovzxbq_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovzxwd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovzxwd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmovzxwd_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmovzxwd_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxwd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxwd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovzxwd_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovzxwd_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxwd_YMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxwd_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovzxwd_YMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovzxwd_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovzxwq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovzxwq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmovzxwq_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmovzxwq_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxwq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxwq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovzxwq_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovzxwq_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxwq_YMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxwq_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovzxwq_YMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovzxwq_YMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovzxdq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pmovzxdq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pmovzxdq_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pmovzxdq_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxdq_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxdq_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovzxdq_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovzxdq_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxdq_YMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpmovzxdq_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vpmovzxdq_YMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpmovzxdq_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pmovzxbw_pmovzxbd_pmovzxbq_pmovzxwd_pmovzxwq_pmovzxdq(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesBW[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0x00ff00ff00ff00ff, 0x00ff00ff00ff00ff, 0x00ff00ff00ff00ff, 0x00ff00ff00ff00ff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x0011001100220022, 0x0033003300440044, 0x0055005500660066, 0x0077007700880088) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x00b40021002f00a8, 0x0056004c009b00a2, 0x009c005c00e00073, 0x00930009009600bb) }, + }; + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesBD[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0x000000ff000000ff, 0x000000ff000000ff, 0x000000ff000000ff, 0x000000ff000000ff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x0000005500000055, 0x0000006600000066, 0x0000007700000077, 0x0000008800000088) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x0000009c0000005c, 0x000000e000000073, 0x0000009300000009, 0x00000096000000bb) }, + }; + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesBQ[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0x00000000000000ff, 0x00000000000000ff, 0x00000000000000ff, 0x00000000000000ff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x0000000000000077, 0x0000000000000077, 0x0000000000000088, 0x0000000000000088) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x0000000000000093, 0x0000000000000009, 0x0000000000000096, 0x00000000000000bb) }, + }; + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesWD[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0x0000ffff0000ffff, 0x0000ffff0000ffff, 0x0000ffff0000ffff, 0x0000ffff0000ffff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x0000111100002222, 0x0000333300004444, 0x0000555500006666, 0x0000777700008888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x0000b42100002fa8, 0x0000564c00009ba2, 0x00009c5c0000e073, 0x00009309000096bb) }, + }; + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesWQ[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0x000000000000ffff, 0x000000000000ffff, 0x000000000000ffff, 0x000000000000ffff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x0000000000005555, 0x0000000000006666, 0x0000000000007777, 0x0000000000008888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x0000000000009c5c, 0x000000000000e073, 0x0000000000009309, 0x00000000000096bb) }, + }; + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValuesDQ[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(0x00000000ffffffff, 0x00000000ffffffff, 0x00000000ffffffff, 0x00000000ffffffff) }, + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(0x0000000011112222, 0x0000000033334444, 0x0000000055556666, 0x0000000077778888) }, + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(0x00000000b4212fa8, 0x00000000564c9ba2, 0x000000009c5ce073, 0x00000000930996bb) }, + }; + + /** @todo Some variants produce different results wrt. to #DB vs #AC exceptions on real hardware (i7-6700K) and in a VM. + * The exception encountered on real hardware is put in the comment, the X86_XCPT_DB is when emulating the instruction using IEM. + * Needs investigation + */ + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_pmovzxbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_pmovzxbw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + + { bs3CpuInstr3_pmovzxbd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_pmovzxbd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + + { bs3CpuInstr3_pmovzxbq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_pmovzxbq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_YMM1_FSxBX_icebp_c16, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + + { bs3CpuInstr3_pmovzxwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_pmovzxwd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + + { bs3CpuInstr3_pmovzxwq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_pmovzxwq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_YMM1_FSxBX_icebp_c16, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + + { bs3CpuInstr3_pmovzxdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_pmovzxdq_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_XMM1_FSxBX_icebp_c16, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_YMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_YMM1_FSxBX_icebp_c16, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_pmovzxbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_pmovzxbw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_YMM1_FSxBX_icebp_c32, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + + { bs3CpuInstr3_pmovzxbd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_pmovzxbd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + + { bs3CpuInstr3_pmovzxbq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_pmovzxbq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_YMM1_FSxBX_icebp_c32, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + + { bs3CpuInstr3_pmovzxwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_pmovzxwd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_YMM1_FSxBX_icebp_c32, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + + { bs3CpuInstr3_pmovzxwq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_pmovzxwq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_YMM1_FSxBX_icebp_c32, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + + { bs3CpuInstr3_pmovzxdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_pmovzxdq_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_XMM1_FSxBX_icebp_c32, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_YMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_pmovzxbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_pmovzxbw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_pmovzxbw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_pmovzxbw_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + { bs3CpuInstr3_vpmovzxbw_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesBW), s_aValuesBW }, + + { bs3CpuInstr3_pmovzxbd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_pmovzxbd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_pmovzxbd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_pmovzxbd_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + { bs3CpuInstr3_vpmovzxbd_YMM9_FSxBX_icebp_c64, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesBD), s_aValuesBD }, + + { bs3CpuInstr3_pmovzxbq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_pmovzxbq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_pmovzxbq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_pmovzxbq_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_YMM1_FSxBX_icebp_c64, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + { bs3CpuInstr3_vpmovzxbq_YMM9_FSxBX_icebp_c64, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesBQ), s_aValuesBQ }, + + { bs3CpuInstr3_pmovzxwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_pmovzxwd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_pmovzxwd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_pmovzxwd_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + { bs3CpuInstr3_vpmovzxwd_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesWD), s_aValuesWD }, + + { bs3CpuInstr3_pmovzxwq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_pmovzxwq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_pmovzxwq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_pmovzxwq_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_YMM1_FSxBX_icebp_c64, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + { bs3CpuInstr3_vpmovzxwq_YMM9_FSxBX_icebp_c64, X86_XCPT_DB /*AC*/, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesWQ), s_aValuesWQ }, + + { bs3CpuInstr3_pmovzxdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_pmovzxdq_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_pmovzxdq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_pmovzxdq_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_XMM1_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_XMM9_FSxBX_icebp_c64, X86_XCPT_AC, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_YMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_YMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + { bs3CpuInstr3_vpmovzxdq_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValuesDQ), s_aValuesDQ }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5), X86_EFL_STATUS_BITS); +} + + +/* + * [V]LDDQU - Load unaligned integer from memory. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_lddqu_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_lddqu_XMM10_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vlddqu_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vlddqu_XMM11_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vlddqu_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vlddqu_YMM12_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_lddqu(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_lddqu_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vlddqu_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vlddqu_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_lddqu_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vlddqu_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vlddqu_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_lddqu_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_lddqu_XMM10_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_SSE3, 10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vlddqu_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vlddqu_XMM11_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + + { bs3CpuInstr3_vlddqu_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + { bs3CpuInstr3_vlddqu_YMM12_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4Unaligned, RT_ELEMENTS(g_aXcptConfig4Unaligned), 0 /*cbMaxAlign*/); +} + + +/* + * [V]PHMINPOSUW + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phminposuw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_phminposuw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_phminposuw_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_phminposuw_XMM9_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphminposuw_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vphminposuw_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vphminposuw_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vphminposuw_XMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_phminposuw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST3_VALUES_T const s_aValues[] = + { + { RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ RTUINT256_INIT_C(1, 2, 0x0000000000000000, 0x000000000000ffff) }, /* No 256-bit variant */ + { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff2121, 0x1111222233334444, 0x5555666677778888), + /* => */ RTUINT256_INIT_C(5, 6, 0x0000000000000000, 0x0000000000071111) }, /* No 256-bit variant */ + { RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /* => */ RTUINT256_INIT_C(9, 10, 0x0000000000000000, 0x0000000000062fa8) }, /* No 256-bit variant */ + }; + + static BS3CPUINSTR3_TEST3_T const s_aTests16[] = + { + { bs3CpuInstr3_phminposuw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_phminposuw_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vphminposuw_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vphminposuw_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests32[] = + { + { bs3CpuInstr3_phminposuw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_phminposuw_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vphminposuw_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vphminposuw_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST3_T const s_aTests64[] = + { + { bs3CpuInstr3_phminposuw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_phminposuw_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_phminposuw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_phminposuw_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vphminposuw_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vphminposuw_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vphminposuw_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vphminposuw_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS); +} + + +/* + * Test type #4 - two source MM/XMM/YMM operands, outputs only eflags. + * + * Probably only used by the PTEST instruction. + */ + +typedef struct BS3CPUINSTR3_TEST4_VALUES_T +{ + RTUINT256U uSrc2; + RTUINT256U uSrc1; + uint16_t afEflOut[3]; /* [0]=MM result, [1]=XMM result, [2]=YMM result */ +} BS3CPUINSTR3_TEST4_VALUES_T; + +typedef struct BS3CPUINSTR3_TEST4_T +{ + FPFNBS3FAR pfnWorker; + uint8_t bAvxMisalignXcpt; + uint8_t enmRm; + uint8_t enmType; + uint8_t iRegSrc1; + uint8_t iRegSrc2; + uint8_t cValues; + BS3CPUINSTR3_TEST4_VALUES_T const BS3_FAR *paValues; +} BS3CPUINSTR3_TEST4_T; + +typedef struct BS3CPUINSTR3_TEST4_MODE_T +{ + BS3CPUINSTR3_TEST4_T const BS3_FAR *paTests; + unsigned cTests; +} BS3CPUINSTR3_TEST4_MODE_T; + +/** Initializer for a BS3CPUINSTR3_TEST4_MODE_T array (three entries). */ +#define BS3CPUINSTR3_TEST4_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ + { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } + + +/** + * Test type #4 worker. + */ +static uint8_t bs3CpuInstr3_WorkerTestType4(uint8_t bMode, BS3CPUINSTR3_TEST4_T const BS3_FAR *paTests, unsigned cTests, + PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs, uint32_t fEflCheck) +{ + BS3REGCTX Ctx; + BS3TRAPFRAME TrapFrame; + const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); + uint8_t BS3_FAR *pbBuf = g_pbBuf; + uint32_t cbBuf = g_cbBuf; + uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; + PBS3EXTCTX pExtCtxOut; + PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); + if (!pExtCtx) + return 0; + + /* Ensure the structures are allocated before we sample the stack pointer. */ + Bs3MemSet(&Ctx, 0, sizeof(Ctx)); + Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); + + /* + * Create test context. + */ + Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); + bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); + pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); + + /* + * Run the tests in all rings since alignment issues may behave + * differently in ring-3 compared to ring-0. + */ + for (;;) + { + unsigned iCfg; + for (iCfg = 0; iCfg < cConfigs; iCfg++) + { + unsigned iTest; + BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; + if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) + continue; /* unsupported config */ + + /* + * Iterate the tests. + */ + for (iTest = 0; iTest < cTests; iTest++) + { + BS3CPUINSTR3_TEST4_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; + uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; + unsigned const cValues = paTests[iTest].cValues; + bool const fMmxInstr = paTests[iTest].enmType < T_SSE; + bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; + bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; + uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 + : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; + uint8_t const cbMemOp = cbOperand; + uint8_t const cbAlign = RT_MIN(cbOperand, 16); + PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]); + uint8_t const idxEflOut = cbOperand == 32 ? 2 : cbOperand == 16 ? 1 : 0; + uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD + : fMmxInstr ? paConfigs[iCfg].bXcptMmx + : fSseInstr ? paConfigs[iCfg].bXcptSse + : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; + uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; + unsigned iVal; + + /* If testing unaligned memory accesses, skip register-only tests. This allows + setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ + if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck)) + continue; + + /* #AC is only raised in ring-3.: */ + if (bXcptExpect == X86_XCPT_AC) + { + if (bRing != 3) + bXcptExpect = X86_XCPT_DB; + else if (fAvxInstr) + bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ + } + + Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); + + /* + * Iterate the test values and do the actual testing. + */ + for (iVal = 0; iVal < cValues; iVal++, idTestStep++) + { + unsigned iEflVariation; + uint32_t const fSavedEfl = Ctx.rflags.u32; + for (iEflVariation = 0; iEflVariation < 2; iEflVariation++) + { + uint16_t cErrors; + uint16_t uSavedFtw = 0xff; + RTUINT256U uMemOpExpect; + + /* + * Set up the context and some expectations. + */ + /* eflags */ + if (iEflVariation) + Ctx.rflags.u32 = fSavedEfl | X86_EFL_STATUS_BITS; + else + Ctx.rflags.u32 = fSavedEfl & ~X86_EFL_STATUS_BITS; + + /* source1 */ + if (paTests[iTest].iRegSrc1 == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + BS3_ASSERT(paTests[iTest].iRegSrc2 != UINT8_MAX); + Bs3MemCpy(puMemOp, &paValues[iVal].uSrc1, cbMemOp); + uMemOpExpect = paValues[iVal].uSrc1; + } + else if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc1, paValues[iVal].uSrc1.QWords.qw0, BS3EXTCTXTOPMM_ZERO); + else if (fSseInstr) + Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1.DQWords.dqw0); + else + Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1, 32); + + /* source2 */ + if (paTests[iTest].iRegSrc2 == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + BS3_ASSERT(paTests[iTest].iRegSrc1 != UINT8_MAX); + Bs3MemCpy(puMemOp, &paValues[iVal].uSrc2, cbMemOp); + uMemOpExpect = paValues[iVal].uSrc2; + } + else if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, paValues[iVal].uSrc2.QWords.qw0, BS3EXTCTXTOPMM_ZERO); + else if (fSseInstr) + Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2.DQWords.dqw0); + else + Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2, 32); + + /* Memory pointer. */ + if (paTests[iTest].enmRm >= RM_MEM) + { + BS3_ASSERT( paTests[iTest].iRegSrc1 == UINT8_MAX + || paTests[iTest].iRegSrc2 == UINT8_MAX); + Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); + } + + /* + * Execute. + */ + Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); + + /* + * Check the result: + */ + cErrors = Bs3TestSubErrorCount(); + + if (bXcptExpect == X86_XCPT_DB && fMmxInstr) + { + uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); + Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); + } + Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); + + if (TrapFrame.bXcpt != bXcptExpect) + Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); + + /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ + if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) + { + if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) + Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); + TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; + } + if (bXcptExpect == X86_XCPT_DB) + Ctx.rflags.u32 = (Ctx.rflags.u32 & ~fEflCheck) | paValues[iVal].afEflOut[idxEflOut]; + Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, + bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, + pszMode, idTestStep); + + if ( paTests[iTest].enmRm >= RM_MEM + && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0) + Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp); + + if (cErrors != Bs3TestSubErrorCount()) + { + if (paConfigs[iCfg].fAligned) + Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u/efl#%u failed (bXcptExpect=%#x)", + bRing, iCfg, iTest, iVal, iEflVariation, bXcptExpect); + else + Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u/efl#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", + bRing, iCfg, iTest, iVal, iEflVariation, bXcptExpect, + puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); + Bs3TestPrintf("\n"); + } + + if (uSavedFtw != 0xff) + Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); + } + Ctx.rflags.u32 = fSavedEfl; + } + } + + bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); + } + + /* + * Next ring. + */ + bRing++; + if (bRing > 3 || bMode == BS3_MODE_RM) + break; + Bs3RegCtxConvertToRingX(&Ctx, bRing); + } + + /* + * Cleanup. + */ + bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); + bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); + return 0; +} + + +/* + * PTEST + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_ptest_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_ptest_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_ptest_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_ptest_XMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vptest_XMM9_XMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vptest_XMM9_FSxBX_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_YMM1_YMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vptest_YMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_vptest_YMM9_YMM8_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vptest_YMM9_FSxBX_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_ptest(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST4_VALUES_T const s_aValues[] = + { + { /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ { 0, X86_EFL_ZF | X86_EFL_CF, X86_EFL_ZF | X86_EFL_CF } }, + { /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /*src1*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /* => */ { 0, X86_EFL_CF, X86_EFL_CF } }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ { 0, 0, 0 } }, + { /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ { 0, 0, 0 } }, + { /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ { 0, 0, 0 } }, + { /*src2*/ RTUINT256_INIT_C(0x4d09f02a6cdc73d5, 0x3ef417c8666b3fe6, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), + /*src1*/ RTUINT256_INIT_C(0x1eddddac09633294, 0xf95c8eec40725633, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), + /* => */ { 0, 0, 0 } }, + }; + + static BS3CPUINSTR3_TEST4_T const s_aTests16[] = + { + { bs3CpuInstr3_ptest_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_ptest_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_XMM1_XMM2_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_XMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_YMM1_YMM2_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_YMM1_FSxBX_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST4_T const s_aTests32[] = + { + { bs3CpuInstr3_ptest_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_ptest_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_XMM1_XMM2_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_XMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_YMM1_YMM2_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_YMM1_FSxBX_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST4_T const s_aTests64[] = + { + { bs3CpuInstr3_ptest_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_ptest_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_ptest_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SSE4_1, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_ptest_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_XMM1_XMM2_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_XMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_XMM9_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_XMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_YMM1_YMM2_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_YMM1_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 255, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_YMM9_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 9, 8, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vptest_YMM9_FSxBX_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 9, 255, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST4_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST4_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType4(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS); +} + + +/* + * Test type #5 - three source MM/XMM/YMM operands. + * + * Probably only used by the [P]BLEND instruction. + */ + +typedef struct BS3CPUINSTR3_TEST5_VALUES_T +{ + RTUINT256U uSrc3; + RTUINT256U uSrc2; + RTUINT256U uSrc1; + RTUINT256U uDstOut; +} BS3CPUINSTR3_TEST5_VALUES_T; + +typedef struct BS3CPUINSTR3_TEST5_T +{ + FPFNBS3FAR pfnWorker; + uint8_t bAvxMisalignXcpt; + uint8_t enmRm; + uint8_t enmType; + uint8_t iRegDst; + uint8_t iRegSrc1; + uint8_t iRegSrc2; + uint8_t iRegSrc3; + uint8_t cValues; + BS3CPUINSTR3_TEST5_VALUES_T const BS3_FAR *paValues; +} BS3CPUINSTR3_TEST5_T; + +typedef struct BS3CPUINSTR3_TEST5_MODE_T +{ + BS3CPUINSTR3_TEST5_T const BS3_FAR *paTests; + unsigned cTests; +} BS3CPUINSTR3_TEST5_MODE_T; + +/** Initializer for a BS3CPUINSTR3_TEST5_MODE_T array (three entries). */ +#define BS3CPUINSTR3_TEST5_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ + { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } + + +/** + * Test type #5 worker. + */ +static uint8_t bs3CpuInstr3_WorkerTestType5(uint8_t bMode, BS3CPUINSTR3_TEST5_T const BS3_FAR *paTests, unsigned cTests, + PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs) +{ + BS3REGCTX Ctx; + BS3TRAPFRAME TrapFrame; + const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); + uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; + uint8_t BS3_FAR *pbBuf = g_pbBuf; + uint32_t cbBuf = g_cbBuf; + PBS3EXTCTX pExtCtxOut; + PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); + if (!pExtCtx) + return 0; + + /* Ensure the structures are allocated before we sample the stack pointer. */ + Bs3MemSet(&Ctx, 0, sizeof(Ctx)); + Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); + + /* + * Create test context. + */ + pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); + Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); + bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); + //Bs3TestPrintf("FTW=%#x mm1/st1=%.16Rhxs\n", pExtCtx->Ctx.x87.FTW, &pExtCtx->Ctx.x87.aRegs[1]); + + /* + * Run the tests in all rings since alignment issues may behave + * differently in ring-3 compared to ring-0. + */ + for (;;) + { + unsigned iCfg; + for (iCfg = 0; iCfg < cConfigs; iCfg++) + { + unsigned iTest; + BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; + if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) + continue; /* unsupported config */ + + /* + * Iterate the tests. + */ + for (iTest = 0; iTest < cTests; iTest++) + { + BS3CPUINSTR3_TEST5_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; + uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; + unsigned const cValues = paTests[iTest].cValues; + bool const fMmxInstr = paTests[iTest].enmType < T_SSE; + bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; + bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; + uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 + : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; + uint8_t const cbMemOp = bs3CpuInstr3MemOpSize(cbOperand, paTests[iTest].enmRm); + uint8_t const cbAlign = cbMemOp; + PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]); + uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD + : fMmxInstr ? paConfigs[iCfg].bXcptMmx + : fSseInstr ? paConfigs[iCfg].bXcptSse + : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; + uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; + unsigned iVal; + + /* If testing unaligned memory accesses, skip register-only tests. This allows + setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ + if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck)) + continue; + + /* #AC is only raised in ring-3.: */ + if (bXcptExpect == X86_XCPT_AC) + { + if (bRing != 3) + bXcptExpect = X86_XCPT_DB; + else if (fAvxInstr) + bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ + } + + Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); + + /* + * Iterate the test values and do the actual testing. + */ + for (iVal = 0; iVal < cValues; iVal++, idTestStep++) + { + uint16_t cErrors; + uint16_t uSavedFtw = 0xff; + RTUINT256U uMemOpExpect; + + /* + * Set up the context and some expectations. + */ + /* dest */ + if (paTests[iTest].iRegDst == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + Bs3MemSet(puMemOp, 0xcc, cbMemOp); + if (bXcptExpect == X86_XCPT_DB) + uMemOpExpect = paValues[iVal].uDstOut; + else + Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); + } + else if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, ~paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_ZERO); + + /* source #1 (/ destination for MMX and SSE) */ + if (paTests[iTest].iRegSrc1 == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + Bs3MemCpy(puMemOp, &paValues[iVal].uSrc1, cbMemOp); + if (paTests[iTest].iRegDst == UINT8_MAX) + BS3_ASSERT(fSseInstr); + else + uMemOpExpect = paValues[iVal].uSrc1; + } + else if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc1, paValues[iVal].uSrc1.QWords.qw0, BS3EXTCTXTOPMM_ZERO); + else if (fSseInstr) + Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1.DQWords.dqw0); + else + Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1, 32); + + /* source #2 */ + if (paTests[iTest].iRegSrc2 == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX && paTests[iTest].iRegSrc1 != UINT8_MAX); + Bs3MemCpy(puMemOp, &paValues[iVal].uSrc2, cbMemOp); + uMemOpExpect = paValues[iVal].uSrc2; + } + else if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, paValues[iVal].uSrc2.QWords.qw0, BS3EXTCTXTOPMM_ZERO); + else if (fSseInstr) + Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2.DQWords.dqw0); + else + Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2, 32); + + /* source #3 */ + if (paTests[iTest].iRegSrc3 == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX && paTests[iTest].iRegSrc1 != UINT8_MAX); + Bs3MemCpy(puMemOp, &paValues[iVal].uSrc3, cbMemOp); + uMemOpExpect = paValues[iVal].uSrc3; + } + else if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc3, paValues[iVal].uSrc3.QWords.qw0, BS3EXTCTXTOPMM_ZERO); + else if (fSseInstr) + Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc3, &paValues[iVal].uSrc3.DQWords.dqw0); + else + Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc3, &paValues[iVal].uSrc3, 32); + + /* Memory pointer. */ + if (paTests[iTest].enmRm >= RM_MEM) + { + BS3_ASSERT( paTests[iTest].iRegDst == UINT8_MAX + || paTests[iTest].iRegSrc1 == UINT8_MAX + || paTests[iTest].iRegSrc2 == UINT8_MAX + || paTests[iTest].iRegSrc3 == UINT8_MAX); + Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); + } + + /* + * Execute. + */ + Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); + + /* + * Check the result: + */ + cErrors = Bs3TestSubErrorCount(); + + if (fMmxInstr && bXcptExpect == X86_XCPT_DB) + { + uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); + Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); /* Observed on 10980xe after pxor mm1, mm2. */ + } + if (bXcptExpect == X86_XCPT_DB && paTests[iTest].iRegDst != UINT8_MAX) + { + if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegDst, paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_SET); + else if (fSseInstr) + Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut.DQWords.dqw0); + else + Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut, cbOperand); + } + Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); + + if (TrapFrame.bXcpt != bXcptExpect) + Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); + + /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ + if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) + { + if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) + Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); + TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; + } + Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, + bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, + pszMode, idTestStep); + + if ( paTests[iTest].enmRm >= RM_MEM + && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0) + Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp); + + if (cErrors != Bs3TestSubErrorCount()) + { + if (paConfigs[iCfg].fAligned) + Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)", + bRing, iCfg, iTest, iVal, bXcptExpect); + else + Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", + bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); + Bs3TestPrintf("\n"); + } + + if (uSavedFtw != 0xff) + Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); + } + } + + bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); + } + + /* + * Next ring. + */ + bRing++; + if (bRing > 3 || bMode == BS3_MODE_RM) + break; + Bs3RegCtxConvertToRingX(&Ctx, bRing); + } + + /* + * Cleanup. + */ + bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); + bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); + return 0; +} + + +/* + * PBLENDVB + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pblendvb_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pblendvb_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_pblendvb_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pblendvb_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendvb_XMM1_XMM2_XMM3_XMM4_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendvb_XMM1_XMM2_FSxBX_XMM4_icebp); +extern FNBS3FAR bs3CpuInstr3_vpblendvb_XMM8_XMM9_XMM10_XMM11_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpblendvb_XMM8_XMM9_FSxBX_XMM11_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendvb_YMM1_YMM2_YMM3_YMM4_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendvb_YMM1_YMM2_FSxBX_YMM4_icebp); +extern FNBS3FAR bs3CpuInstr3_vpblendvb_YMM8_YMM9_YMM10_YMM11_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpblendvb_YMM8_YMM9_FSxBX_YMM11_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pblendvb(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues[] = + { + { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { /*mask*/ RTUINT256_INIT_C(0x0000008000000000, 0x0000091000007f00, 0, 0x8080808080808080), + /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xb1b2b3f4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) }, + { /*mask*/ RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), + /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, + { /*mask*/ RTUINT256_INIT_C(0x1234567890abcdef, 0xfedcba0987654321, 0xfedcba0987654321, 0x1234567890abcdef), + /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0xddddeeee77778888, 0x111122aa33bbcccc, 0x111122aa33bbcccc, 0xddddeeee77778888) }, + }; + + static BS3CPUINSTR3_TEST5_T const s_aTests16[] = + { + { bs3CpuInstr3_pblendvb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pblendvb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vpblendvb_XMM1_XMM2_XMM3_XMM4_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpblendvb_XMM1_XMM2_FSxBX_XMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpblendvb_YMM1_YMM2_YMM3_YMM4_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpblendvb_YMM1_YMM2_FSxBX_YMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST5_T const s_aTests32[] = + { + { bs3CpuInstr3_pblendvb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pblendvb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vpblendvb_XMM1_XMM2_XMM3_XMM4_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpblendvb_XMM1_XMM2_FSxBX_XMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpblendvb_YMM1_YMM2_YMM3_YMM4_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpblendvb_YMM1_YMM2_FSxBX_YMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST5_T const s_aTests64[] = + { + { bs3CpuInstr3_pblendvb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pblendvb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pblendvb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_pblendvb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vpblendvb_XMM1_XMM2_XMM3_XMM4_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpblendvb_XMM1_XMM2_FSxBX_XMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpblendvb_XMM8_XMM9_XMM10_XMM11_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpblendvb_XMM8_XMM9_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vpblendvb_YMM1_YMM2_YMM3_YMM4_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpblendvb_YMM1_YMM2_FSxBX_YMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpblendvb_YMM8_YMM9_YMM10_YMM11_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vpblendvb_YMM8_YMM9_FSxBX_YMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST5_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST5_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType5(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * BLENDPS + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendvps_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendvps_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_blendvps_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_blendvps_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvps_XMM1_XMM2_XMM3_XMM4_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvps_XMM1_XMM2_FSxBX_XMM4_icebp); +extern FNBS3FAR bs3CpuInstr3_vblendvps_XMM8_XMM9_XMM10_XMM11_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendvps_XMM8_XMM9_FSxBX_XMM11_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvps_YMM1_YMM2_YMM3_YMM4_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvps_YMM1_YMM2_FSxBX_YMM4_icebp); +extern FNBS3FAR bs3CpuInstr3_vblendvps_YMM8_YMM9_YMM10_YMM11_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendvps_YMM8_YMM9_FSxBX_YMM11_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_blendvps(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues[] = + { + { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { /*mask*/ RTUINT256_INIT_C(0x0000008000000000, 0x0000091000007f00, 0, 0x8080808080808080), + /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) }, + { /*mask*/ RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), + /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, + { /*mask*/ RTUINT256_INIT_C(0x1234567890abcdef, 0xfedcba0987654321, 0xfedcba0987654321, 0x1234567890abcdef), + /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0xddddeeee77778888, 0x1111222233334444, 0x1111222233334444, 0xddddeeee77778888) }, + }; + + static BS3CPUINSTR3_TEST5_T const s_aTests16[] = + { + { bs3CpuInstr3_blendvps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_blendvps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vblendvps_XMM1_XMM2_XMM3_XMM4_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvps_XMM1_XMM2_FSxBX_XMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvps_YMM1_YMM2_YMM3_YMM4_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvps_YMM1_YMM2_FSxBX_YMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST5_T const s_aTests32[] = + { + { bs3CpuInstr3_blendvps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_blendvps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vblendvps_XMM1_XMM2_XMM3_XMM4_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvps_XMM1_XMM2_FSxBX_XMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvps_YMM1_YMM2_YMM3_YMM4_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvps_YMM1_YMM2_FSxBX_YMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST5_T const s_aTests64[] = + { + { bs3CpuInstr3_blendvps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_blendvps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_blendvps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_blendvps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vblendvps_XMM1_XMM2_XMM3_XMM4_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvps_XMM1_XMM2_FSxBX_XMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvps_XMM8_XMM9_XMM10_XMM11_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvps_XMM8_XMM9_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vblendvps_YMM1_YMM2_YMM3_YMM4_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvps_YMM1_YMM2_FSxBX_YMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvps_YMM8_YMM9_YMM10_YMM11_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvps_YMM8_YMM9_FSxBX_YMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST5_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST5_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType5(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * BLENDPD + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendvpd_XMM1_XMM2_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendvpd_XMM1_FSxBX_icebp); +extern FNBS3FAR bs3CpuInstr3_blendvpd_XMM8_XMM9_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_blendvpd_XMM8_FSxBX_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvpd_XMM1_XMM2_XMM3_XMM4_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvpd_XMM1_XMM2_FSxBX_XMM4_icebp); +extern FNBS3FAR bs3CpuInstr3_vblendvpd_XMM8_XMM9_XMM10_XMM11_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendvpd_XMM8_XMM9_FSxBX_XMM11_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvpd_YMM1_YMM2_YMM3_YMM4_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvpd_YMM1_YMM2_FSxBX_YMM4_icebp); +extern FNBS3FAR bs3CpuInstr3_vblendvpd_YMM8_YMM9_YMM10_YMM11_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vblendvpd_YMM8_YMM9_FSxBX_YMM11_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_blendvpd(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues[] = + { + { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, + { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), + /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), + /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, + { /*mask*/ RTUINT256_INIT_C(0x0000008000000000, 0x0000091000007f00, 0, 0x8080808080808080), + /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) }, + { /*mask*/ RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), + /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), + /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), + /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, + { /*mask*/ RTUINT256_INIT_C(0x1234567890abcdef, 0xfedcba0987654321, 0xfedcba0987654321, 0x1234567890abcdef), + /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), + /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), + /* => */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x1111222233334444, 0x1111222233334444, 0xddddeeeeffff0000) }, + }; + + static BS3CPUINSTR3_TEST5_T const s_aTests16[] = + { + { bs3CpuInstr3_blendvpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_blendvpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vblendvpd_XMM1_XMM2_XMM3_XMM4_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvpd_XMM1_XMM2_FSxBX_XMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvpd_YMM1_YMM2_YMM3_YMM4_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvpd_YMM1_YMM2_FSxBX_YMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST5_T const s_aTests32[] = + { + { bs3CpuInstr3_blendvpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_blendvpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vblendvpd_XMM1_XMM2_XMM3_XMM4_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvpd_XMM1_XMM2_FSxBX_XMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvpd_YMM1_YMM2_YMM3_YMM4_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvpd_YMM1_YMM2_FSxBX_YMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST5_T const s_aTests64[] = + { + { bs3CpuInstr3_blendvpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_blendvpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_blendvpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, 0, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_blendvpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vblendvpd_XMM1_XMM2_XMM3_XMM4_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvpd_XMM1_XMM2_FSxBX_XMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvpd_XMM8_XMM9_XMM10_XMM11_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvpd_XMM8_XMM9_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, + + { bs3CpuInstr3_vblendvpd_YMM1_YMM2_YMM3_YMM4_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvpd_YMM1_YMM2_FSxBX_YMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvpd_YMM8_YMM9_YMM10_YMM11_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, + { bs3CpuInstr3_vblendvpd_YMM8_YMM9_FSxBX_YMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, + }; + static BS3CPUINSTR3_TEST5_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST5_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType5(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); +} + + +/* + * Test type #6 - MM/XMM/YMM <- GPR, no VVVV. + * + * Used probably only by the PINSRW testcases + */ + +typedef struct BS3CPUINSTR3_TEST6_VALUES_T +{ + RTUINT256U uMediaSrc; + uint64_t uGpr; + RTUINT256U uMediaDst; +} BS3CPUINSTR3_TEST6_VALUES_T; + +typedef struct BS3CPUINSTR3_TEST6_T +{ + FPFNBS3FAR pfnWorker; + uint8_t bAvxMisalignXcpt; + uint8_t enmRm; + uint8_t enmType; + uint8_t cbGpr; + uint8_t cBitsGprValMask; + uint8_t iGprReg; + uint8_t iMediaRegSrc; + uint8_t iMediaRegDst; + uint8_t cValues; + BS3CPUINSTR3_TEST6_VALUES_T const BS3_FAR *paValues; +} BS3CPUINSTR3_TEST6_T; + +typedef struct BS3CPUINSTR3_TEST6_MODE_T +{ + BS3CPUINSTR3_TEST6_T const BS3_FAR *paTests; + unsigned cTests; +} BS3CPUINSTR3_TEST6_MODE_T; + +/** Initializer for a BS3CPUINSTR3_TEST6_MODE_T array (three entries). */ +#define BS3CPUINSTR3_TEST6_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ + { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } + + +/** + * Test type #6 worker. + */ +static uint8_t bs3CpuInstr3_WorkerTestType6(uint8_t bMode, BS3CPUINSTR3_TEST6_T const BS3_FAR *paTests, unsigned cTests, + PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs) +{ + BS3REGCTX Ctx; + BS3TRAPFRAME TrapFrame; + const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); + uint8_t BS3_FAR *pbBuf = g_pbBuf; + uint32_t cbBuf = g_cbBuf; + uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; + PBS3EXTCTX pExtCtxOut; + PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); + if (!pExtCtx) + return 0; + + /* Ensure the structures are allocated before we sample the stack pointer. */ + Bs3MemSet(&Ctx, 0, sizeof(Ctx)); + Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); + + /* + * Create test context. + */ + pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); + Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); + bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); + + /* + * Run the tests in all rings since alignment issues may behave + * differently in ring-3 compared to ring-0. + */ + for (;;) + { + unsigned iCfg; + for (iCfg = 0; iCfg < cConfigs; iCfg++) + { + unsigned iTest; + BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; + if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) + continue; /* unsupported config */ + + /* + * Iterate the tests. + */ + for (iTest = 0; iTest < cTests; iTest++) + { + BS3CPUINSTR3_TEST6_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; + uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; + unsigned const cValues = paTests[iTest].cValues; + bool const fMmxInstr = paTests[iTest].enmType < T_SSE; + bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; + bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; + uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 + : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; + uint8_t const cbMemOp = bs3CpuInstr3MemOpSize(cbOperand, paTests[iTest].enmRm); + uint8_t const cbAlign = RT_MIN(cbOperand, 16); + PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]); + uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD + : fMmxInstr ? paConfigs[iCfg].bXcptMmx + : fSseInstr ? paConfigs[iCfg].bXcptSse + : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; + uint64_t const fGprValMask = paTests[iTest].cBitsGprValMask == 64 ? UINT64_MAX + : RT_BIT_64(paTests[iTest].cBitsGprValMask) - 1; + uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; + unsigned iVal; + + /* If testing unaligned memory accesses, skip register-only tests. This allows + setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ + if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck)) + continue; + + /* #AC is only raised in ring-3.: */ + if (bXcptExpect == X86_XCPT_AC) + { + if (bRing != 3) + bXcptExpect = X86_XCPT_DB; + else if (fAvxInstr) + bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ + } + + Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); + + /* + * Iterate the test values and do the actual testing. + */ + for (iVal = 0; iVal < cValues; iVal++, idTestStep++) + { + uint16_t cErrors; + uint16_t uSavedFtw = 0xff; + RTUINT256U uMemOpExpect; + + /* + * Set up the context and some expectations. + */ + /* source - media */ + BS3_ASSERT(paTests[iTest].iMediaRegSrc != UINT8_MAX); + if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaRegSrc, paValues[iVal].uMediaSrc.QWords.qw0, BS3EXTCTXTOPMM_ZERO); + else if (fSseInstr) + Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaRegSrc, &paValues[iVal].uMediaSrc.DQWords.dqw0); + else + Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaRegSrc, &paValues[iVal].uMediaSrc, 32); + + /* source - gpr/mem */ + if (paTests[iTest].iGprReg == UINT8_MAX) + { + BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); + Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); + if (bXcptExpect == X86_XCPT_DB) + switch (paTests[iTest].cbGpr) + { + case 1: uMemOpExpect.au8[0] = (uint8_t) (paValues[iVal].uGpr & fGprValMask); break; + case 2: uMemOpExpect.au16[0] = (uint16_t)(paValues[iVal].uGpr & fGprValMask); break; + case 4: uMemOpExpect.au32[0] = (uint32_t)(paValues[iVal].uGpr & fGprValMask); break; + case 8: uMemOpExpect.au64[0] = (paValues[iVal].uGpr & fGprValMask); break; + default: BS3_ASSERT(0); + } + Bs3MemCpy(puMemOp, &uMemOpExpect, cbMemOp); + } + else + Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, paValues[iVal].uGpr & fGprValMask, paTests[iTest].cbGpr); + + /* Memory pointer. */ + if (paTests[iTest].enmRm >= RM_MEM) + { + BS3_ASSERT(paTests[iTest].iGprReg == UINT8_MAX || paTests[iTest].iMediaRegSrc == UINT8_MAX); + Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); + } + + /* + * Execute. + */ + Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); + + /* + * Check the result: + */ + cErrors = Bs3TestSubErrorCount(); + + if (fMmxInstr && bXcptExpect == X86_XCPT_DB) + { + uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); + Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); + } + + if (bXcptExpect == X86_XCPT_DB) + { + if (fMmxInstr) + Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaRegDst, paValues[iVal].uMediaDst.QWords.qw0, BS3EXTCTXTOPMM_SET); + else if (fSseInstr) + Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaRegDst, &paValues[iVal].uMediaDst.DQWords.dqw0); + else + Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaRegDst, &paValues[iVal].uMediaDst, 32); + } + + Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); + + if (TrapFrame.bXcpt != bXcptExpect) + Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); + + /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ + if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) + { + if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) + Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); + TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; + } + Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, + bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, + pszMode, idTestStep); + + if ( paTests[iTest].enmRm >= RM_MEM + && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0) + Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp); + + if (cErrors != Bs3TestSubErrorCount()) + { + if (paConfigs[iCfg].fAligned) + Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)", + bRing, iCfg, iTest, iVal, bXcptExpect); + else + Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", + bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); + Bs3TestPrintf("\n"); + } + + if (uSavedFtw != 0xff) + Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); + } + } + + bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); + } + + /* + * Next ring. + */ + bRing++; + if (bRing > 3 || bMode == BS3_MODE_RM) + break; + Bs3RegCtxConvertToRingX(&Ctx, bRing); + } + + /* + * Cleanup. + */ + bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); + bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); + return 0; +} + + +/* + * [V]PINSRW. + */ +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_pinsrw_MM1_R9D_000h_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp); +extern FNBS3FAR bs3CpuInstr3_pinsrw_MM1_R9D_0FFh_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_pinsrw_XMM8_R9D_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pinsrw_XMM8_FSxBX_000h_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp); +extern FNBS3FAR bs3CpuInstr3_pinsrw_XMM8_R9D_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_pinsrw_XMM8_FSxBX_0FFh_icebp_c64; + +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp); +extern FNBS3FAR bs3CpuInstr3_vpinsrw_XMM8_XMM9_R9D_000h_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpinsrw_XMM8_XMM9_FSxBX_000h_icebp_c64; +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp); +BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp); +extern FNBS3FAR bs3CpuInstr3_vpinsrw_XMM8_XMM9_R9D_0FFh_icebp_c64; +extern FNBS3FAR bs3CpuInstr3_vpinsrw_XMM8_XMM9_FSxBX_0FFh_icebp_c64; + +BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pinsrw(uint8_t bMode) +{ + static BS3CPUINSTR3_TEST6_VALUES_T const s_aValues00[] = + { + /* Media source GPR word Media dest. */ + { RTUINT256_INIT_C(0, 0, 0, 0), UINT64_C(0x1234), RTUINT256_INIT_C(0, 0, 0, 0x0000000000001234) }, + }; + static BS3CPUINSTR3_TEST6_VALUES_T const s_aValuesFF_64[] = + { + /* Media source GPR word Media dest. */ + { RTUINT256_INIT_C(0, 0, 0, 0), UINT64_C(0x1234), RTUINT256_INIT_C(0, 0, 0, 0x1234000000000000) }, + }; + static BS3CPUINSTR3_TEST6_VALUES_T const s_aValuesFF[] = + { + /* Media source GPR word Media dest. */ + { RTUINT256_INIT_C(0, 0, 0, 0), UINT64_C(0x1234), RTUINT256_INIT_C(0, 0, 0x1234000000000000, 0) }, + }; + + static BS3CPUINSTR3_TEST6_T const s_aTests16[] = + { + { bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp_c16, 255, RM_REG, T_MMX_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp_c16, 255, RM_MEM32, T_MMX_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_MMX_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, + { bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM32, T_MMX_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, + + { bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp_c16, 255, RM_REG, T_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM32, T_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM32, T_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + }; + static BS3CPUINSTR3_TEST6_T const s_aTests32[] = + { + { bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp_c32, 255, RM_REG, T_MMX_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp_c32, 255, RM_MEM32, T_MMX_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_MMX_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, + { bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM32, T_MMX_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, + + { bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp_c32, 255, RM_REG, T_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM32, T_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM32, T_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + }; + static BS3CPUINSTR3_TEST6_T const s_aTests64[] = + { + { bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pinsrw_MM1_R9D_000h_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, 9, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_MMX_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, + { bs3CpuInstr3_pinsrw_MM1_R9D_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, 9, 1, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, + { bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_MMX_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, + + { bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp_c64, 255, RM_REG, T_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_pinsrw_XMM8_R9D_000h_icebp_c64, 255, RM_REG, T_SSE, 4, 32, 9, 8, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pinsrw_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE, 4, 32, 255, 8, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_pinsrw_XMM8_R9D_0FFh_icebp_c64, 255, RM_REG, T_SSE, 4, 32, 9, 8, 8, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_pinsrw_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE, 4, 32, 255, 8, 8, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + + { bs3CpuInstr3_vpinsrw_XMM8_XMM9_R9D_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 9, 9, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpinsrw_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 9, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, + { bs3CpuInstr3_vpinsrw_XMM8_XMM9_R9D_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 9, 9, 8, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + { bs3CpuInstr3_vpinsrw_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 9, 8, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, + }; + static BS3CPUINSTR3_TEST6_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST6_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); + unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); + return bs3CpuInstr3_WorkerTestType6(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, + g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); +} + + + + +/** + * The 32-bit protected mode main function. + * + * The tests a driven by 32-bit test drivers, even for real-mode tests (though + * we'll switch between PE32 and RM for each test step we perform). Given that + * we test MMX, SSE and AVX here, we don't need to worry about 286 or 8086. + * + * Some extra steps needs to be taken to properly handle extended state in LM64 + * (Bs3ExtCtxRestoreEx & Bs3ExtCtxSaveEx) and when testing real mode + * (Bs3RegCtxSaveForMode & Bs3TrapSetJmpAndRestoreWithExtCtxAndRm). + */ +BS3_DECL(void) Main_pe32() +{ + static const BS3TESTMODEBYONEENTRY g_aTests[] = + { +#if 1 /*ndef DEBUG_bird*/ +# define ALL_TESTS +#endif +#if defined(ALL_TESTS) + { "[v]andps/[v]andpd/[v]pand", bs3CpuInstr3_v_andps_andpd_pand, 0 }, + { "[v]andnps/[v]andnpd/[v]pandn", bs3CpuInstr3_v_andnps_andnpd_pandn, 0 }, + { "[v]orps/[v]orpd/[v]or", bs3CpuInstr3_v_orps_orpd_por, 0 }, + { "[v]xorps/[v]xorpd/[v]pxor", bs3CpuInstr3_v_xorps_xorpd_pxor, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]pcmpgtb/[v]pcmpgtw/[v]pcmpgtd/[v]pcmpgtq", bs3CpuInstr3_v_pcmpgtb_pcmpgtw_pcmpgtd_pcmpgtq, 0 }, + { "[v]pcmpeqb/[v]pcmpeqw/[v]pcmpeqd/[v]pcmpeqq", bs3CpuInstr3_v_pcmpeqb_pcmpeqw_pcmpeqd_pcmpeqq, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]paddb/[v]paddw/[v]paddd/[v]paddq", bs3CpuInstr3_v_paddb_paddw_paddd_paddq, 0 }, + { "[v]psubb/[v]psubw/[v]psubd/[v]psubq", bs3CpuInstr3_v_psubb_psubw_psubd_psubq, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]pmullw/[v]pmulld", bs3CpuInstr3_v_pmullw_pmulld, 0 }, + { "[v]pmulhw", bs3CpuInstr3_v_pmulhw, 0 }, + { "[v]pmulhuw", bs3CpuInstr3_v_pmulhuw, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]pmovmskb", bs3CpuInstr3_v_pmovmskb, 0 }, + { "pshufb", bs3CpuInstr3_pshufb, 0 }, + { "pshufw", bs3CpuInstr3_pshufw, 0 }, + { "[v]pshufhw", bs3CpuInstr3_v_pshufhw, 0 }, + { "[v]pshuflw", bs3CpuInstr3_v_pshuflw, 0 }, + { "[v]pshufd", bs3CpuInstr3_v_pshufd, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]punpckhbw", bs3CpuInstr3_v_punpckhbw, 0 }, + { "[v]punpckhwd", bs3CpuInstr3_v_punpckhwd, 0 }, + { "[v]punpckhdq", bs3CpuInstr3_v_punpckhdq, 0 }, + { "[v]punpckhqdq", bs3CpuInstr3_v_punpckhqdq, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]punpcklbw", bs3CpuInstr3_v_punpcklbw, 0 }, + { "[v]punpcklwd", bs3CpuInstr3_v_punpcklwd, 0 }, + { "[v]punpckldq", bs3CpuInstr3_v_punpckldq, 0 }, + { "[v]punpcklqdq", bs3CpuInstr3_v_punpcklqdq, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]packsswb", bs3CpuInstr3_v_packsswb, 0 }, + { "[v]packssdw", bs3CpuInstr3_v_packssdw, 0 }, + { "[v]packuswb", bs3CpuInstr3_v_packuswb, 0 }, + { "[v]packusdw", bs3CpuInstr3_v_packusdw, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]pmaxub/[v]pmaxuw/[v]pmaxud", bs3CpuInstr3_v_pmaxub_pmaxuw_pmaxud, 0 }, + { "[v]pmaxsb/[v]pmaxsw/[v]pmaxsd", bs3CpuInstr3_v_pmaxsb_pmaxsw_pmaxsd, 0 }, + { "[v]pminub/[v]pminuw/[v]pminud", bs3CpuInstr3_v_pminub_pminuw_pminud, 0 }, + { "[v]pminsb/[v]pminsw/[v]pminsd", bs3CpuInstr3_v_pminsb_pminsw_pminsd, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]movntdqa", bs3CpuInstr3_v_movntdqa, 0 }, + { "[v]movntdq", bs3CpuInstr3_v_movntdq, 0 }, + { "[v]movntps_movntpd", bs3CpuInstr3_v_movntps_movntpd, 0 }, + { "[v]movups", bs3CpuInstr3_v_movups, 0 }, + { "[v]movupd", bs3CpuInstr3_v_movupd, 0 }, + { "[v]movss", bs3CpuInstr3_v_movss, 0 }, + { "[v]movsd", bs3CpuInstr3_v_movsd, 0 }, + { "[v]movhlps", bs3CpuInstr3_v_movhlps, 0 }, + { "[v]movlps/[v]movlpd", bs3CpuInstr3_v_movlps_movlpd, 0 }, + { "[v]movhps/[v]movhpd", bs3CpuInstr3_v_movhps_movhpd, 0 }, + { "[v]movsldup", bs3CpuInstr3_v_movsldup, 0 }, + { "[v]movshdup", bs3CpuInstr3_v_movshdup, 0 }, + { "[v]movddup", bs3CpuInstr3_v_movddup, 0 }, + { "[v]movaps_movapd", bs3CpuInstr3_v_movaps_movapd, 0 }, + { "[v]movd_movq", bs3CpuInstr3_v_movd_movq, 0 }, + { "[v]movdqu", bs3CpuInstr3_v_movdqu, 0 }, + { "[v]movdqa", bs3CpuInstr3_v_movdqa, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]ptest", bs3CpuInstr3_v_ptest, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]pavgb/[v]pavgw", bs3CpuInstr3_v_pavgb_pavgw, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]pabsb/[v]pabsw/[v]pabsd", bs3CpuInstr3_v_pabsb_pabsw_pabsd, 0 }, + { "[v]psignb/[v]psignw/[v]psignd", bs3CpuInstr3_v_psignb_psignw_psignd, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]phaddw/[v]phaddd", bs3CpuInstr3_v_phaddw_phaddd, 0 }, + { "[v]phsubw/[v]phsubd", bs3CpuInstr3_v_phsubw_phsubd, 0 }, + { "[v]phaddsw", bs3CpuInstr3_v_phaddsw, 0 }, + { "[v]phsubsw", bs3CpuInstr3_v_phsubsw, 0 }, + { "[v]pmaddubsw", bs3CpuInstr3_v_pmaddubsw, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]pmulhrsw", bs3CpuInstr3_v_pmulhrsw, 0 }, + { "[v]psadbw", bs3CpuInstr3_v_psadbw, 0 }, + { "[v]pmuldq", bs3CpuInstr3_v_pmuldq, 0 }, + { "[v]pmuludq", bs3CpuInstr3_v_pmuludq, 0 }, + { "[v]punpcklps/[v]punpcklpd", bs3CpuInstr3_v_punpcklps_punpcklpd, 0 }, + { "[v]punpckhps/[v]punpckhpd", bs3CpuInstr3_v_punpckhps_punpckhpd, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]pmovsxbw/[v]pmovsxbd/[v]pmovsxbq/[v]pmovsxwd/[v]pmovsxwq/[v]pmovsxdq", + bs3CpuInstr3_v_pmovsxbw_pmovsxbd_pmovsxbq_pmovsxwd_pmovsxwq_pmovsxdq, 0 }, + { "[v]pmovzxbw/[v]pmovzxbd/[v]pmovzxbq/[v]pmovzxwd/[v]pmovzxwq/[v]pmovzxdq", + bs3CpuInstr3_v_pmovzxbw_pmovzxbd_pmovzxbq_pmovzxwd_pmovzxwq_pmovzxdq, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]shufps", bs3CpuInstr3_v_shufps, 0 }, + { "[v]shufpd", bs3CpuInstr3_v_shufpd, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]lddqu", bs3CpuInstr3_v_lddqu, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]phminposuw", bs3CpuInstr3_v_phminposuw, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]pblendvb", bs3CpuInstr3_v_pblendvb, 0 }, + { "[v]blendvps", bs3CpuInstr3_v_blendvps, 0 }, + { "[v]blendvpd", bs3CpuInstr3_v_blendvpd, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]palignr", bs3CpuInstr3_v_palignr, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]pblendw", bs3CpuInstr3_v_pblendw, 0 }, + { "[v]blendps", bs3CpuInstr3_v_blendps, 0 }, + { "[v]blendpd", bs3CpuInstr3_v_blendpd, 0 }, +#endif +#if defined(ALL_TESTS) + { "[v]pclmulqdq", bs3CpuInstr3_v_pclmulqdq, 0 }, + { "[v]pinsrw", bs3CpuInstr3_v_pinsrw, 0 }, + { "[v]pextrw", bs3CpuInstr3_v_pextrw, 0 }, + { "[v]movmskps/[v]movmskpd", bs3CpuInstr3_v_movmskps_movmskpd, 0 }, + +#endif + }; + Bs3TestInit("bs3-cpu-instr-3"); + + /* + * Initialize globals. + */ + if (g_uBs3CpuDetected & BS3CPU_F_CPUID) + { + uint32_t fEbx, fEcx, fEdx; + ASMCpuIdExSlow(1, 0, 0, 0, NULL, NULL, &fEcx, &fEdx); + g_afTypeSupports[T_MMX] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_MMX); + g_afTypeSupports[T_MMX_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE); + g_afTypeSupports[T_MMX_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2); + g_afTypeSupports[T_MMX_SSSE3] = RT_BOOL(fEdx & X86_CPUID_FEATURE_ECX_SSSE3); + g_afTypeSupports[T_SSE] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE); + g_afTypeSupports[T_SSE2] = RT_BOOL(fEdx & X86_CPUID_FEATURE_EDX_SSE2); + g_afTypeSupports[T_SSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE3); + g_afTypeSupports[T_SSSE3] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSSE3); + g_afTypeSupports[T_SSE4_1] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_1); + g_afTypeSupports[T_SSE4_2] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_SSE4_2); + g_afTypeSupports[T_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL); + g_afTypeSupports[T_AVX_128] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX); + g_afTypeSupports[T_AVX_256] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX); + g_afTypeSupports[T_AVX_PCLMUL] = RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_PCLMUL) + && RT_BOOL(fEcx & X86_CPUID_FEATURE_ECX_AVX); + + if (ASMCpuId_EAX(0) >= 7) + { + ASMCpuIdExSlow(7, 0, 0, 0, NULL, &fEbx, NULL, NULL); + g_afTypeSupports[T_AVX2_128] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2); + g_afTypeSupports[T_AVX2_256] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2); + } + + if (g_uBs3CpuDetected & BS3CPU_F_CPUID_EXT_LEAVES) + { + ASMCpuIdExSlow(UINT32_C(0x80000001), 0, 0, 0, NULL, NULL, &fEcx, &fEdx); + g_afTypeSupports[T_AXMMX] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_EDX_AXMMX); + g_afTypeSupports[T_SSE4A] = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_SSE4A); + g_fAmdMisalignedSse = RT_BOOL(fEcx & X86_CPUID_AMD_FEATURE_ECX_MISALNSSE); + } + g_afTypeSupports[T_AXMMX_OR_SSE] = g_afTypeSupports[T_AXMMX] || g_afTypeSupports[T_SSE]; + } + + /* + * Allocate a buffer for testing. + */ + g_cbBuf = X86_PAGE_SIZE * 4; + g_pbBuf = (uint8_t BS3_FAR *)Bs3MemAlloc(BS3MEMKIND_REAL, g_cbBuf); + if (g_pbBuf) + { + /* + * Do the tests. + */ + Bs3TestDoModesByOne_pe32(g_aTests, RT_ELEMENTS(g_aTests), BS3TESTMODEBYONEENTRY_F_REAL_MODE_READY); + } + else + Bs3TestFailed("Failed to allocate 16K buffer"); + + Bs3TestTerm(); +} + |