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Diffstat (limited to 'src/VBox/ValidationKit/bootsectors/bs3-cpu-weird-1-template.mac')
| -rw-r--r-- | src/VBox/ValidationKit/bootsectors/bs3-cpu-weird-1-template.mac | 167 |
1 files changed, 167 insertions, 0 deletions
diff --git a/src/VBox/ValidationKit/bootsectors/bs3-cpu-weird-1-template.mac b/src/VBox/ValidationKit/bootsectors/bs3-cpu-weird-1-template.mac new file mode 100644 index 00000000..9247db83 --- /dev/null +++ b/src/VBox/ValidationKit/bootsectors/bs3-cpu-weird-1-template.mac @@ -0,0 +1,167 @@ +; $Id: bs3-cpu-weird-1-template.mac $ +;; @file +; BS3Kit - bs3-cpu-weird-1 assembly template. +; + +; +; Copyright (C) 2007-2023 Oracle and/or its affiliates. +; +; This file is part of VirtualBox base platform packages, as +; available from https://www.virtualbox.org. +; +; This program is free software; you can redistribute it and/or +; modify it under the terms of the GNU General Public License +; as published by the Free Software Foundation, in version 3 of the +; License. +; +; This program is distributed in the hope that it will be useful, but +; WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +; General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program; if not, see <https://www.gnu.org/licenses>. +; +; The contents of this file may alternatively be used under the terms +; of the Common Development and Distribution License Version 1.0 +; (CDDL), a copy of it is provided in the "COPYING.CDDL" file included +; in the VirtualBox distribution, in which case the provisions of the +; CDDL are applicable instead of those of the GPL. +; +; You may elect to license modified versions of this file under the +; terms and conditions of either the GPL or the CDDL or both. +; +; SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0 +; + + +;********************************************************************************************************************************* +;* Header Files * +;********************************************************************************************************************************* +%include "bs3kit-template-header.mac" ; setup environment + + +;********************************************************************************************************************************* +;* External Symbols * +;********************************************************************************************************************************* +TMPL_BEGIN_TEXT + + +; +; Test code snippets containing code which differs between 16-bit, 32-bit +; and 64-bit CPUs modes. +; +%ifdef BS3_INSTANTIATING_CMN + + +; +; Inhibited int 80h. +; +BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedInt80, BS3_PBC_NEAR + ; Load SS from stack. This instruction causes fusing. +%if TMPL_BITS != 64 + pop ss +%else + mov ss, [rsp] +%endif + ; The ring transition instruction. +BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedInt80_int80), , 0 + int 80h + ; We shouldn't get here! +.ud2_again: + ud2 + jmp .ud2_again +BS3_PROC_END_CMN bs3CpuWeird1_InhibitedInt80 + +; +; Inhibited int 3. +; +BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedInt3, BS3_PBC_NEAR + ; Load SS from stack. This instruction causes fusing. +%if TMPL_BITS != 64 + pop ss +%else + mov ss, [rsp] +%endif + ; The ring transition instruction. +BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedInt3_int3), , 0 + int 3 + ; We shouldn't get here! +.ud2_again: + ud2 + jmp .ud2_again +AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_InhibitedInt3_int3) == 2) +BS3_PROC_END_CMN bs3CpuWeird1_InhibitedInt3 + + +; +; Inhibited int3. +; +BS3_PROC_BEGIN_CMN bs3CpuWeird1_InhibitedBp, BS3_PBC_NEAR + ; Load SS from stack. This instruction causes fusing. +%if TMPL_BITS != 64 + pop ss +%else + mov ss, [rsp] +%endif + ; The ring transition instruction. +BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuWeird1_InhibitedBp_int3), , 0 + int3 + ; We shouldn't get here! +.ud2_again: + ud2 + jmp .ud2_again +AssertCompile(.ud2_again - BS3_CMN_NM(bs3CpuWeird1_InhibitedBp_int3) == 1) +BS3_PROC_END_CMN bs3CpuWeird1_InhibitedBp + + +; +; PC (IP/EIP) wrapper templates. +; These will potentially trigger VM exits, except for the benign one. +; +; Note! Single instructions as the testcase will shift multibyte variations +; across the wrap-around boundary and that would cause unpredictable +; results for the 16-bit if there is more than one instruction. +; + +BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapBenign1, BS3_PBC_NEAR + nop +BS3_PROC_END_CMN bs3CpuWeird1_PcWrapBenign1 + +BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapBenign2, BS3_PBC_NEAR + xor xDX, xAX +BS3_PROC_END_CMN bs3CpuWeird1_PcWrapBenign2 + +BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapCpuId, BS3_PBC_NEAR + cpuid +BS3_PROC_END_CMN bs3CpuWeird1_PcWrapCpuId + +BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapIn80, BS3_PBC_NEAR + in al, 80h +BS3_PROC_END_CMN bs3CpuWeird1_PcWrapIn80 + +BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapOut80, BS3_PBC_NEAR + out 80h, al +BS3_PROC_END_CMN bs3CpuWeird1_PcWrapOut80 + +BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapSmsw, BS3_PBC_NEAR + smsw si +BS3_PROC_END_CMN bs3CpuWeird1_PcWrapSmsw + +BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapRdCr0, BS3_PBC_NEAR + mov sAX, cr0 +BS3_PROC_END_CMN bs3CpuWeird1_PcWrapRdCr0 + +BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapRdDr0, BS3_PBC_NEAR + mov sAX, dr0 +BS3_PROC_END_CMN bs3CpuWeird1_PcWrapRdDr0 + +BS3_PROC_BEGIN_CMN bs3CpuWeird1_PcWrapWrDr0, BS3_PBC_NEAR + mov dr0, sAX +BS3_PROC_END_CMN bs3CpuWeird1_PcWrapWrDr0 + + +%endif ; BS3_INSTANTIATING_CMN + +%include "bs3kit-template-footer.mac" ; reset environment + |