diff options
Diffstat (limited to 'js/src/jit/arm/disasm')
| -rw-r--r-- | js/src/jit/arm/disasm/Constants-arm.cpp | 117 | ||||
| -rw-r--r-- | js/src/jit/arm/disasm/Constants-arm.h | 684 | ||||
| -rw-r--r-- | js/src/jit/arm/disasm/Disasm-arm.cpp | 2031 | ||||
| -rw-r--r-- | js/src/jit/arm/disasm/Disasm-arm.h | 141 |
4 files changed, 2973 insertions, 0 deletions
diff --git a/js/src/jit/arm/disasm/Constants-arm.cpp b/js/src/jit/arm/disasm/Constants-arm.cpp new file mode 100644 index 0000000000..408e2df686 --- /dev/null +++ b/js/src/jit/arm/disasm/Constants-arm.cpp @@ -0,0 +1,117 @@ +/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 2 -*- + * vim: set ts=8 sts=2 et sw=2 tw=80: + */ +// Copyright 2009 the V8 project authors. All rights reserved. +// Use of this source code is governed by a BSD-style license that can be +// found in the LICENSE file. + +#include "jit/arm/disasm/Constants-arm.h" + +#ifdef JS_DISASM_ARM + +namespace js { +namespace jit { +namespace disasm { + +double Instruction::DoubleImmedVmov() const { + // Reconstruct a double from the immediate encoded in the vmov instruction. + // + // instruction: [xxxxxxxx,xxxxabcd,xxxxxxxx,xxxxefgh] + // double: [aBbbbbbb,bbcdefgh,00000000,00000000, + // 00000000,00000000,00000000,00000000] + // + // where B = ~b. Only the high 16 bits are affected. + uint64_t high16; + high16 = (Bits(17, 16) << 4) | Bits(3, 0); // xxxxxxxx,xxcdefgh. + high16 |= (0xff * Bit(18)) << 6; // xxbbbbbb,bbxxxxxx. + high16 |= (Bit(18) ^ 1) << 14; // xBxxxxxx,xxxxxxxx. + high16 |= Bit(19) << 15; // axxxxxxx,xxxxxxxx. + + uint64_t imm = high16 << 48; + double d; + memcpy(&d, &imm, 8); + return d; +} + +// These register names are defined in a way to match the native disassembler +// formatting. See for example the command "objdump -d <binary file>". +const char* Registers::names_[kNumRegisters] = { + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "fp", "ip", "sp", "lr", "pc", +}; + +// List of alias names which can be used when referring to ARM registers. +const Registers::RegisterAlias Registers::aliases_[] = { + {10, "sl"}, {11, "r11"}, {12, "r12"}, {13, "r13"}, + {14, "r14"}, {15, "r15"}, {kNoRegister, NULL}}; + +const char* Registers::Name(int reg) { + const char* result; + if ((0 <= reg) && (reg < kNumRegisters)) { + result = names_[reg]; + } else { + result = "noreg"; + } + return result; +} + +// Support for VFP registers s0 to s31 (d0 to d15) and d16-d31. +// Note that "sN:sM" is the same as "dN/2" up to d15. +// These register names are defined in a way to match the native disassembler +// formatting. See for example the command "objdump -d <binary file>". +const char* VFPRegisters::names_[kNumVFPRegisters] = { + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", + "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", + "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", "d0", + "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11", + "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22", + "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31"}; + +const char* VFPRegisters::Name(int reg, bool is_double) { + MOZ_ASSERT((0 <= reg) && (reg < kNumVFPRegisters)); + return names_[reg + (is_double ? kNumVFPSingleRegisters : 0)]; +} + +int VFPRegisters::Number(const char* name, bool* is_double) { + for (int i = 0; i < kNumVFPRegisters; i++) { + if (strcmp(names_[i], name) == 0) { + if (i < kNumVFPSingleRegisters) { + *is_double = false; + return i; + } else { + *is_double = true; + return i - kNumVFPSingleRegisters; + } + } + } + + // No register with the requested name found. + return kNoRegister; +} + +int Registers::Number(const char* name) { + // Look through the canonical names. + for (int i = 0; i < kNumRegisters; i++) { + if (strcmp(names_[i], name) == 0) { + return i; + } + } + + // Look through the alias names. + int i = 0; + while (aliases_[i].reg != kNoRegister) { + if (strcmp(aliases_[i].name, name) == 0) { + return aliases_[i].reg; + } + i++; + } + + // No register with the requested name found. + return kNoRegister; +} + +} // namespace disasm +} // namespace jit +} // namespace js + +#endif // JS_DISASM_ARM diff --git a/js/src/jit/arm/disasm/Constants-arm.h b/js/src/jit/arm/disasm/Constants-arm.h new file mode 100644 index 0000000000..0128062b3f --- /dev/null +++ b/js/src/jit/arm/disasm/Constants-arm.h @@ -0,0 +1,684 @@ +/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 2 -*- + * vim: set ts=8 sts=2 et sw=2 tw=80: + */ +// Copyright 2011 the V8 project authors. All rights reserved. +// Use of this source code is governed by a BSD-style license that can be +// found in the LICENSE file. + +#ifndef jit_arm_disasm_Constants_arm_h +#define jit_arm_disasm_Constants_arm_h + +#ifdef JS_DISASM_ARM + +# include "mozilla/Assertions.h" +# include "mozilla/Types.h" + +# include <string.h> + +namespace js { +namespace jit { +namespace disasm { + +// Constant pool marker. +// Use UDF, the permanently undefined instruction. +const int kConstantPoolMarkerMask = 0xfff000f0; +const int kConstantPoolMarker = 0xe7f000f0; +const int kConstantPoolLengthMaxMask = 0xffff; + +inline int EncodeConstantPoolLength(int length) { + MOZ_ASSERT((length & kConstantPoolLengthMaxMask) == length); + return ((length & 0xfff0) << 4) | (length & 0xf); +} + +inline int DecodeConstantPoolLength(int instr) { + MOZ_ASSERT((instr & kConstantPoolMarkerMask) == kConstantPoolMarker); + return ((instr >> 4) & 0xfff0) | (instr & 0xf); +} + +// Used in code age prologue - ldr(pc, MemOperand(pc, -4)) +const int kCodeAgeJumpInstruction = 0xe51ff004; + +// Number of registers in normal ARM mode. +const int kNumRegisters = 16; + +// VFP support. +const int kNumVFPSingleRegisters = 32; +const int kNumVFPDoubleRegisters = 32; +const int kNumVFPRegisters = kNumVFPSingleRegisters + kNumVFPDoubleRegisters; + +// PC is register 15. +const int kPCRegister = 15; +const int kNoRegister = -1; + +// ----------------------------------------------------------------------------- +// Conditions. + +// Defines constants and accessor classes to assemble, disassemble and +// simulate ARM instructions. +// +// Section references in the code refer to the "ARM Architecture Reference +// Manual" from July 2005 (available at http://www.arm.com/miscPDFs/14128.pdf) +// +// Constants for specific fields are defined in their respective named enums. +// General constants are in an anonymous enum in class Instr. + +// Values for the condition field as defined in section A3.2 +enum Condition { + kNoCondition = -1, + + eq = 0 << 28, // Z set Equal. + ne = 1 << 28, // Z clear Not equal. + cs = 2 << 28, // C set Unsigned higher or same. + cc = 3 << 28, // C clear Unsigned lower. + mi = 4 << 28, // N set Negative. + pl = 5 << 28, // N clear Positive or zero. + vs = 6 << 28, // V set Overflow. + vc = 7 << 28, // V clear No overflow. + hi = 8 << 28, // C set, Z clear Unsigned higher. + ls = 9 << 28, // C clear or Z set Unsigned lower or same. + ge = 10 << 28, // N == V Greater or equal. + lt = 11 << 28, // N != V Less than. + gt = 12 << 28, // Z clear, N == V Greater than. + le = 13 << 28, // Z set or N != V Less then or equal + al = 14 << 28, // Always. + + kSpecialCondition = 15 << 28, // Special condition (refer to section A3.2.1). + kNumberOfConditions = 16, + + // Aliases. + hs = cs, // C set Unsigned higher or same. + lo = cc // C clear Unsigned lower. +}; + +inline Condition NegateCondition(Condition cond) { + MOZ_ASSERT(cond != al); + return static_cast<Condition>(cond ^ ne); +} + +// Commute a condition such that {a cond b == b cond' a}. +inline Condition CommuteCondition(Condition cond) { + switch (cond) { + case lo: + return hi; + case hi: + return lo; + case hs: + return ls; + case ls: + return hs; + case lt: + return gt; + case gt: + return lt; + case ge: + return le; + case le: + return ge; + default: + return cond; + } +} + +// ----------------------------------------------------------------------------- +// Instructions encoding. + +// Instr is merely used by the Assembler to distinguish 32bit integers +// representing instructions from usual 32 bit values. +// Instruction objects are pointers to 32bit values, and provide methods to +// access the various ISA fields. +typedef int32_t Instr; + +// Opcodes for Data-processing instructions (instructions with a type 0 and 1) +// as defined in section A3.4 +enum Opcode { + AND = 0 << 21, // Logical AND. + EOR = 1 << 21, // Logical Exclusive OR. + SUB = 2 << 21, // Subtract. + RSB = 3 << 21, // Reverse Subtract. + ADD = 4 << 21, // Add. + ADC = 5 << 21, // Add with Carry. + SBC = 6 << 21, // Subtract with Carry. + RSC = 7 << 21, // Reverse Subtract with Carry. + TST = 8 << 21, // Test. + TEQ = 9 << 21, // Test Equivalence. + CMP = 10 << 21, // Compare. + CMN = 11 << 21, // Compare Negated. + ORR = 12 << 21, // Logical (inclusive) OR. + MOV = 13 << 21, // Move. + BIC = 14 << 21, // Bit Clear. + MVN = 15 << 21 // Move Not. +}; + +// The bits for bit 7-4 for some type 0 miscellaneous instructions. +enum MiscInstructionsBits74 { + // With bits 22-21 01. + BX = 1 << 4, + BXJ = 2 << 4, + BLX = 3 << 4, + BKPT = 7 << 4, + + // With bits 22-21 11. + CLZ = 1 << 4 +}; + +// Load and store exclusive instructions. + +// Bit positions. +enum { + ExclusiveOpHi = 24, // Hi bit of opcode field + ExclusiveOpLo = 23, // Lo bit of opcode field + ExclusiveSizeHi = 22, // Hi bit of operand size field + ExclusiveSizeLo = 21, // Lo bit of operand size field + ExclusiveLoad = 20 // Bit indicating load +}; + +// Opcode bits for exclusive instructions. +enum { ExclusiveOpcode = 3 }; + +// Operand size, Bits(ExclusiveSizeHi,ExclusiveSizeLo). +enum { + ExclusiveWord = 0, + ExclusiveDouble = 1, + ExclusiveByte = 2, + ExclusiveHalf = 3 +}; + +// Instruction encoding bits and masks. +enum { + H = 1 << 5, // Halfword (or byte). + S6 = 1 << 6, // Signed (or unsigned). + L = 1 << 20, // Load (or store). + S = 1 << 20, // Set condition code (or leave unchanged). + W = 1 << 21, // Writeback base register (or leave unchanged). + A = 1 << 21, // Accumulate in multiply instruction (or not). + B = 1 << 22, // Unsigned byte (or word). + N = 1 << 22, // Long (or short). + U = 1 << 23, // Positive (or negative) offset/index. + P = 1 << 24, // Offset/pre-indexed addressing (or post-indexed addressing). + I = 1 << 25, // Immediate shifter operand (or not). + B0 = 1 << 0, + B4 = 1 << 4, + B5 = 1 << 5, + B6 = 1 << 6, + B7 = 1 << 7, + B8 = 1 << 8, + B9 = 1 << 9, + B12 = 1 << 12, + B16 = 1 << 16, + B17 = 1 << 17, + B18 = 1 << 18, + B19 = 1 << 19, + B20 = 1 << 20, + B21 = 1 << 21, + B22 = 1 << 22, + B23 = 1 << 23, + B24 = 1 << 24, + B25 = 1 << 25, + B26 = 1 << 26, + B27 = 1 << 27, + B28 = 1 << 28, + + // Instruction bit masks. + kCondMask = 15 << 28, + kALUMask = 0x6f << 21, + kRdMask = 15 << 12, // In str instruction. + kCoprocessorMask = 15 << 8, + kOpCodeMask = 15 << 21, // In data-processing instructions. + kImm24Mask = (1 << 24) - 1, + kImm16Mask = (1 << 16) - 1, + kImm8Mask = (1 << 8) - 1, + kOff12Mask = (1 << 12) - 1, + kOff8Mask = (1 << 8) - 1 +}; + +// ----------------------------------------------------------------------------- +// Addressing modes and instruction variants. + +// Condition code updating mode. +enum SBit { + SetCC = 1 << 20, // Set condition code. + LeaveCC = 0 << 20 // Leave condition code unchanged. +}; + +// Status register selection. +enum SRegister { CPSR = 0 << 22, SPSR = 1 << 22 }; + +// Shifter types for Data-processing operands as defined in section A5.1.2. +enum ShiftOp { + LSL = 0 << 5, // Logical shift left. + LSR = 1 << 5, // Logical shift right. + ASR = 2 << 5, // Arithmetic shift right. + ROR = 3 << 5, // Rotate right. + + // RRX is encoded as ROR with shift_imm == 0. + // Use a special code to make the distinction. The RRX ShiftOp is only used + // as an argument, and will never actually be encoded. The Assembler will + // detect it and emit the correct ROR shift operand with shift_imm == 0. + RRX = -1, + kNumberOfShifts = 4 +}; + +// Status register fields. +enum SRegisterField { + CPSR_c = CPSR | 1 << 16, + CPSR_x = CPSR | 1 << 17, + CPSR_s = CPSR | 1 << 18, + CPSR_f = CPSR | 1 << 19, + SPSR_c = SPSR | 1 << 16, + SPSR_x = SPSR | 1 << 17, + SPSR_s = SPSR | 1 << 18, + SPSR_f = SPSR | 1 << 19 +}; + +// Status register field mask (or'ed SRegisterField enum values). +typedef uint32_t SRegisterFieldMask; + +// Memory operand addressing mode. +enum AddrMode { + // Bit encoding P U W. + Offset = (8 | 4 | 0) << 21, // Offset (without writeback to base). + PreIndex = (8 | 4 | 1) << 21, // Pre-indexed addressing with writeback. + PostIndex = (0 | 4 | 0) << 21, // Post-indexed addressing with writeback. + NegOffset = + (8 | 0 | 0) << 21, // Negative offset (without writeback to base). + NegPreIndex = (8 | 0 | 1) << 21, // Negative pre-indexed with writeback. + NegPostIndex = (0 | 0 | 0) << 21 // Negative post-indexed with writeback. +}; + +// Load/store multiple addressing mode. +enum BlockAddrMode { + // Bit encoding P U W . + da = (0 | 0 | 0) << 21, // Decrement after. + ia = (0 | 4 | 0) << 21, // Increment after. + db = (8 | 0 | 0) << 21, // Decrement before. + ib = (8 | 4 | 0) << 21, // Increment before. + da_w = (0 | 0 | 1) << 21, // Decrement after with writeback to base. + ia_w = (0 | 4 | 1) << 21, // Increment after with writeback to base. + db_w = (8 | 0 | 1) << 21, // Decrement before with writeback to base. + ib_w = (8 | 4 | 1) << 21, // Increment before with writeback to base. + + // Alias modes for comparison when writeback does not matter. + da_x = (0 | 0 | 0) << 21, // Decrement after. + ia_x = (0 | 4 | 0) << 21, // Increment after. + db_x = (8 | 0 | 0) << 21, // Decrement before. + ib_x = (8 | 4 | 0) << 21, // Increment before. + + kBlockAddrModeMask = (8 | 4 | 1) << 21 +}; + +// Coprocessor load/store operand size. +enum LFlag { + Long = 1 << 22, // Long load/store coprocessor. + Short = 0 << 22 // Short load/store coprocessor. +}; + +// NEON data type +enum NeonDataType { + NeonS8 = 0x1, // U = 0, imm3 = 0b001 + NeonS16 = 0x2, // U = 0, imm3 = 0b010 + NeonS32 = 0x4, // U = 0, imm3 = 0b100 + NeonU8 = 1 << 24 | 0x1, // U = 1, imm3 = 0b001 + NeonU16 = 1 << 24 | 0x2, // U = 1, imm3 = 0b010 + NeonU32 = 1 << 24 | 0x4, // U = 1, imm3 = 0b100 + NeonDataTypeSizeMask = 0x7, + NeonDataTypeUMask = 1 << 24 +}; + +enum NeonListType { nlt_1 = 0x7, nlt_2 = 0xA, nlt_3 = 0x6, nlt_4 = 0x2 }; + +enum NeonSize { Neon8 = 0x0, Neon16 = 0x1, Neon32 = 0x2, Neon64 = 0x3 }; + +// ----------------------------------------------------------------------------- +// Supervisor Call (svc) specific support. + +// Special Software Interrupt codes when used in the presence of the ARM +// simulator. +// svc (formerly swi) provides a 24bit immediate value. Use bits 22:0 for +// standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature. +enum SoftwareInterruptCodes { + // transition to C code + kCallRtRedirected = 0x10, + // break point + kBreakpoint = 0x20, + // stop + kStopCode = 1 << 23 +}; +const uint32_t kStopCodeMask = kStopCode - 1; +const uint32_t kMaxStopCode = kStopCode - 1; +const int32_t kDefaultStopCode = -1; + +// Type of VFP register. Determines register encoding. +enum VFPRegPrecision { kSinglePrecision = 0, kDoublePrecision = 1 }; + +// VFP FPSCR constants. +enum VFPConversionMode { kFPSCRRounding = 0, kDefaultRoundToZero = 1 }; + +// This mask does not include the "inexact" or "input denormal" cumulative +// exceptions flags, because we usually don't want to check for it. +const uint32_t kVFPExceptionMask = 0xf; +const uint32_t kVFPInvalidOpExceptionBit = 1 << 0; +const uint32_t kVFPOverflowExceptionBit = 1 << 2; +const uint32_t kVFPUnderflowExceptionBit = 1 << 3; +const uint32_t kVFPInexactExceptionBit = 1 << 4; +const uint32_t kVFPFlushToZeroMask = 1 << 24; +const uint32_t kVFPDefaultNaNModeControlBit = 1 << 25; + +const uint32_t kVFPNConditionFlagBit = 1 << 31; +const uint32_t kVFPZConditionFlagBit = 1 << 30; +const uint32_t kVFPCConditionFlagBit = 1 << 29; +const uint32_t kVFPVConditionFlagBit = 1 << 28; + +// VFP rounding modes. See ARM DDI 0406B Page A2-29. +enum VFPRoundingMode { + RN = 0 << 22, // Round to Nearest. + RP = 1 << 22, // Round towards Plus Infinity. + RM = 2 << 22, // Round towards Minus Infinity. + RZ = 3 << 22, // Round towards zero. + + // Aliases. + kRoundToNearest = RN, + kRoundToPlusInf = RP, + kRoundToMinusInf = RM, + kRoundToZero = RZ +}; + +const uint32_t kVFPRoundingModeMask = 3 << 22; + +enum CheckForInexactConversion { + kCheckForInexactConversion, + kDontCheckForInexactConversion +}; + +// ----------------------------------------------------------------------------- +// Hints. + +// Branch hints are not used on the ARM. They are defined so that they can +// appear in shared function signatures, but will be ignored in ARM +// implementations. +enum Hint { no_hint }; + +// Hints are not used on the arm. Negating is trivial. +inline Hint NegateHint(Hint ignored) { return no_hint; } + +// ----------------------------------------------------------------------------- +// Instruction abstraction. + +// The class Instruction enables access to individual fields defined in the ARM +// architecture instruction set encoding as described in figure A3-1. +// Note that the Assembler uses typedef int32_t Instr. +// +// Example: Test whether the instruction at ptr does set the condition code +// bits. +// +// bool InstructionSetsConditionCodes(byte* ptr) { +// Instruction* instr = Instruction::At(ptr); +// int type = instr->TypeValue(); +// return ((type == 0) || (type == 1)) && instr->HasS(); +// } +// +class Instruction { + public: + enum { kInstrSize = 4, kInstrSizeLog2 = 2, kPCReadOffset = 8 }; + + // Helper macro to define static accessors. + // We use the cast to char* trick to bypass the strict anti-aliasing rules. +# define DECLARE_STATIC_TYPED_ACCESSOR(return_type, Name) \ + static inline return_type Name(Instr instr) { \ + char* temp = reinterpret_cast<char*>(&instr); \ + return reinterpret_cast<Instruction*>(temp)->Name(); \ + } + +# define DECLARE_STATIC_ACCESSOR(Name) DECLARE_STATIC_TYPED_ACCESSOR(int, Name) + + // Get the raw instruction bits. + inline Instr InstructionBits() const { + return *reinterpret_cast<const Instr*>(this); + } + + // Set the raw instruction bits to value. + inline void SetInstructionBits(Instr value) { + *reinterpret_cast<Instr*>(this) = value; + } + + // Read one particular bit out of the instruction bits. + inline int Bit(int nr) const { return (InstructionBits() >> nr) & 1; } + + // Read a bit field's value out of the instruction bits. + inline int Bits(int hi, int lo) const { + return (InstructionBits() >> lo) & ((2 << (hi - lo)) - 1); + } + + // Read a bit field out of the instruction bits. + inline int BitField(int hi, int lo) const { + return InstructionBits() & (((2 << (hi - lo)) - 1) << lo); + } + + // Static support. + + // Read one particular bit out of the instruction bits. + static inline int Bit(Instr instr, int nr) { return (instr >> nr) & 1; } + + // Read the value of a bit field out of the instruction bits. + static inline int Bits(Instr instr, int hi, int lo) { + return (instr >> lo) & ((2 << (hi - lo)) - 1); + } + + // Read a bit field out of the instruction bits. + static inline int BitField(Instr instr, int hi, int lo) { + return instr & (((2 << (hi - lo)) - 1) << lo); + } + + // Accessors for the different named fields used in the ARM encoding. + // The naming of these accessor corresponds to figure A3-1. + // + // Two kind of accessors are declared: + // - <Name>Field() will return the raw field, i.e. the field's bits at their + // original place in the instruction encoding. + // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as + // 0xC0810002 ConditionField(instr) will return 0xC0000000. + // - <Name>Value() will return the field value, shifted back to bit 0. + // e.g. if instr is the 'addgt r0, r1, r2' instruction, encoded as + // 0xC0810002 ConditionField(instr) will return 0xC. + + // Generally applicable fields + inline Condition ConditionValue() const { + return static_cast<Condition>(Bits(31, 28)); + } + inline Condition ConditionField() const { + return static_cast<Condition>(BitField(31, 28)); + } + DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionValue); + DECLARE_STATIC_TYPED_ACCESSOR(Condition, ConditionField); + + inline int TypeValue() const { return Bits(27, 25); } + inline int SpecialValue() const { return Bits(27, 23); } + + inline int RnValue() const { return Bits(19, 16); } + DECLARE_STATIC_ACCESSOR(RnValue); + inline int RdValue() const { return Bits(15, 12); } + DECLARE_STATIC_ACCESSOR(RdValue); + + inline int CoprocessorValue() const { return Bits(11, 8); } + // Support for VFP. + // Vn(19-16) | Vd(15-12) | Vm(3-0) + inline int VnValue() const { return Bits(19, 16); } + inline int VmValue() const { return Bits(3, 0); } + inline int VdValue() const { return Bits(15, 12); } + inline int NValue() const { return Bit(7); } + inline int MValue() const { return Bit(5); } + inline int DValue() const { return Bit(22); } + inline int RtValue() const { return Bits(15, 12); } + inline int PValue() const { return Bit(24); } + inline int UValue() const { return Bit(23); } + inline int Opc1Value() const { return (Bit(23) << 2) | Bits(21, 20); } + inline int Opc2Value() const { return Bits(19, 16); } + inline int Opc3Value() const { return Bits(7, 6); } + inline int SzValue() const { return Bit(8); } + inline int VLValue() const { return Bit(20); } + inline int VCValue() const { return Bit(8); } + inline int VAValue() const { return Bits(23, 21); } + inline int VBValue() const { return Bits(6, 5); } + inline int VFPNRegValue(VFPRegPrecision pre) { + return VFPGlueRegValue(pre, 16, 7); + } + inline int VFPMRegValue(VFPRegPrecision pre) { + return VFPGlueRegValue(pre, 0, 5); + } + inline int VFPDRegValue(VFPRegPrecision pre) { + return VFPGlueRegValue(pre, 12, 22); + } + + // Fields used in Data processing instructions + inline int OpcodeValue() const { return static_cast<Opcode>(Bits(24, 21)); } + inline Opcode OpcodeField() const { + return static_cast<Opcode>(BitField(24, 21)); + } + inline int SValue() const { return Bit(20); } + // with register + inline int RmValue() const { return Bits(3, 0); } + DECLARE_STATIC_ACCESSOR(RmValue); + inline int ShiftValue() const { return static_cast<ShiftOp>(Bits(6, 5)); } + inline ShiftOp ShiftField() const { + return static_cast<ShiftOp>(BitField(6, 5)); + } + inline int RegShiftValue() const { return Bit(4); } + inline int RsValue() const { return Bits(11, 8); } + inline int ShiftAmountValue() const { return Bits(11, 7); } + // with immediate + inline int RotateValue() const { return Bits(11, 8); } + DECLARE_STATIC_ACCESSOR(RotateValue); + inline int Immed8Value() const { return Bits(7, 0); } + DECLARE_STATIC_ACCESSOR(Immed8Value); + inline int Immed4Value() const { return Bits(19, 16); } + inline int ImmedMovwMovtValue() const { + return Immed4Value() << 12 | Offset12Value(); + } + DECLARE_STATIC_ACCESSOR(ImmedMovwMovtValue); + + // Fields used in Load/Store instructions + inline int PUValue() const { return Bits(24, 23); } + inline int PUField() const { return BitField(24, 23); } + inline int BValue() const { return Bit(22); } + inline int WValue() const { return Bit(21); } + inline int LValue() const { return Bit(20); } + // with register uses same fields as Data processing instructions above + // with immediate + inline int Offset12Value() const { return Bits(11, 0); } + // multiple + inline int RlistValue() const { return Bits(15, 0); } + // extra loads and stores + inline int SignValue() const { return Bit(6); } + inline int HValue() const { return Bit(5); } + inline int ImmedHValue() const { return Bits(11, 8); } + inline int ImmedLValue() const { return Bits(3, 0); } + + // Fields used in Branch instructions + inline int LinkValue() const { return Bit(24); } + inline int SImmed24Value() const { return ((InstructionBits() << 8) >> 8); } + + // Fields used in Software interrupt instructions + inline SoftwareInterruptCodes SvcValue() const { + return static_cast<SoftwareInterruptCodes>(Bits(23, 0)); + } + + // Test for special encodings of type 0 instructions (extra loads and stores, + // as well as multiplications). + inline bool IsSpecialType0() const { return (Bit(7) == 1) && (Bit(4) == 1); } + + // Test for miscellaneous instructions encodings of type 0 instructions. + inline bool IsMiscType0() const { + return (Bit(24) == 1) && (Bit(23) == 0) && (Bit(20) == 0) && + ((Bit(7) == 0)); + } + + // Test for a nop instruction, which falls under type 1. + inline bool IsNopType1() const { return Bits(24, 0) == 0x0120F000; } + + // Test for a nop instruction, which falls under type 1. + inline bool IsCsdbType1() const { return Bits(24, 0) == 0x0120F014; } + + // Test for a stop instruction. + inline bool IsStop() const { + return (TypeValue() == 7) && (Bit(24) == 1) && (SvcValue() >= kStopCode); + } + + // Special accessors that test for existence of a value. + inline bool HasS() const { return SValue() == 1; } + inline bool HasB() const { return BValue() == 1; } + inline bool HasW() const { return WValue() == 1; } + inline bool HasL() const { return LValue() == 1; } + inline bool HasU() const { return UValue() == 1; } + inline bool HasSign() const { return SignValue() == 1; } + inline bool HasH() const { return HValue() == 1; } + inline bool HasLink() const { return LinkValue() == 1; } + + // Decoding the double immediate in the vmov instruction. + double DoubleImmedVmov() const; + + // Instructions are read of out a code stream. The only way to get a + // reference to an instruction is to convert a pointer. There is no way + // to allocate or create instances of class Instruction. + // Use the At(pc) function to create references to Instruction. + static Instruction* At(uint8_t* pc) { + return reinterpret_cast<Instruction*>(pc); + } + + private: + // Join split register codes, depending on single or double precision. + // four_bit is the position of the least-significant bit of the four + // bit specifier. one_bit is the position of the additional single bit + // specifier. + inline int VFPGlueRegValue(VFPRegPrecision pre, int four_bit, int one_bit) { + if (pre == kSinglePrecision) { + return (Bits(four_bit + 3, four_bit) << 1) | Bit(one_bit); + } + return (Bit(one_bit) << 4) | Bits(four_bit + 3, four_bit); + } + + // We need to prevent the creation of instances of class Instruction. + Instruction() = delete; + Instruction(const Instruction&) = delete; + void operator=(const Instruction&) = delete; +}; + +// Helper functions for converting between register numbers and names. +class Registers { + public: + // Return the name of the register. + static const char* Name(int reg); + + // Lookup the register number for the name provided. + static int Number(const char* name); + + struct RegisterAlias { + int reg; + const char* name; + }; + + private: + static const char* names_[kNumRegisters]; + static const RegisterAlias aliases_[]; +}; + +// Helper functions for converting between VFP register numbers and names. +class VFPRegisters { + public: + // Return the name of the register. + static const char* Name(int reg, bool is_double); + + // Lookup the register number for the name provided. + // Set flag pointed by is_double to true if register + // is double-precision. + static int Number(const char* name, bool* is_double); + + private: + static const char* names_[kNumVFPRegisters]; +}; + +} // namespace disasm +} // namespace jit +} // namespace js + +#endif // JS_DISASM_ARM + +#endif // jit_arm_disasm_Constants_arm_h diff --git a/js/src/jit/arm/disasm/Disasm-arm.cpp b/js/src/jit/arm/disasm/Disasm-arm.cpp new file mode 100644 index 0000000000..97f39e1331 --- /dev/null +++ b/js/src/jit/arm/disasm/Disasm-arm.cpp @@ -0,0 +1,2031 @@ +/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 2 -*- + * vim: set ts=8 sts=2 et sw=2 tw=80: + */ +// Copyright 2011 the V8 project authors. All rights reserved. +// Use of this source code is governed by a BSD-style license that can be +// found in the LICENSE file. + +// A Disassembler object is used to disassemble a block of code instruction by +// instruction. The default implementation of the NameConverter object can be +// overriden to modify register names or to do symbol lookup on addresses. +// +// The example below will disassemble a block of code and print it to stdout. +// +// disasm::NameConverter converter; +// disasm::Disassembler d(converter); +// for (uint8_t* pc = begin; pc < end;) { +// disasm::EmbeddedVector<char, disasm::ReasonableBufferSize> buffer; +// uint8_t* prev_pc = pc; +// pc += d.InstructionDecode(buffer, pc); +// printf("%p %08x %s\n", +// prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer); +// } +// +// The Disassembler class also has a convenience method to disassemble a block +// of code into a FILE*, meaning that the above functionality could also be +// achieved by just calling Disassembler::Disassemble(stdout, begin, end); + +#include "jit/arm/disasm/Disasm-arm.h" + +#ifdef JS_DISASM_ARM + +# include <stdarg.h> +# include <stdio.h> +# include <string.h> + +# include "jit/arm/disasm/Constants-arm.h" + +namespace js { +namespace jit { +namespace disasm { + +// Helper function for printing to a Vector. +static int MOZ_FORMAT_PRINTF(2, 3) + SNPrintF(V8Vector<char> str, const char* format, ...) { + va_list args; + va_start(args, format); + int result = vsnprintf(str.start(), str.length(), format, args); + va_end(args); + return result; +} + +//------------------------------------------------------------------------------ + +// Decoder decodes and disassembles instructions into an output buffer. +// It uses the converter to convert register names and call destinations into +// more informative description. +class Decoder { + public: + Decoder(const disasm::NameConverter& converter, V8Vector<char> out_buffer) + : converter_(converter), out_buffer_(out_buffer), out_buffer_pos_(0) { + out_buffer_[out_buffer_pos_] = '\0'; + } + + ~Decoder() {} + + // Writes one disassembled instruction into 'buffer' (0-terminated). + // Returns the length of the disassembled machine instruction in bytes. + int InstructionDecode(uint8_t* instruction); + + static bool IsConstantPoolAt(uint8_t* instr_ptr); + static int ConstantPoolSizeAt(uint8_t* instr_ptr); + + private: + // Bottleneck functions to print into the out_buffer. + void PrintChar(const char ch); + void Print(const char* str); + + // Printing of common values. + void PrintRegister(int reg); + void PrintSRegister(int reg); + void PrintDRegister(int reg); + int FormatVFPRegister(Instruction* instr, const char* format); + void PrintMovwMovt(Instruction* instr); + int FormatVFPinstruction(Instruction* instr, const char* format); + void PrintCondition(Instruction* instr); + void PrintShiftRm(Instruction* instr); + void PrintShiftImm(Instruction* instr); + void PrintShiftSat(Instruction* instr); + void PrintPU(Instruction* instr); + void PrintSoftwareInterrupt(SoftwareInterruptCodes svc); + + // Handle formatting of instructions and their options. + int FormatRegister(Instruction* instr, const char* option); + void FormatNeonList(int Vd, int type); + void FormatNeonMemory(int Rn, int align, int Rm); + int FormatOption(Instruction* instr, const char* option); + void Format(Instruction* instr, const char* format); + void Unknown(Instruction* instr); + + // Each of these functions decodes one particular instruction type, a 3-bit + // field in the instruction encoding. + // Types 0 and 1 are combined as they are largely the same except for the way + // they interpret the shifter operand. + void DecodeType01(Instruction* instr); + void DecodeType2(Instruction* instr); + void DecodeType3(Instruction* instr); + void DecodeType4(Instruction* instr); + void DecodeType5(Instruction* instr); + void DecodeType6(Instruction* instr); + // Type 7 includes special Debugger instructions. + int DecodeType7(Instruction* instr); + // For VFP support. + void DecodeTypeVFP(Instruction* instr); + void DecodeType6CoprocessorIns(Instruction* instr); + + void DecodeSpecialCondition(Instruction* instr); + + void DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instruction* instr); + void DecodeVCMP(Instruction* instr); + void DecodeVCVTBetweenDoubleAndSingle(Instruction* instr); + void DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr); + + const disasm::NameConverter& converter_; + V8Vector<char> out_buffer_; + int out_buffer_pos_; + + // Disallow copy and assign. + Decoder(const Decoder&) = delete; + void operator=(const Decoder&) = delete; +}; + +// Support for assertions in the Decoder formatting functions. +# define STRING_STARTS_WITH(string, compare_string) \ + (strncmp(string, compare_string, strlen(compare_string)) == 0) + +// Append the ch to the output buffer. +void Decoder::PrintChar(const char ch) { out_buffer_[out_buffer_pos_++] = ch; } + +// Append the str to the output buffer. +void Decoder::Print(const char* str) { + char cur = *str++; + while (cur != '\0' && (out_buffer_pos_ < int(out_buffer_.length() - 1))) { + PrintChar(cur); + cur = *str++; + } + out_buffer_[out_buffer_pos_] = 0; +} + +// These condition names are defined in a way to match the native disassembler +// formatting. See for example the command "objdump -d <binary file>". +static const char* const cond_names[kNumberOfConditions] = { + "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", + "hi", "ls", "ge", "lt", "gt", "le", "", "invalid", +}; + +// Print the condition guarding the instruction. +void Decoder::PrintCondition(Instruction* instr) { + Print(cond_names[instr->ConditionValue()]); +} + +// Print the register name according to the active name converter. +void Decoder::PrintRegister(int reg) { + Print(converter_.NameOfCPURegister(reg)); +} + +// Print the VFP S register name according to the active name converter. +void Decoder::PrintSRegister(int reg) { Print(VFPRegisters::Name(reg, false)); } + +// Print the VFP D register name according to the active name converter. +void Decoder::PrintDRegister(int reg) { Print(VFPRegisters::Name(reg, true)); } + +// These shift names are defined in a way to match the native disassembler +// formatting. See for example the command "objdump -d <binary file>". +static const char* const shift_names[kNumberOfShifts] = {"lsl", "lsr", "asr", + "ror"}; + +// Print the register shift operands for the instruction. Generally used for +// data processing instructions. +void Decoder::PrintShiftRm(Instruction* instr) { + ShiftOp shift = instr->ShiftField(); + int shift_index = instr->ShiftValue(); + int shift_amount = instr->ShiftAmountValue(); + int rm = instr->RmValue(); + + PrintRegister(rm); + + if ((instr->RegShiftValue() == 0) && (shift == LSL) && (shift_amount == 0)) { + // Special case for using rm only. + return; + } + if (instr->RegShiftValue() == 0) { + // by immediate + if ((shift == ROR) && (shift_amount == 0)) { + Print(", RRX"); + return; + } else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) { + shift_amount = 32; + } + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, ", %s #%d", + shift_names[shift_index], shift_amount); + } else { + // by register + int rs = instr->RsValue(); + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, ", %s ", + shift_names[shift_index]); + PrintRegister(rs); + } +} + +static inline uint32_t RotateRight32(uint32_t value, uint32_t shift) { + if (shift == 0) return value; + return (value >> shift) | (value << (32 - shift)); +} + +// Print the immediate operand for the instruction. Generally used for data +// processing instructions. +void Decoder::PrintShiftImm(Instruction* instr) { + int rotate = instr->RotateValue() * 2; + int immed8 = instr->Immed8Value(); + int imm = RotateRight32(immed8, rotate); + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "#%d", imm); +} + +// Print the optional shift and immediate used by saturating instructions. +void Decoder::PrintShiftSat(Instruction* instr) { + int shift = instr->Bits(11, 7); + if (shift > 0) { + out_buffer_pos_ += + SNPrintF(out_buffer_ + out_buffer_pos_, ", %s #%d", + shift_names[instr->Bit(6) * 2], instr->Bits(11, 7)); + } +} + +// Print PU formatting to reduce complexity of FormatOption. +void Decoder::PrintPU(Instruction* instr) { + switch (instr->PUField()) { + case da_x: { + Print("da"); + break; + } + case ia_x: { + Print("ia"); + break; + } + case db_x: { + Print("db"); + break; + } + case ib_x: { + Print("ib"); + break; + } + default: { + MOZ_CRASH(); + break; + } + } +} + +// Print SoftwareInterrupt codes. Factoring this out reduces the complexity of +// the FormatOption method. +void Decoder::PrintSoftwareInterrupt(SoftwareInterruptCodes svc) { + switch (svc) { + case kCallRtRedirected: + Print("call rt redirected"); + return; + case kBreakpoint: + Print("breakpoint"); + return; + default: + if (svc >= kStopCode) { + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d - 0x%x", + svc & kStopCodeMask, svc & kStopCodeMask); + } else { + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", svc); + } + return; + } +} + +// Handle all register based formatting in this function to reduce the +// complexity of FormatOption. +int Decoder::FormatRegister(Instruction* instr, const char* format) { + MOZ_ASSERT(format[0] == 'r'); + if (format[1] == 'n') { // 'rn: Rn register + int reg = instr->RnValue(); + PrintRegister(reg); + return 2; + } else if (format[1] == 'd') { // 'rd: Rd register + int reg = instr->RdValue(); + PrintRegister(reg); + return 2; + } else if (format[1] == 's') { // 'rs: Rs register + int reg = instr->RsValue(); + PrintRegister(reg); + return 2; + } else if (format[1] == 'm') { // 'rm: Rm register + int reg = instr->RmValue(); + PrintRegister(reg); + return 2; + } else if (format[1] == 't') { // 'rt: Rt register + int reg = instr->RtValue(); + PrintRegister(reg); + return 2; + } else if (format[1] == 'l') { + // 'rlist: register list for load and store multiple instructions + MOZ_ASSERT(STRING_STARTS_WITH(format, "rlist")); + int rlist = instr->RlistValue(); + int reg = 0; + Print("{"); + // Print register list in ascending order, by scanning the bit mask. + while (rlist != 0) { + if ((rlist & 1) != 0) { + PrintRegister(reg); + if ((rlist >> 1) != 0) { + Print(", "); + } + } + reg++; + rlist >>= 1; + } + Print("}"); + return 5; + } + MOZ_CRASH(); + return -1; +} + +// Handle all VFP register based formatting in this function to reduce the +// complexity of FormatOption. +int Decoder::FormatVFPRegister(Instruction* instr, const char* format) { + MOZ_ASSERT((format[0] == 'S') || (format[0] == 'D')); + + VFPRegPrecision precision = + format[0] == 'D' ? kDoublePrecision : kSinglePrecision; + + int retval = 2; + int reg = -1; + if (format[1] == 'n') { + reg = instr->VFPNRegValue(precision); + } else if (format[1] == 'm') { + reg = instr->VFPMRegValue(precision); + } else if (format[1] == 'd') { + if ((instr->TypeValue() == 7) && (instr->Bit(24) == 0x0) && + (instr->Bits(11, 9) == 0x5) && (instr->Bit(4) == 0x1)) { + // vmov.32 has Vd in a different place. + reg = instr->Bits(19, 16) | (instr->Bit(7) << 4); + } else { + reg = instr->VFPDRegValue(precision); + } + + if (format[2] == '+') { + int immed8 = instr->Immed8Value(); + if (format[0] == 'S') reg += immed8 - 1; + if (format[0] == 'D') reg += (immed8 / 2 - 1); + } + if (format[2] == '+') retval = 3; + } else { + MOZ_CRASH(); + } + + if (precision == kSinglePrecision) { + PrintSRegister(reg); + } else { + PrintDRegister(reg); + } + + return retval; +} + +int Decoder::FormatVFPinstruction(Instruction* instr, const char* format) { + Print(format); + return 0; +} + +void Decoder::FormatNeonList(int Vd, int type) { + if (type == nlt_1) { + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "{d%d}", Vd); + } else if (type == nlt_2) { + out_buffer_pos_ += + SNPrintF(out_buffer_ + out_buffer_pos_, "{d%d, d%d}", Vd, Vd + 1); + } else if (type == nlt_3) { + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, + "{d%d, d%d, d%d}", Vd, Vd + 1, Vd + 2); + } else if (type == nlt_4) { + out_buffer_pos_ += + SNPrintF(out_buffer_ + out_buffer_pos_, "{d%d, d%d, d%d, d%d}", Vd, + Vd + 1, Vd + 2, Vd + 3); + } +} + +void Decoder::FormatNeonMemory(int Rn, int align, int Rm) { + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "[r%d", Rn); + if (align != 0) { + out_buffer_pos_ += + SNPrintF(out_buffer_ + out_buffer_pos_, ":%d", (1 << align) << 6); + } + if (Rm == 15) { + Print("]"); + } else if (Rm == 13) { + Print("]!"); + } else { + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "], r%d", Rm); + } +} + +// Print the movw or movt instruction. +void Decoder::PrintMovwMovt(Instruction* instr) { + int imm = instr->ImmedMovwMovtValue(); + int rd = instr->RdValue(); + PrintRegister(rd); + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, ", #%d", imm); +} + +// FormatOption takes a formatting string and interprets it based on +// the current instructions. The format string points to the first +// character of the option string (the option escape has already been +// consumed by the caller.) FormatOption returns the number of +// characters that were consumed from the formatting string. +int Decoder::FormatOption(Instruction* instr, const char* format) { + switch (format[0]) { + case 'a': { // 'a: accumulate multiplies + if (instr->Bit(21) == 0) { + Print("ul"); + } else { + Print("la"); + } + return 1; + } + case 'b': { // 'b: byte loads or stores + if (instr->HasB()) { + Print("b"); + } + return 1; + } + case 'c': { // 'cond: conditional execution + MOZ_ASSERT(STRING_STARTS_WITH(format, "cond")); + PrintCondition(instr); + return 4; + } + case 'd': { // 'd: vmov double immediate. + double d = instr->DoubleImmedVmov(); + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "#%g", d); + return 1; + } + case 'f': { // 'f: bitfield instructions - v7 and above. + uint32_t lsbit = instr->Bits(11, 7); + uint32_t width = instr->Bits(20, 16) + 1; + if (instr->Bit(21) == 0) { + // BFC/BFI: + // Bits 20-16 represent most-significant bit. Covert to width. + width -= lsbit; + MOZ_ASSERT(width > 0); + } + MOZ_ASSERT((width + lsbit) <= 32); + out_buffer_pos_ += + SNPrintF(out_buffer_ + out_buffer_pos_, "#%d, #%d", lsbit, width); + return 1; + } + case 'h': { // 'h: halfword operation for extra loads and stores + if (instr->HasH()) { + Print("h"); + } else { + Print("b"); + } + return 1; + } + case 'i': { // 'i: immediate value from adjacent bits. + // Expects tokens in the form imm%02d@%02d, i.e. imm05@07, imm10@16 + int width = (format[3] - '0') * 10 + (format[4] - '0'); + int lsb = (format[6] - '0') * 10 + (format[7] - '0'); + + MOZ_ASSERT((width >= 1) && (width <= 32)); + MOZ_ASSERT((lsb >= 0) && (lsb <= 31)); + MOZ_ASSERT((width + lsb) <= 32); + + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", + instr->Bits(width + lsb - 1, lsb)); + return 8; + } + case 'l': { // 'l: branch and link + if (instr->HasLink()) { + Print("l"); + } + return 1; + } + case 'm': { + if (format[1] == 'w') { + // 'mw: movt/movw instructions. + PrintMovwMovt(instr); + return 2; + } + if (format[1] == 'e') { // 'memop: load/store instructions. + MOZ_ASSERT(STRING_STARTS_WITH(format, "memop")); + if (instr->HasL()) { + Print("ldr"); + } else { + if ((instr->Bits(27, 25) == 0) && (instr->Bit(20) == 0) && + (instr->Bits(7, 6) == 3) && (instr->Bit(4) == 1)) { + if (instr->Bit(5) == 1) { + Print("strd"); + } else { + Print("ldrd"); + } + return 5; + } + Print("str"); + } + return 5; + } + // 'msg: for simulator break instructions + MOZ_ASSERT(STRING_STARTS_WITH(format, "msg")); + uint8_t* str = + reinterpret_cast<uint8_t*>(instr->InstructionBits() & 0x0fffffff); + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%s", + converter_.NameInCode(str)); + return 3; + } + case 'o': { + if ((format[3] == '1') && (format[4] == '2')) { + // 'off12: 12-bit offset for load and store instructions + MOZ_ASSERT(STRING_STARTS_WITH(format, "off12")); + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", + instr->Offset12Value()); + return 5; + } else if (format[3] == '0') { + // 'off0to3and8to19 16-bit immediate encoded in bits 19-8 and 3-0. + MOZ_ASSERT(STRING_STARTS_WITH(format, "off0to3and8to19")); + out_buffer_pos_ += + SNPrintF(out_buffer_ + out_buffer_pos_, "%d", + (instr->Bits(19, 8) << 4) + instr->Bits(3, 0)); + return 15; + } + // 'off8: 8-bit offset for extra load and store instructions + MOZ_ASSERT(STRING_STARTS_WITH(format, "off8")); + int offs8 = (instr->ImmedHValue() << 4) | instr->ImmedLValue(); + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%d", offs8); + return 4; + } + case 'p': { // 'pu: P and U bits for load and store instructions + MOZ_ASSERT(STRING_STARTS_WITH(format, "pu")); + PrintPU(instr); + return 2; + } + case 'r': { + return FormatRegister(instr, format); + } + case 's': { + if (format[1] == 'h') { // 'shift_op or 'shift_rm or 'shift_sat. + if (format[6] == 'o') { // 'shift_op + MOZ_ASSERT(STRING_STARTS_WITH(format, "shift_op")); + if (instr->TypeValue() == 0) { + PrintShiftRm(instr); + } else { + MOZ_ASSERT(instr->TypeValue() == 1); + PrintShiftImm(instr); + } + return 8; + } else if (format[6] == 's') { // 'shift_sat. + MOZ_ASSERT(STRING_STARTS_WITH(format, "shift_sat")); + PrintShiftSat(instr); + return 9; + } else { // 'shift_rm + MOZ_ASSERT(STRING_STARTS_WITH(format, "shift_rm")); + PrintShiftRm(instr); + return 8; + } + } else if (format[1] == 'v') { // 'svc + MOZ_ASSERT(STRING_STARTS_WITH(format, "svc")); + PrintSoftwareInterrupt(instr->SvcValue()); + return 3; + } else if (format[1] == 'i') { // 'sign: signed extra loads and stores + MOZ_ASSERT(STRING_STARTS_WITH(format, "sign")); + if (instr->HasSign()) { + Print("s"); + } + return 4; + } + // 's: S field of data processing instructions + if (instr->HasS()) { + Print("s"); + } + return 1; + } + case 't': { // 'target: target of branch instructions + MOZ_ASSERT(STRING_STARTS_WITH(format, "target")); + int off = (instr->SImmed24Value() << 2) + 8; + out_buffer_pos_ += SNPrintF( + out_buffer_ + out_buffer_pos_, "%+d -> %s", off, + converter_.NameOfAddress(reinterpret_cast<uint8_t*>(instr) + off)); + return 6; + } + case 'u': { // 'u: signed or unsigned multiplies + // The manual gets the meaning of bit 22 backwards in the multiply + // instruction overview on page A3.16.2. The instructions that + // exist in u and s variants are the following: + // smull A4.1.87 + // umull A4.1.129 + // umlal A4.1.128 + // smlal A4.1.76 + // For these 0 means u and 1 means s. As can be seen on their individual + // pages. The other 18 mul instructions have the bit set or unset in + // arbitrary ways that are unrelated to the signedness of the instruction. + // None of these 18 instructions exist in both a 'u' and an 's' variant. + + if (instr->Bit(22) == 0) { + Print("u"); + } else { + Print("s"); + } + return 1; + } + case 'v': { + return FormatVFPinstruction(instr, format); + } + case 'S': + case 'D': { + return FormatVFPRegister(instr, format); + } + case 'w': { // 'w: W field of load and store instructions + if (instr->HasW()) { + Print("!"); + } + return 1; + } + default: { + MOZ_CRASH(); + break; + } + } + MOZ_CRASH(); + return -1; +} + +// Format takes a formatting string for a whole instruction and prints it into +// the output buffer. All escaped options are handed to FormatOption to be +// parsed further. +void Decoder::Format(Instruction* instr, const char* format) { + char cur = *format++; + while ((cur != 0) && (out_buffer_pos_ < (out_buffer_.length() - 1))) { + if (cur == '\'') { // Single quote is used as the formatting escape. + format += FormatOption(instr, format); + } else { + out_buffer_[out_buffer_pos_++] = cur; + } + cur = *format++; + } + out_buffer_[out_buffer_pos_] = '\0'; +} + +// The disassembler may end up decoding data inlined in the code. We do not want +// it to crash if the data does not ressemble any known instruction. +# define VERIFY(condition) \ + if (!(condition)) { \ + Unknown(instr); \ + return; \ + } + +// For currently unimplemented decodings the disassembler calls Unknown(instr) +// which will just print "unknown" of the instruction bits. +void Decoder::Unknown(Instruction* instr) { Format(instr, "unknown"); } + +void Decoder::DecodeType01(Instruction* instr) { + int type = instr->TypeValue(); + if ((type == 0) && instr->IsSpecialType0()) { + // multiply instruction or extra loads and stores + if (instr->Bits(7, 4) == 9) { + if (instr->Bit(24) == 0) { + // multiply instructions + if (instr->Bit(23) == 0) { + if (instr->Bit(21) == 0) { + // The MUL instruction description (A 4.1.33) refers to Rd as being + // the destination for the operation, but it confusingly uses the + // Rn field to encode it. + Format(instr, "mul'cond's 'rn, 'rm, 'rs"); + } else { + if (instr->Bit(22) == 0) { + // The MLA instruction description (A 4.1.28) refers to the order + // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the + // Rn field to encode the Rd register and the Rd field to encode + // the Rn register. + Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); + } else { + // The MLS instruction description (A 4.1.29) refers to the order + // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the + // Rn field to encode the Rd register and the Rd field to encode + // the Rn register. + Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd"); + } + } + } else { + // The signed/long multiply instructions use the terms RdHi and RdLo + // when referring to the target registers. They are mapped to the Rn + // and Rd fields as follows: + // RdLo == Rd field + // RdHi == Rn field + // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs> + Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs"); + } + } else { + if (instr->Bits(ExclusiveOpHi, ExclusiveOpLo) == ExclusiveOpcode) { + if (instr->Bit(ExclusiveLoad) == 1) { + switch (instr->Bits(ExclusiveSizeHi, ExclusiveSizeLo)) { + case ExclusiveWord: + Format(instr, "ldrex'cond 'rt, ['rn]"); + break; + case ExclusiveDouble: + Format(instr, "ldrexd'cond 'rt, ['rn]"); + break; + case ExclusiveByte: + Format(instr, "ldrexb'cond 'rt, ['rn]"); + break; + case ExclusiveHalf: + Format(instr, "ldrexh'cond 'rt, ['rn]"); + break; + } + } else { + // The documentation names the low four bits of the + // store-exclusive instructions "Rt" but canonically + // for disassembly they are really "Rm". + switch (instr->Bits(ExclusiveSizeHi, ExclusiveSizeLo)) { + case ExclusiveWord: + Format(instr, "strex'cond 'rd, 'rm, ['rn]"); + break; + case ExclusiveDouble: + Format(instr, "strexd'cond 'rd, 'rm, ['rn]"); + break; + case ExclusiveByte: + Format(instr, "strexb'cond 'rd, 'rm, ['rn]"); + break; + case ExclusiveHalf: + Format(instr, "strexh'cond 'rd, 'rm, ['rn]"); + break; + } + } + } else { + Unknown(instr); + } + } + } else if ((instr->Bit(20) == 0) && ((instr->Bits(7, 4) & 0xd) == 0xd)) { + // ldrd, strd + switch (instr->PUField()) { + case da_x: { + if (instr->Bit(22) == 0) { + Format(instr, "'memop'cond's 'rd, ['rn], -'rm"); + } else { + Format(instr, "'memop'cond's 'rd, ['rn], #-'off8"); + } + break; + } + case ia_x: { + if (instr->Bit(22) == 0) { + Format(instr, "'memop'cond's 'rd, ['rn], +'rm"); + } else { + Format(instr, "'memop'cond's 'rd, ['rn], #+'off8"); + } + break; + } + case db_x: { + if (instr->Bit(22) == 0) { + Format(instr, "'memop'cond's 'rd, ['rn, -'rm]'w"); + } else { + Format(instr, "'memop'cond's 'rd, ['rn, #-'off8]'w"); + } + break; + } + case ib_x: { + if (instr->Bit(22) == 0) { + Format(instr, "'memop'cond's 'rd, ['rn, +'rm]'w"); + } else { + Format(instr, "'memop'cond's 'rd, ['rn, #+'off8]'w"); + } + break; + } + default: { + // The PU field is a 2-bit field. + MOZ_CRASH(); + break; + } + } + } else { + // extra load/store instructions + switch (instr->PUField()) { + case da_x: { + if (instr->Bit(22) == 0) { + Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm"); + } else { + Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8"); + } + break; + } + case ia_x: { + if (instr->Bit(22) == 0) { + Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm"); + } else { + Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8"); + } + break; + } + case db_x: { + if (instr->Bit(22) == 0) { + Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w"); + } else { + Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w"); + } + break; + } + case ib_x: { + if (instr->Bit(22) == 0) { + Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w"); + } else { + Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w"); + } + break; + } + default: { + // The PU field is a 2-bit field. + MOZ_CRASH(); + break; + } + } + return; + } + } else if ((type == 0) && instr->IsMiscType0()) { + if (instr->Bits(22, 21) == 1) { + switch (instr->BitField(7, 4)) { + case BX: + Format(instr, "bx'cond 'rm"); + break; + case BLX: + Format(instr, "blx'cond 'rm"); + break; + case BKPT: + Format(instr, "bkpt 'off0to3and8to19"); + break; + default: + Unknown(instr); // not used by V8 + break; + } + } else if (instr->Bits(22, 21) == 3) { + switch (instr->BitField(7, 4)) { + case CLZ: + Format(instr, "clz'cond 'rd, 'rm"); + break; + default: + Unknown(instr); // not used by V8 + break; + } + } else { + Unknown(instr); // not used by V8 + } + } else if ((type == 1) && instr->IsNopType1()) { + Format(instr, "nop'cond"); + } else if ((type == 1) && instr->IsCsdbType1()) { + Format(instr, "csdb'cond"); + } else { + switch (instr->OpcodeField()) { + case AND: { + Format(instr, "and'cond's 'rd, 'rn, 'shift_op"); + break; + } + case EOR: { + Format(instr, "eor'cond's 'rd, 'rn, 'shift_op"); + break; + } + case SUB: { + Format(instr, "sub'cond's 'rd, 'rn, 'shift_op"); + break; + } + case RSB: { + Format(instr, "rsb'cond's 'rd, 'rn, 'shift_op"); + break; + } + case ADD: { + Format(instr, "add'cond's 'rd, 'rn, 'shift_op"); + break; + } + case ADC: { + Format(instr, "adc'cond's 'rd, 'rn, 'shift_op"); + break; + } + case SBC: { + Format(instr, "sbc'cond's 'rd, 'rn, 'shift_op"); + break; + } + case RSC: { + Format(instr, "rsc'cond's 'rd, 'rn, 'shift_op"); + break; + } + case TST: { + if (instr->HasS()) { + Format(instr, "tst'cond 'rn, 'shift_op"); + } else { + Format(instr, "movw'cond 'mw"); + } + break; + } + case TEQ: { + if (instr->HasS()) { + Format(instr, "teq'cond 'rn, 'shift_op"); + } else { + // Other instructions matching this pattern are handled in the + // miscellaneous instructions part above. + MOZ_CRASH(); + } + break; + } + case CMP: { + if (instr->HasS()) { + Format(instr, "cmp'cond 'rn, 'shift_op"); + } else { + Format(instr, "movt'cond 'mw"); + } + break; + } + case CMN: { + if (instr->HasS()) { + Format(instr, "cmn'cond 'rn, 'shift_op"); + } else { + // Other instructions matching this pattern are handled in the + // miscellaneous instructions part above. + MOZ_CRASH(); + } + break; + } + case ORR: { + Format(instr, "orr'cond's 'rd, 'rn, 'shift_op"); + break; + } + case MOV: { + Format(instr, "mov'cond's 'rd, 'shift_op"); + break; + } + case BIC: { + Format(instr, "bic'cond's 'rd, 'rn, 'shift_op"); + break; + } + case MVN: { + Format(instr, "mvn'cond's 'rd, 'shift_op"); + break; + } + default: { + // The Opcode field is a 4-bit field. + MOZ_CRASH(); + break; + } + } + } +} + +void Decoder::DecodeType2(Instruction* instr) { + switch (instr->PUField()) { + case da_x: { + if (instr->HasW()) { + Unknown(instr); // not used in V8 + return; + } + Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12"); + break; + } + case ia_x: { + if (instr->HasW()) { + Unknown(instr); // not used in V8 + return; + } + Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12"); + break; + } + case db_x: { + Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w"); + break; + } + case ib_x: { + Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w"); + break; + } + default: { + // The PU field is a 2-bit field. + MOZ_CRASH(); + break; + } + } +} + +void Decoder::DecodeType3(Instruction* instr) { + switch (instr->PUField()) { + case da_x: { + VERIFY(!instr->HasW()); + Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm"); + break; + } + case ia_x: { + if (instr->Bit(4) == 0) { + Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm"); + } else { + if (instr->Bit(5) == 0) { + switch (instr->Bits(22, 21)) { + case 0: + if (instr->Bit(20) == 0) { + if (instr->Bit(6) == 0) { + Format(instr, "pkhbt'cond 'rd, 'rn, 'rm, lsl #'imm05@07"); + } else { + if (instr->Bits(11, 7) == 0) { + Format(instr, "pkhtb'cond 'rd, 'rn, 'rm, asr #32"); + } else { + Format(instr, "pkhtb'cond 'rd, 'rn, 'rm, asr #'imm05@07"); + } + } + } else { + MOZ_CRASH(); + } + break; + case 1: + MOZ_CRASH(); + break; + case 2: + MOZ_CRASH(); + break; + case 3: + Format(instr, "usat 'rd, #'imm05@16, 'rm'shift_sat"); + break; + } + } else { + switch (instr->Bits(22, 21)) { + case 0: + MOZ_CRASH(); + break; + case 1: + if (instr->Bits(9, 6) == 1) { + if (instr->Bit(20) == 0) { + if (instr->Bits(19, 16) == 0xF) { + switch (instr->Bits(11, 10)) { + case 0: + Format(instr, "sxtb'cond 'rd, 'rm"); + break; + case 1: + Format(instr, "sxtb'cond 'rd, 'rm, ror #8"); + break; + case 2: + Format(instr, "sxtb'cond 'rd, 'rm, ror #16"); + break; + case 3: + Format(instr, "sxtb'cond 'rd, 'rm, ror #24"); + break; + } + } else { + switch (instr->Bits(11, 10)) { + case 0: + Format(instr, "sxtab'cond 'rd, 'rn, 'rm"); + break; + case 1: + Format(instr, "sxtab'cond 'rd, 'rn, 'rm, ror #8"); + break; + case 2: + Format(instr, "sxtab'cond 'rd, 'rn, 'rm, ror #16"); + break; + case 3: + Format(instr, "sxtab'cond 'rd, 'rn, 'rm, ror #24"); + break; + } + } + } else { + if (instr->Bits(19, 16) == 0xF) { + switch (instr->Bits(11, 10)) { + case 0: + Format(instr, "sxth'cond 'rd, 'rm"); + break; + case 1: + Format(instr, "sxth'cond 'rd, 'rm, ror #8"); + break; + case 2: + Format(instr, "sxth'cond 'rd, 'rm, ror #16"); + break; + case 3: + Format(instr, "sxth'cond 'rd, 'rm, ror #24"); + break; + } + } else { + switch (instr->Bits(11, 10)) { + case 0: + Format(instr, "sxtah'cond 'rd, 'rn, 'rm"); + break; + case 1: + Format(instr, "sxtah'cond 'rd, 'rn, 'rm, ror #8"); + break; + case 2: + Format(instr, "sxtah'cond 'rd, 'rn, 'rm, ror #16"); + break; + case 3: + Format(instr, "sxtah'cond 'rd, 'rn, 'rm, ror #24"); + break; + } + } + } + } else { + MOZ_CRASH(); + } + break; + case 2: + if ((instr->Bit(20) == 0) && (instr->Bits(9, 6) == 1)) { + if (instr->Bits(19, 16) == 0xF) { + switch (instr->Bits(11, 10)) { + case 0: + Format(instr, "uxtb16'cond 'rd, 'rm"); + break; + case 1: + Format(instr, "uxtb16'cond 'rd, 'rm, ror #8"); + break; + case 2: + Format(instr, "uxtb16'cond 'rd, 'rm, ror #16"); + break; + case 3: + Format(instr, "uxtb16'cond 'rd, 'rm, ror #24"); + break; + } + } else { + MOZ_CRASH(); + } + } else { + MOZ_CRASH(); + } + break; + case 3: + if ((instr->Bits(9, 6) == 1)) { + if ((instr->Bit(20) == 0)) { + if (instr->Bits(19, 16) == 0xF) { + switch (instr->Bits(11, 10)) { + case 0: + Format(instr, "uxtb'cond 'rd, 'rm"); + break; + case 1: + Format(instr, "uxtb'cond 'rd, 'rm, ror #8"); + break; + case 2: + Format(instr, "uxtb'cond 'rd, 'rm, ror #16"); + break; + case 3: + Format(instr, "uxtb'cond 'rd, 'rm, ror #24"); + break; + } + } else { + switch (instr->Bits(11, 10)) { + case 0: + Format(instr, "uxtab'cond 'rd, 'rn, 'rm"); + break; + case 1: + Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #8"); + break; + case 2: + Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #16"); + break; + case 3: + Format(instr, "uxtab'cond 'rd, 'rn, 'rm, ror #24"); + break; + } + } + } else { + if (instr->Bits(19, 16) == 0xF) { + switch (instr->Bits(11, 10)) { + case 0: + Format(instr, "uxth'cond 'rd, 'rm"); + break; + case 1: + Format(instr, "uxth'cond 'rd, 'rm, ror #8"); + break; + case 2: + Format(instr, "uxth'cond 'rd, 'rm, ror #16"); + break; + case 3: + Format(instr, "uxth'cond 'rd, 'rm, ror #24"); + break; + } + } else { + switch (instr->Bits(11, 10)) { + case 0: + Format(instr, "uxtah'cond 'rd, 'rn, 'rm"); + break; + case 1: + Format(instr, "uxtah'cond 'rd, 'rn, 'rm, ror #8"); + break; + case 2: + Format(instr, "uxtah'cond 'rd, 'rn, 'rm, ror #16"); + break; + case 3: + Format(instr, "uxtah'cond 'rd, 'rn, 'rm, ror #24"); + break; + } + } + } + } else { + MOZ_CRASH(); + } + break; + } + } + } + break; + } + case db_x: { + if (instr->Bits(22, 20) == 0x5) { + if (instr->Bits(7, 4) == 0x1) { + if (instr->Bits(15, 12) == 0xF) { + Format(instr, "smmul'cond 'rn, 'rm, 'rs"); + } else { + // SMMLA (in V8 notation matching ARM ISA format) + Format(instr, "smmla'cond 'rn, 'rm, 'rs, 'rd"); + } + break; + } + } + bool FLAG_enable_sudiv = true; // Flag doesn't exist in our engine. + if (FLAG_enable_sudiv) { + if (instr->Bits(5, 4) == 0x1) { + if ((instr->Bit(22) == 0x0) && (instr->Bit(20) == 0x1)) { + if (instr->Bit(21) == 0x1) { + // UDIV (in V8 notation matching ARM ISA format) rn = rm/rs + Format(instr, "udiv'cond'b 'rn, 'rm, 'rs"); + } else { + // SDIV (in V8 notation matching ARM ISA format) rn = rm/rs + Format(instr, "sdiv'cond'b 'rn, 'rm, 'rs"); + } + break; + } + } + } + Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w"); + break; + } + case ib_x: { + if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) { + uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16)); + uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7)); + uint32_t msbit = widthminus1 + lsbit; + if (msbit <= 31) { + if (instr->Bit(22)) { + Format(instr, "ubfx'cond 'rd, 'rm, 'f"); + } else { + Format(instr, "sbfx'cond 'rd, 'rm, 'f"); + } + } else { + MOZ_CRASH(); + } + } else if (!instr->HasW() && (instr->Bits(6, 4) == 0x1)) { + uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7)); + uint32_t msbit = static_cast<uint32_t>(instr->Bits(20, 16)); + if (msbit >= lsbit) { + if (instr->RmValue() == 15) { + Format(instr, "bfc'cond 'rd, 'f"); + } else { + Format(instr, "bfi'cond 'rd, 'rm, 'f"); + } + } else { + MOZ_CRASH(); + } + } else { + Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w"); + } + break; + } + default: { + // The PU field is a 2-bit field. + MOZ_CRASH(); + break; + } + } +} + +void Decoder::DecodeType4(Instruction* instr) { + if (instr->Bit(22) != 0) { + // Privileged mode currently not supported. + Unknown(instr); + } else { + if (instr->HasL()) { + Format(instr, "ldm'cond'pu 'rn'w, 'rlist"); + } else { + Format(instr, "stm'cond'pu 'rn'w, 'rlist"); + } + } +} + +void Decoder::DecodeType5(Instruction* instr) { + Format(instr, "b'l'cond 'target"); +} + +void Decoder::DecodeType6(Instruction* instr) { + DecodeType6CoprocessorIns(instr); +} + +int Decoder::DecodeType7(Instruction* instr) { + if (instr->Bit(24) == 1) { + if (instr->SvcValue() >= kStopCode) { + Format(instr, "stop'cond 'svc"); + // Also print the stop message. Its address is encoded + // in the following 4 bytes. + out_buffer_pos_ += SNPrintF( + out_buffer_ + out_buffer_pos_, "\n %p %08x stop message: %s", + reinterpret_cast<void*>(instr + Instruction::kInstrSize), + *reinterpret_cast<uint32_t*>(instr + Instruction::kInstrSize), + *reinterpret_cast<char**>(instr + Instruction::kInstrSize)); + // We have decoded 2 * Instruction::kInstrSize bytes. + return 2 * Instruction::kInstrSize; + } else { + Format(instr, "svc'cond 'svc"); + } + } else { + DecodeTypeVFP(instr); + } + return Instruction::kInstrSize; +} + +// void Decoder::DecodeTypeVFP(Instruction* instr) +// vmov: Sn = Rt +// vmov: Rt = Sn +// vcvt: Dd = Sm +// vcvt: Sd = Dm +// vcvt.f64.s32 Dd, Dd, #<fbits> +// Dd = vabs(Dm) +// Sd = vabs(Sm) +// Dd = vneg(Dm) +// Sd = vneg(Sm) +// Dd = vadd(Dn, Dm) +// Sd = vadd(Sn, Sm) +// Dd = vsub(Dn, Dm) +// Sd = vsub(Sn, Sm) +// Dd = vmul(Dn, Dm) +// Sd = vmul(Sn, Sm) +// Dd = vmla(Dn, Dm) +// Sd = vmla(Sn, Sm) +// Dd = vmls(Dn, Dm) +// Sd = vmls(Sn, Sm) +// Dd = vdiv(Dn, Dm) +// Sd = vdiv(Sn, Sm) +// vcmp(Dd, Dm) +// vcmp(Sd, Sm) +// Dd = vsqrt(Dm) +// Sd = vsqrt(Sm) +// vmrs +// vmsr +void Decoder::DecodeTypeVFP(Instruction* instr) { + VERIFY((instr->TypeValue() == 7) && (instr->Bit(24) == 0x0)); + VERIFY(instr->Bits(11, 9) == 0x5); + + if (instr->Bit(4) == 0) { + if (instr->Opc1Value() == 0x7) { + // Other data processing instructions + if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x1)) { + // vmov register to register. + if (instr->SzValue() == 0x1) { + Format(instr, "vmov'cond.f64 'Dd, 'Dm"); + } else { + Format(instr, "vmov'cond.f32 'Sd, 'Sm"); + } + } else if ((instr->Opc2Value() == 0x0) && (instr->Opc3Value() == 0x3)) { + // vabs + if (instr->SzValue() == 0x1) { + Format(instr, "vabs'cond.f64 'Dd, 'Dm"); + } else { + Format(instr, "vabs'cond.f32 'Sd, 'Sm"); + } + } else if ((instr->Opc2Value() == 0x1) && (instr->Opc3Value() == 0x1)) { + // vneg + if (instr->SzValue() == 0x1) { + Format(instr, "vneg'cond.f64 'Dd, 'Dm"); + } else { + Format(instr, "vneg'cond.f32 'Sd, 'Sm"); + } + } else if ((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)) { + DecodeVCVTBetweenDoubleAndSingle(instr); + } else if ((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) { + DecodeVCVTBetweenFloatingPointAndInteger(instr); + } else if ((instr->Opc2Value() == 0xA) && (instr->Opc3Value() == 0x3) && + (instr->Bit(8) == 1)) { + // vcvt.f64.s32 Dd, Dd, #<fbits> + int fraction_bits = 32 - ((instr->Bits(3, 0) << 1) | instr->Bit(5)); + Format(instr, "vcvt'cond.f64.s32 'Dd, 'Dd"); + out_buffer_pos_ += + SNPrintF(out_buffer_ + out_buffer_pos_, ", #%d", fraction_bits); + } else if (((instr->Opc2Value() >> 1) == 0x6) && + (instr->Opc3Value() & 0x1)) { + DecodeVCVTBetweenFloatingPointAndInteger(instr); + } else if (((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) && + (instr->Opc3Value() & 0x1)) { + DecodeVCMP(instr); + } else if (((instr->Opc2Value() == 0x1)) && (instr->Opc3Value() == 0x3)) { + if (instr->SzValue() == 0x1) { + Format(instr, "vsqrt'cond.f64 'Dd, 'Dm"); + } else { + Format(instr, "vsqrt'cond.f32 'Sd, 'Sm"); + } + } else if (instr->Opc3Value() == 0x0) { + if (instr->SzValue() == 0x1) { + Format(instr, "vmov'cond.f64 'Dd, 'd"); + } else { + Unknown(instr); // Not used by V8. + } + } else if (((instr->Opc2Value() == 0x6)) && instr->Opc3Value() == 0x3) { + // vrintz - round towards zero (truncate) + if (instr->SzValue() == 0x1) { + Format(instr, "vrintz'cond.f64.f64 'Dd, 'Dm"); + } else { + Format(instr, "vrintz'cond.f32.f32 'Sd, 'Sm"); + } + } else { + Unknown(instr); // Not used by V8. + } + } else if (instr->Opc1Value() == 0x3) { + if (instr->SzValue() == 0x1) { + if (instr->Opc3Value() & 0x1) { + Format(instr, "vsub'cond.f64 'Dd, 'Dn, 'Dm"); + } else { + Format(instr, "vadd'cond.f64 'Dd, 'Dn, 'Dm"); + } + } else { + if (instr->Opc3Value() & 0x1) { + Format(instr, "vsub'cond.f32 'Sd, 'Sn, 'Sm"); + } else { + Format(instr, "vadd'cond.f32 'Sd, 'Sn, 'Sm"); + } + } + } else if ((instr->Opc1Value() == 0x2) && !(instr->Opc3Value() & 0x1)) { + if (instr->SzValue() == 0x1) { + Format(instr, "vmul'cond.f64 'Dd, 'Dn, 'Dm"); + } else { + Format(instr, "vmul'cond.f32 'Sd, 'Sn, 'Sm"); + } + } else if ((instr->Opc1Value() == 0x0) && !(instr->Opc3Value() & 0x1)) { + if (instr->SzValue() == 0x1) { + Format(instr, "vmla'cond.f64 'Dd, 'Dn, 'Dm"); + } else { + Format(instr, "vmla'cond.f32 'Sd, 'Sn, 'Sm"); + } + } else if ((instr->Opc1Value() == 0x0) && (instr->Opc3Value() & 0x1)) { + if (instr->SzValue() == 0x1) { + Format(instr, "vmls'cond.f64 'Dd, 'Dn, 'Dm"); + } else { + Format(instr, "vmls'cond.f32 'Sd, 'Sn, 'Sm"); + } + } else if ((instr->Opc1Value() == 0x4) && !(instr->Opc3Value() & 0x1)) { + if (instr->SzValue() == 0x1) { + Format(instr, "vdiv'cond.f64 'Dd, 'Dn, 'Dm"); + } else { + Format(instr, "vdiv'cond.f32 'Sd, 'Sn, 'Sm"); + } + } else { + Unknown(instr); // Not used by V8. + } + } else { + if ((instr->VCValue() == 0x0) && (instr->VAValue() == 0x0)) { + DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr); + } else if ((instr->VLValue() == 0x0) && (instr->VCValue() == 0x1) && + (instr->Bit(23) == 0x0)) { + if (instr->Bit(21) == 0x0) { + Format(instr, "vmov'cond.32 'Dd[0], 'rt"); + } else { + Format(instr, "vmov'cond.32 'Dd[1], 'rt"); + } + } else if ((instr->VLValue() == 0x1) && (instr->VCValue() == 0x1) && + (instr->Bit(23) == 0x0)) { + if (instr->Bit(21) == 0x0) { + Format(instr, "vmov'cond.32 'rt, 'Dd[0]"); + } else { + Format(instr, "vmov'cond.32 'rt, 'Dd[1]"); + } + } else if ((instr->VCValue() == 0x0) && (instr->VAValue() == 0x7) && + (instr->Bits(19, 16) == 0x1)) { + if (instr->VLValue() == 0) { + if (instr->Bits(15, 12) == 0xF) { + Format(instr, "vmsr'cond FPSCR, APSR"); + } else { + Format(instr, "vmsr'cond FPSCR, 'rt"); + } + } else { + if (instr->Bits(15, 12) == 0xF) { + Format(instr, "vmrs'cond APSR, FPSCR"); + } else { + Format(instr, "vmrs'cond 'rt, FPSCR"); + } + } + } + } +} + +void Decoder::DecodeVMOVBetweenCoreAndSinglePrecisionRegisters( + Instruction* instr) { + VERIFY((instr->Bit(4) == 1) && (instr->VCValue() == 0x0) && + (instr->VAValue() == 0x0)); + + bool to_arm_register = (instr->VLValue() == 0x1); + + if (to_arm_register) { + Format(instr, "vmov'cond 'rt, 'Sn"); + } else { + Format(instr, "vmov'cond 'Sn, 'rt"); + } +} + +void Decoder::DecodeVCMP(Instruction* instr) { + VERIFY((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7)); + VERIFY(((instr->Opc2Value() == 0x4) || (instr->Opc2Value() == 0x5)) && + (instr->Opc3Value() & 0x1)); + + // Comparison. + bool dp_operation = (instr->SzValue() == 1); + bool raise_exception_for_qnan = (instr->Bit(7) == 0x1); + + if (dp_operation && !raise_exception_for_qnan) { + if (instr->Opc2Value() == 0x4) { + Format(instr, "vcmp'cond.f64 'Dd, 'Dm"); + } else if (instr->Opc2Value() == 0x5) { + Format(instr, "vcmp'cond.f64 'Dd, #0.0"); + } else { + Unknown(instr); // invalid + } + } else if (!raise_exception_for_qnan) { + if (instr->Opc2Value() == 0x4) { + Format(instr, "vcmp'cond.f32 'Sd, 'Sm"); + } else if (instr->Opc2Value() == 0x5) { + Format(instr, "vcmp'cond.f32 'Sd, #0.0"); + } else { + Unknown(instr); // invalid + } + } else { + Unknown(instr); // Not used by V8. + } +} + +void Decoder::DecodeVCVTBetweenDoubleAndSingle(Instruction* instr) { + VERIFY((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7)); + VERIFY((instr->Opc2Value() == 0x7) && (instr->Opc3Value() == 0x3)); + + bool double_to_single = (instr->SzValue() == 1); + + if (double_to_single) { + Format(instr, "vcvt'cond.f32.f64 'Sd, 'Dm"); + } else { + Format(instr, "vcvt'cond.f64.f32 'Dd, 'Sm"); + } +} + +void Decoder::DecodeVCVTBetweenFloatingPointAndInteger(Instruction* instr) { + VERIFY((instr->Bit(4) == 0) && (instr->Opc1Value() == 0x7)); + VERIFY(((instr->Opc2Value() == 0x8) && (instr->Opc3Value() & 0x1)) || + (((instr->Opc2Value() >> 1) == 0x6) && (instr->Opc3Value() & 0x1))); + + bool to_integer = (instr->Bit(18) == 1); + bool dp_operation = (instr->SzValue() == 1); + if (to_integer) { + bool unsigned_integer = (instr->Bit(16) == 0); + + if (dp_operation) { + if (unsigned_integer) { + Format(instr, "vcvt'cond.u32.f64 'Sd, 'Dm"); + } else { + Format(instr, "vcvt'cond.s32.f64 'Sd, 'Dm"); + } + } else { + if (unsigned_integer) { + Format(instr, "vcvt'cond.u32.f32 'Sd, 'Sm"); + } else { + Format(instr, "vcvt'cond.s32.f32 'Sd, 'Sm"); + } + } + } else { + bool unsigned_integer = (instr->Bit(7) == 0); + + if (dp_operation) { + if (unsigned_integer) { + Format(instr, "vcvt'cond.f64.u32 'Dd, 'Sm"); + } else { + Format(instr, "vcvt'cond.f64.s32 'Dd, 'Sm"); + } + } else { + if (unsigned_integer) { + Format(instr, "vcvt'cond.f32.u32 'Sd, 'Sm"); + } else { + Format(instr, "vcvt'cond.f32.s32 'Sd, 'Sm"); + } + } + } +} + +// Decode Type 6 coprocessor instructions. +// Dm = vmov(Rt, Rt2) +// <Rt, Rt2> = vmov(Dm) +// Ddst = MEM(Rbase + 4*offset). +// MEM(Rbase + 4*offset) = Dsrc. +void Decoder::DecodeType6CoprocessorIns(Instruction* instr) { + VERIFY(instr->TypeValue() == 6); + + if (instr->CoprocessorValue() == 0xA) { + switch (instr->OpcodeValue()) { + case 0x8: + case 0xA: + if (instr->HasL()) { + Format(instr, "vldr'cond 'Sd, ['rn - 4*'imm08@00]"); + } else { + Format(instr, "vstr'cond 'Sd, ['rn - 4*'imm08@00]"); + } + break; + case 0xC: + case 0xE: + if (instr->HasL()) { + Format(instr, "vldr'cond 'Sd, ['rn + 4*'imm08@00]"); + } else { + Format(instr, "vstr'cond 'Sd, ['rn + 4*'imm08@00]"); + } + break; + case 0x4: + case 0x5: + case 0x6: + case 0x7: + case 0x9: + case 0xB: { + bool to_vfp_register = (instr->VLValue() == 0x1); + if (to_vfp_register) { + Format(instr, "vldm'cond'pu 'rn'w, {'Sd-'Sd+}"); + } else { + Format(instr, "vstm'cond'pu 'rn'w, {'Sd-'Sd+}"); + } + break; + } + default: + Unknown(instr); // Not used by V8. + } + } else if (instr->CoprocessorValue() == 0xB) { + switch (instr->OpcodeValue()) { + case 0x2: + // Load and store double to two GP registers + if (instr->Bits(7, 6) != 0 || instr->Bit(4) != 1) { + Unknown(instr); // Not used by V8. + } else if (instr->HasL()) { + Format(instr, "vmov'cond 'rt, 'rn, 'Dm"); + } else { + Format(instr, "vmov'cond 'Dm, 'rt, 'rn"); + } + break; + case 0x8: + case 0xA: + if (instr->HasL()) { + Format(instr, "vldr'cond 'Dd, ['rn - 4*'imm08@00]"); + } else { + Format(instr, "vstr'cond 'Dd, ['rn - 4*'imm08@00]"); + } + break; + case 0xC: + case 0xE: + if (instr->HasL()) { + Format(instr, "vldr'cond 'Dd, ['rn + 4*'imm08@00]"); + } else { + Format(instr, "vstr'cond 'Dd, ['rn + 4*'imm08@00]"); + } + break; + case 0x4: + case 0x5: + case 0x6: + case 0x7: + case 0x9: + case 0xB: { + bool to_vfp_register = (instr->VLValue() == 0x1); + if (to_vfp_register) { + Format(instr, "vldm'cond'pu 'rn'w, {'Dd-'Dd+}"); + } else { + Format(instr, "vstm'cond'pu 'rn'w, {'Dd-'Dd+}"); + } + break; + } + default: + Unknown(instr); // Not used by V8. + } + } else { + Unknown(instr); // Not used by V8. + } +} + +void Decoder::DecodeSpecialCondition(Instruction* instr) { + switch (instr->SpecialValue()) { + case 5: + if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) && + (instr->Bit(4) == 1)) { + // vmovl signed + if ((instr->VdValue() & 1) != 0) Unknown(instr); + int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); + int Vm = (instr->Bit(5) << 4) | instr->VmValue(); + int imm3 = instr->Bits(21, 19); + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, + "vmovl.s%d q%d, d%d", imm3 * 8, Vd, Vm); + } else { + Unknown(instr); + } + break; + case 7: + if ((instr->Bits(18, 16) == 0) && (instr->Bits(11, 6) == 0x28) && + (instr->Bit(4) == 1)) { + // vmovl unsigned + if ((instr->VdValue() & 1) != 0) Unknown(instr); + int Vd = (instr->Bit(22) << 3) | (instr->VdValue() >> 1); + int Vm = (instr->Bit(5) << 4) | instr->VmValue(); + int imm3 = instr->Bits(21, 19); + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, + "vmovl.u%d q%d, d%d", imm3 * 8, Vd, Vm); + } else { + Unknown(instr); + } + break; + case 8: + if (instr->Bits(21, 20) == 0) { + // vst1 + int Vd = (instr->Bit(22) << 4) | instr->VdValue(); + int Rn = instr->VnValue(); + int type = instr->Bits(11, 8); + int size = instr->Bits(7, 6); + int align = instr->Bits(5, 4); + int Rm = instr->VmValue(); + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "vst1.%d ", + (1 << size) << 3); + FormatNeonList(Vd, type); + Print(", "); + FormatNeonMemory(Rn, align, Rm); + } else if (instr->Bits(21, 20) == 2) { + // vld1 + int Vd = (instr->Bit(22) << 4) | instr->VdValue(); + int Rn = instr->VnValue(); + int type = instr->Bits(11, 8); + int size = instr->Bits(7, 6); + int align = instr->Bits(5, 4); + int Rm = instr->VmValue(); + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "vld1.%d ", + (1 << size) << 3); + FormatNeonList(Vd, type); + Print(", "); + FormatNeonMemory(Rn, align, Rm); + } else { + Unknown(instr); + } + break; + case 9: + if (instr->Bits(21, 20) == 0 && instr->Bits(9, 8) == 0) { + // vst1 + int Vd = (instr->Bit(22) << 4) | instr->VdValue(); + int Rn = instr->VnValue(); + int size = instr->Bits(11, 10); + int index = instr->Bits(7, 5); + int align = instr->Bit(4); + int Rm = instr->VmValue(); + out_buffer_pos_ += + SNPrintF(out_buffer_ + out_buffer_pos_, "vst1.%d {d%d[%d]}, ", + (1 << size) << 3, Vd, index); + FormatNeonMemory(Rn, align, Rm); + } else if (instr->Bits(21, 20) == 2 && instr->Bits(9, 8) == 0) { + // vld1 + int Vd = (instr->Bit(22) << 4) | instr->VdValue(); + int Rn = instr->VnValue(); + int size = instr->Bits(11, 10); + int index = instr->Bits(7, 5); + int align = instr->Bit(4); + int Rm = instr->VmValue(); + out_buffer_pos_ += + SNPrintF(out_buffer_ + out_buffer_pos_, "vld1.%d {d%d[%d]}, ", + (1 << size) << 3, Vd, index); + FormatNeonMemory(Rn, align, Rm); + } else { + Unknown(instr); + } + break; + case 0xA: + if (instr->Bits(22, 20) == 7) { + const char* option = "?"; + switch (instr->Bits(3, 0)) { + case 2: + option = "oshst"; + break; + case 3: + option = "osh"; + break; + case 6: + option = "nshst"; + break; + case 7: + option = "nsh"; + break; + case 10: + option = "ishst"; + break; + case 11: + option = "ish"; + break; + case 14: + option = "st"; + break; + case 15: + option = "sy"; + break; + } + switch (instr->Bits(7, 4)) { + case 1: + Print("clrex"); + break; + case 4: + out_buffer_pos_ += + SNPrintF(out_buffer_ + out_buffer_pos_, "dsb %s", option); + break; + case 5: + out_buffer_pos_ += + SNPrintF(out_buffer_ + out_buffer_pos_, "dmb %s", option); + break; + default: + Unknown(instr); + } + break; + } + [[fallthrough]]; + case 0xB: + if ((instr->Bits(22, 20) == 5) && (instr->Bits(15, 12) == 0xf)) { + int Rn = instr->Bits(19, 16); + int offset = instr->Bits(11, 0); + if (offset == 0) { + out_buffer_pos_ += + SNPrintF(out_buffer_ + out_buffer_pos_, "pld [r%d]", Rn); + } else if (instr->Bit(23) == 0) { + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, + "pld [r%d, #-%d]", Rn, offset); + } else { + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, + "pld [r%d, #+%d]", Rn, offset); + } + } else { + Unknown(instr); + } + break; + case 0x1D: + if (instr->Opc1Value() == 0x7 && instr->Bits(19, 18) == 0x2 && + instr->Bits(11, 9) == 0x5 && instr->Bits(7, 6) == 0x1 && + instr->Bit(4) == 0x0) { + // VRINTA, VRINTN, VRINTP, VRINTM (floating-point) + bool dp_operation = (instr->SzValue() == 1); + int rounding_mode = instr->Bits(17, 16); + switch (rounding_mode) { + case 0x0: + if (dp_operation) { + Format(instr, "vrinta.f64.f64 'Dd, 'Dm"); + } else { + Unknown(instr); + } + break; + case 0x1: + if (dp_operation) { + Format(instr, "vrintn.f64.f64 'Dd, 'Dm"); + } else { + Unknown(instr); + } + break; + case 0x2: + if (dp_operation) { + Format(instr, "vrintp.f64.f64 'Dd, 'Dm"); + } else { + Unknown(instr); + } + break; + case 0x3: + if (dp_operation) { + Format(instr, "vrintm.f64.f64 'Dd, 'Dm"); + } else { + Unknown(instr); + } + break; + default: + MOZ_CRASH(); // Case analysis is exhaustive. + break; + } + } else { + Unknown(instr); + } + break; + default: + Unknown(instr); + break; + } +} + +# undef VERIFIY + +bool Decoder::IsConstantPoolAt(uint8_t* instr_ptr) { + int instruction_bits = *(reinterpret_cast<int*>(instr_ptr)); + return (instruction_bits & kConstantPoolMarkerMask) == kConstantPoolMarker; +} + +int Decoder::ConstantPoolSizeAt(uint8_t* instr_ptr) { + if (IsConstantPoolAt(instr_ptr)) { + int instruction_bits = *(reinterpret_cast<int*>(instr_ptr)); + return DecodeConstantPoolLength(instruction_bits); + } else { + return -1; + } +} + +// Disassemble the instruction at *instr_ptr into the output buffer. +int Decoder::InstructionDecode(uint8_t* instr_ptr) { + Instruction* instr = Instruction::At(instr_ptr); + // Print raw instruction bytes. + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%08x ", + instr->InstructionBits()); + if (instr->ConditionField() == kSpecialCondition) { + DecodeSpecialCondition(instr); + return Instruction::kInstrSize; + } + int instruction_bits = *(reinterpret_cast<int*>(instr_ptr)); + if ((instruction_bits & kConstantPoolMarkerMask) == kConstantPoolMarker) { + out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, + "constant pool begin (length %d)", + DecodeConstantPoolLength(instruction_bits)); + return Instruction::kInstrSize; + } else if (instruction_bits == kCodeAgeJumpInstruction) { + // The code age prologue has a constant immediatly following the jump + // instruction. + Instruction* target = Instruction::At(instr_ptr + Instruction::kInstrSize); + DecodeType2(instr); + SNPrintF(out_buffer_ + out_buffer_pos_, " (0x%08x)", + target->InstructionBits()); + return 2 * Instruction::kInstrSize; + } + switch (instr->TypeValue()) { + case 0: + case 1: { + DecodeType01(instr); + break; + } + case 2: { + DecodeType2(instr); + break; + } + case 3: { + DecodeType3(instr); + break; + } + case 4: { + DecodeType4(instr); + break; + } + case 5: { + DecodeType5(instr); + break; + } + case 6: { + DecodeType6(instr); + break; + } + case 7: { + return DecodeType7(instr); + } + default: { + // The type field is 3-bits in the ARM encoding. + MOZ_CRASH(); + break; + } + } + return Instruction::kInstrSize; +} + +} // namespace disasm + +# undef STRING_STARTS_WITH +# undef VERIFY + +//------------------------------------------------------------------------------ + +namespace disasm { + +const char* NameConverter::NameOfAddress(uint8_t* addr) const { + SNPrintF(tmp_buffer_, "%p", addr); + return tmp_buffer_.start(); +} + +const char* NameConverter::NameOfConstant(uint8_t* addr) const { + return NameOfAddress(addr); +} + +const char* NameConverter::NameOfCPURegister(int reg) const { + return disasm::Registers::Name(reg); +} + +const char* NameConverter::NameOfByteCPURegister(int reg) const { + MOZ_CRASH(); // ARM does not have the concept of a byte register + return "nobytereg"; +} + +const char* NameConverter::NameOfXMMRegister(int reg) const { + MOZ_CRASH(); // ARM does not have any XMM registers + return "noxmmreg"; +} + +const char* NameConverter::NameInCode(uint8_t* addr) const { + // The default name converter is called for unknown code. So we will not try + // to access any memory. + return ""; +} + +//------------------------------------------------------------------------------ + +Disassembler::Disassembler(const NameConverter& converter) + : converter_(converter) {} + +Disassembler::~Disassembler() {} + +int Disassembler::InstructionDecode(V8Vector<char> buffer, + uint8_t* instruction) { + Decoder d(converter_, buffer); + return d.InstructionDecode(instruction); +} + +int Disassembler::ConstantPoolSizeAt(uint8_t* instruction) { + return Decoder::ConstantPoolSizeAt(instruction); +} + +void Disassembler::Disassemble(FILE* f, uint8_t* begin, uint8_t* end) { + NameConverter converter; + Disassembler d(converter); + for (uint8_t* pc = begin; pc < end;) { + EmbeddedVector<char, ReasonableBufferSize> buffer; + buffer[0] = '\0'; + uint8_t* prev_pc = pc; + pc += d.InstructionDecode(buffer, pc); + fprintf(f, "%p %08x %s\n", prev_pc, + *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); + } +} + +} // namespace disasm +} // namespace jit +} // namespace js + +#endif // JS_DISASM_ARM diff --git a/js/src/jit/arm/disasm/Disasm-arm.h b/js/src/jit/arm/disasm/Disasm-arm.h new file mode 100644 index 0000000000..8a0dd97c32 --- /dev/null +++ b/js/src/jit/arm/disasm/Disasm-arm.h @@ -0,0 +1,141 @@ +/* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 2 -*- + * vim: set ts=8 sts=2 et sw=2 tw=80: + */ +// Copyright 2007-2008 the V8 project authors. All rights reserved. +// Use of this source code is governed by a BSD-style license that can be +// found in the LICENSE file. + +#ifndef jit_arm_disasm_Disasm_arm_h +#define jit_arm_disasm_Disasm_arm_h + +#ifdef JS_DISASM_ARM + +# include "mozilla/Assertions.h" +# include "mozilla/Types.h" + +# include <stdio.h> + +namespace js { +namespace jit { +namespace disasm { + +typedef unsigned char byte; + +// A reasonable (ie, safe) buffer size for the disassembly of a single +// instruction. +const int ReasonableBufferSize = 256; + +// Vector as used by the original code to allow for minimal modification. +// Functions exactly like a character array with helper methods. +template <typename T> +class V8Vector { + public: + V8Vector() : start_(nullptr), length_(0) {} + V8Vector(T* data, int length) : start_(data), length_(length) { + MOZ_ASSERT(length == 0 || (length > 0 && data != nullptr)); + } + + // Returns the length of the vector. + int length() const { return length_; } + + // Returns the pointer to the start of the data in the vector. + T* start() const { return start_; } + + // Access individual vector elements - checks bounds in debug mode. + T& operator[](int index) const { + MOZ_ASSERT(0 <= index && index < length_); + return start_[index]; + } + + V8Vector<T> operator+(int offset) const { + MOZ_ASSERT(offset < length_); + return V8Vector<T>(start_ + offset, length_ - offset); + } + + private: + T* start_; + int length_; +}; + +template <typename T, int kSize> +class EmbeddedVector : public V8Vector<T> { + public: + EmbeddedVector() : V8Vector<T>(buffer_, kSize) {} + + explicit EmbeddedVector(T initial_value) : V8Vector<T>(buffer_, kSize) { + for (int i = 0; i < kSize; ++i) { + buffer_[i] = initial_value; + } + } + + // When copying, make underlying Vector to reference our buffer. + EmbeddedVector(const EmbeddedVector& rhs) : V8Vector<T>(rhs) { + MemCopy(buffer_, rhs.buffer_, sizeof(T) * kSize); + this->set_start(buffer_); + } + + EmbeddedVector& operator=(const EmbeddedVector& rhs) { + if (this == &rhs) return *this; + V8Vector<T>::operator=(rhs); + MemCopy(buffer_, rhs.buffer_, sizeof(T) * kSize); + this->set_start(buffer_); + return *this; + } + + private: + T buffer_[kSize]; +}; + +// Interface and default implementation for converting addresses and +// register-numbers to text. The default implementation is machine +// specific. +class NameConverter { + public: + virtual ~NameConverter() {} + virtual const char* NameOfCPURegister(int reg) const; + virtual const char* NameOfByteCPURegister(int reg) const; + virtual const char* NameOfXMMRegister(int reg) const; + virtual const char* NameOfAddress(byte* addr) const; + virtual const char* NameOfConstant(byte* addr) const; + virtual const char* NameInCode(byte* addr) const; + + protected: + EmbeddedVector<char, 128> tmp_buffer_; +}; + +// A generic Disassembler interface +class Disassembler { + public: + // Caller deallocates converter. + explicit Disassembler(const NameConverter& converter); + + virtual ~Disassembler(); + + // Writes one disassembled instruction into 'buffer' (0-terminated). + // Returns the length of the disassembled machine instruction in bytes. + int InstructionDecode(V8Vector<char> buffer, uint8_t* instruction); + + // Returns -1 if instruction does not mark the beginning of a constant pool, + // or the number of entries in the constant pool beginning here. + int ConstantPoolSizeAt(byte* instruction); + + // Write disassembly into specified file 'f' using specified NameConverter + // (see constructor). + static void Disassemble(FILE* f, uint8_t* begin, uint8_t* end); + + private: + const NameConverter& converter_; + + // Disallow implicit constructors. + Disassembler() = delete; + Disassembler(const Disassembler&) = delete; + void operator=(const Disassembler&) = delete; +}; + +} // namespace disasm +} // namespace jit +} // namespace js + +#endif // JS_DISASM_ARM + +#endif // jit_arm_disasm_Disasm_arm_h |