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authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-07 18:49:59 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-07 18:49:59 +0000
commit01997497f915e8f79871f3f2acb55ac465051d24 (patch)
tree1ce1afd7246e1014199e15cbf854bf7924458e5d /debian/patches/features/arm64/arm64-dts-rockchip-Enable-the-USB-2.0-ports-on-ODROI.patch
parentAdding upstream version 6.1.76. (diff)
downloadlinux-01997497f915e8f79871f3f2acb55ac465051d24.tar.xz
linux-01997497f915e8f79871f3f2acb55ac465051d24.zip
Adding debian version 6.1.76-1.debian/6.1.76-1
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'debian/patches/features/arm64/arm64-dts-rockchip-Enable-the-USB-2.0-ports-on-ODROI.patch')
-rw-r--r--debian/patches/features/arm64/arm64-dts-rockchip-Enable-the-USB-2.0-ports-on-ODROI.patch108
1 files changed, 108 insertions, 0 deletions
diff --git a/debian/patches/features/arm64/arm64-dts-rockchip-Enable-the-USB-2.0-ports-on-ODROI.patch b/debian/patches/features/arm64/arm64-dts-rockchip-Enable-the-USB-2.0-ports-on-ODROI.patch
new file mode 100644
index 000000000..c27944417
--- /dev/null
+++ b/debian/patches/features/arm64/arm64-dts-rockchip-Enable-the-USB-2.0-ports-on-ODROI.patch
@@ -0,0 +1,108 @@
+From: Aurelien Jarno <aurelien@aurel32.net>
+Date: Fri, 30 Sep 2022 07:12:42 +0200
+Subject: [09/13] arm64: dts: rockchip: Enable the USB 2.0 ports on ODROID-M1
+Origin: https://git.kernel.org/linus/4685d7b68aaac199ab0d950d2047405bf551f964
+
+The Rockchip RK3568 has two USB OHCI/EHCI controllers connected to a PHY
+providing one host-only port and one OTG port. On the ODROID-M1, they
+are both used in host mode. The USB ports are powered by a DC/DC
+converter providing 5V and named VCC5V0_SYS on the schematics, followed
+by a power switch.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Tested-by: Dan Johansen <strit@manjaro.org>
+Link: https://lore.kernel.org/r/20220930051246.391614-10-aurelien@aurel32.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3568-odroid-m1.dts | 61 +++++++++++++++++++
+ 1 file changed, 61 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+index e4b7699d3eea..2e4cc20bd676 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+@@ -105,6 +105,28 @@ vcc3v3_sys: vcc3v3-sys-regulator {
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
++
++ vcc5v0_sys: vcc5v0-sys-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_sys";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&dc_12v>;
++ };
++
++ vcc5v0_usb_host: vcc5v0-usb-host-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_usb_host";
++ enable-active-high;
++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&vcc5v0_usb_host_en_pin>;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc5v0_sys>;
++ };
+ };
+
+ &cpu0 {
+@@ -463,6 +485,15 @@ hp_det_pin: hp-det-pin {
+ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
++
++ usb {
++ vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin {
++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ vcc5v0_usb_otg_en_pin: vcc5v0-usb-otg-en-pin {
++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
+ };
+
+ &pmu_io_domains {
+@@ -561,6 +592,36 @@ &uart2 {
+ status = "okay";
+ };
+
++&usb_host0_ehci {
++ status = "okay";
++};
++
++&usb_host0_ohci {
++ status = "okay";
++};
++
++&usb_host1_ehci {
++ status = "okay";
++};
++
++&usb_host1_ohci {
++ status = "okay";
++};
++
++&usb2phy1 {
++ status = "okay";
++};
++
++&usb2phy1_host {
++ phy-supply = <&vcc5v0_usb_host>;
++ status = "okay";
++};
++
++&usb2phy1_otg {
++ phy-supply = <&vcc5v0_usb_host>;
++ status = "okay";
++};
++
+ &vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+--
+2.35.1
+