diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts new file mode 100644 index 000000000..470ff8e31 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 Avnet Embedded GmbH + */ + +/dts-v1/; + +#include "imx8mp-msc-sm2s-14N0600E.dtsi" +#include <dt-bindings/clock/imx8mp-clock.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "MSC SM2-MB-EP1 Carrier Board with SM2S-IMX8PLUS-QC6-14N0600E SoM"; + compatible = "avnet,sm2s-imx8mp-14N0600E-ep1", + "avnet,sm2s-imx8mp-14N0600E", "avnet,sm2s-imx8mp", + "fsl,imx8mp"; +}; + +&flexcan1 { + status = "okay"; +}; + +&flexcan2 { + status = "okay"; +}; + +&usdhc2 { + no-1-8-v; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_smarc_gpio>; + + pinctrl_smarc_gpio: smarcgpiosgrp { + fsl,pins = + <MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x19>, /* GPIO0 */ + <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x19>, /* GPIO1 */ + <MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19>, /* GPIO2 */ + <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x19>, /* GPIO3 */ + <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x19>, /* GPIO4 */ + <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x19>, /* GPIO5 */ + <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19>, /* GPIO6 */ + <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19>, /* GPIO7 */ + <MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x19>, /* GPIO8 */ + <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19>, /* GPIO9 */ + <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19>, /* GPIO10 */ + <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x19>, /* GPIO11 */ + <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19>, /* GPIO12 */ + <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19>; /* GPIO13 */ + }; +}; |