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diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts
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@@ -0,0 +1,1024 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * dts file for Xilinx ZynqMP ZCU102 RevA
+ *
+ * (C) Copyright 2015 - 2021, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include <dt-bindings/phy/phy.h>
+
+/ {
+ model = "ZynqMP ZCU102 RevA";
+ compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem3;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci1;
+ nvmem0 = &eeprom;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ spi0 = &qspi;
+ usb0 = &usb0;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ switch-19 {
+ label = "sw19";
+ gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_DOWN>;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ heartbeat-led {
+ label = "heartbeat";
+ gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ ina226-u76 {
+ compatible = "iio-hwmon";
+ io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
+ };
+ ina226-u77 {
+ compatible = "iio-hwmon";
+ io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
+ };
+ ina226-u78 {
+ compatible = "iio-hwmon";
+ io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
+ };
+ ina226-u87 {
+ compatible = "iio-hwmon";
+ io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
+ };
+ ina226-u85 {
+ compatible = "iio-hwmon";
+ io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
+ };
+ ina226-u86 {
+ compatible = "iio-hwmon";
+ io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
+ };
+ ina226-u93 {
+ compatible = "iio-hwmon";
+ io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
+ };
+ ina226-u88 {
+ compatible = "iio-hwmon";
+ io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
+ };
+ ina226-u15 {
+ compatible = "iio-hwmon";
+ io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
+ };
+ ina226-u92 {
+ compatible = "iio-hwmon";
+ io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
+ };
+ ina226-u79 {
+ compatible = "iio-hwmon";
+ io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
+ };
+ ina226-u81 {
+ compatible = "iio-hwmon";
+ io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
+ };
+ ina226-u80 {
+ compatible = "iio-hwmon";
+ io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
+ };
+ ina226-u84 {
+ compatible = "iio-hwmon";
+ io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
+ };
+ ina226-u16 {
+ compatible = "iio-hwmon";
+ io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
+ };
+ ina226-u65 {
+ compatible = "iio-hwmon";
+ io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
+ };
+ ina226-u74 {
+ compatible = "iio-hwmon";
+ io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
+ };
+ ina226-u75 {
+ compatible = "iio-hwmon";
+ io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
+ };
+
+ /* 48MHz reference crystal */
+ ref48: ref48M {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ refhdmi: refhdmi {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <114285000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can1_default>;
+};
+
+&dcc {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gem3 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gem3_default>;
+ phy0: ethernet-phy@21 {
+ reg = <21>;
+ ti,rx-internal-delay = <0x8>;
+ ti,tx-internal-delay = <0xa>;
+ ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
+ /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
+ };
+};
+
+&gpio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_default>;
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ pinctrl-1 = <&pinctrl_i2c0_gpio>;
+ scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
+
+ tca6416_u97: gpio@20 {
+ compatible = "ti,tca6416";
+ reg = <0x20>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
+ "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
+ "", "", "", "", "", "", "", "", "";
+ gtr-sel0-hog {
+ gpio-hog;
+ gpios = <0 0>;
+ output-low; /* PCIE = 0, DP = 1 */
+ line-name = "sel0";
+ };
+ gtr-sel1-hog {
+ gpio-hog;
+ gpios = <1 0>;
+ output-high; /* PCIE = 0, DP = 1 */
+ line-name = "sel1";
+ };
+ gtr-sel2-hog {
+ gpio-hog;
+ gpios = <2 0>;
+ output-high; /* PCIE = 0, USB0 = 1 */
+ line-name = "sel2";
+ };
+ gtr-sel3-hog {
+ gpio-hog;
+ gpios = <3 0>;
+ output-high; /* PCIE = 0, SATA = 1 */
+ line-name = "sel3";
+ };
+ };
+
+ tca6416_u61: gpio@21 {
+ compatible = "ti,tca6416";
+ reg = <0x21>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "VCCPSPLL_EN", "MGTRAVCC_EN", "MGTRAVTT_EN", "VCCPSDDRPLL_EN", "MIO26_PMU_INPUT_LS",
+ "PL_PMBUS_ALERT", "PS_PMBUS_ALERT", "MAXIM_PMBUS_ALERT", "PL_DDR4_VTERM_EN",
+ "PL_DDR4_VPP_2V5_EN", "PS_DIMM_VDDQ_TO_PSVCCO_ON", "PS_DIMM_SUSPEND_EN",
+ "PS_DDR4_VTERM_EN", "PS_DDR4_VPP_2V5_EN", "", "";
+ };
+
+ i2c-mux@75 { /* u60 */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* PS_PMBUS */
+ u76: ina226@40 { /* u76 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u76";
+ reg = <0x40>;
+ shunt-resistor = <5000>;
+ };
+ u77: ina226@41 { /* u77 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u77";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ u78: ina226@42 { /* u78 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u78";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ u87: ina226@43 { /* u87 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u87";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ u85: ina226@44 { /* u85 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u85";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ u86: ina226@45 { /* u86 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u86";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ u93: ina226@46 { /* u93 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u93";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ u88: ina226@47 { /* u88 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u88";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ u15: ina226@4a { /* u15 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u15";
+ reg = <0x4a>;
+ shunt-resistor = <5000>;
+ };
+ u92: ina226@4b { /* u92 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u92";
+ reg = <0x4b>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* PL_PMBUS */
+ u79: ina226@40 { /* u79 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u79";
+ reg = <0x40>;
+ shunt-resistor = <2000>;
+ };
+ u81: ina226@41 { /* u81 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u81";
+ reg = <0x41>;
+ shunt-resistor = <5000>;
+ };
+ u80: ina226@42 { /* u80 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u80";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ u84: ina226@43 { /* u84 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u84";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ u16: ina226@44 { /* u16 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u16";
+ reg = <0x44>;
+ shunt-resistor = <5000>;
+ };
+ u65: ina226@45 { /* u65 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u65";
+ reg = <0x45>;
+ shunt-resistor = <5000>;
+ };
+ u74: ina226@46 { /* u74 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u74";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ u75: ina226@47 { /* u75 */
+ compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u75";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* MAXIM_PMBUS - 00 */
+ max15301@a { /* u46 */
+ compatible = "maxim,max15301";
+ reg = <0xa>;
+ };
+ max15303@b { /* u4 */
+ compatible = "maxim,max15303";
+ reg = <0xb>;
+ };
+ max15303@10 { /* u13 */
+ compatible = "maxim,max15303";
+ reg = <0x10>;
+ };
+ max15301@13 { /* u47 */
+ compatible = "maxim,max15301";
+ reg = <0x13>;
+ };
+ max15303@14 { /* u7 */
+ compatible = "maxim,max15303";
+ reg = <0x14>;
+ };
+ max15303@15 { /* u6 */
+ compatible = "maxim,max15303";
+ reg = <0x15>;
+ };
+ max15303@16 { /* u10 */
+ compatible = "maxim,max15303";
+ reg = <0x16>;
+ };
+ max15303@17 { /* u9 */
+ compatible = "maxim,max15303";
+ reg = <0x17>;
+ };
+ max15301@18 { /* u63 */
+ compatible = "maxim,max15301";
+ reg = <0x18>;
+ };
+ max15303@1a { /* u49 */
+ compatible = "maxim,max15303";
+ reg = <0x1a>;
+ };
+ max15303@1d { /* u18 */
+ compatible = "maxim,max15303";
+ reg = <0x1d>;
+ };
+ max15303@20 { /* u8 */
+ compatible = "maxim,max15303";
+ status = "disabled"; /* unreachable */
+ reg = <0x20>;
+ };
+ max20751@72 { /* u95 */
+ compatible = "maxim,max20751";
+ reg = <0x72>;
+ };
+ max20751@73 { /* u96 */
+ compatible = "maxim,max20751";
+ reg = <0x73>;
+ };
+ };
+ /* Bus 3 is not connected */
+ };
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
+
+ /* PL i2c via PCA9306 - u45 */
+ i2c-mux@74 { /* u34 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /*
+ * IIC_EEPROM 1kB memory which uses 256B blocks
+ * where every block has different address.
+ * 0 - 256B address 0x54
+ * 256B - 512B address 0x55
+ * 512B - 768B address 0x56
+ * 768B - 1024B address 0x57
+ */
+ eeprom: eeprom@54 { /* u23 */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ si5341: clock-generator@36 { /* SI5341 - u69 */
+ compatible = "silabs,si5341";
+ reg = <0x36>;
+ #clock-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&ref48>;
+ clock-names = "xtal";
+ clock-output-names = "si5341";
+
+ si5341_0: out@0 {
+ /* refclk0 for PS-GT, used for DP */
+ reg = <0>;
+ always-on;
+ };
+ si5341_2: out@2 {
+ /* refclk2 for PS-GT, used for USB3 */
+ reg = <2>;
+ always-on;
+ };
+ si5341_3: out@3 {
+ /* refclk3 for PS-GT, used for SATA */
+ reg = <3>;
+ always-on;
+ };
+ si5341_4: out@4 {
+ /* refclk4 for PS-GT, used for PCIE slot */
+ reg = <4>;
+ always-on;
+ };
+ si5341_5: out@5 {
+ /* refclk5 for PS-GT, used for PCIE */
+ reg = <5>;
+ always-on;
+ };
+ si5341_6: out@6 {
+ /* refclk6 PL CLK125 */
+ reg = <6>;
+ always-on;
+ };
+ si5341_7: out@7 {
+ /* refclk7 PL CLK74 */
+ reg = <7>;
+ always-on;
+ };
+ si5341_9: out@9 {
+ /* refclk9 used for PS_REF_CLK 33.3 MHz */
+ reg = <9>;
+ always-on;
+ };
+ };
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_1: clock-generator@5d { /* USER SI570 - u42 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>;
+ factory-fout = <300000000>;
+ clock-frequency = <300000000>;
+ clock-output-names = "si570_user";
+ };
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_2: clock-generator@5d { /* USER MGT SI570 - u56 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>;
+ temperature-stability = <50>; /* copy from zc702 */
+ factory-fout = <156250000>;
+ clock-frequency = <148500000>;
+ clock-output-names = "si570_mgt";
+ };
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SI5328 - u20 */
+ };
+ /* 5 - 7 unconnected */
+ };
+
+ i2c-mux@75 {
+ compatible = "nxp,pca9548"; /* u135 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x75>;
+
+ i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* HPC0_IIC */
+ };
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* HPC1_IIC */
+ };
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ /* SYSMON */
+ };
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ /* DDR4 SODIMM */
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* SEP 3 */
+ };
+ i2c@5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ /* SEP 2 */
+ };
+ i2c@6 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ /* SEP 1 */
+ };
+ i2c@7 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <7>;
+ /* SEP 0 */
+ };
+ };
+};
+
+&pinctrl0 {
+ status = "okay";
+ pinctrl_i2c0_default: i2c0-default {
+ mux {
+ groups = "i2c0_3_grp";
+ function = "i2c0";
+ };
+
+ conf {
+ groups = "i2c0_3_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c0_gpio: i2c0-gpio {
+ mux {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_14_grp", "gpio0_15_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_default: i2c1-default {
+ mux {
+ groups = "i2c1_4_grp";
+ function = "i2c1";
+ };
+
+ conf {
+ groups = "i2c1_4_grp";
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio {
+ mux {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ function = "gpio0";
+ };
+
+ conf {
+ groups = "gpio0_16_grp", "gpio0_17_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_uart0_default: uart0-default {
+ mux {
+ groups = "uart0_4_grp";
+ function = "uart0";
+ };
+
+ conf {
+ groups = "uart0_4_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO18";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO19";
+ bias-disable;
+ };
+ };
+
+ pinctrl_uart1_default: uart1-default {
+ mux {
+ groups = "uart1_5_grp";
+ function = "uart1";
+ };
+
+ conf {
+ groups = "uart1_5_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO21";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO20";
+ bias-disable;
+ };
+ };
+
+ pinctrl_usb0_default: usb0-default {
+ mux {
+ groups = "usb0_0_grp";
+ function = "usb0";
+ };
+
+ conf {
+ groups = "usb0_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO52", "MIO53", "MIO55";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
+ "MIO60", "MIO61", "MIO62", "MIO63";
+ bias-disable;
+ };
+ };
+
+ pinctrl_gem3_default: gem3-default {
+ mux {
+ function = "ethernet3";
+ groups = "ethernet3_0_grp";
+ };
+
+ conf {
+ groups = "ethernet3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
+ "MIO75";
+ bias-high-impedance;
+ low-power-disable;
+ };
+
+ conf-tx {
+ pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
+ "MIO69";
+ bias-disable;
+ low-power-enable;
+ };
+
+ mux-mdio {
+ function = "mdio3";
+ groups = "mdio3_0_grp";
+ };
+
+ conf-mdio {
+ groups = "mdio3_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_can1_default: can1-default {
+ mux {
+ function = "can1";
+ groups = "can1_6_grp";
+ };
+
+ conf {
+ groups = "can1_6_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-rx {
+ pins = "MIO25";
+ bias-high-impedance;
+ };
+
+ conf-tx {
+ pins = "MIO24";
+ bias-disable;
+ };
+ };
+
+ pinctrl_sdhci1_default: sdhci1-default {
+ mux {
+ groups = "sdio1_0_grp";
+ function = "sdio1";
+ };
+
+ conf {
+ groups = "sdio1_0_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ bias-disable;
+ };
+
+ mux-cd {
+ groups = "sdio1_cd_0_grp";
+ function = "sdio1_cd";
+ };
+
+ conf-cd {
+ groups = "sdio1_cd_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-wp {
+ groups = "sdio1_wp_0_grp";
+ function = "sdio1_wp";
+ };
+
+ conf-wp {
+ groups = "sdio1_wp_0_grp";
+ bias-high-impedance;
+ bias-pull-up;
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+ };
+
+ pinctrl_gpio_default: gpio-default {
+ mux-sw {
+ function = "gpio0";
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ };
+
+ conf-sw {
+ groups = "gpio0_22_grp", "gpio0_23_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ mux-msp {
+ function = "gpio0";
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ };
+
+ conf-msp {
+ groups = "gpio0_13_grp", "gpio0_38_grp";
+ slew-rate = <SLEW_RATE_SLOW>;
+ power-source = <IO_STANDARD_LVCMOS18>;
+ };
+
+ conf-pull-up {
+ pins = "MIO22", "MIO23";
+ bias-pull-up;
+ };
+
+ conf-pull-none {
+ pins = "MIO13", "MIO38";
+ bias-disable;
+ };
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+&psgtr {
+ status = "okay";
+ /* pcie, sata, usb3, dp */
+ clocks = <&si5341 0 5>, <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
+ clock-names = "ref0", "ref1", "ref2", "ref3";
+};
+
+&qspi {
+ status = "okay";
+ flash@0 {
+ compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
+ spi-max-frequency = <108000000>; /* Based on DC1 spec */
+ };
+};
+
+&rtc {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+ /* SATA OOB timing settings */
+ ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
+ ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
+ ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
+ ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
+ phy-names = "sata-phy";
+ phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
+};
+
+/* SD1 with level shifter */
+&sdhci1 {
+ status = "okay";
+ /*
+ * 1.0 revision has level shifter and this property should be
+ * removed for supporting UHS mode
+ */
+ no-1-8-v;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci1_default>;
+ xlnx,mio-bank = <1>;
+};
+
+&uart0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_default>;
+};
+
+/* ULPI SMSC USB3320 */
+&usb0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0_default>;
+ phy-names = "usb3-phy";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ snps,usb3_lpm_capable;
+ maximum-speed = "super-speed";
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&zynqmp_dpdma {
+ status = "okay";
+};
+
+&zynqmp_dpsub {
+ status = "okay";
+ phy-names = "dp-phy0";
+ phys = <&psgtr 1 PHY_TYPE_DP 0 3>;
+};
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-29 04:07:31 +0000