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-rw-r--r--arch/sh/include/cpu-sh3/cpu/adc.h29
-rw-r--r--arch/sh/include/cpu-sh3/cpu/cache.h40
-rw-r--r--arch/sh/include/cpu-sh3/cpu/dac.h42
-rw-r--r--arch/sh/include/cpu-sh3/cpu/dma-register.h38
-rw-r--r--arch/sh/include/cpu-sh3/cpu/dma.h19
-rw-r--r--arch/sh/include/cpu-sh3/cpu/freq.h24
-rw-r--r--arch/sh/include/cpu-sh3/cpu/gpio.h78
-rw-r--r--arch/sh/include/cpu-sh3/cpu/mmu_context.h42
-rw-r--r--arch/sh/include/cpu-sh3/cpu/serial.h11
-rw-r--r--arch/sh/include/cpu-sh3/cpu/sh7720.h175
-rw-r--r--arch/sh/include/cpu-sh3/cpu/watchdog.h22
11 files changed, 520 insertions, 0 deletions
diff --git a/arch/sh/include/cpu-sh3/cpu/adc.h b/arch/sh/include/cpu-sh3/cpu/adc.h
new file mode 100644
index 000000000..2ee206c9b
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/adc.h
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_CPU_SH3_ADC_H
+#define __ASM_CPU_SH3_ADC_H
+
+/*
+ * Copyright (C) 2004 Andriy Skulysh
+ */
+
+
+#define ADDRAH 0xa4000080
+#define ADDRAL 0xa4000082
+#define ADDRBH 0xa4000084
+#define ADDRBL 0xa4000086
+#define ADDRCH 0xa4000088
+#define ADDRCL 0xa400008a
+#define ADDRDH 0xa400008c
+#define ADDRDL 0xa400008e
+#define ADCSR 0xa4000090
+
+#define ADCSR_ADF 0x80
+#define ADCSR_ADIE 0x40
+#define ADCSR_ADST 0x20
+#define ADCSR_MULTI 0x10
+#define ADCSR_CKS 0x08
+#define ADCSR_CH_MASK 0x07
+
+#define ADCR 0xa4000092
+
+#endif /* __ASM_CPU_SH3_ADC_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/cache.h b/arch/sh/include/cpu-sh3/cpu/cache.h
new file mode 100644
index 000000000..f57124826
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/cache.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * include/asm-sh/cpu-sh3/cache.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ */
+#ifndef __ASM_CPU_SH3_CACHE_H
+#define __ASM_CPU_SH3_CACHE_H
+
+#define L1_CACHE_SHIFT 4
+
+#define SH_CACHE_VALID 1
+#define SH_CACHE_UPDATED 2
+#define SH_CACHE_COMBINED 4
+#define SH_CACHE_ASSOC 8
+
+#define SH_CCR 0xffffffec /* Address of Cache Control Register */
+
+#define CCR_CACHE_CE 0x01 /* Cache Enable */
+#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
+#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */
+#define CCR_CACHE_CF 0x08 /* Cache Flush */
+#define CCR_CACHE_ORA 0x20 /* RAM mode */
+
+#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
+#define CACHE_PHYSADDR_MASK 0x1ffffc00
+
+#define CCR_CACHE_ENABLE CCR_CACHE_CE
+#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define CCR3_REG 0xa40000b4
+#define CCR_CACHE_16KB 0x00010000
+#define CCR_CACHE_32KB 0x00020000
+#endif
+
+#endif /* __ASM_CPU_SH3_CACHE_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/dac.h b/arch/sh/include/cpu-sh3/cpu/dac.h
new file mode 100644
index 000000000..fd0233160
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/dac.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_CPU_SH3_DAC_H
+#define __ASM_CPU_SH3_DAC_H
+
+/*
+ * Copyright (C) 2003 Andriy Skulysh
+ */
+
+
+#define DADR0 0xa40000a0
+#define DADR1 0xa40000a2
+#define DACR 0xa40000a4
+#define DACR_DAOE1 0x80
+#define DACR_DAOE0 0x40
+#define DACR_DAE 0x20
+
+
+static __inline__ void sh_dac_enable(int channel)
+{
+ unsigned char v;
+ v = __raw_readb(DACR);
+ if(channel) v |= DACR_DAOE1;
+ else v |= DACR_DAOE0;
+ __raw_writeb(v,DACR);
+}
+
+static __inline__ void sh_dac_disable(int channel)
+{
+ unsigned char v;
+ v = __raw_readb(DACR);
+ if(channel) v &= ~DACR_DAOE1;
+ else v &= ~DACR_DAOE0;
+ __raw_writeb(v,DACR);
+}
+
+static __inline__ void sh_dac_output(u8 value, int channel)
+{
+ if(channel) __raw_writeb(value,DADR1);
+ else __raw_writeb(value,DADR0);
+}
+
+#endif /* __ASM_CPU_SH3_DAC_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/dma-register.h b/arch/sh/include/cpu-sh3/cpu/dma-register.h
new file mode 100644
index 000000000..c0f921fb4
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/dma-register.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * SH3 CPU-specific DMA definitions, used by both DMA drivers
+ *
+ * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ */
+#ifndef CPU_DMA_REGISTER_H
+#define CPU_DMA_REGISTER_H
+
+#define CHCR_TS_LOW_MASK 0x18
+#define CHCR_TS_LOW_SHIFT 3
+#define CHCR_TS_HIGH_MASK 0
+#define CHCR_TS_HIGH_SHIFT 0
+
+#define DMAOR_INIT DMAOR_DME
+
+/*
+ * The SuperH DMAC supports a number of transmit sizes, we list them here,
+ * with their respective values as they appear in the CHCR registers.
+ */
+enum {
+ XMIT_SZ_8BIT,
+ XMIT_SZ_16BIT,
+ XMIT_SZ_32BIT,
+ XMIT_SZ_128BIT,
+};
+
+/* log2(size / 8) - used to calculate number of transfers */
+#define TS_SHIFT { \
+ [XMIT_SZ_8BIT] = 0, \
+ [XMIT_SZ_16BIT] = 1, \
+ [XMIT_SZ_32BIT] = 2, \
+ [XMIT_SZ_128BIT] = 4, \
+}
+
+#define TS_INDEX2VAL(i) (((i) & 3) << CHCR_TS_LOW_SHIFT)
+
+#endif
diff --git a/arch/sh/include/cpu-sh3/cpu/dma.h b/arch/sh/include/cpu-sh3/cpu/dma.h
new file mode 100644
index 000000000..cd139681a
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/dma.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_CPU_SH3_DMA_H
+#define __ASM_CPU_SH3_DMA_H
+
+#include <linux/sh_intc.h>
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7721) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7712)
+#define SH_DMAC_BASE0 0xa4010020
+#else /* SH7705/06/07/09 */
+#define SH_DMAC_BASE0 0xa4000020
+#endif
+
+#define DMTE0_IRQ evt2irq(0x800)
+#define DMTE4_IRQ evt2irq(0xb80)
+
+#endif /* __ASM_CPU_SH3_DMA_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/freq.h b/arch/sh/include/cpu-sh3/cpu/freq.h
new file mode 100644
index 000000000..7290f02b7
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/freq.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * include/asm-sh/cpu-sh3/freq.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ */
+#ifndef __ASM_CPU_SH3_FREQ_H
+#define __ASM_CPU_SH3_FREQ_H
+
+#ifdef CONFIG_CPU_SUBTYPE_SH7712
+#define FRQCR 0xA415FF80
+#else
+#define FRQCR 0xffffff80
+#endif
+
+#define MIN_DIVISOR_NR 0
+#define MAX_DIVISOR_NR 4
+
+#define FRQCR_CKOEN 0x0100
+#define FRQCR_PLLEN 0x0080
+#define FRQCR_PSTBY 0x0040
+
+#endif /* __ASM_CPU_SH3_FREQ_H */
+
diff --git a/arch/sh/include/cpu-sh3/cpu/gpio.h b/arch/sh/include/cpu-sh3/cpu/gpio.h
new file mode 100644
index 000000000..aeb0588ac
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/gpio.h
@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * include/asm-sh/cpu-sh3/gpio.h
+ *
+ * Copyright (C) 2007 Markus Brunner, Mark Jonas
+ *
+ * Addresses for the Pin Function Controller
+ */
+#ifndef _CPU_SH3_GPIO_H
+#define _CPU_SH3_GPIO_H
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7721)
+
+/* Control registers */
+#define PORT_PACR 0xA4050100UL
+#define PORT_PBCR 0xA4050102UL
+#define PORT_PCCR 0xA4050104UL
+#define PORT_PDCR 0xA4050106UL
+#define PORT_PECR 0xA4050108UL
+#define PORT_PFCR 0xA405010AUL
+#define PORT_PGCR 0xA405010CUL
+#define PORT_PHCR 0xA405010EUL
+#define PORT_PJCR 0xA4050110UL
+#define PORT_PKCR 0xA4050112UL
+#define PORT_PLCR 0xA4050114UL
+#define PORT_PMCR 0xA4050116UL
+#define PORT_PPCR 0xA4050118UL
+#define PORT_PRCR 0xA405011AUL
+#define PORT_PSCR 0xA405011CUL
+#define PORT_PTCR 0xA405011EUL
+#define PORT_PUCR 0xA4050120UL
+#define PORT_PVCR 0xA4050122UL
+
+/* Data registers */
+#define PORT_PADR 0xA4050140UL
+/* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */
+#define PORT_PBDR 0xA4050142UL
+#define PORT_PCDR 0xA4050144UL
+#define PORT_PDDR 0xA4050146UL
+#define PORT_PEDR 0xA4050148UL
+#define PORT_PFDR 0xA405014AUL
+#define PORT_PGDR 0xA405014CUL
+#define PORT_PHDR 0xA405014EUL
+#define PORT_PJDR 0xA4050150UL
+#define PORT_PKDR 0xA4050152UL
+#define PORT_PLDR 0xA4050154UL
+#define PORT_PMDR 0xA4050156UL
+#define PORT_PPDR 0xA4050158UL
+#define PORT_PRDR 0xA405015AUL
+#define PORT_PSDR 0xA405015CUL
+#define PORT_PTDR 0xA405015EUL
+#define PORT_PUDR 0xA4050160UL
+#define PORT_PVDR 0xA4050162UL
+
+/* Pin Select Registers */
+#define PORT_PSELA 0xA4050124UL
+#define PORT_PSELB 0xA4050126UL
+#define PORT_PSELC 0xA4050128UL
+#define PORT_PSELD 0xA405012AUL
+
+#elif defined(CONFIG_CPU_SUBTYPE_SH7709)
+
+/* Control registers */
+#define PORT_PACR 0xa4000100UL
+#define PORT_PBCR 0xa4000102UL
+#define PORT_PCCR 0xa4000104UL
+#define PORT_PFCR 0xa400010aUL
+
+/* Data registers */
+#define PORT_PADR 0xa4000120UL
+#define PORT_PBDR 0xa4000122UL
+#define PORT_PCDR 0xa4000124UL
+#define PORT_PFDR 0xa400012aUL
+
+#endif
+
+#endif
diff --git a/arch/sh/include/cpu-sh3/cpu/mmu_context.h b/arch/sh/include/cpu-sh3/cpu/mmu_context.h
new file mode 100644
index 000000000..ead9a6f72
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/mmu_context.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * include/asm-sh/cpu-sh3/mmu_context.h
+ *
+ * Copyright (C) 1999 Niibe Yutaka
+ */
+#ifndef __ASM_CPU_SH3_MMU_CONTEXT_H
+#define __ASM_CPU_SH3_MMU_CONTEXT_H
+
+#define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */
+#define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */
+#define MMU_TTB 0xFFFFFFF8 /* Translation table base register */
+#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */
+
+#define MMUCR 0xFFFFFFE0 /* MMU Control Register */
+#define MMUCR_TI (1 << 2) /* TLB flush bit */
+
+#define MMU_TLB_ADDRESS_ARRAY 0xF2000000
+#define MMU_PAGE_ASSOC_BIT 0x80
+
+#define MMU_NTLB_ENTRIES 128 /* for 7708 */
+#define MMU_NTLB_WAYS 4
+#define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */
+
+#define TRA 0xffffffd0
+#define EXPEVT 0xffffffd4
+
+#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7706) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7707) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7709) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7710) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7712) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7720) || \
+ defined(CONFIG_CPU_SUBTYPE_SH7721)
+#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
+#else
+#define INTEVT 0xffffffd8
+#endif
+
+#endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */
+
diff --git a/arch/sh/include/cpu-sh3/cpu/serial.h b/arch/sh/include/cpu-sh3/cpu/serial.h
new file mode 100644
index 000000000..7b2ce6e30
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/serial.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __CPU_SH3_SERIAL_H
+#define __CPU_SH3_SERIAL_H
+
+#include <linux/serial_sci.h>
+
+extern struct plat_sci_port_ops sh770x_sci_port_ops;
+extern struct plat_sci_port_ops sh7710_sci_port_ops;
+extern struct plat_sci_port_ops sh7720_sci_port_ops;
+
+#endif /* __CPU_SH3_SERIAL_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/sh7720.h b/arch/sh/include/cpu-sh3/cpu/sh7720.h
new file mode 100644
index 000000000..449790c9e
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/sh7720.h
@@ -0,0 +1,175 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __ASM_SH7720_H__
+#define __ASM_SH7720_H__
+
+enum {
+ /* PTA */
+ GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
+ GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
+
+ /* PTB */
+ GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
+ GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
+
+ /* PTC */
+ GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
+ GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
+
+ /* PTD */
+ GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
+ GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
+
+ /* PTE */
+ GPIO_PTE6, GPIO_PTE5, GPIO_PTE4, GPIO_PTE3,
+ GPIO_PTE2, GPIO_PTE1, GPIO_PTE0,
+
+ /* PTF */
+ GPIO_PTF6, GPIO_PTF5, GPIO_PTF4, GPIO_PTF3,
+ GPIO_PTF2, GPIO_PTF1, GPIO_PTF0, GPIO_PTG6,
+
+ /* PTG */
+ GPIO_PTG5, GPIO_PTG4, GPIO_PTG3, GPIO_PTG2,
+ GPIO_PTG1, GPIO_PTG0,
+
+ /* PTH */
+ GPIO_PTH6, GPIO_PTH5, GPIO_PTH4, GPIO_PTH3,
+ GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
+
+ /* PTJ */
+ GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ4, GPIO_PTJ3,
+ GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0,
+
+ /* PTK */
+ GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
+
+ /* PTL */
+ GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4, GPIO_PTL3,
+
+ /* PTM */
+ GPIO_PTM7, GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
+ GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
+
+ /* PTP */
+ GPIO_PTP4, GPIO_PTP3, GPIO_PTP2, GPIO_PTP1, GPIO_PTP0,
+
+ /* PTR */
+ GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
+ GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
+
+ /* PTS */
+ GPIO_PTS4, GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
+
+ /* PTT */
+ GPIO_PTT4, GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
+
+ /* PTU */
+ GPIO_PTU4, GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
+
+ /* PTV */
+ GPIO_PTV4, GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
+
+ /* BSC */
+ GPIO_FN_D31, GPIO_FN_D30, GPIO_FN_D29, GPIO_FN_D28,
+ GPIO_FN_D27, GPIO_FN_D26, GPIO_FN_D25, GPIO_FN_D24,
+ GPIO_FN_D23, GPIO_FN_D22, GPIO_FN_D21, GPIO_FN_D20,
+ GPIO_FN_D19, GPIO_FN_D18, GPIO_FN_D17, GPIO_FN_D16,
+ GPIO_FN_IOIS16, GPIO_FN_RAS, GPIO_FN_CAS, GPIO_FN_CKE,
+ GPIO_FN_CS5B_CE1A, GPIO_FN_CS6B_CE1B,
+ GPIO_FN_A25, GPIO_FN_A24, GPIO_FN_A23, GPIO_FN_A22,
+ GPIO_FN_A21, GPIO_FN_A20, GPIO_FN_A19, GPIO_FN_A0,
+ GPIO_FN_REFOUT, GPIO_FN_IRQOUT,
+
+ /* LCDC */
+ GPIO_FN_LCD_DATA15, GPIO_FN_LCD_DATA14,
+ GPIO_FN_LCD_DATA13, GPIO_FN_LCD_DATA12,
+ GPIO_FN_LCD_DATA11, GPIO_FN_LCD_DATA10,
+ GPIO_FN_LCD_DATA9, GPIO_FN_LCD_DATA8,
+ GPIO_FN_LCD_DATA7, GPIO_FN_LCD_DATA6,
+ GPIO_FN_LCD_DATA5, GPIO_FN_LCD_DATA4,
+ GPIO_FN_LCD_DATA3, GPIO_FN_LCD_DATA2,
+ GPIO_FN_LCD_DATA1, GPIO_FN_LCD_DATA0,
+ GPIO_FN_LCD_M_DISP,
+ GPIO_FN_LCD_CL1, GPIO_FN_LCD_CL2,
+ GPIO_FN_LCD_DON, GPIO_FN_LCD_FLM,
+ GPIO_FN_LCD_VEPWC, GPIO_FN_LCD_VCPWC,
+
+ /* AFEIF */
+ GPIO_FN_AFE_RXIN, GPIO_FN_AFE_RDET,
+ GPIO_FN_AFE_FS, GPIO_FN_AFE_TXOUT,
+ GPIO_FN_AFE_SCLK, GPIO_FN_AFE_RLYCNT,
+ GPIO_FN_AFE_HC1,
+
+ /* IIC */
+ GPIO_FN_IIC_SCL, GPIO_FN_IIC_SDA,
+
+ /* DAC */
+ GPIO_FN_DA1, GPIO_FN_DA0,
+
+ /* ADC */
+ GPIO_FN_AN3, GPIO_FN_AN2, GPIO_FN_AN1, GPIO_FN_AN0, GPIO_FN_ADTRG,
+
+ /* USB */
+ GPIO_FN_USB1D_RCV, GPIO_FN_USB1D_TXSE0,
+ GPIO_FN_USB1D_TXDPLS, GPIO_FN_USB1D_DMNS,
+ GPIO_FN_USB1D_DPLS, GPIO_FN_USB1D_SPEED,
+ GPIO_FN_USB1D_TXENL, GPIO_FN_USB2_PWR_EN,
+ GPIO_FN_USB1_PWR_EN_USBF_UPLUP, GPIO_FN_USB1D_SUSPEND,
+
+ /* INTC */
+ GPIO_FN_IRQ5, GPIO_FN_IRQ4,
+ GPIO_FN_IRQ3_IRL3, GPIO_FN_IRQ2_IRL2,
+ GPIO_FN_IRQ1_IRL1, GPIO_FN_IRQ0_IRL0,
+
+ /* PCC */
+ GPIO_FN_PCC_REG, GPIO_FN_PCC_DRV,
+ GPIO_FN_PCC_BVD2, GPIO_FN_PCC_BVD1,
+ GPIO_FN_PCC_CD2, GPIO_FN_PCC_CD1,
+ GPIO_FN_PCC_RESET, GPIO_FN_PCC_RDY,
+ GPIO_FN_PCC_VS2, GPIO_FN_PCC_VS1,
+
+ /* HUDI */
+ GPIO_FN_AUDATA3, GPIO_FN_AUDATA2, GPIO_FN_AUDATA1, GPIO_FN_AUDATA0,
+ GPIO_FN_AUDCK, GPIO_FN_AUDSYNC, GPIO_FN_ASEBRKAK, GPIO_FN_TRST,
+ GPIO_FN_TMS, GPIO_FN_TDO, GPIO_FN_TDI, GPIO_FN_TCK,
+
+ /* DMAC */
+ GPIO_FN_DACK1, GPIO_FN_DREQ1, GPIO_FN_DACK0, GPIO_FN_DREQ0,
+ GPIO_FN_TEND1, GPIO_FN_TEND0,
+
+ /* SIOF0 */
+ GPIO_FN_SIOF0_SYNC, GPIO_FN_SIOF0_MCLK,
+ GPIO_FN_SIOF0_TXD, GPIO_FN_SIOF0_RXD,
+ GPIO_FN_SIOF0_SCK,
+
+ /* SIOF1 */
+ GPIO_FN_SIOF1_SYNC, GPIO_FN_SIOF1_MCLK,
+ GPIO_FN_SIOF1_TXD, GPIO_FN_SIOF1_RXD,
+ GPIO_FN_SIOF1_SCK,
+
+ /* SCIF0 */
+ GPIO_FN_SCIF0_TXD, GPIO_FN_SCIF0_RXD,
+ GPIO_FN_SCIF0_RTS, GPIO_FN_SCIF0_CTS, GPIO_FN_SCIF0_SCK,
+
+ /* SCIF1 */
+ GPIO_FN_SCIF1_TXD, GPIO_FN_SCIF1_RXD,
+ GPIO_FN_SCIF1_RTS, GPIO_FN_SCIF1_CTS, GPIO_FN_SCIF1_SCK,
+
+ /* TPU */
+ GPIO_FN_TPU_TO1, GPIO_FN_TPU_TO0,
+ GPIO_FN_TPU_TI3B, GPIO_FN_TPU_TI3A,
+ GPIO_FN_TPU_TI2B, GPIO_FN_TPU_TI2A,
+ GPIO_FN_TPU_TO3, GPIO_FN_TPU_TO2,
+
+ /* SIM */
+ GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST,
+
+ /* MMC */
+ GPIO_FN_MMC_DAT, GPIO_FN_MMC_CMD,
+ GPIO_FN_MMC_CLK, GPIO_FN_MMC_VDDON,
+ GPIO_FN_MMC_ODMOD,
+
+ /* SYSC */
+ GPIO_FN_STATUS0, GPIO_FN_STATUS1,
+};
+
+#endif /* __ASM_SH7720_H__ */
diff --git a/arch/sh/include/cpu-sh3/cpu/watchdog.h b/arch/sh/include/cpu-sh3/cpu/watchdog.h
new file mode 100644
index 000000000..9d7e9d986
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/watchdog.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * include/asm-sh/cpu-sh3/watchdog.h
+ *
+ * Copyright (C) 2002, 2003 Paul Mundt
+ */
+#ifndef __ASM_CPU_SH3_WATCHDOG_H
+#define __ASM_CPU_SH3_WATCHDOG_H
+
+/* Register definitions */
+#define WTCNT 0xffffff84
+#define WTCSR 0xffffff86
+
+/* Bit definitions */
+#define WTCSR_TME 0x80
+#define WTCSR_WT 0x40
+#define WTCSR_RSTS 0x20
+#define WTCSR_WOVF 0x10
+#define WTCSR_IOVF 0x08
+
+#endif /* __ASM_CPU_SH3_WATCHDOG_H */
+
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-16 10:28:22 +0000