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-rw-r--r--drivers/media/i2c/ccs/Kconfig11
-rw-r--r--drivers/media/i2c/ccs/Makefile6
-rw-r--r--drivers/media/i2c/ccs/ccs-core.c3766
-rw-r--r--drivers/media/i2c/ccs/ccs-data-defs.h221
-rw-r--r--drivers/media/i2c/ccs/ccs-data.c979
-rw-r--r--drivers/media/i2c/ccs/ccs-data.h230
-rw-r--r--drivers/media/i2c/ccs/ccs-limits.c243
-rw-r--r--drivers/media/i2c/ccs/ccs-limits.h263
-rw-r--r--drivers/media/i2c/ccs/ccs-quirk.c218
-rw-r--r--drivers/media/i2c/ccs/ccs-quirk.h79
-rw-r--r--drivers/media/i2c/ccs/ccs-reg-access.c416
-rw-r--r--drivers/media/i2c/ccs/ccs-reg-access.h42
-rw-r--r--drivers/media/i2c/ccs/ccs-regs.h958
-rw-r--r--drivers/media/i2c/ccs/ccs.h290
-rw-r--r--drivers/media/i2c/ccs/smiapp-reg-defs.h582
15 files changed, 8304 insertions, 0 deletions
diff --git a/drivers/media/i2c/ccs/Kconfig b/drivers/media/i2c/ccs/Kconfig
new file mode 100644
index 000000000..71671db3d
--- /dev/null
+++ b/drivers/media/i2c/ccs/Kconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config VIDEO_CCS
+ tristate "MIPI CCS/SMIA++/SMIA sensor support"
+ depends on I2C && VIDEO_DEV && HAVE_CLK
+ select MEDIA_CONTROLLER
+ select VIDEO_V4L2_SUBDEV_API
+ select VIDEO_CCS_PLL
+ select V4L2_FWNODE
+ help
+ This is a generic driver for MIPI CCS, SMIA++ and SMIA compliant
+ camera sensors.
diff --git a/drivers/media/i2c/ccs/Makefile b/drivers/media/i2c/ccs/Makefile
new file mode 100644
index 000000000..44601ba8c
--- /dev/null
+++ b/drivers/media/i2c/ccs/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+ccs-objs += ccs-core.o ccs-reg-access.o \
+ ccs-quirk.o ccs-limits.o ccs-data.o
+obj-$(CONFIG_VIDEO_CCS) += ccs.o
+
+ccflags-y += -I $(srctree)/drivers/media/i2c
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
new file mode 100644
index 000000000..5fdb922d2
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -0,0 +1,3766 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * drivers/media/i2c/ccs/ccs-core.c
+ *
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
+ *
+ * Copyright (C) 2020 Intel Corporation
+ * Copyright (C) 2010--2012 Nokia Corporation
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
+ *
+ * Based on smiapp driver by Vimarsh Zutshi
+ * Based on jt8ev1.c by Vimarsh Zutshi
+ * Based on smia-sensor.c by Tuukka Toivonen <tuukkat76@gmail.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/firmware.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/property.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <linux/smiapp.h>
+#include <linux/v4l2-mediabus.h>
+#include <media/v4l2-fwnode.h>
+#include <media/v4l2-device.h>
+#include <uapi/linux/ccs.h>
+
+#include "ccs.h"
+
+#define CCS_ALIGN_DIM(dim, flags) \
+ ((flags) & V4L2_SEL_FLAG_GE \
+ ? ALIGN((dim), 2) \
+ : (dim) & ~1)
+
+static struct ccs_limit_offset {
+ u16 lim;
+ u16 info;
+} ccs_limit_offsets[CCS_L_LAST + 1];
+
+/*
+ * ccs_module_idents - supported camera modules
+ */
+static const struct ccs_module_ident ccs_module_idents[] = {
+ CCS_IDENT_L(0x01, 0x022b, -1, "vs6555"),
+ CCS_IDENT_L(0x01, 0x022e, -1, "vw6558"),
+ CCS_IDENT_L(0x07, 0x7698, -1, "ovm7698"),
+ CCS_IDENT_L(0x0b, 0x4242, -1, "smiapp-003"),
+ CCS_IDENT_L(0x0c, 0x208a, -1, "tcm8330md"),
+ CCS_IDENT_LQ(0x0c, 0x2134, -1, "tcm8500md", &smiapp_tcm8500md_quirk),
+ CCS_IDENT_L(0x0c, 0x213e, -1, "et8en2"),
+ CCS_IDENT_L(0x0c, 0x2184, -1, "tcm8580md"),
+ CCS_IDENT_LQ(0x0c, 0x560f, -1, "jt8ew9", &smiapp_jt8ew9_quirk),
+ CCS_IDENT_LQ(0x10, 0x4141, -1, "jt8ev1", &smiapp_jt8ev1_quirk),
+ CCS_IDENT_LQ(0x10, 0x4241, -1, "imx125es", &smiapp_imx125es_quirk),
+};
+
+#define CCS_DEVICE_FLAG_IS_SMIA BIT(0)
+
+struct ccs_device {
+ unsigned char flags;
+};
+
+static const char * const ccs_regulators[] = { "vcore", "vio", "vana" };
+
+/*
+ *
+ * Dynamic Capability Identification
+ *
+ */
+
+static void ccs_assign_limit(void *ptr, unsigned int width, u32 val)
+{
+ switch (width) {
+ case sizeof(u8):
+ *(u8 *)ptr = val;
+ break;
+ case sizeof(u16):
+ *(u16 *)ptr = val;
+ break;
+ case sizeof(u32):
+ *(u32 *)ptr = val;
+ break;
+ }
+}
+
+static int ccs_limit_ptr(struct ccs_sensor *sensor, unsigned int limit,
+ unsigned int offset, void **__ptr)
+{
+ const struct ccs_limit *linfo;
+
+ if (WARN_ON(limit >= CCS_L_LAST))
+ return -EINVAL;
+
+ linfo = &ccs_limits[ccs_limit_offsets[limit].info];
+
+ if (WARN_ON(!sensor->ccs_limits) ||
+ WARN_ON(offset + ccs_reg_width(linfo->reg) >
+ ccs_limit_offsets[limit + 1].lim))
+ return -EINVAL;
+
+ *__ptr = sensor->ccs_limits + ccs_limit_offsets[limit].lim + offset;
+
+ return 0;
+}
+
+void ccs_replace_limit(struct ccs_sensor *sensor,
+ unsigned int limit, unsigned int offset, u32 val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ const struct ccs_limit *linfo;
+ void *ptr;
+ int ret;
+
+ ret = ccs_limit_ptr(sensor, limit, offset, &ptr);
+ if (ret)
+ return;
+
+ linfo = &ccs_limits[ccs_limit_offsets[limit].info];
+
+ dev_dbg(&client->dev, "quirk: 0x%8.8x \"%s\" %u = %u, 0x%x\n",
+ linfo->reg, linfo->name, offset, val, val);
+
+ ccs_assign_limit(ptr, ccs_reg_width(linfo->reg), val);
+}
+
+u32 ccs_get_limit(struct ccs_sensor *sensor, unsigned int limit,
+ unsigned int offset)
+{
+ void *ptr;
+ u32 val;
+ int ret;
+
+ ret = ccs_limit_ptr(sensor, limit, offset, &ptr);
+ if (ret)
+ return 0;
+
+ switch (ccs_reg_width(ccs_limits[ccs_limit_offsets[limit].info].reg)) {
+ case sizeof(u8):
+ val = *(u8 *)ptr;
+ break;
+ case sizeof(u16):
+ val = *(u16 *)ptr;
+ break;
+ case sizeof(u32):
+ val = *(u32 *)ptr;
+ break;
+ default:
+ WARN_ON(1);
+ return 0;
+ }
+
+ return ccs_reg_conv(sensor, ccs_limits[limit].reg, val);
+}
+
+static int ccs_read_all_limits(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ void *ptr, *alloc, *end;
+ unsigned int i, l;
+ int ret;
+
+ kfree(sensor->ccs_limits);
+ sensor->ccs_limits = NULL;
+
+ alloc = kzalloc(ccs_limit_offsets[CCS_L_LAST].lim, GFP_KERNEL);
+ if (!alloc)
+ return -ENOMEM;
+
+ end = alloc + ccs_limit_offsets[CCS_L_LAST].lim;
+
+ for (i = 0, l = 0, ptr = alloc; ccs_limits[i].size; i++) {
+ u32 reg = ccs_limits[i].reg;
+ unsigned int width = ccs_reg_width(reg);
+ unsigned int j;
+
+ if (l == CCS_L_LAST) {
+ dev_err(&client->dev,
+ "internal error --- end of limit array\n");
+ ret = -EINVAL;
+ goto out_err;
+ }
+
+ for (j = 0; j < ccs_limits[i].size / width;
+ j++, reg += width, ptr += width) {
+ u32 val;
+
+ ret = ccs_read_addr_noconv(sensor, reg, &val);
+ if (ret)
+ goto out_err;
+
+ if (ptr + width > end) {
+ dev_err(&client->dev,
+ "internal error --- no room for regs\n");
+ ret = -EINVAL;
+ goto out_err;
+ }
+
+ if (!val && j)
+ break;
+
+ ccs_assign_limit(ptr, width, val);
+
+ dev_dbg(&client->dev, "0x%8.8x \"%s\" = %u, 0x%x\n",
+ reg, ccs_limits[i].name, val, val);
+ }
+
+ if (ccs_limits[i].flags & CCS_L_FL_SAME_REG)
+ continue;
+
+ l++;
+ ptr = alloc + ccs_limit_offsets[l].lim;
+ }
+
+ if (l != CCS_L_LAST) {
+ dev_err(&client->dev,
+ "internal error --- insufficient limits\n");
+ ret = -EINVAL;
+ goto out_err;
+ }
+
+ sensor->ccs_limits = alloc;
+
+ if (CCS_LIM(sensor, SCALER_N_MIN) < 16)
+ ccs_replace_limit(sensor, CCS_L_SCALER_N_MIN, 0, 16);
+
+ return 0;
+
+out_err:
+ kfree(alloc);
+
+ return ret;
+}
+
+static int ccs_read_frame_fmt(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ u8 fmt_model_type, fmt_model_subtype, ncol_desc, nrow_desc;
+ unsigned int i;
+ int pixel_count = 0;
+ int line_count = 0;
+
+ fmt_model_type = CCS_LIM(sensor, FRAME_FORMAT_MODEL_TYPE);
+ fmt_model_subtype = CCS_LIM(sensor, FRAME_FORMAT_MODEL_SUBTYPE);
+
+ ncol_desc = (fmt_model_subtype
+ & CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK)
+ >> CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT;
+ nrow_desc = fmt_model_subtype
+ & CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_MASK;
+
+ dev_dbg(&client->dev, "format_model_type %s\n",
+ fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE
+ ? "2 byte" :
+ fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE
+ ? "4 byte" : "is simply bad");
+
+ dev_dbg(&client->dev, "%u column and %u row descriptors\n",
+ ncol_desc, nrow_desc);
+
+ for (i = 0; i < ncol_desc + nrow_desc; i++) {
+ u32 desc;
+ u32 pixelcode;
+ u32 pixels;
+ char *which;
+ char *what;
+
+ if (fmt_model_type == CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE) {
+ desc = CCS_LIM_AT(sensor, FRAME_FORMAT_DESCRIPTOR, i);
+
+ pixelcode =
+ (desc
+ & CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MASK)
+ >> CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_SHIFT;
+ pixels = desc & CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_MASK;
+ } else if (fmt_model_type
+ == CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE) {
+ desc = CCS_LIM_AT(sensor, FRAME_FORMAT_DESCRIPTOR_4, i);
+
+ pixelcode =
+ (desc
+ & CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MASK)
+ >> CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_SHIFT;
+ pixels = desc &
+ CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_MASK;
+ } else {
+ dev_dbg(&client->dev,
+ "invalid frame format model type %u\n",
+ fmt_model_type);
+ return -EINVAL;
+ }
+
+ if (i < ncol_desc)
+ which = "columns";
+ else
+ which = "rows";
+
+ switch (pixelcode) {
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED:
+ what = "embedded";
+ break;
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DUMMY_PIXEL:
+ what = "dummy";
+ break;
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_BLACK_PIXEL:
+ what = "black";
+ break;
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DARK_PIXEL:
+ what = "dark";
+ break;
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL:
+ what = "visible";
+ break;
+ default:
+ what = "invalid";
+ break;
+ }
+
+ dev_dbg(&client->dev,
+ "%s pixels: %u %s (pixelcode %u)\n",
+ what, pixels, which, pixelcode);
+
+ if (i < ncol_desc) {
+ if (pixelcode ==
+ CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL)
+ sensor->visible_pixel_start = pixel_count;
+ pixel_count += pixels;
+ continue;
+ }
+
+ /* Handle row descriptors */
+ switch (pixelcode) {
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED:
+ if (sensor->embedded_end)
+ break;
+ sensor->embedded_start = line_count;
+ sensor->embedded_end = line_count + pixels;
+ break;
+ case CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL:
+ sensor->image_start = line_count;
+ break;
+ }
+ line_count += pixels;
+ }
+
+ if (sensor->embedded_end > sensor->image_start) {
+ dev_dbg(&client->dev,
+ "adjusting image start line to %u (was %u)\n",
+ sensor->embedded_end, sensor->image_start);
+ sensor->image_start = sensor->embedded_end;
+ }
+
+ dev_dbg(&client->dev, "embedded data from lines %u to %u\n",
+ sensor->embedded_start, sensor->embedded_end);
+ dev_dbg(&client->dev, "image data starts at line %u\n",
+ sensor->image_start);
+
+ return 0;
+}
+
+static int ccs_pll_configure(struct ccs_sensor *sensor)
+{
+ struct ccs_pll *pll = &sensor->pll;
+ int rval;
+
+ rval = ccs_write(sensor, VT_PIX_CLK_DIV, pll->vt_bk.pix_clk_div);
+ if (rval < 0)
+ return rval;
+
+ rval = ccs_write(sensor, VT_SYS_CLK_DIV, pll->vt_bk.sys_clk_div);
+ if (rval < 0)
+ return rval;
+
+ rval = ccs_write(sensor, PRE_PLL_CLK_DIV, pll->vt_fr.pre_pll_clk_div);
+ if (rval < 0)
+ return rval;
+
+ rval = ccs_write(sensor, PLL_MULTIPLIER, pll->vt_fr.pll_multiplier);
+ if (rval < 0)
+ return rval;
+
+ if (!(CCS_LIM(sensor, PHY_CTRL_CAPABILITY) &
+ CCS_PHY_CTRL_CAPABILITY_AUTO_PHY_CTL)) {
+ /* Lane op clock ratio does not apply here. */
+ rval = ccs_write(sensor, REQUESTED_LINK_RATE,
+ DIV_ROUND_UP(pll->op_bk.sys_clk_freq_hz,
+ 1000000 / 256 / 256) *
+ (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+ sensor->pll.csi2.lanes : 1) <<
+ (pll->flags & CCS_PLL_FLAG_OP_SYS_DDR ?
+ 1 : 0));
+ if (rval < 0)
+ return rval;
+ }
+
+ if (sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
+ return 0;
+
+ rval = ccs_write(sensor, OP_PIX_CLK_DIV, pll->op_bk.pix_clk_div);
+ if (rval < 0)
+ return rval;
+
+ rval = ccs_write(sensor, OP_SYS_CLK_DIV, pll->op_bk.sys_clk_div);
+ if (rval < 0)
+ return rval;
+
+ if (!(pll->flags & CCS_PLL_FLAG_DUAL_PLL))
+ return 0;
+
+ rval = ccs_write(sensor, PLL_MODE, CCS_PLL_MODE_DUAL);
+ if (rval < 0)
+ return rval;
+
+ rval = ccs_write(sensor, OP_PRE_PLL_CLK_DIV,
+ pll->op_fr.pre_pll_clk_div);
+ if (rval < 0)
+ return rval;
+
+ return ccs_write(sensor, OP_PLL_MULTIPLIER, pll->op_fr.pll_multiplier);
+}
+
+static int ccs_pll_try(struct ccs_sensor *sensor, struct ccs_pll *pll)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ struct ccs_pll_limits lim = {
+ .vt_fr = {
+ .min_pre_pll_clk_div = CCS_LIM(sensor, MIN_PRE_PLL_CLK_DIV),
+ .max_pre_pll_clk_div = CCS_LIM(sensor, MAX_PRE_PLL_CLK_DIV),
+ .min_pll_ip_clk_freq_hz = CCS_LIM(sensor, MIN_PLL_IP_CLK_FREQ_MHZ),
+ .max_pll_ip_clk_freq_hz = CCS_LIM(sensor, MAX_PLL_IP_CLK_FREQ_MHZ),
+ .min_pll_multiplier = CCS_LIM(sensor, MIN_PLL_MULTIPLIER),
+ .max_pll_multiplier = CCS_LIM(sensor, MAX_PLL_MULTIPLIER),
+ .min_pll_op_clk_freq_hz = CCS_LIM(sensor, MIN_PLL_OP_CLK_FREQ_MHZ),
+ .max_pll_op_clk_freq_hz = CCS_LIM(sensor, MAX_PLL_OP_CLK_FREQ_MHZ),
+ },
+ .op_fr = {
+ .min_pre_pll_clk_div = CCS_LIM(sensor, MIN_OP_PRE_PLL_CLK_DIV),
+ .max_pre_pll_clk_div = CCS_LIM(sensor, MAX_OP_PRE_PLL_CLK_DIV),
+ .min_pll_ip_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PLL_IP_CLK_FREQ_MHZ),
+ .max_pll_ip_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PLL_IP_CLK_FREQ_MHZ),
+ .min_pll_multiplier = CCS_LIM(sensor, MIN_OP_PLL_MULTIPLIER),
+ .max_pll_multiplier = CCS_LIM(sensor, MAX_OP_PLL_MULTIPLIER),
+ .min_pll_op_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PLL_OP_CLK_FREQ_MHZ),
+ .max_pll_op_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PLL_OP_CLK_FREQ_MHZ),
+ },
+ .op_bk = {
+ .min_sys_clk_div = CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV),
+ .max_sys_clk_div = CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV),
+ .min_pix_clk_div = CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV),
+ .max_pix_clk_div = CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV),
+ .min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_OP_SYS_CLK_FREQ_MHZ),
+ .max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_OP_SYS_CLK_FREQ_MHZ),
+ .min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_OP_PIX_CLK_FREQ_MHZ),
+ .max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_OP_PIX_CLK_FREQ_MHZ),
+ },
+ .vt_bk = {
+ .min_sys_clk_div = CCS_LIM(sensor, MIN_VT_SYS_CLK_DIV),
+ .max_sys_clk_div = CCS_LIM(sensor, MAX_VT_SYS_CLK_DIV),
+ .min_pix_clk_div = CCS_LIM(sensor, MIN_VT_PIX_CLK_DIV),
+ .max_pix_clk_div = CCS_LIM(sensor, MAX_VT_PIX_CLK_DIV),
+ .min_sys_clk_freq_hz = CCS_LIM(sensor, MIN_VT_SYS_CLK_FREQ_MHZ),
+ .max_sys_clk_freq_hz = CCS_LIM(sensor, MAX_VT_SYS_CLK_FREQ_MHZ),
+ .min_pix_clk_freq_hz = CCS_LIM(sensor, MIN_VT_PIX_CLK_FREQ_MHZ),
+ .max_pix_clk_freq_hz = CCS_LIM(sensor, MAX_VT_PIX_CLK_FREQ_MHZ),
+ },
+ .min_line_length_pck_bin = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN),
+ .min_line_length_pck = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK),
+ };
+
+ return ccs_pll_calculate(&client->dev, &lim, pll);
+}
+
+static int ccs_pll_update(struct ccs_sensor *sensor)
+{
+ struct ccs_pll *pll = &sensor->pll;
+ int rval;
+
+ pll->binning_horizontal = sensor->binning_horizontal;
+ pll->binning_vertical = sensor->binning_vertical;
+ pll->link_freq =
+ sensor->link_freq->qmenu_int[sensor->link_freq->val];
+ pll->scale_m = sensor->scale_m;
+ pll->bits_per_pixel = sensor->csi_format->compressed;
+
+ rval = ccs_pll_try(sensor, pll);
+ if (rval < 0)
+ return rval;
+
+ __v4l2_ctrl_s_ctrl_int64(sensor->pixel_rate_parray,
+ pll->pixel_rate_pixel_array);
+ __v4l2_ctrl_s_ctrl_int64(sensor->pixel_rate_csi, pll->pixel_rate_csi);
+
+ return 0;
+}
+
+
+/*
+ *
+ * V4L2 Controls handling
+ *
+ */
+
+static void __ccs_update_exposure_limits(struct ccs_sensor *sensor)
+{
+ struct v4l2_ctrl *ctrl = sensor->exposure;
+ int max;
+
+ max = sensor->pixel_array->crop[CCS_PA_PAD_SRC].height
+ + sensor->vblank->val
+ - CCS_LIM(sensor, COARSE_INTEGRATION_TIME_MAX_MARGIN);
+
+ __v4l2_ctrl_modify_range(ctrl, ctrl->minimum, max, ctrl->step, max);
+}
+
+/*
+ * Order matters.
+ *
+ * 1. Bits-per-pixel, descending.
+ * 2. Bits-per-pixel compressed, descending.
+ * 3. Pixel order, same as in pixel_order_str. Formats for all four pixel
+ * orders must be defined.
+ */
+static const struct ccs_csi_data_format ccs_csi_data_formats[] = {
+ { MEDIA_BUS_FMT_SGRBG16_1X16, 16, 16, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB16_1X16, 16, 16, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR16_1X16, 16, 16, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG16_1X16, 16, 16, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG14_1X14, 14, 14, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB14_1X14, 14, 14, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR14_1X14, 14, 14, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG14_1X14, 14, 14, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG12_1X12, 12, 12, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB12_1X12, 12, 12, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR12_1X12, 12, 12, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG12_1X12, 12, 12, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG10_1X10, 10, 10, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB10_1X10, 10, 10, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR10_1X10, 10, 10, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG10_1X10, 10, 10, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8, 10, 8, CCS_PIXEL_ORDER_GBRG, },
+ { MEDIA_BUS_FMT_SGRBG8_1X8, 8, 8, CCS_PIXEL_ORDER_GRBG, },
+ { MEDIA_BUS_FMT_SRGGB8_1X8, 8, 8, CCS_PIXEL_ORDER_RGGB, },
+ { MEDIA_BUS_FMT_SBGGR8_1X8, 8, 8, CCS_PIXEL_ORDER_BGGR, },
+ { MEDIA_BUS_FMT_SGBRG8_1X8, 8, 8, CCS_PIXEL_ORDER_GBRG, },
+};
+
+static const char *pixel_order_str[] = { "GRBG", "RGGB", "BGGR", "GBRG" };
+
+#define to_csi_format_idx(fmt) (((unsigned long)(fmt) \
+ - (unsigned long)ccs_csi_data_formats) \
+ / sizeof(*ccs_csi_data_formats))
+
+static u32 ccs_pixel_order(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int flip = 0;
+
+ if (sensor->hflip) {
+ if (sensor->hflip->val)
+ flip |= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR;
+
+ if (sensor->vflip->val)
+ flip |= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
+ }
+
+ flip ^= sensor->hvflip_inv_mask;
+
+ dev_dbg(&client->dev, "flip %u\n", flip);
+ return sensor->default_pixel_order ^ flip;
+}
+
+static void ccs_update_mbus_formats(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ unsigned int csi_format_idx =
+ to_csi_format_idx(sensor->csi_format) & ~3;
+ unsigned int internal_csi_format_idx =
+ to_csi_format_idx(sensor->internal_csi_format) & ~3;
+ unsigned int pixel_order = ccs_pixel_order(sensor);
+
+ if (WARN_ON_ONCE(max(internal_csi_format_idx, csi_format_idx) +
+ pixel_order >= ARRAY_SIZE(ccs_csi_data_formats)))
+ return;
+
+ sensor->mbus_frame_fmts =
+ sensor->default_mbus_frame_fmts << pixel_order;
+ sensor->csi_format =
+ &ccs_csi_data_formats[csi_format_idx + pixel_order];
+ sensor->internal_csi_format =
+ &ccs_csi_data_formats[internal_csi_format_idx
+ + pixel_order];
+
+ dev_dbg(&client->dev, "new pixel order %s\n",
+ pixel_order_str[pixel_order]);
+}
+
+static const char * const ccs_test_patterns[] = {
+ "Disabled",
+ "Solid Colour",
+ "Eight Vertical Colour Bars",
+ "Colour Bars With Fade to Grey",
+ "Pseudorandom Sequence (PN9)",
+};
+
+static int ccs_set_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct ccs_sensor *sensor =
+ container_of(ctrl->handler, struct ccs_subdev, ctrl_handler)
+ ->sensor;
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int pm_status;
+ u32 orient = 0;
+ unsigned int i;
+ int exposure;
+ int rval;
+
+ switch (ctrl->id) {
+ case V4L2_CID_HFLIP:
+ case V4L2_CID_VFLIP:
+ if (sensor->streaming)
+ return -EBUSY;
+
+ if (sensor->hflip->val)
+ orient |= CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR;
+
+ if (sensor->vflip->val)
+ orient |= CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
+
+ orient ^= sensor->hvflip_inv_mask;
+
+ ccs_update_mbus_formats(sensor);
+
+ break;
+ case V4L2_CID_VBLANK:
+ exposure = sensor->exposure->val;
+
+ __ccs_update_exposure_limits(sensor);
+
+ if (exposure > sensor->exposure->maximum) {
+ sensor->exposure->val = sensor->exposure->maximum;
+ rval = ccs_set_ctrl(sensor->exposure);
+ if (rval < 0)
+ return rval;
+ }
+
+ break;
+ case V4L2_CID_LINK_FREQ:
+ if (sensor->streaming)
+ return -EBUSY;
+
+ rval = ccs_pll_update(sensor);
+ if (rval)
+ return rval;
+
+ return 0;
+ case V4L2_CID_TEST_PATTERN:
+ for (i = 0; i < ARRAY_SIZE(sensor->test_data); i++)
+ v4l2_ctrl_activate(
+ sensor->test_data[i],
+ ctrl->val ==
+ V4L2_SMIAPP_TEST_PATTERN_MODE_SOLID_COLOUR);
+
+ break;
+ }
+
+ pm_status = pm_runtime_get_if_active(&client->dev, true);
+ if (!pm_status)
+ return 0;
+
+ switch (ctrl->id) {
+ case V4L2_CID_ANALOGUE_GAIN:
+ rval = ccs_write(sensor, ANALOG_GAIN_CODE_GLOBAL, ctrl->val);
+
+ break;
+
+ case V4L2_CID_CCS_ANALOGUE_LINEAR_GAIN:
+ rval = ccs_write(sensor, ANALOG_LINEAR_GAIN_GLOBAL, ctrl->val);
+
+ break;
+
+ case V4L2_CID_CCS_ANALOGUE_EXPONENTIAL_GAIN:
+ rval = ccs_write(sensor, ANALOG_EXPONENTIAL_GAIN_GLOBAL,
+ ctrl->val);
+
+ break;
+
+ case V4L2_CID_DIGITAL_GAIN:
+ if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
+ CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL) {
+ rval = ccs_write(sensor, DIGITAL_GAIN_GLOBAL,
+ ctrl->val);
+ break;
+ }
+
+ rval = ccs_write_addr(sensor,
+ SMIAPP_REG_U16_DIGITAL_GAIN_GREENR,
+ ctrl->val);
+ if (rval)
+ break;
+
+ rval = ccs_write_addr(sensor,
+ SMIAPP_REG_U16_DIGITAL_GAIN_RED,
+ ctrl->val);
+ if (rval)
+ break;
+
+ rval = ccs_write_addr(sensor,
+ SMIAPP_REG_U16_DIGITAL_GAIN_BLUE,
+ ctrl->val);
+ if (rval)
+ break;
+
+ rval = ccs_write_addr(sensor,
+ SMIAPP_REG_U16_DIGITAL_GAIN_GREENB,
+ ctrl->val);
+
+ break;
+ case V4L2_CID_EXPOSURE:
+ rval = ccs_write(sensor, COARSE_INTEGRATION_TIME, ctrl->val);
+
+ break;
+ case V4L2_CID_HFLIP:
+ case V4L2_CID_VFLIP:
+ rval = ccs_write(sensor, IMAGE_ORIENTATION, orient);
+
+ break;
+ case V4L2_CID_VBLANK:
+ rval = ccs_write(sensor, FRAME_LENGTH_LINES,
+ sensor->pixel_array->crop[
+ CCS_PA_PAD_SRC].height
+ + ctrl->val);
+
+ break;
+ case V4L2_CID_HBLANK:
+ rval = ccs_write(sensor, LINE_LENGTH_PCK,
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].width
+ + ctrl->val);
+
+ break;
+ case V4L2_CID_TEST_PATTERN:
+ rval = ccs_write(sensor, TEST_PATTERN_MODE, ctrl->val);
+
+ break;
+ case V4L2_CID_TEST_PATTERN_RED:
+ rval = ccs_write(sensor, TEST_DATA_RED, ctrl->val);
+
+ break;
+ case V4L2_CID_TEST_PATTERN_GREENR:
+ rval = ccs_write(sensor, TEST_DATA_GREENR, ctrl->val);
+
+ break;
+ case V4L2_CID_TEST_PATTERN_BLUE:
+ rval = ccs_write(sensor, TEST_DATA_BLUE, ctrl->val);
+
+ break;
+ case V4L2_CID_TEST_PATTERN_GREENB:
+ rval = ccs_write(sensor, TEST_DATA_GREENB, ctrl->val);
+
+ break;
+ case V4L2_CID_CCS_SHADING_CORRECTION:
+ rval = ccs_write(sensor, SHADING_CORRECTION_EN,
+ ctrl->val ? CCS_SHADING_CORRECTION_EN_ENABLE :
+ 0);
+
+ if (!rval && sensor->luminance_level)
+ v4l2_ctrl_activate(sensor->luminance_level, ctrl->val);
+
+ break;
+ case V4L2_CID_CCS_LUMINANCE_CORRECTION_LEVEL:
+ rval = ccs_write(sensor, LUMINANCE_CORRECTION_LEVEL, ctrl->val);
+
+ break;
+ case V4L2_CID_PIXEL_RATE:
+ /* For v4l2_ctrl_s_ctrl_int64() used internally. */
+ rval = 0;
+
+ break;
+ default:
+ rval = -EINVAL;
+ }
+
+ if (pm_status > 0) {
+ pm_runtime_mark_last_busy(&client->dev);
+ pm_runtime_put_autosuspend(&client->dev);
+ }
+
+ return rval;
+}
+
+static const struct v4l2_ctrl_ops ccs_ctrl_ops = {
+ .s_ctrl = ccs_set_ctrl,
+};
+
+static int ccs_init_controls(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+
+ rval = v4l2_ctrl_handler_init(&sensor->pixel_array->ctrl_handler, 17);
+ if (rval)
+ return rval;
+
+ sensor->pixel_array->ctrl_handler.lock = &sensor->mutex;
+
+ switch (CCS_LIM(sensor, ANALOG_GAIN_CAPABILITY)) {
+ case CCS_ANALOG_GAIN_CAPABILITY_GLOBAL: {
+ struct {
+ const char *name;
+ u32 id;
+ s32 value;
+ } const gain_ctrls[] = {
+ { "Analogue Gain m0", V4L2_CID_CCS_ANALOGUE_GAIN_M0,
+ CCS_LIM(sensor, ANALOG_GAIN_M0), },
+ { "Analogue Gain c0", V4L2_CID_CCS_ANALOGUE_GAIN_C0,
+ CCS_LIM(sensor, ANALOG_GAIN_C0), },
+ { "Analogue Gain m1", V4L2_CID_CCS_ANALOGUE_GAIN_M1,
+ CCS_LIM(sensor, ANALOG_GAIN_M1), },
+ { "Analogue Gain c1", V4L2_CID_CCS_ANALOGUE_GAIN_C1,
+ CCS_LIM(sensor, ANALOG_GAIN_C1), },
+ };
+ struct v4l2_ctrl_config ctrl_cfg = {
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .ops = &ccs_ctrl_ops,
+ .flags = V4L2_CTRL_FLAG_READ_ONLY,
+ .step = 1,
+ };
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gain_ctrls); i++) {
+ ctrl_cfg.name = gain_ctrls[i].name;
+ ctrl_cfg.id = gain_ctrls[i].id;
+ ctrl_cfg.min = ctrl_cfg.max = ctrl_cfg.def =
+ gain_ctrls[i].value;
+
+ v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
+ &ctrl_cfg, NULL);
+ }
+
+ v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler,
+ &ccs_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN),
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MAX),
+ max(CCS_LIM(sensor, ANALOG_GAIN_CODE_STEP),
+ 1U),
+ CCS_LIM(sensor, ANALOG_GAIN_CODE_MIN));
+ }
+ break;
+
+ case CCS_ANALOG_GAIN_CAPABILITY_ALTERNATE_GLOBAL: {
+ struct {
+ const char *name;
+ u32 id;
+ u16 min, max, step;
+ } const gain_ctrls[] = {
+ {
+ "Analogue Linear Gain",
+ V4L2_CID_CCS_ANALOGUE_LINEAR_GAIN,
+ CCS_LIM(sensor, ANALOG_LINEAR_GAIN_MIN),
+ CCS_LIM(sensor, ANALOG_LINEAR_GAIN_MAX),
+ max(CCS_LIM(sensor,
+ ANALOG_LINEAR_GAIN_STEP_SIZE),
+ 1U),
+ },
+ {
+ "Analogue Exponential Gain",
+ V4L2_CID_CCS_ANALOGUE_EXPONENTIAL_GAIN,
+ CCS_LIM(sensor, ANALOG_EXPONENTIAL_GAIN_MIN),
+ CCS_LIM(sensor, ANALOG_EXPONENTIAL_GAIN_MAX),
+ max(CCS_LIM(sensor,
+ ANALOG_EXPONENTIAL_GAIN_STEP_SIZE),
+ 1U),
+ },
+ };
+ struct v4l2_ctrl_config ctrl_cfg = {
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .ops = &ccs_ctrl_ops,
+ };
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gain_ctrls); i++) {
+ ctrl_cfg.name = gain_ctrls[i].name;
+ ctrl_cfg.min = ctrl_cfg.def = gain_ctrls[i].min;
+ ctrl_cfg.max = gain_ctrls[i].max;
+ ctrl_cfg.step = gain_ctrls[i].step;
+ ctrl_cfg.id = gain_ctrls[i].id;
+
+ v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
+ &ctrl_cfg, NULL);
+ }
+ }
+ }
+
+ if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
+ (CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING |
+ CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION)) {
+ const struct v4l2_ctrl_config ctrl_cfg = {
+ .name = "Shading Correction",
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .id = V4L2_CID_CCS_SHADING_CORRECTION,
+ .ops = &ccs_ctrl_ops,
+ .max = 1,
+ .step = 1,
+ };
+
+ v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
+ &ctrl_cfg, NULL);
+ }
+
+ if (CCS_LIM(sensor, SHADING_CORRECTION_CAPABILITY) &
+ CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION) {
+ const struct v4l2_ctrl_config ctrl_cfg = {
+ .name = "Luminance Correction Level",
+ .type = V4L2_CTRL_TYPE_BOOLEAN,
+ .id = V4L2_CID_CCS_LUMINANCE_CORRECTION_LEVEL,
+ .ops = &ccs_ctrl_ops,
+ .max = 255,
+ .step = 1,
+ .def = 128,
+ };
+
+ sensor->luminance_level =
+ v4l2_ctrl_new_custom(&sensor->pixel_array->ctrl_handler,
+ &ctrl_cfg, NULL);
+ }
+
+ if (CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
+ CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL ||
+ CCS_LIM(sensor, DIGITAL_GAIN_CAPABILITY) ==
+ SMIAPP_DIGITAL_GAIN_CAPABILITY_PER_CHANNEL)
+ v4l2_ctrl_new_std(&sensor->pixel_array->ctrl_handler,
+ &ccs_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
+ CCS_LIM(sensor, DIGITAL_GAIN_MIN),
+ CCS_LIM(sensor, DIGITAL_GAIN_MAX),
+ max(CCS_LIM(sensor, DIGITAL_GAIN_STEP_SIZE),
+ 1U),
+ 0x100);
+
+ /* Exposure limits will be updated soon, use just something here. */
+ sensor->exposure = v4l2_ctrl_new_std(
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_EXPOSURE, 0, 0, 1, 0);
+
+ sensor->hflip = v4l2_ctrl_new_std(
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_HFLIP, 0, 1, 1, 0);
+ sensor->vflip = v4l2_ctrl_new_std(
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_VFLIP, 0, 1, 1, 0);
+
+ sensor->vblank = v4l2_ctrl_new_std(
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_VBLANK, 0, 1, 1, 0);
+
+ if (sensor->vblank)
+ sensor->vblank->flags |= V4L2_CTRL_FLAG_UPDATE;
+
+ sensor->hblank = v4l2_ctrl_new_std(
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_HBLANK, 0, 1, 1, 0);
+
+ if (sensor->hblank)
+ sensor->hblank->flags |= V4L2_CTRL_FLAG_UPDATE;
+
+ sensor->pixel_rate_parray = v4l2_ctrl_new_std(
+ &sensor->pixel_array->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
+
+ v4l2_ctrl_new_std_menu_items(&sensor->pixel_array->ctrl_handler,
+ &ccs_ctrl_ops, V4L2_CID_TEST_PATTERN,
+ ARRAY_SIZE(ccs_test_patterns) - 1,
+ 0, 0, ccs_test_patterns);
+
+ if (sensor->pixel_array->ctrl_handler.error) {
+ dev_err(&client->dev,
+ "pixel array controls initialization failed (%d)\n",
+ sensor->pixel_array->ctrl_handler.error);
+ return sensor->pixel_array->ctrl_handler.error;
+ }
+
+ sensor->pixel_array->sd.ctrl_handler =
+ &sensor->pixel_array->ctrl_handler;
+
+ v4l2_ctrl_cluster(2, &sensor->hflip);
+
+ rval = v4l2_ctrl_handler_init(&sensor->src->ctrl_handler, 0);
+ if (rval)
+ return rval;
+
+ sensor->src->ctrl_handler.lock = &sensor->mutex;
+
+ sensor->pixel_rate_csi = v4l2_ctrl_new_std(
+ &sensor->src->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
+
+ if (sensor->src->ctrl_handler.error) {
+ dev_err(&client->dev,
+ "src controls initialization failed (%d)\n",
+ sensor->src->ctrl_handler.error);
+ return sensor->src->ctrl_handler.error;
+ }
+
+ sensor->src->sd.ctrl_handler = &sensor->src->ctrl_handler;
+
+ return 0;
+}
+
+/*
+ * For controls that require information on available media bus codes
+ * and linke frequencies.
+ */
+static int ccs_init_late_controls(struct ccs_sensor *sensor)
+{
+ unsigned long *valid_link_freqs = &sensor->valid_link_freqs[
+ sensor->csi_format->compressed - sensor->compressed_min_bpp];
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(sensor->test_data); i++) {
+ int max_value = (1 << sensor->csi_format->width) - 1;
+
+ sensor->test_data[i] = v4l2_ctrl_new_std(
+ &sensor->pixel_array->ctrl_handler,
+ &ccs_ctrl_ops, V4L2_CID_TEST_PATTERN_RED + i,
+ 0, max_value, 1, max_value);
+ }
+
+ sensor->link_freq = v4l2_ctrl_new_int_menu(
+ &sensor->src->ctrl_handler, &ccs_ctrl_ops,
+ V4L2_CID_LINK_FREQ, __fls(*valid_link_freqs),
+ __ffs(*valid_link_freqs), sensor->hwcfg.op_sys_clock);
+
+ return sensor->src->ctrl_handler.error;
+}
+
+static void ccs_free_controls(struct ccs_sensor *sensor)
+{
+ unsigned int i;
+
+ for (i = 0; i < sensor->ssds_used; i++)
+ v4l2_ctrl_handler_free(&sensor->ssds[i].ctrl_handler);
+}
+
+static int ccs_get_mbus_formats(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ struct ccs_pll *pll = &sensor->pll;
+ u8 compressed_max_bpp = 0;
+ unsigned int type, n;
+ unsigned int i, pixel_order;
+ int rval;
+
+ type = CCS_LIM(sensor, DATA_FORMAT_MODEL_TYPE);
+
+ dev_dbg(&client->dev, "data_format_model_type %u\n", type);
+
+ rval = ccs_read(sensor, PIXEL_ORDER, &pixel_order);
+ if (rval)
+ return rval;
+
+ if (pixel_order >= ARRAY_SIZE(pixel_order_str)) {
+ dev_dbg(&client->dev, "bad pixel order %u\n", pixel_order);
+ return -EINVAL;
+ }
+
+ dev_dbg(&client->dev, "pixel order %u (%s)\n", pixel_order,
+ pixel_order_str[pixel_order]);
+
+ switch (type) {
+ case CCS_DATA_FORMAT_MODEL_TYPE_NORMAL:
+ n = SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N;
+ break;
+ case CCS_DATA_FORMAT_MODEL_TYPE_EXTENDED:
+ n = CCS_LIM_DATA_FORMAT_DESCRIPTOR_MAX_N + 1;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ sensor->default_pixel_order = pixel_order;
+ sensor->mbus_frame_fmts = 0;
+
+ for (i = 0; i < n; i++) {
+ unsigned int fmt, j;
+
+ fmt = CCS_LIM_AT(sensor, DATA_FORMAT_DESCRIPTOR, i);
+
+ dev_dbg(&client->dev, "%u: bpp %u, compressed %u\n",
+ i, fmt >> 8, (u8)fmt);
+
+ for (j = 0; j < ARRAY_SIZE(ccs_csi_data_formats); j++) {
+ const struct ccs_csi_data_format *f =
+ &ccs_csi_data_formats[j];
+
+ if (f->pixel_order != CCS_PIXEL_ORDER_GRBG)
+ continue;
+
+ if (f->width != fmt >>
+ CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_SHIFT ||
+ f->compressed !=
+ (fmt & CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK))
+ continue;
+
+ dev_dbg(&client->dev, "jolly good! %u\n", j);
+
+ sensor->default_mbus_frame_fmts |= 1 << j;
+ }
+ }
+
+ /* Figure out which BPP values can be used with which formats. */
+ pll->binning_horizontal = 1;
+ pll->binning_vertical = 1;
+ pll->scale_m = sensor->scale_m;
+
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
+ sensor->compressed_min_bpp =
+ min(ccs_csi_data_formats[i].compressed,
+ sensor->compressed_min_bpp);
+ compressed_max_bpp =
+ max(ccs_csi_data_formats[i].compressed,
+ compressed_max_bpp);
+ }
+
+ sensor->valid_link_freqs = devm_kcalloc(
+ &client->dev,
+ compressed_max_bpp - sensor->compressed_min_bpp + 1,
+ sizeof(*sensor->valid_link_freqs), GFP_KERNEL);
+ if (!sensor->valid_link_freqs)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
+ const struct ccs_csi_data_format *f =
+ &ccs_csi_data_formats[i];
+ unsigned long *valid_link_freqs =
+ &sensor->valid_link_freqs[
+ f->compressed - sensor->compressed_min_bpp];
+ unsigned int j;
+
+ if (!(sensor->default_mbus_frame_fmts & 1 << i))
+ continue;
+
+ pll->bits_per_pixel = f->compressed;
+
+ for (j = 0; sensor->hwcfg.op_sys_clock[j]; j++) {
+ pll->link_freq = sensor->hwcfg.op_sys_clock[j];
+
+ rval = ccs_pll_try(sensor, pll);
+ dev_dbg(&client->dev, "link freq %u Hz, bpp %u %s\n",
+ pll->link_freq, pll->bits_per_pixel,
+ rval ? "not ok" : "ok");
+ if (rval)
+ continue;
+
+ set_bit(j, valid_link_freqs);
+ }
+
+ if (!*valid_link_freqs) {
+ dev_info(&client->dev,
+ "no valid link frequencies for %u bpp\n",
+ f->compressed);
+ sensor->default_mbus_frame_fmts &= ~BIT(i);
+ continue;
+ }
+
+ if (!sensor->csi_format
+ || f->width > sensor->csi_format->width
+ || (f->width == sensor->csi_format->width
+ && f->compressed > sensor->csi_format->compressed)) {
+ sensor->csi_format = f;
+ sensor->internal_csi_format = f;
+ }
+ }
+
+ if (!sensor->csi_format) {
+ dev_err(&client->dev, "no supported mbus code found\n");
+ return -EINVAL;
+ }
+
+ ccs_update_mbus_formats(sensor);
+
+ return 0;
+}
+
+static void ccs_update_blanking(struct ccs_sensor *sensor)
+{
+ struct v4l2_ctrl *vblank = sensor->vblank;
+ struct v4l2_ctrl *hblank = sensor->hblank;
+ u16 min_fll, max_fll, min_llp, max_llp, min_lbp;
+ int min, max;
+
+ if (sensor->binning_vertical > 1 || sensor->binning_horizontal > 1) {
+ min_fll = CCS_LIM(sensor, MIN_FRAME_LENGTH_LINES_BIN);
+ max_fll = CCS_LIM(sensor, MAX_FRAME_LENGTH_LINES_BIN);
+ min_llp = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK_BIN);
+ max_llp = CCS_LIM(sensor, MAX_LINE_LENGTH_PCK_BIN);
+ min_lbp = CCS_LIM(sensor, MIN_LINE_BLANKING_PCK_BIN);
+ } else {
+ min_fll = CCS_LIM(sensor, MIN_FRAME_LENGTH_LINES);
+ max_fll = CCS_LIM(sensor, MAX_FRAME_LENGTH_LINES);
+ min_llp = CCS_LIM(sensor, MIN_LINE_LENGTH_PCK);
+ max_llp = CCS_LIM(sensor, MAX_LINE_LENGTH_PCK);
+ min_lbp = CCS_LIM(sensor, MIN_LINE_BLANKING_PCK);
+ }
+
+ min = max_t(int,
+ CCS_LIM(sensor, MIN_FRAME_BLANKING_LINES),
+ min_fll - sensor->pixel_array->crop[CCS_PA_PAD_SRC].height);
+ max = max_fll - sensor->pixel_array->crop[CCS_PA_PAD_SRC].height;
+
+ __v4l2_ctrl_modify_range(vblank, min, max, vblank->step, min);
+
+ min = max_t(int,
+ min_llp - sensor->pixel_array->crop[CCS_PA_PAD_SRC].width,
+ min_lbp);
+ max = max_llp - sensor->pixel_array->crop[CCS_PA_PAD_SRC].width;
+
+ __v4l2_ctrl_modify_range(hblank, min, max, hblank->step, min);
+
+ __ccs_update_exposure_limits(sensor);
+}
+
+static int ccs_pll_blanking_update(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+
+ rval = ccs_pll_update(sensor);
+ if (rval < 0)
+ return rval;
+
+ /* Output from pixel array, including blanking */
+ ccs_update_blanking(sensor);
+
+ dev_dbg(&client->dev, "vblank\t\t%d\n", sensor->vblank->val);
+ dev_dbg(&client->dev, "hblank\t\t%d\n", sensor->hblank->val);
+
+ dev_dbg(&client->dev, "real timeperframe\t100/%d\n",
+ sensor->pll.pixel_rate_pixel_array /
+ ((sensor->pixel_array->crop[CCS_PA_PAD_SRC].width
+ + sensor->hblank->val) *
+ (sensor->pixel_array->crop[CCS_PA_PAD_SRC].height
+ + sensor->vblank->val) / 100));
+
+ return 0;
+}
+
+/*
+ *
+ * SMIA++ NVM handling
+ *
+ */
+
+static int ccs_read_nvm_page(struct ccs_sensor *sensor, u32 p, u8 *nvm,
+ u8 *status)
+{
+ unsigned int i;
+ int rval;
+ u32 s;
+
+ *status = 0;
+
+ rval = ccs_write(sensor, DATA_TRANSFER_IF_1_PAGE_SELECT, p);
+ if (rval)
+ return rval;
+
+ rval = ccs_write(sensor, DATA_TRANSFER_IF_1_CTRL,
+ CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE);
+ if (rval)
+ return rval;
+
+ rval = ccs_read(sensor, DATA_TRANSFER_IF_1_STATUS, &s);
+ if (rval)
+ return rval;
+
+ if (s & CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE) {
+ *status = s;
+ return -ENODATA;
+ }
+
+ if (CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
+ CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING) {
+ for (i = 1000; i > 0; i--) {
+ if (s & CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY)
+ break;
+
+ rval = ccs_read(sensor, DATA_TRANSFER_IF_1_STATUS, &s);
+ if (rval)
+ return rval;
+ }
+
+ if (!i)
+ return -ETIMEDOUT;
+ }
+
+ for (i = 0; i <= CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P; i++) {
+ u32 v;
+
+ rval = ccs_read(sensor, DATA_TRANSFER_IF_1_DATA(i), &v);
+ if (rval)
+ return rval;
+
+ *nvm++ = v;
+ }
+
+ return 0;
+}
+
+static int ccs_read_nvm(struct ccs_sensor *sensor, unsigned char *nvm,
+ size_t nvm_size)
+{
+ u8 status = 0;
+ u32 p;
+ int rval = 0, rval2;
+
+ for (p = 0; p < nvm_size / (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1)
+ && !rval; p++) {
+ rval = ccs_read_nvm_page(sensor, p, nvm, &status);
+ nvm += CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1;
+ }
+
+ if (rval == -ENODATA &&
+ status & CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE)
+ rval = 0;
+
+ rval2 = ccs_write(sensor, DATA_TRANSFER_IF_1_CTRL, 0);
+ if (rval < 0)
+ return rval;
+ else
+ return rval2 ?: p * (CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P + 1);
+}
+
+/*
+ *
+ * SMIA++ CCI address control
+ *
+ */
+static int ccs_change_cci_addr(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+ u32 val;
+
+ client->addr = sensor->hwcfg.i2c_addr_dfl;
+
+ rval = ccs_write(sensor, CCI_ADDRESS_CTRL,
+ sensor->hwcfg.i2c_addr_alt << 1);
+ if (rval)
+ return rval;
+
+ client->addr = sensor->hwcfg.i2c_addr_alt;
+
+ /* verify addr change went ok */
+ rval = ccs_read(sensor, CCI_ADDRESS_CTRL, &val);
+ if (rval)
+ return rval;
+
+ if (val != sensor->hwcfg.i2c_addr_alt << 1)
+ return -ENODEV;
+
+ return 0;
+}
+
+/*
+ *
+ * SMIA++ Mode Control
+ *
+ */
+static int ccs_setup_flash_strobe(struct ccs_sensor *sensor)
+{
+ struct ccs_flash_strobe_parms *strobe_setup;
+ unsigned int ext_freq = sensor->hwcfg.ext_clk;
+ u32 tmp;
+ u32 strobe_adjustment;
+ u32 strobe_width_high_rs;
+ int rval;
+
+ strobe_setup = sensor->hwcfg.strobe_setup;
+
+ /*
+ * How to calculate registers related to strobe length. Please
+ * do not change, or if you do at least know what you're
+ * doing. :-)
+ *
+ * Sakari Ailus <sakari.ailus@linux.intel.com> 2010-10-25
+ *
+ * flash_strobe_length [us] / 10^6 = (tFlash_strobe_width_ctrl
+ * / EXTCLK freq [Hz]) * flash_strobe_adjustment
+ *
+ * tFlash_strobe_width_ctrl E N, [1 - 0xffff]
+ * flash_strobe_adjustment E N, [1 - 0xff]
+ *
+ * The formula above is written as below to keep it on one
+ * line:
+ *
+ * l / 10^6 = w / e * a
+ *
+ * Let's mark w * a by x:
+ *
+ * x = w * a
+ *
+ * Thus, we get:
+ *
+ * x = l * e / 10^6
+ *
+ * The strobe width must be at least as long as requested,
+ * thus rounding upwards is needed.
+ *
+ * x = (l * e + 10^6 - 1) / 10^6
+ * -----------------------------
+ *
+ * Maximum possible accuracy is wanted at all times. Thus keep
+ * a as small as possible.
+ *
+ * Calculate a, assuming maximum w, with rounding upwards:
+ *
+ * a = (x + (2^16 - 1) - 1) / (2^16 - 1)
+ * -------------------------------------
+ *
+ * Thus, we also get w, with that a, with rounding upwards:
+ *
+ * w = (x + a - 1) / a
+ * -------------------
+ *
+ * To get limits:
+ *
+ * x E [1, (2^16 - 1) * (2^8 - 1)]
+ *
+ * Substituting maximum x to the original formula (with rounding),
+ * the maximum l is thus
+ *
+ * (2^16 - 1) * (2^8 - 1) * 10^6 = l * e + 10^6 - 1
+ *
+ * l = (10^6 * (2^16 - 1) * (2^8 - 1) - 10^6 + 1) / e
+ * --------------------------------------------------
+ *
+ * flash_strobe_length must be clamped between 1 and
+ * (10^6 * (2^16 - 1) * (2^8 - 1) - 10^6 + 1) / EXTCLK freq.
+ *
+ * Then,
+ *
+ * flash_strobe_adjustment = ((flash_strobe_length *
+ * EXTCLK freq + 10^6 - 1) / 10^6 + (2^16 - 1) - 1) / (2^16 - 1)
+ *
+ * tFlash_strobe_width_ctrl = ((flash_strobe_length *
+ * EXTCLK freq + 10^6 - 1) / 10^6 +
+ * flash_strobe_adjustment - 1) / flash_strobe_adjustment
+ */
+ tmp = div_u64(1000000ULL * ((1 << 16) - 1) * ((1 << 8) - 1) -
+ 1000000 + 1, ext_freq);
+ strobe_setup->strobe_width_high_us =
+ clamp_t(u32, strobe_setup->strobe_width_high_us, 1, tmp);
+
+ tmp = div_u64(((u64)strobe_setup->strobe_width_high_us * (u64)ext_freq +
+ 1000000 - 1), 1000000ULL);
+ strobe_adjustment = (tmp + (1 << 16) - 1 - 1) / ((1 << 16) - 1);
+ strobe_width_high_rs = (tmp + strobe_adjustment - 1) /
+ strobe_adjustment;
+
+ rval = ccs_write(sensor, FLASH_MODE_RS, strobe_setup->mode);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(sensor, FLASH_STROBE_ADJUSTMENT, strobe_adjustment);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(sensor, TFLASH_STROBE_WIDTH_HIGH_RS_CTRL,
+ strobe_width_high_rs);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(sensor, TFLASH_STROBE_DELAY_RS_CTRL,
+ strobe_setup->strobe_delay);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(sensor, FLASH_STROBE_START_POINT,
+ strobe_setup->stobe_start_point);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(sensor, FLASH_TRIGGER_RS, strobe_setup->trigger);
+
+out:
+ sensor->hwcfg.strobe_setup->trigger = 0;
+
+ return rval;
+}
+
+/* -----------------------------------------------------------------------------
+ * Power management
+ */
+
+static int ccs_write_msr_regs(struct ccs_sensor *sensor)
+{
+ int rval;
+
+ rval = ccs_write_data_regs(sensor,
+ sensor->sdata.sensor_manufacturer_regs,
+ sensor->sdata.num_sensor_manufacturer_regs);
+ if (rval)
+ return rval;
+
+ return ccs_write_data_regs(sensor,
+ sensor->mdata.module_manufacturer_regs,
+ sensor->mdata.num_module_manufacturer_regs);
+}
+
+static int ccs_update_phy_ctrl(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ u8 val;
+
+ if (!sensor->ccs_limits)
+ return 0;
+
+ if (CCS_LIM(sensor, PHY_CTRL_CAPABILITY) &
+ CCS_PHY_CTRL_CAPABILITY_AUTO_PHY_CTL) {
+ val = CCS_PHY_CTRL_AUTO;
+ } else if (CCS_LIM(sensor, PHY_CTRL_CAPABILITY) &
+ CCS_PHY_CTRL_CAPABILITY_UI_PHY_CTL) {
+ val = CCS_PHY_CTRL_UI;
+ } else {
+ dev_err(&client->dev, "manual PHY control not supported\n");
+ return -EINVAL;
+ }
+
+ return ccs_write(sensor, PHY_CTRL, val);
+}
+
+static int ccs_power_on(struct device *dev)
+{
+ struct v4l2_subdev *subdev = dev_get_drvdata(dev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ /*
+ * The sub-device related to the I2C device is always the
+ * source one, i.e. ssds[0].
+ */
+ struct ccs_sensor *sensor =
+ container_of(ssd, struct ccs_sensor, ssds[0]);
+ const struct ccs_device *ccsdev = device_get_match_data(dev);
+ int rval;
+
+ rval = regulator_bulk_enable(ARRAY_SIZE(ccs_regulators),
+ sensor->regulators);
+ if (rval) {
+ dev_err(dev, "failed to enable vana regulator\n");
+ return rval;
+ }
+
+ if (sensor->reset || sensor->xshutdown || sensor->ext_clk) {
+ unsigned int sleep;
+
+ rval = clk_prepare_enable(sensor->ext_clk);
+ if (rval < 0) {
+ dev_dbg(dev, "failed to enable xclk\n");
+ goto out_xclk_fail;
+ }
+
+ gpiod_set_value(sensor->reset, 0);
+ gpiod_set_value(sensor->xshutdown, 1);
+
+ if (ccsdev->flags & CCS_DEVICE_FLAG_IS_SMIA)
+ sleep = SMIAPP_RESET_DELAY(sensor->hwcfg.ext_clk);
+ else
+ sleep = 5000;
+
+ usleep_range(sleep, sleep);
+ }
+
+ /*
+ * Failures to respond to the address change command have been noticed.
+ * Those failures seem to be caused by the sensor requiring a longer
+ * boot time than advertised. An additional 10ms delay seems to work
+ * around the issue, but the SMIA++ I2C write retry hack makes the delay
+ * unnecessary. The failures need to be investigated to find a proper
+ * fix, and a delay will likely need to be added here if the I2C write
+ * retry hack is reverted before the root cause of the boot time issue
+ * is found.
+ */
+
+ if (!sensor->reset && !sensor->xshutdown) {
+ u8 retry = 100;
+ u32 reset;
+
+ rval = ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON);
+ if (rval < 0) {
+ dev_err(dev, "software reset failed\n");
+ goto out_cci_addr_fail;
+ }
+
+ do {
+ rval = ccs_read(sensor, SOFTWARE_RESET, &reset);
+ reset = !rval && reset == CCS_SOFTWARE_RESET_OFF;
+ if (reset)
+ break;
+
+ usleep_range(1000, 2000);
+ } while (--retry);
+
+ if (!reset) {
+ dev_err(dev, "software reset failed\n");
+ rval = -EIO;
+ goto out_cci_addr_fail;
+ }
+ }
+
+ if (sensor->hwcfg.i2c_addr_alt) {
+ rval = ccs_change_cci_addr(sensor);
+ if (rval) {
+ dev_err(dev, "cci address change error\n");
+ goto out_cci_addr_fail;
+ }
+ }
+
+ rval = ccs_write(sensor, COMPRESSION_MODE,
+ CCS_COMPRESSION_MODE_DPCM_PCM_SIMPLE);
+ if (rval) {
+ dev_err(dev, "compression mode set failed\n");
+ goto out_cci_addr_fail;
+ }
+
+ rval = ccs_write(sensor, EXTCLK_FREQUENCY_MHZ,
+ sensor->hwcfg.ext_clk / (1000000 / (1 << 8)));
+ if (rval) {
+ dev_err(dev, "extclk frequency set failed\n");
+ goto out_cci_addr_fail;
+ }
+
+ rval = ccs_write(sensor, CSI_LANE_MODE, sensor->hwcfg.lanes - 1);
+ if (rval) {
+ dev_err(dev, "csi lane mode set failed\n");
+ goto out_cci_addr_fail;
+ }
+
+ rval = ccs_write(sensor, FAST_STANDBY_CTRL,
+ CCS_FAST_STANDBY_CTRL_FRAME_TRUNCATION);
+ if (rval) {
+ dev_err(dev, "fast standby set failed\n");
+ goto out_cci_addr_fail;
+ }
+
+ rval = ccs_write(sensor, CSI_SIGNALING_MODE,
+ sensor->hwcfg.csi_signalling_mode);
+ if (rval) {
+ dev_err(dev, "csi signalling mode set failed\n");
+ goto out_cci_addr_fail;
+ }
+
+ rval = ccs_update_phy_ctrl(sensor);
+ if (rval < 0)
+ goto out_cci_addr_fail;
+
+ rval = ccs_write_msr_regs(sensor);
+ if (rval)
+ goto out_cci_addr_fail;
+
+ rval = ccs_call_quirk(sensor, post_poweron);
+ if (rval) {
+ dev_err(dev, "post_poweron quirks failed\n");
+ goto out_cci_addr_fail;
+ }
+
+ return 0;
+
+out_cci_addr_fail:
+ gpiod_set_value(sensor->reset, 1);
+ gpiod_set_value(sensor->xshutdown, 0);
+ clk_disable_unprepare(sensor->ext_clk);
+
+out_xclk_fail:
+ regulator_bulk_disable(ARRAY_SIZE(ccs_regulators),
+ sensor->regulators);
+
+ return rval;
+}
+
+static int ccs_power_off(struct device *dev)
+{
+ struct v4l2_subdev *subdev = dev_get_drvdata(dev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct ccs_sensor *sensor =
+ container_of(ssd, struct ccs_sensor, ssds[0]);
+
+ /*
+ * Currently power/clock to lens are enable/disabled separately
+ * but they are essentially the same signals. So if the sensor is
+ * powered off while the lens is powered on the sensor does not
+ * really see a power off and next time the cci address change
+ * will fail. So do a soft reset explicitly here.
+ */
+ if (sensor->hwcfg.i2c_addr_alt)
+ ccs_write(sensor, SOFTWARE_RESET, CCS_SOFTWARE_RESET_ON);
+
+ gpiod_set_value(sensor->reset, 1);
+ gpiod_set_value(sensor->xshutdown, 0);
+ clk_disable_unprepare(sensor->ext_clk);
+ usleep_range(5000, 5000);
+ regulator_bulk_disable(ARRAY_SIZE(ccs_regulators),
+ sensor->regulators);
+ sensor->streaming = false;
+
+ return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * Video stream management
+ */
+
+static int ccs_start_streaming(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ unsigned int binning_mode;
+ int rval;
+
+ mutex_lock(&sensor->mutex);
+
+ rval = ccs_write(sensor, CSI_DATA_FORMAT,
+ (sensor->csi_format->width << 8) |
+ sensor->csi_format->compressed);
+ if (rval)
+ goto out;
+
+ /* Binning configuration */
+ if (sensor->binning_horizontal == 1 &&
+ sensor->binning_vertical == 1) {
+ binning_mode = 0;
+ } else {
+ u8 binning_type =
+ (sensor->binning_horizontal << 4)
+ | sensor->binning_vertical;
+
+ rval = ccs_write(sensor, BINNING_TYPE, binning_type);
+ if (rval < 0)
+ goto out;
+
+ binning_mode = 1;
+ }
+ rval = ccs_write(sensor, BINNING_MODE, binning_mode);
+ if (rval < 0)
+ goto out;
+
+ /* Set up PLL */
+ rval = ccs_pll_configure(sensor);
+ if (rval)
+ goto out;
+
+ /* Analog crop start coordinates */
+ rval = ccs_write(sensor, X_ADDR_START,
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].left);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(sensor, Y_ADDR_START,
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].top);
+ if (rval < 0)
+ goto out;
+
+ /* Analog crop end coordinates */
+ rval = ccs_write(
+ sensor, X_ADDR_END,
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].left
+ + sensor->pixel_array->crop[CCS_PA_PAD_SRC].width - 1);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(
+ sensor, Y_ADDR_END,
+ sensor->pixel_array->crop[CCS_PA_PAD_SRC].top
+ + sensor->pixel_array->crop[CCS_PA_PAD_SRC].height - 1);
+ if (rval < 0)
+ goto out;
+
+ /*
+ * Output from pixel array, including blanking, is set using
+ * controls below. No need to set here.
+ */
+
+ /* Digital crop */
+ if (CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
+ == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_X_OFFSET,
+ sensor->scaler->crop[CCS_PAD_SINK].left);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_Y_OFFSET,
+ sensor->scaler->crop[CCS_PAD_SINK].top);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_IMAGE_WIDTH,
+ sensor->scaler->crop[CCS_PAD_SINK].width);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(
+ sensor, DIGITAL_CROP_IMAGE_HEIGHT,
+ sensor->scaler->crop[CCS_PAD_SINK].height);
+ if (rval < 0)
+ goto out;
+ }
+
+ /* Scaling */
+ if (CCS_LIM(sensor, SCALING_CAPABILITY)
+ != CCS_SCALING_CAPABILITY_NONE) {
+ rval = ccs_write(sensor, SCALING_MODE, sensor->scaling_mode);
+ if (rval < 0)
+ goto out;
+
+ rval = ccs_write(sensor, SCALE_M, sensor->scale_m);
+ if (rval < 0)
+ goto out;
+ }
+
+ /* Output size from sensor */
+ rval = ccs_write(sensor, X_OUTPUT_SIZE,
+ sensor->src->crop[CCS_PAD_SRC].width);
+ if (rval < 0)
+ goto out;
+ rval = ccs_write(sensor, Y_OUTPUT_SIZE,
+ sensor->src->crop[CCS_PAD_SRC].height);
+ if (rval < 0)
+ goto out;
+
+ if (CCS_LIM(sensor, FLASH_MODE_CAPABILITY) &
+ (CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE |
+ SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE) &&
+ sensor->hwcfg.strobe_setup != NULL &&
+ sensor->hwcfg.strobe_setup->trigger != 0) {
+ rval = ccs_setup_flash_strobe(sensor);
+ if (rval)
+ goto out;
+ }
+
+ rval = ccs_call_quirk(sensor, pre_streamon);
+ if (rval) {
+ dev_err(&client->dev, "pre_streamon quirks failed\n");
+ goto out;
+ }
+
+ rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_STREAMING);
+
+out:
+ mutex_unlock(&sensor->mutex);
+
+ return rval;
+}
+
+static int ccs_stop_streaming(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+
+ mutex_lock(&sensor->mutex);
+ rval = ccs_write(sensor, MODE_SELECT, CCS_MODE_SELECT_SOFTWARE_STANDBY);
+ if (rval)
+ goto out;
+
+ rval = ccs_call_quirk(sensor, post_streamoff);
+ if (rval)
+ dev_err(&client->dev, "post_streamoff quirks failed\n");
+
+out:
+ mutex_unlock(&sensor->mutex);
+ return rval;
+}
+
+/* -----------------------------------------------------------------------------
+ * V4L2 subdev video operations
+ */
+
+static int ccs_pm_get_init(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+
+ /*
+ * It can't use pm_runtime_resume_and_get() here, as the driver
+ * relies at the returned value to detect if the device was already
+ * active or not.
+ */
+ rval = pm_runtime_get_sync(&client->dev);
+ if (rval < 0)
+ goto error;
+
+ /* Device was already active, so don't set controls */
+ if (rval == 1)
+ return 0;
+
+ /* Restore V4L2 controls to the previously suspended device */
+ rval = v4l2_ctrl_handler_setup(&sensor->pixel_array->ctrl_handler);
+ if (rval)
+ goto error;
+
+ rval = v4l2_ctrl_handler_setup(&sensor->src->ctrl_handler);
+ if (rval)
+ goto error;
+
+ /* Keep PM runtime usage_count incremented on success */
+ return 0;
+error:
+ pm_runtime_put(&client->dev);
+ return rval;
+}
+
+static int ccs_set_stream(struct v4l2_subdev *subdev, int enable)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+
+ if (sensor->streaming == enable)
+ return 0;
+
+ if (!enable) {
+ ccs_stop_streaming(sensor);
+ sensor->streaming = false;
+ pm_runtime_mark_last_busy(&client->dev);
+ pm_runtime_put_autosuspend(&client->dev);
+
+ return 0;
+ }
+
+ rval = ccs_pm_get_init(sensor);
+ if (rval)
+ return rval;
+
+ sensor->streaming = true;
+
+ rval = ccs_start_streaming(sensor);
+ if (rval < 0) {
+ sensor->streaming = false;
+ pm_runtime_mark_last_busy(&client->dev);
+ pm_runtime_put_autosuspend(&client->dev);
+ }
+
+ return rval;
+}
+
+static int ccs_pre_streamon(struct v4l2_subdev *subdev, u32 flags)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+
+ if (flags & V4L2_SUBDEV_PRE_STREAMON_FL_MANUAL_LP) {
+ switch (sensor->hwcfg.csi_signalling_mode) {
+ case CCS_CSI_SIGNALING_MODE_CSI_2_DPHY:
+ if (!(CCS_LIM(sensor, PHY_CTRL_CAPABILITY_2) &
+ CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_DPHY))
+ return -EACCES;
+ break;
+ case CCS_CSI_SIGNALING_MODE_CSI_2_CPHY:
+ if (!(CCS_LIM(sensor, PHY_CTRL_CAPABILITY_2) &
+ CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_CPHY))
+ return -EACCES;
+ break;
+ default:
+ return -EACCES;
+ }
+ }
+
+ rval = ccs_pm_get_init(sensor);
+ if (rval)
+ return rval;
+
+ if (flags & V4L2_SUBDEV_PRE_STREAMON_FL_MANUAL_LP) {
+ rval = ccs_write(sensor, MANUAL_LP_CTRL,
+ CCS_MANUAL_LP_CTRL_ENABLE);
+ if (rval)
+ pm_runtime_put(&client->dev);
+ }
+
+ return rval;
+}
+
+static int ccs_post_streamoff(struct v4l2_subdev *subdev)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+
+ return pm_runtime_put(&client->dev);
+}
+
+static int ccs_enum_mbus_code(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ unsigned int i;
+ int idx = -1;
+ int rval = -EINVAL;
+
+ mutex_lock(&sensor->mutex);
+
+ dev_err(&client->dev, "subdev %s, pad %u, index %u\n",
+ subdev->name, code->pad, code->index);
+
+ if (subdev != &sensor->src->sd || code->pad != CCS_PAD_SRC) {
+ if (code->index)
+ goto out;
+
+ code->code = sensor->internal_csi_format->code;
+ rval = 0;
+ goto out;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
+ if (sensor->mbus_frame_fmts & (1 << i))
+ idx++;
+
+ if (idx == code->index) {
+ code->code = ccs_csi_data_formats[i].code;
+ dev_err(&client->dev, "found index %u, i %u, code %x\n",
+ code->index, i, code->code);
+ rval = 0;
+ break;
+ }
+ }
+
+out:
+ mutex_unlock(&sensor->mutex);
+
+ return rval;
+}
+
+static u32 __ccs_get_mbus_code(struct v4l2_subdev *subdev, unsigned int pad)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+
+ if (subdev == &sensor->src->sd && pad == CCS_PAD_SRC)
+ return sensor->csi_format->code;
+ else
+ return sensor->internal_csi_format->code;
+}
+
+static int __ccs_get_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+
+ if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
+ fmt->format = *v4l2_subdev_get_try_format(subdev, sd_state,
+ fmt->pad);
+ } else {
+ struct v4l2_rect *r;
+
+ if (fmt->pad == ssd->source_pad)
+ r = &ssd->crop[ssd->source_pad];
+ else
+ r = &ssd->sink_fmt;
+
+ fmt->format.code = __ccs_get_mbus_code(subdev, fmt->pad);
+ fmt->format.width = r->width;
+ fmt->format.height = r->height;
+ fmt->format.field = V4L2_FIELD_NONE;
+ }
+
+ return 0;
+}
+
+static int ccs_get_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ int rval;
+
+ mutex_lock(&sensor->mutex);
+ rval = __ccs_get_format(subdev, sd_state, fmt);
+ mutex_unlock(&sensor->mutex);
+
+ return rval;
+}
+
+static void ccs_get_crop_compose(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_rect **crops,
+ struct v4l2_rect **comps, int which)
+{
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ unsigned int i;
+
+ if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+ if (crops)
+ for (i = 0; i < subdev->entity.num_pads; i++)
+ crops[i] = &ssd->crop[i];
+ if (comps)
+ *comps = &ssd->compose;
+ } else {
+ if (crops) {
+ for (i = 0; i < subdev->entity.num_pads; i++)
+ crops[i] = v4l2_subdev_get_try_crop(subdev,
+ sd_state,
+ i);
+ }
+ if (comps)
+ *comps = v4l2_subdev_get_try_compose(subdev, sd_state,
+ CCS_PAD_SINK);
+ }
+}
+
+/* Changes require propagation only on sink pad. */
+static void ccs_propagate(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_state *sd_state, int which,
+ int target)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *comp, *crops[CCS_PADS];
+
+ ccs_get_crop_compose(subdev, sd_state, crops, &comp, which);
+
+ switch (target) {
+ case V4L2_SEL_TGT_CROP:
+ comp->width = crops[CCS_PAD_SINK]->width;
+ comp->height = crops[CCS_PAD_SINK]->height;
+ if (which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+ if (ssd == sensor->scaler) {
+ sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN);
+ sensor->scaling_mode =
+ CCS_SCALING_MODE_NO_SCALING;
+ } else if (ssd == sensor->binner) {
+ sensor->binning_horizontal = 1;
+ sensor->binning_vertical = 1;
+ }
+ }
+ fallthrough;
+ case V4L2_SEL_TGT_COMPOSE:
+ *crops[CCS_PAD_SRC] = *comp;
+ break;
+ default:
+ WARN_ON_ONCE(1);
+ }
+}
+
+static const struct ccs_csi_data_format
+*ccs_validate_csi_data_format(struct ccs_sensor *sensor, u32 code)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(ccs_csi_data_formats); i++) {
+ if (sensor->mbus_frame_fmts & (1 << i) &&
+ ccs_csi_data_formats[i].code == code)
+ return &ccs_csi_data_formats[i];
+ }
+
+ return sensor->csi_format;
+}
+
+static int ccs_set_format_source(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ const struct ccs_csi_data_format *csi_format,
+ *old_csi_format = sensor->csi_format;
+ unsigned long *valid_link_freqs;
+ u32 code = fmt->format.code;
+ unsigned int i;
+ int rval;
+
+ rval = __ccs_get_format(subdev, sd_state, fmt);
+ if (rval)
+ return rval;
+
+ /*
+ * Media bus code is changeable on src subdev's source pad. On
+ * other source pads we just get format here.
+ */
+ if (subdev != &sensor->src->sd)
+ return 0;
+
+ csi_format = ccs_validate_csi_data_format(sensor, code);
+
+ fmt->format.code = csi_format->code;
+
+ if (fmt->which != V4L2_SUBDEV_FORMAT_ACTIVE)
+ return 0;
+
+ sensor->csi_format = csi_format;
+
+ if (csi_format->width != old_csi_format->width)
+ for (i = 0; i < ARRAY_SIZE(sensor->test_data); i++)
+ __v4l2_ctrl_modify_range(
+ sensor->test_data[i], 0,
+ (1 << csi_format->width) - 1, 1, 0);
+
+ if (csi_format->compressed == old_csi_format->compressed)
+ return 0;
+
+ valid_link_freqs =
+ &sensor->valid_link_freqs[sensor->csi_format->compressed
+ - sensor->compressed_min_bpp];
+
+ __v4l2_ctrl_modify_range(
+ sensor->link_freq, 0,
+ __fls(*valid_link_freqs), ~*valid_link_freqs,
+ __ffs(*valid_link_freqs));
+
+ return ccs_pll_update(sensor);
+}
+
+static int ccs_set_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_format *fmt)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *crops[CCS_PADS];
+
+ mutex_lock(&sensor->mutex);
+
+ if (fmt->pad == ssd->source_pad) {
+ int rval;
+
+ rval = ccs_set_format_source(subdev, sd_state, fmt);
+
+ mutex_unlock(&sensor->mutex);
+
+ return rval;
+ }
+
+ /* Sink pad. Width and height are changeable here. */
+ fmt->format.code = __ccs_get_mbus_code(subdev, fmt->pad);
+ fmt->format.width &= ~1;
+ fmt->format.height &= ~1;
+ fmt->format.field = V4L2_FIELD_NONE;
+
+ fmt->format.width =
+ clamp(fmt->format.width,
+ CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
+ CCS_LIM(sensor, MAX_X_OUTPUT_SIZE));
+ fmt->format.height =
+ clamp(fmt->format.height,
+ CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
+ CCS_LIM(sensor, MAX_Y_OUTPUT_SIZE));
+
+ ccs_get_crop_compose(subdev, sd_state, crops, NULL, fmt->which);
+
+ crops[ssd->sink_pad]->left = 0;
+ crops[ssd->sink_pad]->top = 0;
+ crops[ssd->sink_pad]->width = fmt->format.width;
+ crops[ssd->sink_pad]->height = fmt->format.height;
+ if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
+ ssd->sink_fmt = *crops[ssd->sink_pad];
+ ccs_propagate(subdev, sd_state, fmt->which, V4L2_SEL_TGT_CROP);
+
+ mutex_unlock(&sensor->mutex);
+
+ return 0;
+}
+
+/*
+ * Calculate goodness of scaled image size compared to expected image
+ * size and flags provided.
+ */
+#define SCALING_GOODNESS 100000
+#define SCALING_GOODNESS_EXTREME 100000000
+static int scaling_goodness(struct v4l2_subdev *subdev, int w, int ask_w,
+ int h, int ask_h, u32 flags)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct i2c_client *client = v4l2_get_subdevdata(subdev);
+ int val = 0;
+
+ w &= ~1;
+ ask_w &= ~1;
+ h &= ~1;
+ ask_h &= ~1;
+
+ if (flags & V4L2_SEL_FLAG_GE) {
+ if (w < ask_w)
+ val -= SCALING_GOODNESS;
+ if (h < ask_h)
+ val -= SCALING_GOODNESS;
+ }
+
+ if (flags & V4L2_SEL_FLAG_LE) {
+ if (w > ask_w)
+ val -= SCALING_GOODNESS;
+ if (h > ask_h)
+ val -= SCALING_GOODNESS;
+ }
+
+ val -= abs(w - ask_w);
+ val -= abs(h - ask_h);
+
+ if (w < CCS_LIM(sensor, MIN_X_OUTPUT_SIZE))
+ val -= SCALING_GOODNESS_EXTREME;
+
+ dev_dbg(&client->dev, "w %d ask_w %d h %d ask_h %d goodness %d\n",
+ w, ask_w, h, ask_h, val);
+
+ return val;
+}
+
+static void ccs_set_compose_binner(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_selection *sel,
+ struct v4l2_rect **crops,
+ struct v4l2_rect *comp)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ unsigned int i;
+ unsigned int binh = 1, binv = 1;
+ int best = scaling_goodness(
+ subdev,
+ crops[CCS_PAD_SINK]->width, sel->r.width,
+ crops[CCS_PAD_SINK]->height, sel->r.height, sel->flags);
+
+ for (i = 0; i < sensor->nbinning_subtypes; i++) {
+ int this = scaling_goodness(
+ subdev,
+ crops[CCS_PAD_SINK]->width
+ / sensor->binning_subtypes[i].horizontal,
+ sel->r.width,
+ crops[CCS_PAD_SINK]->height
+ / sensor->binning_subtypes[i].vertical,
+ sel->r.height, sel->flags);
+
+ if (this > best) {
+ binh = sensor->binning_subtypes[i].horizontal;
+ binv = sensor->binning_subtypes[i].vertical;
+ best = this;
+ }
+ }
+ if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+ sensor->binning_vertical = binv;
+ sensor->binning_horizontal = binh;
+ }
+
+ sel->r.width = (crops[CCS_PAD_SINK]->width / binh) & ~1;
+ sel->r.height = (crops[CCS_PAD_SINK]->height / binv) & ~1;
+}
+
+/*
+ * Calculate best scaling ratio and mode for given output resolution.
+ *
+ * Try all of these: horizontal ratio, vertical ratio and smallest
+ * size possible (horizontally).
+ *
+ * Also try whether horizontal scaler or full scaler gives a better
+ * result.
+ */
+static void ccs_set_compose_scaler(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_selection *sel,
+ struct v4l2_rect **crops,
+ struct v4l2_rect *comp)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ u32 min, max, a, b, max_m;
+ u32 scale_m = CCS_LIM(sensor, SCALER_N_MIN);
+ int mode = CCS_SCALING_MODE_HORIZONTAL;
+ u32 try[4];
+ u32 ntry = 0;
+ unsigned int i;
+ int best = INT_MIN;
+
+ sel->r.width = min_t(unsigned int, sel->r.width,
+ crops[CCS_PAD_SINK]->width);
+ sel->r.height = min_t(unsigned int, sel->r.height,
+ crops[CCS_PAD_SINK]->height);
+
+ a = crops[CCS_PAD_SINK]->width
+ * CCS_LIM(sensor, SCALER_N_MIN) / sel->r.width;
+ b = crops[CCS_PAD_SINK]->height
+ * CCS_LIM(sensor, SCALER_N_MIN) / sel->r.height;
+ max_m = crops[CCS_PAD_SINK]->width
+ * CCS_LIM(sensor, SCALER_N_MIN)
+ / CCS_LIM(sensor, MIN_X_OUTPUT_SIZE);
+
+ a = clamp(a, CCS_LIM(sensor, SCALER_M_MIN),
+ CCS_LIM(sensor, SCALER_M_MAX));
+ b = clamp(b, CCS_LIM(sensor, SCALER_M_MIN),
+ CCS_LIM(sensor, SCALER_M_MAX));
+ max_m = clamp(max_m, CCS_LIM(sensor, SCALER_M_MIN),
+ CCS_LIM(sensor, SCALER_M_MAX));
+
+ dev_dbg(&client->dev, "scaling: a %u b %u max_m %u\n", a, b, max_m);
+
+ min = min(max_m, min(a, b));
+ max = min(max_m, max(a, b));
+
+ try[ntry] = min;
+ ntry++;
+ if (min != max) {
+ try[ntry] = max;
+ ntry++;
+ }
+ if (max != max_m) {
+ try[ntry] = min + 1;
+ ntry++;
+ if (min != max) {
+ try[ntry] = max + 1;
+ ntry++;
+ }
+ }
+
+ for (i = 0; i < ntry; i++) {
+ int this = scaling_goodness(
+ subdev,
+ crops[CCS_PAD_SINK]->width
+ / try[i] * CCS_LIM(sensor, SCALER_N_MIN),
+ sel->r.width,
+ crops[CCS_PAD_SINK]->height,
+ sel->r.height,
+ sel->flags);
+
+ dev_dbg(&client->dev, "trying factor %u (%u)\n", try[i], i);
+
+ if (this > best) {
+ scale_m = try[i];
+ mode = CCS_SCALING_MODE_HORIZONTAL;
+ best = this;
+ }
+
+ if (CCS_LIM(sensor, SCALING_CAPABILITY)
+ == CCS_SCALING_CAPABILITY_HORIZONTAL)
+ continue;
+
+ this = scaling_goodness(
+ subdev, crops[CCS_PAD_SINK]->width
+ / try[i]
+ * CCS_LIM(sensor, SCALER_N_MIN),
+ sel->r.width,
+ crops[CCS_PAD_SINK]->height
+ / try[i]
+ * CCS_LIM(sensor, SCALER_N_MIN),
+ sel->r.height,
+ sel->flags);
+
+ if (this > best) {
+ scale_m = try[i];
+ mode = SMIAPP_SCALING_MODE_BOTH;
+ best = this;
+ }
+ }
+
+ sel->r.width =
+ (crops[CCS_PAD_SINK]->width
+ / scale_m
+ * CCS_LIM(sensor, SCALER_N_MIN)) & ~1;
+ if (mode == SMIAPP_SCALING_MODE_BOTH)
+ sel->r.height =
+ (crops[CCS_PAD_SINK]->height
+ / scale_m
+ * CCS_LIM(sensor, SCALER_N_MIN))
+ & ~1;
+ else
+ sel->r.height = crops[CCS_PAD_SINK]->height;
+
+ if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+ sensor->scale_m = scale_m;
+ sensor->scaling_mode = mode;
+ }
+}
+/* We're only called on source pads. This function sets scaling. */
+static int ccs_set_compose(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_selection *sel)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *comp, *crops[CCS_PADS];
+
+ ccs_get_crop_compose(subdev, sd_state, crops, &comp, sel->which);
+
+ sel->r.top = 0;
+ sel->r.left = 0;
+
+ if (ssd == sensor->binner)
+ ccs_set_compose_binner(subdev, sd_state, sel, crops, comp);
+ else
+ ccs_set_compose_scaler(subdev, sd_state, sel, crops, comp);
+
+ *comp = sel->r;
+ ccs_propagate(subdev, sd_state, sel->which, V4L2_SEL_TGT_COMPOSE);
+
+ if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE)
+ return ccs_pll_blanking_update(sensor);
+
+ return 0;
+}
+
+static int __ccs_sel_supported(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_selection *sel)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+
+ /* We only implement crop in three places. */
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP:
+ case V4L2_SEL_TGT_CROP_BOUNDS:
+ if (ssd == sensor->pixel_array && sel->pad == CCS_PA_PAD_SRC)
+ return 0;
+ if (ssd == sensor->src && sel->pad == CCS_PAD_SRC)
+ return 0;
+ if (ssd == sensor->scaler && sel->pad == CCS_PAD_SINK &&
+ CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
+ == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP)
+ return 0;
+ return -EINVAL;
+ case V4L2_SEL_TGT_NATIVE_SIZE:
+ if (ssd == sensor->pixel_array && sel->pad == CCS_PA_PAD_SRC)
+ return 0;
+ return -EINVAL;
+ case V4L2_SEL_TGT_COMPOSE:
+ case V4L2_SEL_TGT_COMPOSE_BOUNDS:
+ if (sel->pad == ssd->source_pad)
+ return -EINVAL;
+ if (ssd == sensor->binner)
+ return 0;
+ if (ssd == sensor->scaler && CCS_LIM(sensor, SCALING_CAPABILITY)
+ != CCS_SCALING_CAPABILITY_NONE)
+ return 0;
+ fallthrough;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int ccs_set_crop(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_selection *sel)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *src_size, *crops[CCS_PADS];
+ struct v4l2_rect _r;
+
+ ccs_get_crop_compose(subdev, sd_state, crops, NULL, sel->which);
+
+ if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+ if (sel->pad == ssd->sink_pad)
+ src_size = &ssd->sink_fmt;
+ else
+ src_size = &ssd->compose;
+ } else {
+ if (sel->pad == ssd->sink_pad) {
+ _r.left = 0;
+ _r.top = 0;
+ _r.width = v4l2_subdev_get_try_format(subdev,
+ sd_state,
+ sel->pad)
+ ->width;
+ _r.height = v4l2_subdev_get_try_format(subdev,
+ sd_state,
+ sel->pad)
+ ->height;
+ src_size = &_r;
+ } else {
+ src_size = v4l2_subdev_get_try_compose(
+ subdev, sd_state, ssd->sink_pad);
+ }
+ }
+
+ if (ssd == sensor->src && sel->pad == CCS_PAD_SRC) {
+ sel->r.left = 0;
+ sel->r.top = 0;
+ }
+
+ sel->r.width = min(sel->r.width, src_size->width);
+ sel->r.height = min(sel->r.height, src_size->height);
+
+ sel->r.left = min_t(int, sel->r.left, src_size->width - sel->r.width);
+ sel->r.top = min_t(int, sel->r.top, src_size->height - sel->r.height);
+
+ *crops[sel->pad] = sel->r;
+
+ if (ssd != sensor->pixel_array && sel->pad == CCS_PAD_SINK)
+ ccs_propagate(subdev, sd_state, sel->which, V4L2_SEL_TGT_CROP);
+
+ return 0;
+}
+
+static void ccs_get_native_size(struct ccs_subdev *ssd, struct v4l2_rect *r)
+{
+ r->top = 0;
+ r->left = 0;
+ r->width = CCS_LIM(ssd->sensor, X_ADDR_MAX) + 1;
+ r->height = CCS_LIM(ssd->sensor, Y_ADDR_MAX) + 1;
+}
+
+static int __ccs_get_selection(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_selection *sel)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_subdev *ssd = to_ccs_subdev(subdev);
+ struct v4l2_rect *comp, *crops[CCS_PADS];
+ struct v4l2_rect sink_fmt;
+ int ret;
+
+ ret = __ccs_sel_supported(subdev, sel);
+ if (ret)
+ return ret;
+
+ ccs_get_crop_compose(subdev, sd_state, crops, &comp, sel->which);
+
+ if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+ sink_fmt = ssd->sink_fmt;
+ } else {
+ struct v4l2_mbus_framefmt *fmt =
+ v4l2_subdev_get_try_format(subdev, sd_state,
+ ssd->sink_pad);
+
+ sink_fmt.left = 0;
+ sink_fmt.top = 0;
+ sink_fmt.width = fmt->width;
+ sink_fmt.height = fmt->height;
+ }
+
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP_BOUNDS:
+ case V4L2_SEL_TGT_NATIVE_SIZE:
+ if (ssd == sensor->pixel_array)
+ ccs_get_native_size(ssd, &sel->r);
+ else if (sel->pad == ssd->sink_pad)
+ sel->r = sink_fmt;
+ else
+ sel->r = *comp;
+ break;
+ case V4L2_SEL_TGT_CROP:
+ case V4L2_SEL_TGT_COMPOSE_BOUNDS:
+ sel->r = *crops[sel->pad];
+ break;
+ case V4L2_SEL_TGT_COMPOSE:
+ sel->r = *comp;
+ break;
+ }
+
+ return 0;
+}
+
+static int ccs_get_selection(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_selection *sel)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ int rval;
+
+ mutex_lock(&sensor->mutex);
+ rval = __ccs_get_selection(subdev, sd_state, sel);
+ mutex_unlock(&sensor->mutex);
+
+ return rval;
+}
+
+static int ccs_set_selection(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_selection *sel)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ int ret;
+
+ ret = __ccs_sel_supported(subdev, sel);
+ if (ret)
+ return ret;
+
+ mutex_lock(&sensor->mutex);
+
+ sel->r.left = max(0, sel->r.left & ~1);
+ sel->r.top = max(0, sel->r.top & ~1);
+ sel->r.width = CCS_ALIGN_DIM(sel->r.width, sel->flags);
+ sel->r.height = CCS_ALIGN_DIM(sel->r.height, sel->flags);
+
+ sel->r.width = max_t(unsigned int, CCS_LIM(sensor, MIN_X_OUTPUT_SIZE),
+ sel->r.width);
+ sel->r.height = max_t(unsigned int, CCS_LIM(sensor, MIN_Y_OUTPUT_SIZE),
+ sel->r.height);
+
+ switch (sel->target) {
+ case V4L2_SEL_TGT_CROP:
+ ret = ccs_set_crop(subdev, sd_state, sel);
+ break;
+ case V4L2_SEL_TGT_COMPOSE:
+ ret = ccs_set_compose(subdev, sd_state, sel);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ mutex_unlock(&sensor->mutex);
+ return ret;
+}
+
+static int ccs_get_skip_frames(struct v4l2_subdev *subdev, u32 *frames)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+
+ *frames = sensor->frame_skip;
+ return 0;
+}
+
+static int ccs_get_skip_top_lines(struct v4l2_subdev *subdev, u32 *lines)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+
+ *lines = sensor->image_start;
+
+ return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * sysfs attributes
+ */
+
+static ssize_t
+nvm_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct v4l2_subdev *subdev = i2c_get_clientdata(to_i2c_client(dev));
+ struct i2c_client *client = v4l2_get_subdevdata(subdev);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ int rval;
+
+ if (!sensor->dev_init_done)
+ return -EBUSY;
+
+ rval = ccs_pm_get_init(sensor);
+ if (rval < 0)
+ return -ENODEV;
+
+ rval = ccs_read_nvm(sensor, buf, PAGE_SIZE);
+ if (rval < 0) {
+ pm_runtime_put(&client->dev);
+ dev_err(&client->dev, "nvm read failed\n");
+ return -ENODEV;
+ }
+
+ pm_runtime_mark_last_busy(&client->dev);
+ pm_runtime_put_autosuspend(&client->dev);
+
+ /*
+ * NVM is still way below a PAGE_SIZE, so we can safely
+ * assume this for now.
+ */
+ return rval;
+}
+static DEVICE_ATTR_RO(nvm);
+
+static ssize_t
+ident_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+ struct v4l2_subdev *subdev = i2c_get_clientdata(to_i2c_client(dev));
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ struct ccs_module_info *minfo = &sensor->minfo;
+
+ if (minfo->mipi_manufacturer_id)
+ return sysfs_emit(buf, "%4.4x%4.4x%2.2x\n",
+ minfo->mipi_manufacturer_id, minfo->model_id,
+ minfo->revision_number) + 1;
+ else
+ return sysfs_emit(buf, "%2.2x%4.4x%2.2x\n",
+ minfo->smia_manufacturer_id, minfo->model_id,
+ minfo->revision_number) + 1;
+}
+static DEVICE_ATTR_RO(ident);
+
+/* -----------------------------------------------------------------------------
+ * V4L2 subdev core operations
+ */
+
+static int ccs_identify_module(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ struct ccs_module_info *minfo = &sensor->minfo;
+ unsigned int i;
+ u32 rev;
+ int rval = 0;
+
+ /* Module info */
+ rval = ccs_read(sensor, MODULE_MANUFACTURER_ID,
+ &minfo->mipi_manufacturer_id);
+ if (!rval && !minfo->mipi_manufacturer_id)
+ rval = ccs_read_addr_8only(sensor,
+ SMIAPP_REG_U8_MANUFACTURER_ID,
+ &minfo->smia_manufacturer_id);
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_MODEL_ID,
+ &minfo->model_id);
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_MODULE_REVISION_NUMBER_MAJOR,
+ &rev);
+ if (!rval) {
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_MODULE_REVISION_NUMBER_MINOR,
+ &minfo->revision_number);
+ minfo->revision_number |= rev << 8;
+ }
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_YEAR,
+ &minfo->module_year);
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_MONTH,
+ &minfo->module_month);
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor, CCS_R_MODULE_DATE_DAY,
+ &minfo->module_day);
+
+ /* Sensor info */
+ if (!rval)
+ rval = ccs_read(sensor, SENSOR_MANUFACTURER_ID,
+ &minfo->sensor_mipi_manufacturer_id);
+ if (!rval && !minfo->sensor_mipi_manufacturer_id)
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_MANUFACTURER_ID,
+ &minfo->sensor_smia_manufacturer_id);
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_MODEL_ID,
+ &minfo->sensor_model_id);
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_REVISION_NUMBER,
+ &minfo->sensor_revision_number);
+ if (!rval)
+ rval = ccs_read_addr_8only(sensor,
+ CCS_R_SENSOR_FIRMWARE_VERSION,
+ &minfo->sensor_firmware_version);
+
+ /* SMIA */
+ if (!rval)
+ rval = ccs_read(sensor, MIPI_CCS_VERSION, &minfo->ccs_version);
+ if (!rval && !minfo->ccs_version)
+ rval = ccs_read_addr_8only(sensor, SMIAPP_REG_U8_SMIA_VERSION,
+ &minfo->smia_version);
+ if (!rval && !minfo->ccs_version)
+ rval = ccs_read_addr_8only(sensor, SMIAPP_REG_U8_SMIAPP_VERSION,
+ &minfo->smiapp_version);
+
+ if (rval) {
+ dev_err(&client->dev, "sensor detection failed\n");
+ return -ENODEV;
+ }
+
+ if (minfo->mipi_manufacturer_id)
+ dev_dbg(&client->dev, "MIPI CCS module 0x%4.4x-0x%4.4x\n",
+ minfo->mipi_manufacturer_id, minfo->model_id);
+ else
+ dev_dbg(&client->dev, "SMIA module 0x%2.2x-0x%4.4x\n",
+ minfo->smia_manufacturer_id, minfo->model_id);
+
+ dev_dbg(&client->dev,
+ "module revision 0x%4.4x date %2.2d-%2.2d-%2.2d\n",
+ minfo->revision_number, minfo->module_year, minfo->module_month,
+ minfo->module_day);
+
+ if (minfo->sensor_mipi_manufacturer_id)
+ dev_dbg(&client->dev, "MIPI CCS sensor 0x%4.4x-0x%4.4x\n",
+ minfo->sensor_mipi_manufacturer_id,
+ minfo->sensor_model_id);
+ else
+ dev_dbg(&client->dev, "SMIA sensor 0x%2.2x-0x%4.4x\n",
+ minfo->sensor_smia_manufacturer_id,
+ minfo->sensor_model_id);
+
+ dev_dbg(&client->dev,
+ "sensor revision 0x%2.2x firmware version 0x%2.2x\n",
+ minfo->sensor_revision_number, minfo->sensor_firmware_version);
+
+ if (minfo->ccs_version) {
+ dev_dbg(&client->dev, "MIPI CCS version %u.%u",
+ (minfo->ccs_version & CCS_MIPI_CCS_VERSION_MAJOR_MASK)
+ >> CCS_MIPI_CCS_VERSION_MAJOR_SHIFT,
+ (minfo->ccs_version & CCS_MIPI_CCS_VERSION_MINOR_MASK));
+ minfo->name = CCS_NAME;
+ } else {
+ dev_dbg(&client->dev,
+ "smia version %2.2d smiapp version %2.2d\n",
+ minfo->smia_version, minfo->smiapp_version);
+ minfo->name = SMIAPP_NAME;
+ }
+
+ /*
+ * Some modules have bad data in the lvalues below. Hope the
+ * rvalues have better stuff. The lvalues are module
+ * parameters whereas the rvalues are sensor parameters.
+ */
+ if (minfo->sensor_smia_manufacturer_id &&
+ !minfo->smia_manufacturer_id && !minfo->model_id) {
+ minfo->smia_manufacturer_id =
+ minfo->sensor_smia_manufacturer_id;
+ minfo->model_id = minfo->sensor_model_id;
+ minfo->revision_number = minfo->sensor_revision_number;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(ccs_module_idents); i++) {
+ if (ccs_module_idents[i].mipi_manufacturer_id &&
+ ccs_module_idents[i].mipi_manufacturer_id
+ != minfo->mipi_manufacturer_id)
+ continue;
+ if (ccs_module_idents[i].smia_manufacturer_id &&
+ ccs_module_idents[i].smia_manufacturer_id
+ != minfo->smia_manufacturer_id)
+ continue;
+ if (ccs_module_idents[i].model_id != minfo->model_id)
+ continue;
+ if (ccs_module_idents[i].flags
+ & CCS_MODULE_IDENT_FLAG_REV_LE) {
+ if (ccs_module_idents[i].revision_number_major
+ < (minfo->revision_number >> 8))
+ continue;
+ } else {
+ if (ccs_module_idents[i].revision_number_major
+ != (minfo->revision_number >> 8))
+ continue;
+ }
+
+ minfo->name = ccs_module_idents[i].name;
+ minfo->quirk = ccs_module_idents[i].quirk;
+ break;
+ }
+
+ if (i >= ARRAY_SIZE(ccs_module_idents))
+ dev_warn(&client->dev,
+ "no quirks for this module; let's hope it's fully compliant\n");
+
+ dev_dbg(&client->dev, "the sensor is called %s\n", minfo->name);
+
+ return 0;
+}
+
+static const struct v4l2_subdev_ops ccs_ops;
+static const struct v4l2_subdev_internal_ops ccs_internal_ops;
+static const struct media_entity_operations ccs_entity_ops;
+
+static int ccs_register_subdev(struct ccs_sensor *sensor,
+ struct ccs_subdev *ssd,
+ struct ccs_subdev *sink_ssd,
+ u16 source_pad, u16 sink_pad, u32 link_flags)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+
+ if (!sink_ssd)
+ return 0;
+
+ rval = media_entity_pads_init(&ssd->sd.entity, ssd->npads, ssd->pads);
+ if (rval) {
+ dev_err(&client->dev, "media_entity_pads_init failed\n");
+ return rval;
+ }
+
+ rval = v4l2_device_register_subdev(sensor->src->sd.v4l2_dev, &ssd->sd);
+ if (rval) {
+ dev_err(&client->dev, "v4l2_device_register_subdev failed\n");
+ return rval;
+ }
+
+ rval = media_create_pad_link(&ssd->sd.entity, source_pad,
+ &sink_ssd->sd.entity, sink_pad,
+ link_flags);
+ if (rval) {
+ dev_err(&client->dev, "media_create_pad_link failed\n");
+ v4l2_device_unregister_subdev(&ssd->sd);
+ return rval;
+ }
+
+ return 0;
+}
+
+static void ccs_unregistered(struct v4l2_subdev *subdev)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ unsigned int i;
+
+ for (i = 1; i < sensor->ssds_used; i++)
+ v4l2_device_unregister_subdev(&sensor->ssds[i].sd);
+}
+
+static int ccs_registered(struct v4l2_subdev *subdev)
+{
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ int rval;
+
+ if (sensor->scaler) {
+ rval = ccs_register_subdev(sensor, sensor->binner,
+ sensor->scaler,
+ CCS_PAD_SRC, CCS_PAD_SINK,
+ MEDIA_LNK_FL_ENABLED |
+ MEDIA_LNK_FL_IMMUTABLE);
+ if (rval < 0)
+ return rval;
+ }
+
+ rval = ccs_register_subdev(sensor, sensor->pixel_array, sensor->binner,
+ CCS_PA_PAD_SRC, CCS_PAD_SINK,
+ MEDIA_LNK_FL_ENABLED |
+ MEDIA_LNK_FL_IMMUTABLE);
+ if (rval)
+ goto out_err;
+
+ return 0;
+
+out_err:
+ ccs_unregistered(subdev);
+
+ return rval;
+}
+
+static void ccs_cleanup(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+
+ device_remove_file(&client->dev, &dev_attr_nvm);
+ device_remove_file(&client->dev, &dev_attr_ident);
+
+ ccs_free_controls(sensor);
+}
+
+static void ccs_create_subdev(struct ccs_sensor *sensor,
+ struct ccs_subdev *ssd, const char *name,
+ unsigned short num_pads, u32 function)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+
+ if (!ssd)
+ return;
+
+ if (ssd != sensor->src)
+ v4l2_subdev_init(&ssd->sd, &ccs_ops);
+
+ ssd->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+ ssd->sd.entity.function = function;
+ ssd->sensor = sensor;
+
+ ssd->npads = num_pads;
+ ssd->source_pad = num_pads - 1;
+
+ v4l2_i2c_subdev_set_name(&ssd->sd, client, sensor->minfo.name, name);
+
+ ccs_get_native_size(ssd, &ssd->sink_fmt);
+
+ ssd->compose.width = ssd->sink_fmt.width;
+ ssd->compose.height = ssd->sink_fmt.height;
+ ssd->crop[ssd->source_pad] = ssd->compose;
+ ssd->pads[ssd->source_pad].flags = MEDIA_PAD_FL_SOURCE;
+ if (ssd != sensor->pixel_array) {
+ ssd->crop[ssd->sink_pad] = ssd->compose;
+ ssd->pads[ssd->sink_pad].flags = MEDIA_PAD_FL_SINK;
+ }
+
+ ssd->sd.entity.ops = &ccs_entity_ops;
+
+ if (ssd == sensor->src)
+ return;
+
+ ssd->sd.internal_ops = &ccs_internal_ops;
+ ssd->sd.owner = THIS_MODULE;
+ ssd->sd.dev = &client->dev;
+ v4l2_set_subdevdata(&ssd->sd, client);
+}
+
+static int ccs_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+ struct ccs_subdev *ssd = to_ccs_subdev(sd);
+ struct ccs_sensor *sensor = ssd->sensor;
+ unsigned int i;
+
+ mutex_lock(&sensor->mutex);
+
+ for (i = 0; i < ssd->npads; i++) {
+ struct v4l2_mbus_framefmt *try_fmt =
+ v4l2_subdev_get_try_format(sd, fh->state, i);
+ struct v4l2_rect *try_crop =
+ v4l2_subdev_get_try_crop(sd, fh->state, i);
+ struct v4l2_rect *try_comp;
+
+ ccs_get_native_size(ssd, try_crop);
+
+ try_fmt->width = try_crop->width;
+ try_fmt->height = try_crop->height;
+ try_fmt->code = sensor->internal_csi_format->code;
+ try_fmt->field = V4L2_FIELD_NONE;
+
+ if (ssd == sensor->pixel_array)
+ continue;
+
+ try_comp = v4l2_subdev_get_try_compose(sd, fh->state, i);
+ *try_comp = *try_crop;
+ }
+
+ mutex_unlock(&sensor->mutex);
+
+ return 0;
+}
+
+static const struct v4l2_subdev_video_ops ccs_video_ops = {
+ .s_stream = ccs_set_stream,
+ .pre_streamon = ccs_pre_streamon,
+ .post_streamoff = ccs_post_streamoff,
+};
+
+static const struct v4l2_subdev_pad_ops ccs_pad_ops = {
+ .enum_mbus_code = ccs_enum_mbus_code,
+ .get_fmt = ccs_get_format,
+ .set_fmt = ccs_set_format,
+ .get_selection = ccs_get_selection,
+ .set_selection = ccs_set_selection,
+};
+
+static const struct v4l2_subdev_sensor_ops ccs_sensor_ops = {
+ .g_skip_frames = ccs_get_skip_frames,
+ .g_skip_top_lines = ccs_get_skip_top_lines,
+};
+
+static const struct v4l2_subdev_ops ccs_ops = {
+ .video = &ccs_video_ops,
+ .pad = &ccs_pad_ops,
+ .sensor = &ccs_sensor_ops,
+};
+
+static const struct media_entity_operations ccs_entity_ops = {
+ .link_validate = v4l2_subdev_link_validate,
+};
+
+static const struct v4l2_subdev_internal_ops ccs_internal_src_ops = {
+ .registered = ccs_registered,
+ .unregistered = ccs_unregistered,
+ .open = ccs_open,
+};
+
+static const struct v4l2_subdev_internal_ops ccs_internal_ops = {
+ .open = ccs_open,
+};
+
+/* -----------------------------------------------------------------------------
+ * I2C Driver
+ */
+
+static int __maybe_unused ccs_suspend(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *subdev = i2c_get_clientdata(client);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ bool streaming = sensor->streaming;
+ int rval;
+
+ rval = pm_runtime_resume_and_get(dev);
+ if (rval < 0)
+ return rval;
+
+ if (sensor->streaming)
+ ccs_stop_streaming(sensor);
+
+ /* save state for resume */
+ sensor->streaming = streaming;
+
+ return 0;
+}
+
+static int __maybe_unused ccs_resume(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *subdev = i2c_get_clientdata(client);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ int rval = 0;
+
+ pm_runtime_put(dev);
+
+ if (sensor->streaming)
+ rval = ccs_start_streaming(sensor);
+
+ return rval;
+}
+
+static int ccs_get_hwconfig(struct ccs_sensor *sensor, struct device *dev)
+{
+ struct ccs_hwconfig *hwcfg = &sensor->hwcfg;
+ struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = V4L2_MBUS_UNKNOWN };
+ struct fwnode_handle *ep;
+ struct fwnode_handle *fwnode = dev_fwnode(dev);
+ u32 rotation;
+ unsigned int i;
+ int rval;
+
+ ep = fwnode_graph_get_endpoint_by_id(fwnode, 0, 0,
+ FWNODE_GRAPH_ENDPOINT_NEXT);
+ if (!ep)
+ return -ENODEV;
+
+ /*
+ * Note that we do need to rely on detecting the bus type between CSI-2
+ * D-PHY and CCP2 as the old bindings did not require it.
+ */
+ rval = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
+ if (rval)
+ goto out_err;
+
+ switch (bus_cfg.bus_type) {
+ case V4L2_MBUS_CSI2_DPHY:
+ hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_DPHY;
+ hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
+ break;
+ case V4L2_MBUS_CSI2_CPHY:
+ hwcfg->csi_signalling_mode = CCS_CSI_SIGNALING_MODE_CSI_2_CPHY;
+ hwcfg->lanes = bus_cfg.bus.mipi_csi2.num_data_lanes;
+ break;
+ case V4L2_MBUS_CSI1:
+ case V4L2_MBUS_CCP2:
+ hwcfg->csi_signalling_mode = (bus_cfg.bus.mipi_csi1.strobe) ?
+ SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE :
+ SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_CLOCK;
+ hwcfg->lanes = 1;
+ break;
+ default:
+ dev_err(dev, "unsupported bus %u\n", bus_cfg.bus_type);
+ rval = -EINVAL;
+ goto out_err;
+ }
+
+ rval = fwnode_property_read_u32(fwnode, "rotation", &rotation);
+ if (!rval) {
+ switch (rotation) {
+ case 180:
+ hwcfg->module_board_orient =
+ CCS_MODULE_BOARD_ORIENT_180;
+ fallthrough;
+ case 0:
+ break;
+ default:
+ dev_err(dev, "invalid rotation %u\n", rotation);
+ rval = -EINVAL;
+ goto out_err;
+ }
+ }
+
+ rval = fwnode_property_read_u32(dev_fwnode(dev), "clock-frequency",
+ &hwcfg->ext_clk);
+ if (rval)
+ dev_info(dev, "can't get clock-frequency\n");
+
+ dev_dbg(dev, "clk %u, mode %u\n", hwcfg->ext_clk,
+ hwcfg->csi_signalling_mode);
+
+ if (!bus_cfg.nr_of_link_frequencies) {
+ dev_warn(dev, "no link frequencies defined\n");
+ rval = -EINVAL;
+ goto out_err;
+ }
+
+ hwcfg->op_sys_clock = devm_kcalloc(
+ dev, bus_cfg.nr_of_link_frequencies + 1 /* guardian */,
+ sizeof(*hwcfg->op_sys_clock), GFP_KERNEL);
+ if (!hwcfg->op_sys_clock) {
+ rval = -ENOMEM;
+ goto out_err;
+ }
+
+ for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
+ hwcfg->op_sys_clock[i] = bus_cfg.link_frequencies[i];
+ dev_dbg(dev, "freq %u: %lld\n", i, hwcfg->op_sys_clock[i]);
+ }
+
+ v4l2_fwnode_endpoint_free(&bus_cfg);
+ fwnode_handle_put(ep);
+
+ return 0;
+
+out_err:
+ v4l2_fwnode_endpoint_free(&bus_cfg);
+ fwnode_handle_put(ep);
+
+ return rval;
+}
+
+static int ccs_probe(struct i2c_client *client)
+{
+ struct ccs_sensor *sensor;
+ const struct firmware *fw;
+ char filename[40];
+ unsigned int i;
+ int rval;
+
+ sensor = devm_kzalloc(&client->dev, sizeof(*sensor), GFP_KERNEL);
+ if (sensor == NULL)
+ return -ENOMEM;
+
+ rval = ccs_get_hwconfig(sensor, &client->dev);
+ if (rval)
+ return rval;
+
+ sensor->src = &sensor->ssds[sensor->ssds_used];
+
+ v4l2_i2c_subdev_init(&sensor->src->sd, client, &ccs_ops);
+ sensor->src->sd.internal_ops = &ccs_internal_src_ops;
+
+ sensor->regulators = devm_kcalloc(&client->dev,
+ ARRAY_SIZE(ccs_regulators),
+ sizeof(*sensor->regulators),
+ GFP_KERNEL);
+ if (!sensor->regulators)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(ccs_regulators); i++)
+ sensor->regulators[i].supply = ccs_regulators[i];
+
+ rval = devm_regulator_bulk_get(&client->dev, ARRAY_SIZE(ccs_regulators),
+ sensor->regulators);
+ if (rval) {
+ dev_err(&client->dev, "could not get regulators\n");
+ return rval;
+ }
+
+ sensor->ext_clk = devm_clk_get(&client->dev, NULL);
+ if (PTR_ERR(sensor->ext_clk) == -ENOENT) {
+ dev_info(&client->dev, "no clock defined, continuing...\n");
+ sensor->ext_clk = NULL;
+ } else if (IS_ERR(sensor->ext_clk)) {
+ dev_err(&client->dev, "could not get clock (%ld)\n",
+ PTR_ERR(sensor->ext_clk));
+ return -EPROBE_DEFER;
+ }
+
+ if (sensor->ext_clk) {
+ if (sensor->hwcfg.ext_clk) {
+ unsigned long rate;
+
+ rval = clk_set_rate(sensor->ext_clk,
+ sensor->hwcfg.ext_clk);
+ if (rval < 0) {
+ dev_err(&client->dev,
+ "unable to set clock freq to %u\n",
+ sensor->hwcfg.ext_clk);
+ return rval;
+ }
+
+ rate = clk_get_rate(sensor->ext_clk);
+ if (rate != sensor->hwcfg.ext_clk) {
+ dev_err(&client->dev,
+ "can't set clock freq, asked for %u but got %lu\n",
+ sensor->hwcfg.ext_clk, rate);
+ return -EINVAL;
+ }
+ } else {
+ sensor->hwcfg.ext_clk = clk_get_rate(sensor->ext_clk);
+ dev_dbg(&client->dev, "obtained clock freq %u\n",
+ sensor->hwcfg.ext_clk);
+ }
+ } else if (sensor->hwcfg.ext_clk) {
+ dev_dbg(&client->dev, "assuming clock freq %u\n",
+ sensor->hwcfg.ext_clk);
+ } else {
+ dev_err(&client->dev, "unable to obtain clock freq\n");
+ return -EINVAL;
+ }
+
+ if (!sensor->hwcfg.ext_clk) {
+ dev_err(&client->dev, "cannot work with xclk frequency 0\n");
+ return -EINVAL;
+ }
+
+ sensor->reset = devm_gpiod_get_optional(&client->dev, "reset",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(sensor->reset))
+ return PTR_ERR(sensor->reset);
+ /* Support old users that may have used "xshutdown" property. */
+ if (!sensor->reset)
+ sensor->xshutdown = devm_gpiod_get_optional(&client->dev,
+ "xshutdown",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(sensor->xshutdown))
+ return PTR_ERR(sensor->xshutdown);
+
+ rval = ccs_power_on(&client->dev);
+ if (rval < 0)
+ return rval;
+
+ mutex_init(&sensor->mutex);
+
+ rval = ccs_identify_module(sensor);
+ if (rval) {
+ rval = -ENODEV;
+ goto out_power_off;
+ }
+
+ rval = snprintf(filename, sizeof(filename),
+ "ccs/ccs-sensor-%4.4x-%4.4x-%4.4x.fw",
+ sensor->minfo.sensor_mipi_manufacturer_id,
+ sensor->minfo.sensor_model_id,
+ sensor->minfo.sensor_revision_number);
+ if (rval >= sizeof(filename)) {
+ rval = -ENOMEM;
+ goto out_power_off;
+ }
+
+ rval = request_firmware(&fw, filename, &client->dev);
+ if (!rval) {
+ ccs_data_parse(&sensor->sdata, fw->data, fw->size, &client->dev,
+ true);
+ release_firmware(fw);
+ }
+
+ rval = snprintf(filename, sizeof(filename),
+ "ccs/ccs-module-%4.4x-%4.4x-%4.4x.fw",
+ sensor->minfo.mipi_manufacturer_id,
+ sensor->minfo.model_id,
+ sensor->minfo.revision_number);
+ if (rval >= sizeof(filename)) {
+ rval = -ENOMEM;
+ goto out_release_sdata;
+ }
+
+ rval = request_firmware(&fw, filename, &client->dev);
+ if (!rval) {
+ ccs_data_parse(&sensor->mdata, fw->data, fw->size, &client->dev,
+ true);
+ release_firmware(fw);
+ }
+
+ rval = ccs_read_all_limits(sensor);
+ if (rval)
+ goto out_release_mdata;
+
+ rval = ccs_read_frame_fmt(sensor);
+ if (rval) {
+ rval = -ENODEV;
+ goto out_free_ccs_limits;
+ }
+
+ rval = ccs_update_phy_ctrl(sensor);
+ if (rval < 0)
+ goto out_free_ccs_limits;
+
+ /*
+ * Handle Sensor Module orientation on the board.
+ *
+ * The application of H-FLIP and V-FLIP on the sensor is modified by
+ * the sensor orientation on the board.
+ *
+ * For CCS_BOARD_SENSOR_ORIENT_180 the default behaviour is to set
+ * both H-FLIP and V-FLIP for normal operation which also implies
+ * that a set/unset operation for user space HFLIP and VFLIP v4l2
+ * controls will need to be internally inverted.
+ *
+ * Rotation also changes the bayer pattern.
+ */
+ if (sensor->hwcfg.module_board_orient ==
+ CCS_MODULE_BOARD_ORIENT_180)
+ sensor->hvflip_inv_mask =
+ CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR |
+ CCS_IMAGE_ORIENTATION_VERTICAL_FLIP;
+
+ rval = ccs_call_quirk(sensor, limits);
+ if (rval) {
+ dev_err(&client->dev, "limits quirks failed\n");
+ goto out_free_ccs_limits;
+ }
+
+ if (CCS_LIM(sensor, BINNING_CAPABILITY)) {
+ sensor->nbinning_subtypes =
+ min_t(u8, CCS_LIM(sensor, BINNING_SUB_TYPES),
+ CCS_LIM_BINNING_SUB_TYPE_MAX_N);
+
+ for (i = 0; i < sensor->nbinning_subtypes; i++) {
+ sensor->binning_subtypes[i].horizontal =
+ CCS_LIM_AT(sensor, BINNING_SUB_TYPE, i) >>
+ CCS_BINNING_SUB_TYPE_COLUMN_SHIFT;
+ sensor->binning_subtypes[i].vertical =
+ CCS_LIM_AT(sensor, BINNING_SUB_TYPE, i) &
+ CCS_BINNING_SUB_TYPE_ROW_MASK;
+
+ dev_dbg(&client->dev, "binning %xx%x\n",
+ sensor->binning_subtypes[i].horizontal,
+ sensor->binning_subtypes[i].vertical);
+ }
+ }
+ sensor->binning_horizontal = 1;
+ sensor->binning_vertical = 1;
+
+ if (device_create_file(&client->dev, &dev_attr_ident) != 0) {
+ dev_err(&client->dev, "sysfs ident entry creation failed\n");
+ rval = -ENOENT;
+ goto out_free_ccs_limits;
+ }
+
+ if (sensor->minfo.smiapp_version &&
+ CCS_LIM(sensor, DATA_TRANSFER_IF_CAPABILITY) &
+ CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED) {
+ if (device_create_file(&client->dev, &dev_attr_nvm) != 0) {
+ dev_err(&client->dev, "sysfs nvm entry failed\n");
+ rval = -EBUSY;
+ goto out_cleanup;
+ }
+ }
+
+ if (!CCS_LIM(sensor, MIN_OP_SYS_CLK_DIV) ||
+ !CCS_LIM(sensor, MAX_OP_SYS_CLK_DIV) ||
+ !CCS_LIM(sensor, MIN_OP_PIX_CLK_DIV) ||
+ !CCS_LIM(sensor, MAX_OP_PIX_CLK_DIV)) {
+ /* No OP clock branch */
+ sensor->pll.flags |= CCS_PLL_FLAG_NO_OP_CLOCKS;
+ } else if (CCS_LIM(sensor, SCALING_CAPABILITY)
+ != CCS_SCALING_CAPABILITY_NONE ||
+ CCS_LIM(sensor, DIGITAL_CROP_CAPABILITY)
+ == CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP) {
+ /* We have a scaler or digital crop. */
+ sensor->scaler = &sensor->ssds[sensor->ssds_used];
+ sensor->ssds_used++;
+ }
+ sensor->binner = &sensor->ssds[sensor->ssds_used];
+ sensor->ssds_used++;
+ sensor->pixel_array = &sensor->ssds[sensor->ssds_used];
+ sensor->ssds_used++;
+
+ sensor->scale_m = CCS_LIM(sensor, SCALER_N_MIN);
+
+ /* prepare PLL configuration input values */
+ sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY;
+ sensor->pll.csi2.lanes = sensor->hwcfg.lanes;
+ if (CCS_LIM(sensor, CLOCK_CALCULATION) &
+ CCS_CLOCK_CALCULATION_LANE_SPEED) {
+ sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL;
+ if (CCS_LIM(sensor, CLOCK_CALCULATION) &
+ CCS_CLOCK_CALCULATION_LINK_DECOUPLED) {
+ sensor->pll.vt_lanes =
+ CCS_LIM(sensor, NUM_OF_VT_LANES) + 1;
+ sensor->pll.op_lanes =
+ CCS_LIM(sensor, NUM_OF_OP_LANES) + 1;
+ sensor->pll.flags |= CCS_PLL_FLAG_LINK_DECOUPLED;
+ } else {
+ sensor->pll.vt_lanes = sensor->pll.csi2.lanes;
+ sensor->pll.op_lanes = sensor->pll.csi2.lanes;
+ }
+ }
+ if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
+ CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER)
+ sensor->pll.flags |= CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER;
+ if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
+ CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV)
+ sensor->pll.flags |= CCS_PLL_FLAG_FLEXIBLE_OP_PIX_CLK_DIV;
+ if (CCS_LIM(sensor, FIFO_SUPPORT_CAPABILITY) &
+ CCS_FIFO_SUPPORT_CAPABILITY_DERATING)
+ sensor->pll.flags |= CCS_PLL_FLAG_FIFO_DERATING;
+ if (CCS_LIM(sensor, FIFO_SUPPORT_CAPABILITY) &
+ CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING)
+ sensor->pll.flags |= CCS_PLL_FLAG_FIFO_DERATING |
+ CCS_PLL_FLAG_FIFO_OVERRATING;
+ if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
+ CCS_CLOCK_TREE_PLL_CAPABILITY_DUAL_PLL) {
+ if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) &
+ CCS_CLOCK_TREE_PLL_CAPABILITY_SINGLE_PLL) {
+ u32 v;
+
+ /* Use sensor default in PLL mode selection */
+ rval = ccs_read(sensor, PLL_MODE, &v);
+ if (rval)
+ goto out_cleanup;
+
+ if (v == CCS_PLL_MODE_DUAL)
+ sensor->pll.flags |= CCS_PLL_FLAG_DUAL_PLL;
+ } else {
+ sensor->pll.flags |= CCS_PLL_FLAG_DUAL_PLL;
+ }
+ if (CCS_LIM(sensor, CLOCK_CALCULATION) &
+ CCS_CLOCK_CALCULATION_DUAL_PLL_OP_SYS_DDR)
+ sensor->pll.flags |= CCS_PLL_FLAG_OP_SYS_DDR;
+ if (CCS_LIM(sensor, CLOCK_CALCULATION) &
+ CCS_CLOCK_CALCULATION_DUAL_PLL_OP_PIX_DDR)
+ sensor->pll.flags |= CCS_PLL_FLAG_OP_PIX_DDR;
+ }
+ sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE);
+ sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
+ sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);
+
+ ccs_create_subdev(sensor, sensor->scaler, " scaler", 2,
+ MEDIA_ENT_F_PROC_VIDEO_SCALER);
+ ccs_create_subdev(sensor, sensor->binner, " binner", 2,
+ MEDIA_ENT_F_PROC_VIDEO_SCALER);
+ ccs_create_subdev(sensor, sensor->pixel_array, " pixel_array", 1,
+ MEDIA_ENT_F_CAM_SENSOR);
+
+ rval = ccs_init_controls(sensor);
+ if (rval < 0)
+ goto out_cleanup;
+
+ rval = ccs_call_quirk(sensor, init);
+ if (rval)
+ goto out_cleanup;
+
+ rval = ccs_get_mbus_formats(sensor);
+ if (rval) {
+ rval = -ENODEV;
+ goto out_cleanup;
+ }
+
+ rval = ccs_init_late_controls(sensor);
+ if (rval) {
+ rval = -ENODEV;
+ goto out_cleanup;
+ }
+
+ mutex_lock(&sensor->mutex);
+ rval = ccs_pll_blanking_update(sensor);
+ mutex_unlock(&sensor->mutex);
+ if (rval) {
+ dev_err(&client->dev, "update mode failed\n");
+ goto out_cleanup;
+ }
+
+ sensor->streaming = false;
+ sensor->dev_init_done = true;
+
+ rval = media_entity_pads_init(&sensor->src->sd.entity, 2,
+ sensor->src->pads);
+ if (rval < 0)
+ goto out_media_entity_cleanup;
+
+ rval = ccs_write_msr_regs(sensor);
+ if (rval)
+ goto out_media_entity_cleanup;
+
+ pm_runtime_set_active(&client->dev);
+ pm_runtime_get_noresume(&client->dev);
+ pm_runtime_enable(&client->dev);
+
+ rval = v4l2_async_register_subdev_sensor(&sensor->src->sd);
+ if (rval < 0)
+ goto out_disable_runtime_pm;
+
+ pm_runtime_set_autosuspend_delay(&client->dev, 1000);
+ pm_runtime_use_autosuspend(&client->dev);
+ pm_runtime_put_autosuspend(&client->dev);
+
+ return 0;
+
+out_disable_runtime_pm:
+ pm_runtime_put_noidle(&client->dev);
+ pm_runtime_disable(&client->dev);
+
+out_media_entity_cleanup:
+ media_entity_cleanup(&sensor->src->sd.entity);
+
+out_cleanup:
+ ccs_cleanup(sensor);
+
+out_release_mdata:
+ kvfree(sensor->mdata.backing);
+
+out_release_sdata:
+ kvfree(sensor->sdata.backing);
+
+out_free_ccs_limits:
+ kfree(sensor->ccs_limits);
+
+out_power_off:
+ ccs_power_off(&client->dev);
+ mutex_destroy(&sensor->mutex);
+
+ return rval;
+}
+
+static void ccs_remove(struct i2c_client *client)
+{
+ struct v4l2_subdev *subdev = i2c_get_clientdata(client);
+ struct ccs_sensor *sensor = to_ccs_sensor(subdev);
+ unsigned int i;
+
+ v4l2_async_unregister_subdev(subdev);
+
+ pm_runtime_disable(&client->dev);
+ if (!pm_runtime_status_suspended(&client->dev))
+ ccs_power_off(&client->dev);
+ pm_runtime_set_suspended(&client->dev);
+
+ for (i = 0; i < sensor->ssds_used; i++) {
+ v4l2_device_unregister_subdev(&sensor->ssds[i].sd);
+ media_entity_cleanup(&sensor->ssds[i].sd.entity);
+ }
+ ccs_cleanup(sensor);
+ mutex_destroy(&sensor->mutex);
+ kfree(sensor->ccs_limits);
+ kvfree(sensor->sdata.backing);
+ kvfree(sensor->mdata.backing);
+}
+
+static const struct ccs_device smia_device = {
+ .flags = CCS_DEVICE_FLAG_IS_SMIA,
+};
+
+static const struct ccs_device ccs_device = {};
+
+static const struct acpi_device_id ccs_acpi_table[] = {
+ { .id = "MIPI0200", .driver_data = (unsigned long)&ccs_device },
+ { },
+};
+MODULE_DEVICE_TABLE(acpi, ccs_acpi_table);
+
+static const struct of_device_id ccs_of_table[] = {
+ { .compatible = "mipi-ccs-1.1", .data = &ccs_device },
+ { .compatible = "mipi-ccs-1.0", .data = &ccs_device },
+ { .compatible = "mipi-ccs", .data = &ccs_device },
+ { .compatible = "nokia,smia", .data = &smia_device },
+ { },
+};
+MODULE_DEVICE_TABLE(of, ccs_of_table);
+
+static const struct dev_pm_ops ccs_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(ccs_suspend, ccs_resume)
+ SET_RUNTIME_PM_OPS(ccs_power_off, ccs_power_on, NULL)
+};
+
+static struct i2c_driver ccs_i2c_driver = {
+ .driver = {
+ .acpi_match_table = ccs_acpi_table,
+ .of_match_table = ccs_of_table,
+ .name = CCS_NAME,
+ .pm = &ccs_pm_ops,
+ },
+ .probe_new = ccs_probe,
+ .remove = ccs_remove,
+};
+
+static int ccs_module_init(void)
+{
+ unsigned int i, l;
+
+ for (i = 0, l = 0; ccs_limits[i].size && l < CCS_L_LAST; i++) {
+ if (!(ccs_limits[i].flags & CCS_L_FL_SAME_REG)) {
+ ccs_limit_offsets[l + 1].lim =
+ ALIGN(ccs_limit_offsets[l].lim +
+ ccs_limits[i].size,
+ ccs_reg_width(ccs_limits[i + 1].reg));
+ ccs_limit_offsets[l].info = i;
+ l++;
+ } else {
+ ccs_limit_offsets[l].lim += ccs_limits[i].size;
+ }
+ }
+
+ if (WARN_ON(ccs_limits[i].size))
+ return -EINVAL;
+
+ if (WARN_ON(l != CCS_L_LAST))
+ return -EINVAL;
+
+ return i2c_register_driver(THIS_MODULE, &ccs_i2c_driver);
+}
+
+static void ccs_module_cleanup(void)
+{
+ i2c_del_driver(&ccs_i2c_driver);
+}
+
+module_init(ccs_module_init);
+module_exit(ccs_module_cleanup);
+
+MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>");
+MODULE_DESCRIPTION("Generic MIPI CCS/SMIA/SMIA++ camera sensor driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("smiapp");
diff --git a/drivers/media/i2c/ccs/ccs-data-defs.h b/drivers/media/i2c/ccs/ccs-data-defs.h
new file mode 100644
index 000000000..1c9b1d1ac
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-data-defs.h
@@ -0,0 +1,221 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
+/*
+ * CCS static data binary format definitions
+ *
+ * Copyright 2019--2020 Intel Corporation
+ */
+
+#ifndef __CCS_DATA_DEFS_H__
+#define __CCS_DATA_DEFS_H__
+
+#include "ccs-data.h"
+
+#define CCS_STATIC_DATA_VERSION 0
+
+enum __ccs_data_length_specifier_id {
+ CCS_DATA_LENGTH_SPECIFIER_1 = 0,
+ CCS_DATA_LENGTH_SPECIFIER_2 = 1,
+ CCS_DATA_LENGTH_SPECIFIER_3 = 2
+};
+
+#define CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT 6
+
+struct __ccs_data_length_specifier {
+ u8 length;
+} __packed;
+
+struct __ccs_data_length_specifier2 {
+ u8 length[2];
+} __packed;
+
+struct __ccs_data_length_specifier3 {
+ u8 length[3];
+} __packed;
+
+struct __ccs_data_block {
+ u8 id;
+ struct __ccs_data_length_specifier length;
+} __packed;
+
+#define CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT 5
+
+struct __ccs_data_block3 {
+ u8 id;
+ struct __ccs_data_length_specifier2 length;
+} __packed;
+
+struct __ccs_data_block4 {
+ u8 id;
+ struct __ccs_data_length_specifier3 length;
+} __packed;
+
+enum __ccs_data_block_id {
+ CCS_DATA_BLOCK_ID_DUMMY = 1,
+ CCS_DATA_BLOCK_ID_DATA_VERSION = 2,
+ CCS_DATA_BLOCK_ID_SENSOR_READ_ONLY_REGS = 3,
+ CCS_DATA_BLOCK_ID_MODULE_READ_ONLY_REGS = 4,
+ CCS_DATA_BLOCK_ID_SENSOR_MANUFACTURER_REGS = 5,
+ CCS_DATA_BLOCK_ID_MODULE_MANUFACTURER_REGS = 6,
+ CCS_DATA_BLOCK_ID_SENSOR_RULE_BASED_BLOCK = 32,
+ CCS_DATA_BLOCK_ID_MODULE_RULE_BASED_BLOCK = 33,
+ CCS_DATA_BLOCK_ID_SENSOR_PDAF_PIXEL_LOCATION = 36,
+ CCS_DATA_BLOCK_ID_MODULE_PDAF_PIXEL_LOCATION = 37,
+ CCS_DATA_BLOCK_ID_LICENSE = 40,
+ CCS_DATA_BLOCK_ID_END = 127,
+};
+
+struct __ccs_data_block_version {
+ u8 static_data_version_major[2];
+ u8 static_data_version_minor[2];
+ u8 year[2];
+ u8 month;
+ u8 day;
+} __packed;
+
+struct __ccs_data_block_regs {
+ u8 reg_len;
+} __packed;
+
+#define CCS_DATA_BLOCK_REGS_ADDR_MASK 0x07
+#define CCS_DATA_BLOCK_REGS_LEN_SHIFT 3
+#define CCS_DATA_BLOCK_REGS_LEN_MASK 0x38
+#define CCS_DATA_BLOCK_REGS_SEL_SHIFT 6
+
+enum ccs_data_block_regs_sel {
+ CCS_DATA_BLOCK_REGS_SEL_REGS = 0,
+ CCS_DATA_BLOCK_REGS_SEL_REGS2 = 1,
+ CCS_DATA_BLOCK_REGS_SEL_REGS3 = 2,
+};
+
+struct __ccs_data_block_regs2 {
+ u8 reg_len;
+ u8 addr;
+} __packed;
+
+#define CCS_DATA_BLOCK_REGS_2_ADDR_MASK 0x01
+#define CCS_DATA_BLOCK_REGS_2_LEN_SHIFT 1
+#define CCS_DATA_BLOCK_REGS_2_LEN_MASK 0x3e
+
+struct __ccs_data_block_regs3 {
+ u8 reg_len;
+ u8 addr[2];
+} __packed;
+
+#define CCS_DATA_BLOCK_REGS_3_LEN_MASK 0x3f
+
+enum __ccs_data_ffd_pixelcode {
+ CCS_DATA_BLOCK_FFD_PIXELCODE_EMBEDDED = 1,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_DUMMY = 2,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BLACK = 3,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_DARK = 4,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_VISIBLE = 5,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_0 = 8,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_1 = 9,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_2 = 10,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_3 = 11,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_4 = 12,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_5 = 13,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_MS_6 = 14,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_OB = 16,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_OB = 17,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_LEFT_OB = 18,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_RIGHT_OB = 19,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_LEFT_OB = 20,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_RIGHT_OB = 21,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_LEFT_OB = 22,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_RIGHT_OB = 23,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOTAL = 24,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_PDAF = 32,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_PDAF = 33,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_LEFT_PDAF = 34,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_RIGHT_PDAF = 35,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_LEFT_PDAF = 36,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_TOP_RIGHT_PDAF = 37,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_LEFT_PDAF = 38,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_BOTTOM_RIGHT_PDAF = 39,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_SEPARATED_PDAF = 40,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_ORIGINAL_ORDER_PDAF = 41,
+ CCS_DATA_BLOCK_FFD_PIXELCODE_VENDOR_PDAF = 41,
+};
+
+struct __ccs_data_block_ffd_entry {
+ u8 pixelcode;
+ u8 reserved;
+ u8 value[2];
+} __packed;
+
+struct __ccs_data_block_ffd {
+ u8 num_column_descs;
+ u8 num_row_descs;
+} __packed;
+
+enum __ccs_data_block_rule_id {
+ CCS_DATA_BLOCK_RULE_ID_IF = 1,
+ CCS_DATA_BLOCK_RULE_ID_READ_ONLY_REGS = 2,
+ CCS_DATA_BLOCK_RULE_ID_FFD = 3,
+ CCS_DATA_BLOCK_RULE_ID_MSR = 4,
+ CCS_DATA_BLOCK_RULE_ID_PDAF_READOUT = 5,
+};
+
+struct __ccs_data_block_rule_if {
+ u8 addr[2];
+ u8 value;
+ u8 mask;
+} __packed;
+
+enum __ccs_data_block_pdaf_readout_order {
+ CCS_DATA_BLOCK_PDAF_READOUT_ORDER_ORIGINAL = 1,
+ CCS_DATA_BLOCK_PDAF_READOUT_ORDER_SEPARATE_WITHIN_LINE = 2,
+ CCS_DATA_BLOCK_PDAF_READOUT_ORDER_SEPARATE_TYPES_SEPARATE_LINES = 3,
+};
+
+struct __ccs_data_block_pdaf_readout {
+ u8 pdaf_readout_info_reserved;
+ u8 pdaf_readout_info_order;
+} __packed;
+
+struct __ccs_data_block_pdaf_pix_loc_block_desc {
+ u8 block_type_id;
+ u8 repeat_x[2];
+} __packed;
+
+struct __ccs_data_block_pdaf_pix_loc_block_desc_group {
+ u8 num_block_descs[2];
+ u8 repeat_y;
+} __packed;
+
+enum __ccs_data_block_pdaf_pix_loc_pixel_type {
+ CCS_DATA_PDAF_PIXEL_TYPE_LEFT_SEPARATED = 0,
+ CCS_DATA_PDAF_PIXEL_TYPE_RIGHT_SEPARATED = 1,
+ CCS_DATA_PDAF_PIXEL_TYPE_TOP_SEPARATED = 2,
+ CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_SEPARATED = 3,
+ CCS_DATA_PDAF_PIXEL_TYPE_LEFT_SIDE_BY_SIDE = 4,
+ CCS_DATA_PDAF_PIXEL_TYPE_RIGHT_SIDE_BY_SIDE = 5,
+ CCS_DATA_PDAF_PIXEL_TYPE_TOP_SIDE_BY_SIDE = 6,
+ CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_SIDE_BY_SIDE = 7,
+ CCS_DATA_PDAF_PIXEL_TYPE_TOP_LEFT = 8,
+ CCS_DATA_PDAF_PIXEL_TYPE_TOP_RIGHT = 9,
+ CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_LEFT = 10,
+ CCS_DATA_PDAF_PIXEL_TYPE_BOTTOM_RIGHT = 11,
+};
+
+struct __ccs_data_block_pdaf_pix_loc_pixel_desc {
+ u8 pixel_type;
+ u8 small_offset_x;
+ u8 small_offset_y;
+} __packed;
+
+struct __ccs_data_block_pdaf_pix_loc {
+ u8 main_offset_x[2];
+ u8 main_offset_y[2];
+ u8 global_pdaf_type;
+ u8 block_width;
+ u8 block_height;
+ u8 num_block_desc_groups[2];
+} __packed;
+
+struct __ccs_data_block_end {
+ u8 crc[4];
+} __packed;
+
+#endif /* __CCS_DATA_DEFS_H__ */
diff --git a/drivers/media/i2c/ccs/ccs-data.c b/drivers/media/i2c/ccs/ccs-data.c
new file mode 100644
index 000000000..08400edf7
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-data.c
@@ -0,0 +1,979 @@
+// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
+/*
+ * CCS static data binary parser library
+ *
+ * Copyright 2019--2020 Intel Corporation
+ */
+
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/limits.h>
+#include <linux/mm.h>
+#include <linux/slab.h>
+
+#include "ccs-data-defs.h"
+
+struct bin_container {
+ void *base;
+ void *now;
+ void *end;
+ size_t size;
+};
+
+static void *bin_alloc(struct bin_container *bin, size_t len)
+{
+ void *ptr;
+
+ len = ALIGN(len, 8);
+
+ if (bin->end - bin->now < len)
+ return NULL;
+
+ ptr = bin->now;
+ bin->now += len;
+
+ return ptr;
+}
+
+static void bin_reserve(struct bin_container *bin, size_t len)
+{
+ bin->size += ALIGN(len, 8);
+}
+
+static int bin_backing_alloc(struct bin_container *bin)
+{
+ bin->base = bin->now = kvzalloc(bin->size, GFP_KERNEL);
+ if (!bin->base)
+ return -ENOMEM;
+
+ bin->end = bin->base + bin->size;
+
+ return 0;
+}
+
+#define is_contained(var, endp) \
+ (sizeof(*var) <= (endp) - (void *)(var))
+#define has_headroom(ptr, headroom, endp) \
+ ((headroom) <= (endp) - (void *)(ptr))
+#define is_contained_with_headroom(var, headroom, endp) \
+ (sizeof(*var) + (headroom) <= (endp) - (void *)(var))
+
+static int
+ccs_data_parse_length_specifier(const struct __ccs_data_length_specifier *__len,
+ size_t *__hlen, size_t *__plen,
+ const void *endp)
+{
+ size_t hlen, plen;
+
+ if (!is_contained(__len, endp))
+ return -ENODATA;
+
+ switch (__len->length >> CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) {
+ case CCS_DATA_LENGTH_SPECIFIER_1:
+ hlen = sizeof(*__len);
+ plen = __len->length &
+ ((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1);
+ break;
+ case CCS_DATA_LENGTH_SPECIFIER_2: {
+ struct __ccs_data_length_specifier2 *__len2 = (void *)__len;
+
+ if (!is_contained(__len2, endp))
+ return -ENODATA;
+
+ hlen = sizeof(*__len2);
+ plen = ((size_t)
+ (__len2->length[0] &
+ ((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1))
+ << 8) + __len2->length[1];
+ break;
+ }
+ case CCS_DATA_LENGTH_SPECIFIER_3: {
+ struct __ccs_data_length_specifier3 *__len3 = (void *)__len;
+
+ if (!is_contained(__len3, endp))
+ return -ENODATA;
+
+ hlen = sizeof(*__len3);
+ plen = ((size_t)
+ (__len3->length[0] &
+ ((1 << CCS_DATA_LENGTH_SPECIFIER_SIZE_SHIFT) - 1))
+ << 16) + (__len3->length[0] << 8) + __len3->length[1];
+ break;
+ }
+ default:
+ return -EINVAL;
+ }
+
+ if (!has_headroom(__len, hlen + plen, endp))
+ return -ENODATA;
+
+ *__hlen = hlen;
+ *__plen = plen;
+
+ return 0;
+}
+
+static u8
+ccs_data_parse_format_version(const struct __ccs_data_block *block)
+{
+ return block->id >> CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT;
+}
+
+static u8 ccs_data_parse_block_id(const struct __ccs_data_block *block,
+ bool is_first)
+{
+ if (!is_first)
+ return block->id;
+
+ return block->id & ((1 << CCS_DATA_BLOCK_HEADER_ID_VERSION_SHIFT) - 1);
+}
+
+static int ccs_data_parse_version(struct bin_container *bin,
+ struct ccs_data_container *ccsdata,
+ const void *payload, const void *endp)
+{
+ const struct __ccs_data_block_version *v = payload;
+ struct ccs_data_block_version *vv;
+
+ if (v + 1 != endp)
+ return -ENODATA;
+
+ if (!bin->base) {
+ bin_reserve(bin, sizeof(*ccsdata->version));
+ return 0;
+ }
+
+ ccsdata->version = bin_alloc(bin, sizeof(*ccsdata->version));
+ if (!ccsdata->version)
+ return -ENOMEM;
+
+ vv = ccsdata->version;
+ vv->version_major = ((u16)v->static_data_version_major[0] << 8) +
+ v->static_data_version_major[1];
+ vv->version_minor = ((u16)v->static_data_version_minor[0] << 8) +
+ v->static_data_version_minor[1];
+ vv->date_year = ((u16)v->year[0] << 8) + v->year[1];
+ vv->date_month = v->month;
+ vv->date_day = v->day;
+
+ return 0;
+}
+
+static void print_ccs_data_version(struct device *dev,
+ struct ccs_data_block_version *v)
+{
+ dev_dbg(dev,
+ "static data version %4.4x.%4.4x, date %4.4u-%2.2u-%2.2u\n",
+ v->version_major, v->version_minor,
+ v->date_year, v->date_month, v->date_day);
+}
+
+static int ccs_data_block_parse_header(const struct __ccs_data_block *block,
+ bool is_first, unsigned int *__block_id,
+ const void **payload,
+ const struct __ccs_data_block **next_block,
+ const void *endp, struct device *dev,
+ bool verbose)
+{
+ size_t plen, hlen;
+ u8 block_id;
+ int rval;
+
+ if (!is_contained(block, endp))
+ return -ENODATA;
+
+ rval = ccs_data_parse_length_specifier(&block->length, &hlen, &plen,
+ endp);
+ if (rval < 0)
+ return rval;
+
+ block_id = ccs_data_parse_block_id(block, is_first);
+
+ if (verbose)
+ dev_dbg(dev,
+ "Block ID 0x%2.2x, header length %zu, payload length %zu\n",
+ block_id, hlen, plen);
+
+ if (!has_headroom(&block->length, hlen + plen, endp))
+ return -ENODATA;
+
+ if (__block_id)
+ *__block_id = block_id;
+
+ if (payload)
+ *payload = (void *)&block->length + hlen;
+
+ if (next_block)
+ *next_block = (void *)&block->length + hlen + plen;
+
+ return 0;
+}
+
+static int ccs_data_parse_regs(struct bin_container *bin,
+ struct ccs_reg **__regs,
+ size_t *__num_regs, const void *payload,
+ const void *endp, struct device *dev)
+{
+ struct ccs_reg *regs_base = NULL, *regs = NULL;
+ size_t num_regs = 0;
+ u16 addr = 0;
+
+ if (bin->base && __regs) {
+ regs = regs_base = bin_alloc(bin, sizeof(*regs) * *__num_regs);
+ if (!regs)
+ return -ENOMEM;
+ }
+
+ while (payload < endp && num_regs < INT_MAX) {
+ const struct __ccs_data_block_regs *r = payload;
+ size_t len;
+ const void *data;
+
+ if (!is_contained(r, endp))
+ return -ENODATA;
+
+ switch (r->reg_len >> CCS_DATA_BLOCK_REGS_SEL_SHIFT) {
+ case CCS_DATA_BLOCK_REGS_SEL_REGS:
+ addr += r->reg_len & CCS_DATA_BLOCK_REGS_ADDR_MASK;
+ len = ((r->reg_len & CCS_DATA_BLOCK_REGS_LEN_MASK)
+ >> CCS_DATA_BLOCK_REGS_LEN_SHIFT) + 1;
+
+ if (!is_contained_with_headroom(r, len, endp))
+ return -ENODATA;
+
+ data = r + 1;
+ break;
+ case CCS_DATA_BLOCK_REGS_SEL_REGS2: {
+ const struct __ccs_data_block_regs2 *r2 = payload;
+
+ if (!is_contained(r2, endp))
+ return -ENODATA;
+
+ addr += ((u16)(r2->reg_len &
+ CCS_DATA_BLOCK_REGS_2_ADDR_MASK) << 8)
+ + r2->addr;
+ len = ((r2->reg_len & CCS_DATA_BLOCK_REGS_2_LEN_MASK)
+ >> CCS_DATA_BLOCK_REGS_2_LEN_SHIFT) + 1;
+
+ if (!is_contained_with_headroom(r2, len, endp))
+ return -ENODATA;
+
+ data = r2 + 1;
+ break;
+ }
+ case CCS_DATA_BLOCK_REGS_SEL_REGS3: {
+ const struct __ccs_data_block_regs3 *r3 = payload;
+
+ if (!is_contained(r3, endp))
+ return -ENODATA;
+
+ addr = ((u16)r3->addr[0] << 8) + r3->addr[1];
+ len = (r3->reg_len & CCS_DATA_BLOCK_REGS_3_LEN_MASK) + 1;
+
+ if (!is_contained_with_headroom(r3, len, endp))
+ return -ENODATA;
+
+ data = r3 + 1;
+ break;
+ }
+ default:
+ return -EINVAL;
+ }
+
+ num_regs++;
+
+ if (!bin->base) {
+ bin_reserve(bin, len);
+ } else if (__regs) {
+ if (!regs)
+ return -EIO;
+
+ regs->addr = addr;
+ regs->len = len;
+ regs->value = bin_alloc(bin, len);
+ if (!regs->value)
+ return -ENOMEM;
+
+ memcpy(regs->value, data, len);
+ regs++;
+ }
+
+ addr += len;
+ payload = data + len;
+ }
+
+ if (!bin->base)
+ bin_reserve(bin, sizeof(*regs) * num_regs);
+
+ if (__num_regs)
+ *__num_regs = num_regs;
+
+ if (bin->base && __regs) {
+ if (!regs_base)
+ return -EIO;
+
+ *__regs = regs_base;
+ }
+
+ return 0;
+}
+
+static int ccs_data_parse_reg_rules(struct bin_container *bin,
+ struct ccs_reg **__regs,
+ size_t *__num_regs,
+ const void *payload,
+ const void *endp, struct device *dev)
+{
+ int rval;
+
+ if (!bin->base)
+ return ccs_data_parse_regs(bin, NULL, NULL, payload, endp, dev);
+
+ rval = ccs_data_parse_regs(bin, NULL, __num_regs, payload, endp, dev);
+ if (rval)
+ return rval;
+
+ return ccs_data_parse_regs(bin, __regs, __num_regs, payload, endp,
+ dev);
+}
+
+static void assign_ffd_entry(struct ccs_frame_format_desc *desc,
+ const struct __ccs_data_block_ffd_entry *ent)
+{
+ desc->pixelcode = ent->pixelcode;
+ desc->value = ((u16)ent->value[0] << 8) + ent->value[1];
+}
+
+static int ccs_data_parse_ffd(struct bin_container *bin,
+ struct ccs_frame_format_descs **ffd,
+ const void *payload,
+ const void *endp, struct device *dev)
+{
+ const struct __ccs_data_block_ffd *__ffd = payload;
+ const struct __ccs_data_block_ffd_entry *__entry;
+ unsigned int i;
+
+ if (!is_contained(__ffd, endp))
+ return -ENODATA;
+
+ if ((void *)__ffd + sizeof(*__ffd) +
+ ((u32)__ffd->num_column_descs +
+ (u32)__ffd->num_row_descs) *
+ sizeof(struct __ccs_data_block_ffd_entry) != endp)
+ return -ENODATA;
+
+ if (!bin->base) {
+ bin_reserve(bin, sizeof(**ffd));
+ bin_reserve(bin, __ffd->num_column_descs *
+ sizeof(struct ccs_frame_format_desc));
+ bin_reserve(bin, __ffd->num_row_descs *
+ sizeof(struct ccs_frame_format_desc));
+
+ return 0;
+ }
+
+ *ffd = bin_alloc(bin, sizeof(**ffd));
+ if (!*ffd)
+ return -ENOMEM;
+
+ (*ffd)->num_column_descs = __ffd->num_column_descs;
+ (*ffd)->num_row_descs = __ffd->num_row_descs;
+ __entry = (void *)(__ffd + 1);
+
+ (*ffd)->column_descs = bin_alloc(bin, __ffd->num_column_descs *
+ sizeof(*(*ffd)->column_descs));
+ if (!(*ffd)->column_descs)
+ return -ENOMEM;
+
+ for (i = 0; i < __ffd->num_column_descs; i++, __entry++)
+ assign_ffd_entry(&(*ffd)->column_descs[i], __entry);
+
+ (*ffd)->row_descs = bin_alloc(bin, __ffd->num_row_descs *
+ sizeof(*(*ffd)->row_descs));
+ if (!(*ffd)->row_descs)
+ return -ENOMEM;
+
+ for (i = 0; i < __ffd->num_row_descs; i++, __entry++)
+ assign_ffd_entry(&(*ffd)->row_descs[i], __entry);
+
+ if (__entry != endp)
+ return -EPROTO;
+
+ return 0;
+}
+
+static int ccs_data_parse_pdaf_readout(struct bin_container *bin,
+ struct ccs_pdaf_readout **pdaf_readout,
+ const void *payload,
+ const void *endp, struct device *dev)
+{
+ const struct __ccs_data_block_pdaf_readout *__pdaf = payload;
+
+ if (!is_contained(__pdaf, endp))
+ return -ENODATA;
+
+ if (!bin->base) {
+ bin_reserve(bin, sizeof(**pdaf_readout));
+ } else {
+ *pdaf_readout = bin_alloc(bin, sizeof(**pdaf_readout));
+ if (!*pdaf_readout)
+ return -ENOMEM;
+
+ (*pdaf_readout)->pdaf_readout_info_order =
+ __pdaf->pdaf_readout_info_order;
+ }
+
+ return ccs_data_parse_ffd(bin, !bin->base ? NULL : &(*pdaf_readout)->ffd,
+ __pdaf + 1, endp, dev);
+}
+
+static int ccs_data_parse_rules(struct bin_container *bin,
+ struct ccs_rule **__rules,
+ size_t *__num_rules, const void *payload,
+ const void *endp, struct device *dev)
+{
+ struct ccs_rule *rules_base = NULL, *rules = NULL, *next_rule = NULL;
+ size_t num_rules = 0;
+ const void *__next_rule = payload;
+ int rval;
+
+ if (bin->base) {
+ rules_base = next_rule =
+ bin_alloc(bin, sizeof(*rules) * *__num_rules);
+ if (!rules_base)
+ return -ENOMEM;
+ }
+
+ while (__next_rule < endp) {
+ size_t rule_hlen, rule_plen, rule_plen2;
+ const u8 *__rule_type;
+ const void *rule_payload;
+
+ /* Size of a single rule */
+ rval = ccs_data_parse_length_specifier(__next_rule, &rule_hlen,
+ &rule_plen, endp);
+
+ if (rval < 0)
+ return rval;
+
+ __rule_type = __next_rule + rule_hlen;
+
+ if (!is_contained(__rule_type, endp))
+ return -ENODATA;
+
+ rule_payload = __rule_type + 1;
+ rule_plen2 = rule_plen - sizeof(*__rule_type);
+
+ if (*__rule_type == CCS_DATA_BLOCK_RULE_ID_IF) {
+ const struct __ccs_data_block_rule_if *__if_rules =
+ rule_payload;
+ const size_t __num_if_rules =
+ rule_plen2 / sizeof(*__if_rules);
+ struct ccs_if_rule *if_rule;
+
+ if (!has_headroom(__if_rules,
+ sizeof(*__if_rules) * __num_if_rules,
+ rule_payload + rule_plen2))
+ return -ENODATA;
+
+ /* Also check there is no extra data */
+ if (__if_rules + __num_if_rules !=
+ rule_payload + rule_plen2)
+ return -EINVAL;
+
+ if (!bin->base) {
+ bin_reserve(bin,
+ sizeof(*if_rule) *
+ __num_if_rules);
+ num_rules++;
+ } else {
+ unsigned int i;
+
+ if (!next_rule)
+ return -EIO;
+
+ rules = next_rule;
+ next_rule++;
+
+ if_rule = bin_alloc(bin,
+ sizeof(*if_rule) *
+ __num_if_rules);
+ if (!if_rule)
+ return -ENOMEM;
+
+ for (i = 0; i < __num_if_rules; i++) {
+ if_rule[i].addr =
+ ((u16)__if_rules[i].addr[0]
+ << 8) +
+ __if_rules[i].addr[1];
+ if_rule[i].value = __if_rules[i].value;
+ if_rule[i].mask = __if_rules[i].mask;
+ }
+
+ rules->if_rules = if_rule;
+ rules->num_if_rules = __num_if_rules;
+ }
+ } else {
+ /* Check there was an if rule before any other rules */
+ if (bin->base && !rules)
+ return -EINVAL;
+
+ switch (*__rule_type) {
+ case CCS_DATA_BLOCK_RULE_ID_READ_ONLY_REGS:
+ rval = ccs_data_parse_reg_rules(bin,
+ rules ?
+ &rules->read_only_regs : NULL,
+ rules ?
+ &rules->num_read_only_regs : NULL,
+ rule_payload,
+ rule_payload + rule_plen2,
+ dev);
+ if (rval)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_RULE_ID_FFD:
+ rval = ccs_data_parse_ffd(bin, rules ?
+ &rules->frame_format : NULL,
+ rule_payload,
+ rule_payload + rule_plen2,
+ dev);
+ if (rval)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_RULE_ID_MSR:
+ rval = ccs_data_parse_reg_rules(bin,
+ rules ?
+ &rules->manufacturer_regs : NULL,
+ rules ?
+ &rules->num_manufacturer_regs : NULL,
+ rule_payload,
+ rule_payload + rule_plen2,
+ dev);
+ if (rval)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_RULE_ID_PDAF_READOUT:
+ rval = ccs_data_parse_pdaf_readout(bin,
+ rules ?
+ &rules->pdaf_readout : NULL,
+ rule_payload,
+ rule_payload + rule_plen2,
+ dev);
+ if (rval)
+ return rval;
+ break;
+ default:
+ dev_dbg(dev,
+ "Don't know how to handle rule type %u!\n",
+ *__rule_type);
+ return -EINVAL;
+ }
+ }
+ __next_rule = __next_rule + rule_hlen + rule_plen;
+ }
+
+ if (!bin->base) {
+ bin_reserve(bin, sizeof(*rules) * num_rules);
+ *__num_rules = num_rules;
+ } else {
+ if (!rules_base)
+ return -EIO;
+
+ *__rules = rules_base;
+ }
+
+ return 0;
+}
+
+static int ccs_data_parse_pdaf(struct bin_container *bin, struct ccs_pdaf_pix_loc **pdaf,
+ const void *payload, const void *endp,
+ struct device *dev)
+{
+ const struct __ccs_data_block_pdaf_pix_loc *__pdaf = payload;
+ const struct __ccs_data_block_pdaf_pix_loc_block_desc_group *__bdesc_group;
+ const struct __ccs_data_block_pdaf_pix_loc_pixel_desc *__pixel_desc;
+ unsigned int i;
+ u16 num_block_desc_groups;
+ u8 max_block_type_id = 0;
+ const u8 *__num_pixel_descs;
+
+ if (!is_contained(__pdaf, endp))
+ return -ENODATA;
+
+ if (bin->base) {
+ *pdaf = bin_alloc(bin, sizeof(**pdaf));
+ if (!*pdaf)
+ return -ENOMEM;
+ } else {
+ bin_reserve(bin, sizeof(**pdaf));
+ }
+
+ num_block_desc_groups =
+ ((u16)__pdaf->num_block_desc_groups[0] << 8) +
+ __pdaf->num_block_desc_groups[1];
+
+ if (bin->base) {
+ (*pdaf)->main_offset_x =
+ ((u16)__pdaf->main_offset_x[0] << 8) +
+ __pdaf->main_offset_x[1];
+ (*pdaf)->main_offset_y =
+ ((u16)__pdaf->main_offset_y[0] << 8) +
+ __pdaf->main_offset_y[1];
+ (*pdaf)->global_pdaf_type = __pdaf->global_pdaf_type;
+ (*pdaf)->block_width = __pdaf->block_width;
+ (*pdaf)->block_height = __pdaf->block_height;
+ (*pdaf)->num_block_desc_groups = num_block_desc_groups;
+ }
+
+ __bdesc_group = (const void *)(__pdaf + 1);
+
+ if (bin->base) {
+ (*pdaf)->block_desc_groups =
+ bin_alloc(bin,
+ sizeof(struct ccs_pdaf_pix_loc_block_desc_group) *
+ num_block_desc_groups);
+ if (!(*pdaf)->block_desc_groups)
+ return -ENOMEM;
+ } else {
+ bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_block_desc_group) *
+ num_block_desc_groups);
+ }
+
+ for (i = 0; i < num_block_desc_groups; i++) {
+ const struct __ccs_data_block_pdaf_pix_loc_block_desc *__bdesc;
+ u16 num_block_descs;
+ unsigned int j;
+
+ if (!is_contained(__bdesc_group, endp))
+ return -ENODATA;
+
+ num_block_descs =
+ ((u16)__bdesc_group->num_block_descs[0] << 8) +
+ __bdesc_group->num_block_descs[1];
+
+ if (bin->base) {
+ (*pdaf)->block_desc_groups[i].repeat_y =
+ __bdesc_group->repeat_y;
+ (*pdaf)->block_desc_groups[i].num_block_descs =
+ num_block_descs;
+ }
+
+ __bdesc = (const void *)(__bdesc_group + 1);
+
+ if (bin->base) {
+ (*pdaf)->block_desc_groups[i].block_descs =
+ bin_alloc(bin,
+ sizeof(struct ccs_pdaf_pix_loc_block_desc) *
+ num_block_descs);
+ if (!(*pdaf)->block_desc_groups[i].block_descs)
+ return -ENOMEM;
+ } else {
+ bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_block_desc) *
+ num_block_descs);
+ }
+
+ for (j = 0; j < num_block_descs; j++, __bdesc++) {
+ struct ccs_pdaf_pix_loc_block_desc *bdesc;
+
+ if (!is_contained(__bdesc, endp))
+ return -ENODATA;
+
+ if (max_block_type_id <= __bdesc->block_type_id)
+ max_block_type_id = __bdesc->block_type_id + 1;
+
+ if (!bin->base)
+ continue;
+
+ bdesc = &(*pdaf)->block_desc_groups[i].block_descs[j];
+
+ bdesc->repeat_x = ((u16)__bdesc->repeat_x[0] << 8)
+ + __bdesc->repeat_x[1];
+
+ if (__bdesc->block_type_id >= num_block_descs)
+ return -EINVAL;
+
+ bdesc->block_type_id = __bdesc->block_type_id;
+ }
+
+ __bdesc_group = (const void *)__bdesc;
+ }
+
+ __num_pixel_descs = (const void *)__bdesc_group;
+
+ if (bin->base) {
+ (*pdaf)->pixel_desc_groups =
+ bin_alloc(bin,
+ sizeof(struct ccs_pdaf_pix_loc_pixel_desc_group) *
+ max_block_type_id);
+ if (!(*pdaf)->pixel_desc_groups)
+ return -ENOMEM;
+ (*pdaf)->num_pixel_desc_grups = max_block_type_id;
+ } else {
+ bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_pixel_desc_group) *
+ max_block_type_id);
+ }
+
+ for (i = 0; i < max_block_type_id; i++) {
+ struct ccs_pdaf_pix_loc_pixel_desc_group *pdgroup = NULL;
+ unsigned int j;
+
+ if (!is_contained(__num_pixel_descs, endp))
+ return -ENODATA;
+
+ if (bin->base) {
+ pdgroup = &(*pdaf)->pixel_desc_groups[i];
+ pdgroup->descs =
+ bin_alloc(bin,
+ sizeof(struct ccs_pdaf_pix_loc_pixel_desc) *
+ *__num_pixel_descs);
+ if (!pdgroup->descs)
+ return -ENOMEM;
+ pdgroup->num_descs = *__num_pixel_descs;
+ } else {
+ bin_reserve(bin, sizeof(struct ccs_pdaf_pix_loc_pixel_desc) *
+ *__num_pixel_descs);
+ }
+
+ __pixel_desc = (const void *)(__num_pixel_descs + 1);
+
+ for (j = 0; j < *__num_pixel_descs; j++, __pixel_desc++) {
+ struct ccs_pdaf_pix_loc_pixel_desc *pdesc;
+
+ if (!is_contained(__pixel_desc, endp))
+ return -ENODATA;
+
+ if (!bin->base)
+ continue;
+
+ if (!pdgroup)
+ return -EIO;
+
+ pdesc = &pdgroup->descs[j];
+ pdesc->pixel_type = __pixel_desc->pixel_type;
+ pdesc->small_offset_x = __pixel_desc->small_offset_x;
+ pdesc->small_offset_y = __pixel_desc->small_offset_y;
+ }
+
+ __num_pixel_descs = (const void *)(__pixel_desc + 1);
+ }
+
+ return 0;
+}
+
+static int ccs_data_parse_license(struct bin_container *bin,
+ char **__license,
+ size_t *__license_length,
+ const void *payload, const void *endp)
+{
+ size_t size = endp - payload;
+ char *license;
+
+ if (!bin->base) {
+ bin_reserve(bin, size);
+ return 0;
+ }
+
+ license = bin_alloc(bin, size);
+ if (!license)
+ return -ENOMEM;
+
+ memcpy(license, payload, size);
+
+ *__license = license;
+ *__license_length = size;
+
+ return 0;
+}
+
+static int ccs_data_parse_end(bool *end, const void *payload, const void *endp,
+ struct device *dev)
+{
+ const struct __ccs_data_block_end *__end = payload;
+
+ if (__end + 1 != endp) {
+ dev_dbg(dev, "Invalid end block length %u\n",
+ (unsigned int)(endp - payload));
+ return -ENODATA;
+ }
+
+ *end = true;
+
+ return 0;
+}
+
+static int __ccs_data_parse(struct bin_container *bin,
+ struct ccs_data_container *ccsdata,
+ const void *data, size_t len, struct device *dev,
+ bool verbose)
+{
+ const struct __ccs_data_block *block = data;
+ const struct __ccs_data_block *endp = data + len;
+ unsigned int version;
+ bool is_first = true;
+ int rval;
+
+ version = ccs_data_parse_format_version(block);
+ if (version != CCS_STATIC_DATA_VERSION) {
+ dev_dbg(dev, "Don't know how to handle version %u\n", version);
+ return -EINVAL;
+ }
+
+ if (verbose)
+ dev_dbg(dev, "Parsing CCS static data version %u\n", version);
+
+ if (!bin->base)
+ *ccsdata = (struct ccs_data_container){ 0 };
+
+ while (block < endp) {
+ const struct __ccs_data_block *next_block;
+ unsigned int block_id;
+ const void *payload;
+
+ rval = ccs_data_block_parse_header(block, is_first, &block_id,
+ &payload, &next_block, endp,
+ dev,
+ bin->base ? false : verbose);
+
+ if (rval < 0)
+ return rval;
+
+ switch (block_id) {
+ case CCS_DATA_BLOCK_ID_DUMMY:
+ break;
+ case CCS_DATA_BLOCK_ID_DATA_VERSION:
+ rval = ccs_data_parse_version(bin, ccsdata, payload,
+ next_block);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_SENSOR_READ_ONLY_REGS:
+ rval = ccs_data_parse_regs(
+ bin, &ccsdata->sensor_read_only_regs,
+ &ccsdata->num_sensor_read_only_regs, payload,
+ next_block, dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_SENSOR_MANUFACTURER_REGS:
+ rval = ccs_data_parse_regs(
+ bin, &ccsdata->sensor_manufacturer_regs,
+ &ccsdata->num_sensor_manufacturer_regs, payload,
+ next_block, dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_MODULE_READ_ONLY_REGS:
+ rval = ccs_data_parse_regs(
+ bin, &ccsdata->module_read_only_regs,
+ &ccsdata->num_module_read_only_regs, payload,
+ next_block, dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_MODULE_MANUFACTURER_REGS:
+ rval = ccs_data_parse_regs(
+ bin, &ccsdata->module_manufacturer_regs,
+ &ccsdata->num_module_manufacturer_regs, payload,
+ next_block, dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_SENSOR_PDAF_PIXEL_LOCATION:
+ rval = ccs_data_parse_pdaf(bin, &ccsdata->sensor_pdaf,
+ payload, next_block, dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_MODULE_PDAF_PIXEL_LOCATION:
+ rval = ccs_data_parse_pdaf(bin, &ccsdata->module_pdaf,
+ payload, next_block, dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_SENSOR_RULE_BASED_BLOCK:
+ rval = ccs_data_parse_rules(
+ bin, &ccsdata->sensor_rules,
+ &ccsdata->num_sensor_rules, payload, next_block,
+ dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_MODULE_RULE_BASED_BLOCK:
+ rval = ccs_data_parse_rules(
+ bin, &ccsdata->module_rules,
+ &ccsdata->num_module_rules, payload, next_block,
+ dev);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_LICENSE:
+ rval = ccs_data_parse_license(bin, &ccsdata->license,
+ &ccsdata->license_length,
+ payload, next_block);
+ if (rval < 0)
+ return rval;
+ break;
+ case CCS_DATA_BLOCK_ID_END:
+ rval = ccs_data_parse_end(&ccsdata->end, payload,
+ next_block, dev);
+ if (rval < 0)
+ return rval;
+ break;
+ default:
+ dev_dbg(dev, "WARNING: not handling block ID 0x%2.2x\n",
+ block_id);
+ }
+
+ block = next_block;
+ is_first = false;
+ }
+
+ return 0;
+}
+
+/**
+ * ccs_data_parse - Parse a CCS static data file into a usable in-memory
+ * data structure
+ * @ccsdata: CCS static data in-memory data structure
+ * @data: CCS static data binary
+ * @len: Length of @data
+ * @dev: Device the data is related to (used for printing debug messages)
+ * @verbose: Whether to be verbose or not
+ */
+int ccs_data_parse(struct ccs_data_container *ccsdata, const void *data,
+ size_t len, struct device *dev, bool verbose)
+{
+ struct bin_container bin = { 0 };
+ int rval;
+
+ rval = __ccs_data_parse(&bin, ccsdata, data, len, dev, verbose);
+ if (rval)
+ return rval;
+
+ rval = bin_backing_alloc(&bin);
+ if (rval)
+ return rval;
+
+ rval = __ccs_data_parse(&bin, ccsdata, data, len, dev, false);
+ if (rval)
+ goto out_free;
+
+ if (verbose && ccsdata->version)
+ print_ccs_data_version(dev, ccsdata->version);
+
+ if (bin.now != bin.end) {
+ rval = -EPROTO;
+ dev_dbg(dev, "parsing mismatch; base %p; now %p; end %p\n",
+ bin.base, bin.now, bin.end);
+ goto out_free;
+ }
+
+ ccsdata->backing = bin.base;
+
+ return 0;
+
+out_free:
+ kvfree(bin.base);
+
+ return rval;
+}
diff --git a/drivers/media/i2c/ccs/ccs-data.h b/drivers/media/i2c/ccs/ccs-data.h
new file mode 100644
index 000000000..638df6980
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-data.h
@@ -0,0 +1,230 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
+/*
+ * CCS static data in-memory data structure definitions
+ *
+ * Copyright 2019--2020 Intel Corporation
+ */
+
+#ifndef __CCS_DATA_H__
+#define __CCS_DATA_H__
+
+#include <linux/types.h>
+
+struct device;
+
+/**
+ * struct ccs_data_block_version - CCS static data version
+ * @version_major: Major version number
+ * @version_minor: Minor version number
+ * @date_year: Year
+ * @date_month: Month
+ * @date_day: Day
+ */
+struct ccs_data_block_version {
+ u16 version_major;
+ u16 version_minor;
+ u16 date_year;
+ u8 date_month;
+ u8 date_day;
+};
+
+/**
+ * struct ccs_reg - CCS register value
+ * @addr: The 16-bit address of the register
+ * @len: Length of the data
+ * @value: Data
+ */
+struct ccs_reg {
+ u16 addr;
+ u16 len;
+ u8 *value;
+};
+
+/**
+ * struct ccs_if_rule - CCS static data if rule
+ * @addr: Register address
+ * @value: Register value
+ * @mask: Value applied to both actual register value and @value
+ */
+struct ccs_if_rule {
+ u16 addr;
+ u8 value;
+ u8 mask;
+};
+
+/**
+ * struct ccs_frame_format_desc - CCS frame format descriptor
+ * @pixelcode: The pixelcode; CCS_DATA_BLOCK_FFD_PIXELCODE_*
+ * @value: Value related to the pixelcode
+ */
+struct ccs_frame_format_desc {
+ u8 pixelcode;
+ u16 value;
+};
+
+/**
+ * struct ccs_frame_format_descs - A series of CCS frame format descriptors
+ * @num_column_descs: Number of column descriptors
+ * @num_row_descs: Number of row descriptors
+ * @column_descs: Column descriptors
+ * @row_descs: Row descriptors
+ */
+struct ccs_frame_format_descs {
+ u8 num_column_descs;
+ u8 num_row_descs;
+ struct ccs_frame_format_desc *column_descs;
+ struct ccs_frame_format_desc *row_descs;
+};
+
+/**
+ * struct ccs_pdaf_readout - CCS PDAF data readout descriptor
+ * @pdaf_readout_info_order: PDAF readout order
+ * @ffd: Frame format of PDAF data
+ */
+struct ccs_pdaf_readout {
+ u8 pdaf_readout_info_order;
+ struct ccs_frame_format_descs *ffd;
+};
+
+/**
+ * struct ccs_rule - A CCS static data rule
+ * @num_if_rules: Number of if rules
+ * @if_rules: If rules
+ * @num_read_only_regs: Number of read-only registers
+ * @read_only_regs: Read-only registers
+ * @num_manufacturer_regs: Number of manufacturer-specific registers
+ * @manufacturer_regs: Manufacturer-specific registers
+ * @frame_format: Frame format
+ * @pdaf_readout: PDAF readout
+ */
+struct ccs_rule {
+ size_t num_if_rules;
+ struct ccs_if_rule *if_rules;
+ size_t num_read_only_regs;
+ struct ccs_reg *read_only_regs;
+ size_t num_manufacturer_regs;
+ struct ccs_reg *manufacturer_regs;
+ struct ccs_frame_format_descs *frame_format;
+ struct ccs_pdaf_readout *pdaf_readout;
+};
+
+/**
+ * struct ccs_pdaf_pix_loc_block_desc - PDAF pixel location block descriptor
+ * @block_type_id: Block type identifier, from 0 to n
+ * @repeat_x: Number of times this block is repeated to right
+ */
+struct ccs_pdaf_pix_loc_block_desc {
+ u8 block_type_id;
+ u16 repeat_x;
+};
+
+/**
+ * struct ccs_pdaf_pix_loc_block_desc_group - PDAF pixel location block
+ * descriptor group
+ * @repeat_y: Number of times the group is repeated down
+ * @num_block_descs: Number of block descriptors in @block_descs
+ * @block_descs: Block descriptors
+ */
+struct ccs_pdaf_pix_loc_block_desc_group {
+ u8 repeat_y;
+ u16 num_block_descs;
+ struct ccs_pdaf_pix_loc_block_desc *block_descs;
+};
+
+/**
+ * struct ccs_pdaf_pix_loc_pixel_desc - PDAF pixel location block descriptor
+ * @pixel_type: Type of the pixel; CCS_DATA_PDAF_PIXEL_TYPE_*
+ * @small_offset_x: offset X coordinate
+ * @small_offset_y: offset Y coordinate
+ */
+struct ccs_pdaf_pix_loc_pixel_desc {
+ u8 pixel_type;
+ u8 small_offset_x;
+ u8 small_offset_y;
+};
+
+/**
+ * struct ccs_pdaf_pix_loc_pixel_desc_group - PDAF pixel location pixel
+ * descriptor group
+ * @num_descs: Number of descriptors in @descs
+ * @descs: PDAF pixel location pixel descriptors
+ */
+struct ccs_pdaf_pix_loc_pixel_desc_group {
+ u8 num_descs;
+ struct ccs_pdaf_pix_loc_pixel_desc *descs;
+};
+
+/**
+ * struct ccs_pdaf_pix_loc - PDAF pixel locations
+ * @main_offset_x: Start X coordinate of PDAF pixel blocks
+ * @main_offset_y: Start Y coordinate of PDAF pixel blocks
+ * @global_pdaf_type: PDAF pattern type
+ * @block_width: Width of a block in pixels
+ * @block_height: Heigth of a block in pixels
+ * @num_block_desc_groups: Number of block descriptor groups
+ * @block_desc_groups: Block descriptor groups
+ * @num_pixel_desc_grups: Number of pixel descriptor groups
+ * @pixel_desc_groups: Pixel descriptor groups
+ */
+struct ccs_pdaf_pix_loc {
+ u16 main_offset_x;
+ u16 main_offset_y;
+ u8 global_pdaf_type;
+ u8 block_width;
+ u8 block_height;
+ u16 num_block_desc_groups;
+ struct ccs_pdaf_pix_loc_block_desc_group *block_desc_groups;
+ u8 num_pixel_desc_grups;
+ struct ccs_pdaf_pix_loc_pixel_desc_group *pixel_desc_groups;
+};
+
+/**
+ * struct ccs_data_container - In-memory CCS static data
+ * @version: CCS static data version
+ * @num_sensor_read_only_regs: Number of the read-only registers for the sensor
+ * @sensor_read_only_regs: Read-only registers for the sensor
+ * @num_sensor_manufacturer_regs: Number of the manufacturer-specific registers
+ * for the sensor
+ * @sensor_manufacturer_regs: Manufacturer-specific registers for the sensor
+ * @num_sensor_rules: Number of rules for the sensor
+ * @sensor_rules: Rules for the sensor
+ * @num_module_read_only_regs: Number of the read-only registers for the module
+ * @module_read_only_regs: Read-only registers for the module
+ * @num_module_manufacturer_regs: Number of the manufacturer-specific registers
+ * for the module
+ * @module_manufacturer_regs: Manufacturer-specific registers for the module
+ * @num_module_rules: Number of rules for the module
+ * @module_rules: Rules for the module
+ * @sensor_pdaf: PDAF data for the sensor
+ * @module_pdaf: PDAF data for the module
+ * @license_length: Lenght of the license data
+ * @license: License data
+ * @end: Whether or not there's an end block
+ * @backing: Raw data, pointed to from elsewhere so keep it around
+ */
+struct ccs_data_container {
+ struct ccs_data_block_version *version;
+ size_t num_sensor_read_only_regs;
+ struct ccs_reg *sensor_read_only_regs;
+ size_t num_sensor_manufacturer_regs;
+ struct ccs_reg *sensor_manufacturer_regs;
+ size_t num_sensor_rules;
+ struct ccs_rule *sensor_rules;
+ size_t num_module_read_only_regs;
+ struct ccs_reg *module_read_only_regs;
+ size_t num_module_manufacturer_regs;
+ struct ccs_reg *module_manufacturer_regs;
+ size_t num_module_rules;
+ struct ccs_rule *module_rules;
+ struct ccs_pdaf_pix_loc *sensor_pdaf;
+ struct ccs_pdaf_pix_loc *module_pdaf;
+ size_t license_length;
+ char *license;
+ bool end;
+ void *backing;
+};
+
+int ccs_data_parse(struct ccs_data_container *ccsdata, const void *data,
+ size_t len, struct device *dev, bool verbose);
+
+#endif /* __CCS_DATA_H__ */
diff --git a/drivers/media/i2c/ccs/ccs-limits.c b/drivers/media/i2c/ccs/ccs-limits.c
new file mode 100644
index 000000000..4969fa425
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-limits.c
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
+/* Copyright (C) 2019--2020 Intel Corporation */
+/*
+ * Generated by Documentation/driver-api/media/drivers/ccs/mk-ccs-regs;
+ * do not modify.
+ */
+
+#include "ccs-limits.h"
+#include "ccs-regs.h"
+
+const struct ccs_limit ccs_limits[] = {
+ { CCS_R_FRAME_FORMAT_MODEL_TYPE, 1, 0, "frame_format_model_type" },
+ { CCS_R_FRAME_FORMAT_MODEL_SUBTYPE, 1, 0, "frame_format_model_subtype" },
+ { CCS_R_FRAME_FORMAT_DESCRIPTOR(0), 30, 0, "frame_format_descriptor" },
+ { CCS_R_FRAME_FORMAT_DESCRIPTOR_4(0), 32, 0, "frame_format_descriptor_4" },
+ { CCS_R_ANALOG_GAIN_CAPABILITY, 2, 0, "analog_gain_capability" },
+ { CCS_R_ANALOG_GAIN_CODE_MIN, 2, 0, "analog_gain_code_min" },
+ { CCS_R_ANALOG_GAIN_CODE_MAX, 2, 0, "analog_gain_code_max" },
+ { CCS_R_ANALOG_GAIN_CODE_STEP, 2, 0, "analog_gain_code_step" },
+ { CCS_R_ANALOG_GAIN_TYPE, 2, 0, "analog_gain_type" },
+ { CCS_R_ANALOG_GAIN_M0, 2, 0, "analog_gain_m0" },
+ { CCS_R_ANALOG_GAIN_C0, 2, 0, "analog_gain_c0" },
+ { CCS_R_ANALOG_GAIN_M1, 2, 0, "analog_gain_m1" },
+ { CCS_R_ANALOG_GAIN_C1, 2, 0, "analog_gain_c1" },
+ { CCS_R_ANALOG_LINEAR_GAIN_MIN, 2, 0, "analog_linear_gain_min" },
+ { CCS_R_ANALOG_LINEAR_GAIN_MAX, 2, 0, "analog_linear_gain_max" },
+ { CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE, 2, 0, "analog_linear_gain_step_size" },
+ { CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN, 2, 0, "analog_exponential_gain_min" },
+ { CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX, 2, 0, "analog_exponential_gain_max" },
+ { CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE, 2, 0, "analog_exponential_gain_step_size" },
+ { CCS_R_DATA_FORMAT_MODEL_TYPE, 1, 0, "data_format_model_type" },
+ { CCS_R_DATA_FORMAT_MODEL_SUBTYPE, 1, 0, "data_format_model_subtype" },
+ { CCS_R_DATA_FORMAT_DESCRIPTOR(0), 32, 0, "data_format_descriptor" },
+ { CCS_R_INTEGRATION_TIME_CAPABILITY, 2, 0, "integration_time_capability" },
+ { CCS_R_COARSE_INTEGRATION_TIME_MIN, 2, 0, "coarse_integration_time_min" },
+ { CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN, 2, 0, "coarse_integration_time_max_margin" },
+ { CCS_R_FINE_INTEGRATION_TIME_MIN, 2, 0, "fine_integration_time_min" },
+ { CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN, 2, 0, "fine_integration_time_max_margin" },
+ { CCS_R_DIGITAL_GAIN_CAPABILITY, 1, 0, "digital_gain_capability" },
+ { CCS_R_DIGITAL_GAIN_MIN, 2, 0, "digital_gain_min" },
+ { CCS_R_DIGITAL_GAIN_MAX, 2, 0, "digital_gain_max" },
+ { CCS_R_DIGITAL_GAIN_STEP_SIZE, 2, 0, "digital_gain_step_size" },
+ { CCS_R_PEDESTAL_CAPABILITY, 1, 0, "Pedestal_capability" },
+ { CCS_R_ADC_CAPABILITY, 1, 0, "ADC_capability" },
+ { CCS_R_ADC_BIT_DEPTH_CAPABILITY, 4, 0, "ADC_bit_depth_capability" },
+ { CCS_R_MIN_EXT_CLK_FREQ_MHZ, 4, 0, "min_ext_clk_freq_mhz" },
+ { CCS_R_MAX_EXT_CLK_FREQ_MHZ, 4, 0, "max_ext_clk_freq_mhz" },
+ { CCS_R_MIN_PRE_PLL_CLK_DIV, 2, 0, "min_pre_pll_clk_div" },
+ { CCS_R_MAX_PRE_PLL_CLK_DIV, 2, 0, "max_pre_pll_clk_div" },
+ { CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ, 4, 0, "min_pll_ip_clk_freq_mhz" },
+ { CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ, 4, 0, "max_pll_ip_clk_freq_mhz" },
+ { CCS_R_MIN_PLL_MULTIPLIER, 2, 0, "min_pll_multiplier" },
+ { CCS_R_MAX_PLL_MULTIPLIER, 2, 0, "max_pll_multiplier" },
+ { CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ, 4, 0, "min_pll_op_clk_freq_mhz" },
+ { CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ, 4, 0, "max_pll_op_clk_freq_mhz" },
+ { CCS_R_MIN_VT_SYS_CLK_DIV, 2, 0, "min_vt_sys_clk_div" },
+ { CCS_R_MAX_VT_SYS_CLK_DIV, 2, 0, "max_vt_sys_clk_div" },
+ { CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ, 4, 0, "min_vt_sys_clk_freq_mhz" },
+ { CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ, 4, 0, "max_vt_sys_clk_freq_mhz" },
+ { CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ, 4, 0, "min_vt_pix_clk_freq_mhz" },
+ { CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ, 4, 0, "max_vt_pix_clk_freq_mhz" },
+ { CCS_R_MIN_VT_PIX_CLK_DIV, 2, 0, "min_vt_pix_clk_div" },
+ { CCS_R_MAX_VT_PIX_CLK_DIV, 2, 0, "max_vt_pix_clk_div" },
+ { CCS_R_CLOCK_CALCULATION, 1, 0, "clock_calculation" },
+ { CCS_R_NUM_OF_VT_LANES, 1, 0, "num_of_vt_lanes" },
+ { CCS_R_NUM_OF_OP_LANES, 1, 0, "num_of_op_lanes" },
+ { CCS_R_OP_BITS_PER_LANE, 1, 0, "op_bits_per_lane" },
+ { CCS_R_MIN_FRAME_LENGTH_LINES, 2, 0, "min_frame_length_lines" },
+ { CCS_R_MAX_FRAME_LENGTH_LINES, 2, 0, "max_frame_length_lines" },
+ { CCS_R_MIN_LINE_LENGTH_PCK, 2, 0, "min_line_length_pck" },
+ { CCS_R_MAX_LINE_LENGTH_PCK, 2, 0, "max_line_length_pck" },
+ { CCS_R_MIN_LINE_BLANKING_PCK, 2, 0, "min_line_blanking_pck" },
+ { CCS_R_MIN_FRAME_BLANKING_LINES, 2, 0, "min_frame_blanking_lines" },
+ { CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE, 1, 0, "min_line_length_pck_step_size" },
+ { CCS_R_TIMING_MODE_CAPABILITY, 1, 0, "timing_mode_capability" },
+ { CCS_R_FRAME_MARGIN_MAX_VALUE, 2, 0, "frame_margin_max_value" },
+ { CCS_R_FRAME_MARGIN_MIN_VALUE, 1, 0, "frame_margin_min_value" },
+ { CCS_R_GAIN_DELAY_TYPE, 1, 0, "gain_delay_type" },
+ { CCS_R_MIN_OP_SYS_CLK_DIV, 2, 0, "min_op_sys_clk_div" },
+ { CCS_R_MAX_OP_SYS_CLK_DIV, 2, 0, "max_op_sys_clk_div" },
+ { CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ, 4, 0, "min_op_sys_clk_freq_mhz" },
+ { CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ, 4, 0, "max_op_sys_clk_freq_mhz" },
+ { CCS_R_MIN_OP_PIX_CLK_DIV, 2, 0, "min_op_pix_clk_div" },
+ { CCS_R_MAX_OP_PIX_CLK_DIV, 2, 0, "max_op_pix_clk_div" },
+ { CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ, 4, 0, "min_op_pix_clk_freq_mhz" },
+ { CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ, 4, 0, "max_op_pix_clk_freq_mhz" },
+ { CCS_R_X_ADDR_MIN, 2, 0, "x_addr_min" },
+ { CCS_R_Y_ADDR_MIN, 2, 0, "y_addr_min" },
+ { CCS_R_X_ADDR_MAX, 2, 0, "x_addr_max" },
+ { CCS_R_Y_ADDR_MAX, 2, 0, "y_addr_max" },
+ { CCS_R_MIN_X_OUTPUT_SIZE, 2, 0, "min_x_output_size" },
+ { CCS_R_MIN_Y_OUTPUT_SIZE, 2, 0, "min_y_output_size" },
+ { CCS_R_MAX_X_OUTPUT_SIZE, 2, 0, "max_x_output_size" },
+ { CCS_R_MAX_Y_OUTPUT_SIZE, 2, 0, "max_y_output_size" },
+ { CCS_R_X_ADDR_START_DIV_CONSTANT, 1, 0, "x_addr_start_div_constant" },
+ { CCS_R_Y_ADDR_START_DIV_CONSTANT, 1, 0, "y_addr_start_div_constant" },
+ { CCS_R_X_ADDR_END_DIV_CONSTANT, 1, 0, "x_addr_end_div_constant" },
+ { CCS_R_Y_ADDR_END_DIV_CONSTANT, 1, 0, "y_addr_end_div_constant" },
+ { CCS_R_X_SIZE_DIV, 1, 0, "x_size_div" },
+ { CCS_R_Y_SIZE_DIV, 1, 0, "y_size_div" },
+ { CCS_R_X_OUTPUT_DIV, 1, 0, "x_output_div" },
+ { CCS_R_Y_OUTPUT_DIV, 1, 0, "y_output_div" },
+ { CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT, 1, 0, "non_flexible_resolution_support" },
+ { CCS_R_MIN_OP_PRE_PLL_CLK_DIV, 2, 0, "min_op_pre_pll_clk_div" },
+ { CCS_R_MAX_OP_PRE_PLL_CLK_DIV, 2, 0, "max_op_pre_pll_clk_div" },
+ { CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ, 4, 0, "min_op_pll_ip_clk_freq_mhz" },
+ { CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ, 4, 0, "max_op_pll_ip_clk_freq_mhz" },
+ { CCS_R_MIN_OP_PLL_MULTIPLIER, 2, 0, "min_op_pll_multiplier" },
+ { CCS_R_MAX_OP_PLL_MULTIPLIER, 2, 0, "max_op_pll_multiplier" },
+ { CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ, 4, 0, "min_op_pll_op_clk_freq_mhz" },
+ { CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ, 4, 0, "max_op_pll_op_clk_freq_mhz" },
+ { CCS_R_CLOCK_TREE_PLL_CAPABILITY, 1, 0, "clock_tree_pll_capability" },
+ { CCS_R_CLOCK_CAPA_TYPE_CAPABILITY, 1, 0, "clock_capa_type_capability" },
+ { CCS_R_MIN_EVEN_INC, 2, 0, "min_even_inc" },
+ { CCS_R_MIN_ODD_INC, 2, 0, "min_odd_inc" },
+ { CCS_R_MAX_EVEN_INC, 2, 0, "max_even_inc" },
+ { CCS_R_MAX_ODD_INC, 2, 0, "max_odd_inc" },
+ { CCS_R_AUX_SUBSAMP_CAPABILITY, 1, 0, "aux_subsamp_capability" },
+ { CCS_R_AUX_SUBSAMP_MONO_CAPABILITY, 1, 0, "aux_subsamp_mono_capability" },
+ { CCS_R_MONOCHROME_CAPABILITY, 1, 0, "monochrome_capability" },
+ { CCS_R_PIXEL_READOUT_CAPABILITY, 1, 0, "pixel_readout_capability" },
+ { CCS_R_MIN_EVEN_INC_MONO, 2, 0, "min_even_inc_mono" },
+ { CCS_R_MAX_EVEN_INC_MONO, 2, 0, "max_even_inc_mono" },
+ { CCS_R_MIN_ODD_INC_MONO, 2, 0, "min_odd_inc_mono" },
+ { CCS_R_MAX_ODD_INC_MONO, 2, 0, "max_odd_inc_mono" },
+ { CCS_R_MIN_EVEN_INC_BC2, 2, 0, "min_even_inc_bc2" },
+ { CCS_R_MAX_EVEN_INC_BC2, 2, 0, "max_even_inc_bc2" },
+ { CCS_R_MIN_ODD_INC_BC2, 2, 0, "min_odd_inc_bc2" },
+ { CCS_R_MAX_ODD_INC_BC2, 2, 0, "max_odd_inc_bc2" },
+ { CCS_R_MIN_EVEN_INC_MONO_BC2, 2, 0, "min_even_inc_mono_bc2" },
+ { CCS_R_MAX_EVEN_INC_MONO_BC2, 2, 0, "max_even_inc_mono_bc2" },
+ { CCS_R_MIN_ODD_INC_MONO_BC2, 2, 0, "min_odd_inc_mono_bc2" },
+ { CCS_R_MAX_ODD_INC_MONO_BC2, 2, 0, "max_odd_inc_mono_bc2" },
+ { CCS_R_SCALING_CAPABILITY, 2, 0, "scaling_capability" },
+ { CCS_R_SCALER_M_MIN, 2, 0, "scaler_m_min" },
+ { CCS_R_SCALER_M_MAX, 2, 0, "scaler_m_max" },
+ { CCS_R_SCALER_N_MIN, 2, 0, "scaler_n_min" },
+ { CCS_R_SCALER_N_MAX, 2, 0, "scaler_n_max" },
+ { CCS_R_DIGITAL_CROP_CAPABILITY, 1, 0, "digital_crop_capability" },
+ { CCS_R_HDR_CAPABILITY_1, 1, 0, "hdr_capability_1" },
+ { CCS_R_MIN_HDR_BIT_DEPTH, 1, 0, "min_hdr_bit_depth" },
+ { CCS_R_HDR_RESOLUTION_SUB_TYPES, 1, 0, "hdr_resolution_sub_types" },
+ { CCS_R_HDR_RESOLUTION_SUB_TYPE(0), 2, 0, "hdr_resolution_sub_type" },
+ { CCS_R_HDR_CAPABILITY_2, 1, 0, "hdr_capability_2" },
+ { CCS_R_MAX_HDR_BIT_DEPTH, 1, 0, "max_hdr_bit_depth" },
+ { CCS_R_USL_SUPPORT_CAPABILITY, 1, 0, "usl_support_capability" },
+ { CCS_R_USL_CLOCK_MODE_D_CAPABILITY, 1, 0, "usl_clock_mode_d_capability" },
+ { CCS_R_MIN_OP_SYS_CLK_DIV_REV, 1, 0, "min_op_sys_clk_div_rev" },
+ { CCS_R_MAX_OP_SYS_CLK_DIV_REV, 1, 0, "max_op_sys_clk_div_rev" },
+ { CCS_R_MIN_OP_PIX_CLK_DIV_REV, 1, 0, "min_op_pix_clk_div_rev" },
+ { CCS_R_MAX_OP_PIX_CLK_DIV_REV, 1, 0, "max_op_pix_clk_div_rev" },
+ { CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ, 4, 0, "min_op_sys_clk_freq_rev_mhz" },
+ { CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ, 4, 0, "max_op_sys_clk_freq_rev_mhz" },
+ { CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ, 4, 0, "min_op_pix_clk_freq_rev_mhz" },
+ { CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ, 4, 0, "max_op_pix_clk_freq_rev_mhz" },
+ { CCS_R_MAX_BITRATE_REV_D_MODE_MBPS, 4, 0, "max_bitrate_rev_d_mode_mbps" },
+ { CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS, 4, 0, "max_symrate_rev_c_mode_msps" },
+ { CCS_R_COMPRESSION_CAPABILITY, 1, 0, "compression_capability" },
+ { CCS_R_TEST_MODE_CAPABILITY, 2, 0, "test_mode_capability" },
+ { CCS_R_PN9_DATA_FORMAT1, 1, 0, "pn9_data_format1" },
+ { CCS_R_PN9_DATA_FORMAT2, 1, 0, "pn9_data_format2" },
+ { CCS_R_PN9_DATA_FORMAT3, 1, 0, "pn9_data_format3" },
+ { CCS_R_PN9_DATA_FORMAT4, 1, 0, "pn9_data_format4" },
+ { CCS_R_PN9_MISC_CAPABILITY, 1, 0, "pn9_misc_capability" },
+ { CCS_R_TEST_PATTERN_CAPABILITY, 1, 0, "test_pattern_capability" },
+ { CCS_R_PATTERN_SIZE_DIV_M1, 1, 0, "pattern_size_div_m1" },
+ { CCS_R_FIFO_SUPPORT_CAPABILITY, 1, 0, "fifo_support_capability" },
+ { CCS_R_PHY_CTRL_CAPABILITY, 1, 0, "phy_ctrl_capability" },
+ { CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY, 1, 0, "csi_dphy_lane_mode_capability" },
+ { CCS_R_CSI_SIGNALING_MODE_CAPABILITY, 1, 0, "csi_signaling_mode_capability" },
+ { CCS_R_FAST_STANDBY_CAPABILITY, 1, 0, "fast_standby_capability" },
+ { CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY, 1, 0, "csi_address_control_capability" },
+ { CCS_R_DATA_TYPE_CAPABILITY, 1, 0, "data_type_capability" },
+ { CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY, 1, 0, "csi_cphy_lane_mode_capability" },
+ { CCS_R_EMB_DATA_CAPABILITY, 1, 0, "emb_data_capability" },
+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(0), 16, 0, "max_per_lane_bitrate_lane_d_mode_mbps 0" },
+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(4), 16, CCS_L_FL_SAME_REG, "max_per_lane_bitrate_lane_d_mode_mbps 4" },
+ { CCS_R_TEMP_SENSOR_CAPABILITY, 1, 0, "temp_sensor_capability" },
+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(0), 16, 0, "max_per_lane_bitrate_lane_c_mode_mbps 0" },
+ { CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(4), 16, CCS_L_FL_SAME_REG, "max_per_lane_bitrate_lane_c_mode_mbps 4" },
+ { CCS_R_DPHY_EQUALIZATION_CAPABILITY, 1, 0, "dphy_equalization_capability" },
+ { CCS_R_CPHY_EQUALIZATION_CAPABILITY, 1, 0, "cphy_equalization_capability" },
+ { CCS_R_DPHY_PREAMBLE_CAPABILITY, 1, 0, "dphy_preamble_capability" },
+ { CCS_R_DPHY_SSC_CAPABILITY, 1, 0, "dphy_ssc_capability" },
+ { CCS_R_CPHY_CALIBRATION_CAPABILITY, 1, 0, "cphy_calibration_capability" },
+ { CCS_R_DPHY_CALIBRATION_CAPABILITY, 1, 0, "dphy_calibration_capability" },
+ { CCS_R_PHY_CTRL_CAPABILITY_2, 1, 0, "phy_ctrl_capability_2" },
+ { CCS_R_LRTE_CPHY_CAPABILITY, 1, 0, "lrte_cphy_capability" },
+ { CCS_R_LRTE_DPHY_CAPABILITY, 1, 0, "lrte_dphy_capability" },
+ { CCS_R_ALPS_CAPABILITY_DPHY, 1, 0, "alps_capability_dphy" },
+ { CCS_R_ALPS_CAPABILITY_CPHY, 1, 0, "alps_capability_cphy" },
+ { CCS_R_SCRAMBLING_CAPABILITY, 1, 0, "scrambling_capability" },
+ { CCS_R_DPHY_MANUAL_CONSTANT, 1, 0, "dphy_manual_constant" },
+ { CCS_R_CPHY_MANUAL_CONSTANT, 1, 0, "cphy_manual_constant" },
+ { CCS_R_CSI2_INTERFACE_CAPABILITY_MISC, 1, 0, "CSI2_interface_capability_misc" },
+ { CCS_R_PHY_CTRL_CAPABILITY_3, 1, 0, "PHY_ctrl_capability_3" },
+ { CCS_R_DPHY_SF, 1, 0, "dphy_sf" },
+ { CCS_R_CPHY_SF, 1, 0, "cphy_sf" },
+ { CCS_R_DPHY_LIMITS_1, 1, 0, "dphy_limits_1" },
+ { CCS_R_DPHY_LIMITS_2, 1, 0, "dphy_limits_2" },
+ { CCS_R_DPHY_LIMITS_3, 1, 0, "dphy_limits_3" },
+ { CCS_R_DPHY_LIMITS_4, 1, 0, "dphy_limits_4" },
+ { CCS_R_DPHY_LIMITS_5, 1, 0, "dphy_limits_5" },
+ { CCS_R_DPHY_LIMITS_6, 1, 0, "dphy_limits_6" },
+ { CCS_R_CPHY_LIMITS_1, 1, 0, "cphy_limits_1" },
+ { CCS_R_CPHY_LIMITS_2, 1, 0, "cphy_limits_2" },
+ { CCS_R_CPHY_LIMITS_3, 1, 0, "cphy_limits_3" },
+ { CCS_R_MIN_FRAME_LENGTH_LINES_BIN, 2, 0, "min_frame_length_lines_bin" },
+ { CCS_R_MAX_FRAME_LENGTH_LINES_BIN, 2, 0, "max_frame_length_lines_bin" },
+ { CCS_R_MIN_LINE_LENGTH_PCK_BIN, 2, 0, "min_line_length_pck_bin" },
+ { CCS_R_MAX_LINE_LENGTH_PCK_BIN, 2, 0, "max_line_length_pck_bin" },
+ { CCS_R_MIN_LINE_BLANKING_PCK_BIN, 2, 0, "min_line_blanking_pck_bin" },
+ { CCS_R_FINE_INTEGRATION_TIME_MIN_BIN, 2, 0, "fine_integration_time_min_bin" },
+ { CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN, 2, 0, "fine_integration_time_max_margin_bin" },
+ { CCS_R_BINNING_CAPABILITY, 1, 0, "binning_capability" },
+ { CCS_R_BINNING_WEIGHTING_CAPABILITY, 1, 0, "binning_weighting_capability" },
+ { CCS_R_BINNING_SUB_TYPES, 1, 0, "binning_sub_types" },
+ { CCS_R_BINNING_SUB_TYPE(0), 64, 0, "binning_sub_type" },
+ { CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY, 1, 0, "binning_weighting_mono_capability" },
+ { CCS_R_BINNING_SUB_TYPES_MONO, 1, 0, "binning_sub_types_mono" },
+ { CCS_R_BINNING_SUB_TYPE_MONO(0), 64, 0, "binning_sub_type_mono" },
+ { CCS_R_DATA_TRANSFER_IF_CAPABILITY, 1, 0, "data_transfer_if_capability" },
+ { CCS_R_SHADING_CORRECTION_CAPABILITY, 1, 0, "shading_correction_capability" },
+ { CCS_R_GREEN_IMBALANCE_CAPABILITY, 1, 0, "green_imbalance_capability" },
+ { CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY, 1, 0, "module_specific_correction_capability" },
+ { CCS_R_DEFECT_CORRECTION_CAPABILITY, 2, 0, "defect_correction_capability" },
+ { CCS_R_DEFECT_CORRECTION_CAPABILITY_2, 2, 0, "defect_correction_capability_2" },
+ { CCS_R_NF_CAPABILITY, 1, 0, "nf_capability" },
+ { CCS_R_OB_READOUT_CAPABILITY, 1, 0, "ob_readout_capability" },
+ { CCS_R_COLOR_FEEDBACK_CAPABILITY, 1, 0, "color_feedback_capability" },
+ { CCS_R_CFA_PATTERN_CAPABILITY, 1, 0, "CFA_pattern_capability" },
+ { CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY, 1, 0, "CFA_pattern_conversion_capability" },
+ { CCS_R_FLASH_MODE_CAPABILITY, 1, 0, "flash_mode_capability" },
+ { CCS_R_SA_STROBE_MODE_CAPABILITY, 1, 0, "sa_strobe_mode_capability" },
+ { CCS_R_RESET_MAX_DELAY, 1, 0, "reset_max_delay" },
+ { CCS_R_RESET_MIN_TIME, 1, 0, "reset_min_time" },
+ { CCS_R_PDAF_CAPABILITY_1, 1, 0, "pdaf_capability_1" },
+ { CCS_R_PDAF_CAPABILITY_2, 1, 0, "pdaf_capability_2" },
+ { CCS_R_BRACKETING_LUT_CAPABILITY_1, 1, 0, "bracketing_lut_capability_1" },
+ { CCS_R_BRACKETING_LUT_CAPABILITY_2, 1, 0, "bracketing_lut_capability_2" },
+ { CCS_R_BRACKETING_LUT_SIZE, 1, 0, "bracketing_lut_size" },
+ { 0 } /* Guardian */
+};
diff --git a/drivers/media/i2c/ccs/ccs-limits.h b/drivers/media/i2c/ccs/ccs-limits.h
new file mode 100644
index 000000000..551d3ee9d
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-limits.h
@@ -0,0 +1,263 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/* Copyright (C) 2019--2020 Intel Corporation */
+/*
+ * Generated by Documentation/driver-api/media/drivers/ccs/mk-ccs-regs;
+ * do not modify.
+ */
+
+#ifndef __CCS_LIMITS_H__
+#define __CCS_LIMITS_H__
+
+#include <linux/bits.h>
+#include <linux/types.h>
+
+struct ccs_limit {
+ u32 reg;
+ u16 size;
+ u16 flags;
+ const char *name;
+};
+
+#define CCS_L_FL_SAME_REG BIT(0)
+
+extern const struct ccs_limit ccs_limits[];
+
+#define CCS_L_FRAME_FORMAT_MODEL_TYPE 0
+#define CCS_L_FRAME_FORMAT_MODEL_SUBTYPE 1
+#define CCS_L_FRAME_FORMAT_DESCRIPTOR 2
+#define CCS_L_FRAME_FORMAT_DESCRIPTOR_OFFSET(n) ((n) * 2)
+#define CCS_L_FRAME_FORMAT_DESCRIPTOR_4 3
+#define CCS_L_FRAME_FORMAT_DESCRIPTOR_4_OFFSET(n) ((n) * 4)
+#define CCS_L_ANALOG_GAIN_CAPABILITY 4
+#define CCS_L_ANALOG_GAIN_CODE_MIN 5
+#define CCS_L_ANALOG_GAIN_CODE_MAX 6
+#define CCS_L_ANALOG_GAIN_CODE_STEP 7
+#define CCS_L_ANALOG_GAIN_TYPE 8
+#define CCS_L_ANALOG_GAIN_M0 9
+#define CCS_L_ANALOG_GAIN_C0 10
+#define CCS_L_ANALOG_GAIN_M1 11
+#define CCS_L_ANALOG_GAIN_C1 12
+#define CCS_L_ANALOG_LINEAR_GAIN_MIN 13
+#define CCS_L_ANALOG_LINEAR_GAIN_MAX 14
+#define CCS_L_ANALOG_LINEAR_GAIN_STEP_SIZE 15
+#define CCS_L_ANALOG_EXPONENTIAL_GAIN_MIN 16
+#define CCS_L_ANALOG_EXPONENTIAL_GAIN_MAX 17
+#define CCS_L_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE 18
+#define CCS_L_DATA_FORMAT_MODEL_TYPE 19
+#define CCS_L_DATA_FORMAT_MODEL_SUBTYPE 20
+#define CCS_L_DATA_FORMAT_DESCRIPTOR 21
+#define CCS_L_DATA_FORMAT_DESCRIPTOR_OFFSET(n) ((n) * 2)
+#define CCS_L_INTEGRATION_TIME_CAPABILITY 22
+#define CCS_L_COARSE_INTEGRATION_TIME_MIN 23
+#define CCS_L_COARSE_INTEGRATION_TIME_MAX_MARGIN 24
+#define CCS_L_FINE_INTEGRATION_TIME_MIN 25
+#define CCS_L_FINE_INTEGRATION_TIME_MAX_MARGIN 26
+#define CCS_L_DIGITAL_GAIN_CAPABILITY 27
+#define CCS_L_DIGITAL_GAIN_MIN 28
+#define CCS_L_DIGITAL_GAIN_MAX 29
+#define CCS_L_DIGITAL_GAIN_STEP_SIZE 30
+#define CCS_L_PEDESTAL_CAPABILITY 31
+#define CCS_L_ADC_CAPABILITY 32
+#define CCS_L_ADC_BIT_DEPTH_CAPABILITY 33
+#define CCS_L_MIN_EXT_CLK_FREQ_MHZ 34
+#define CCS_L_MAX_EXT_CLK_FREQ_MHZ 35
+#define CCS_L_MIN_PRE_PLL_CLK_DIV 36
+#define CCS_L_MAX_PRE_PLL_CLK_DIV 37
+#define CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ 38
+#define CCS_L_MAX_PLL_IP_CLK_FREQ_MHZ 39
+#define CCS_L_MIN_PLL_MULTIPLIER 40
+#define CCS_L_MAX_PLL_MULTIPLIER 41
+#define CCS_L_MIN_PLL_OP_CLK_FREQ_MHZ 42
+#define CCS_L_MAX_PLL_OP_CLK_FREQ_MHZ 43
+#define CCS_L_MIN_VT_SYS_CLK_DIV 44
+#define CCS_L_MAX_VT_SYS_CLK_DIV 45
+#define CCS_L_MIN_VT_SYS_CLK_FREQ_MHZ 46
+#define CCS_L_MAX_VT_SYS_CLK_FREQ_MHZ 47
+#define CCS_L_MIN_VT_PIX_CLK_FREQ_MHZ 48
+#define CCS_L_MAX_VT_PIX_CLK_FREQ_MHZ 49
+#define CCS_L_MIN_VT_PIX_CLK_DIV 50
+#define CCS_L_MAX_VT_PIX_CLK_DIV 51
+#define CCS_L_CLOCK_CALCULATION 52
+#define CCS_L_NUM_OF_VT_LANES 53
+#define CCS_L_NUM_OF_OP_LANES 54
+#define CCS_L_OP_BITS_PER_LANE 55
+#define CCS_L_MIN_FRAME_LENGTH_LINES 56
+#define CCS_L_MAX_FRAME_LENGTH_LINES 57
+#define CCS_L_MIN_LINE_LENGTH_PCK 58
+#define CCS_L_MAX_LINE_LENGTH_PCK 59
+#define CCS_L_MIN_LINE_BLANKING_PCK 60
+#define CCS_L_MIN_FRAME_BLANKING_LINES 61
+#define CCS_L_MIN_LINE_LENGTH_PCK_STEP_SIZE 62
+#define CCS_L_TIMING_MODE_CAPABILITY 63
+#define CCS_L_FRAME_MARGIN_MAX_VALUE 64
+#define CCS_L_FRAME_MARGIN_MIN_VALUE 65
+#define CCS_L_GAIN_DELAY_TYPE 66
+#define CCS_L_MIN_OP_SYS_CLK_DIV 67
+#define CCS_L_MAX_OP_SYS_CLK_DIV 68
+#define CCS_L_MIN_OP_SYS_CLK_FREQ_MHZ 69
+#define CCS_L_MAX_OP_SYS_CLK_FREQ_MHZ 70
+#define CCS_L_MIN_OP_PIX_CLK_DIV 71
+#define CCS_L_MAX_OP_PIX_CLK_DIV 72
+#define CCS_L_MIN_OP_PIX_CLK_FREQ_MHZ 73
+#define CCS_L_MAX_OP_PIX_CLK_FREQ_MHZ 74
+#define CCS_L_X_ADDR_MIN 75
+#define CCS_L_Y_ADDR_MIN 76
+#define CCS_L_X_ADDR_MAX 77
+#define CCS_L_Y_ADDR_MAX 78
+#define CCS_L_MIN_X_OUTPUT_SIZE 79
+#define CCS_L_MIN_Y_OUTPUT_SIZE 80
+#define CCS_L_MAX_X_OUTPUT_SIZE 81
+#define CCS_L_MAX_Y_OUTPUT_SIZE 82
+#define CCS_L_X_ADDR_START_DIV_CONSTANT 83
+#define CCS_L_Y_ADDR_START_DIV_CONSTANT 84
+#define CCS_L_X_ADDR_END_DIV_CONSTANT 85
+#define CCS_L_Y_ADDR_END_DIV_CONSTANT 86
+#define CCS_L_X_SIZE_DIV 87
+#define CCS_L_Y_SIZE_DIV 88
+#define CCS_L_X_OUTPUT_DIV 89
+#define CCS_L_Y_OUTPUT_DIV 90
+#define CCS_L_NON_FLEXIBLE_RESOLUTION_SUPPORT 91
+#define CCS_L_MIN_OP_PRE_PLL_CLK_DIV 92
+#define CCS_L_MAX_OP_PRE_PLL_CLK_DIV 93
+#define CCS_L_MIN_OP_PLL_IP_CLK_FREQ_MHZ 94
+#define CCS_L_MAX_OP_PLL_IP_CLK_FREQ_MHZ 95
+#define CCS_L_MIN_OP_PLL_MULTIPLIER 96
+#define CCS_L_MAX_OP_PLL_MULTIPLIER 97
+#define CCS_L_MIN_OP_PLL_OP_CLK_FREQ_MHZ 98
+#define CCS_L_MAX_OP_PLL_OP_CLK_FREQ_MHZ 99
+#define CCS_L_CLOCK_TREE_PLL_CAPABILITY 100
+#define CCS_L_CLOCK_CAPA_TYPE_CAPABILITY 101
+#define CCS_L_MIN_EVEN_INC 102
+#define CCS_L_MIN_ODD_INC 103
+#define CCS_L_MAX_EVEN_INC 104
+#define CCS_L_MAX_ODD_INC 105
+#define CCS_L_AUX_SUBSAMP_CAPABILITY 106
+#define CCS_L_AUX_SUBSAMP_MONO_CAPABILITY 107
+#define CCS_L_MONOCHROME_CAPABILITY 108
+#define CCS_L_PIXEL_READOUT_CAPABILITY 109
+#define CCS_L_MIN_EVEN_INC_MONO 110
+#define CCS_L_MAX_EVEN_INC_MONO 111
+#define CCS_L_MIN_ODD_INC_MONO 112
+#define CCS_L_MAX_ODD_INC_MONO 113
+#define CCS_L_MIN_EVEN_INC_BC2 114
+#define CCS_L_MAX_EVEN_INC_BC2 115
+#define CCS_L_MIN_ODD_INC_BC2 116
+#define CCS_L_MAX_ODD_INC_BC2 117
+#define CCS_L_MIN_EVEN_INC_MONO_BC2 118
+#define CCS_L_MAX_EVEN_INC_MONO_BC2 119
+#define CCS_L_MIN_ODD_INC_MONO_BC2 120
+#define CCS_L_MAX_ODD_INC_MONO_BC2 121
+#define CCS_L_SCALING_CAPABILITY 122
+#define CCS_L_SCALER_M_MIN 123
+#define CCS_L_SCALER_M_MAX 124
+#define CCS_L_SCALER_N_MIN 125
+#define CCS_L_SCALER_N_MAX 126
+#define CCS_L_DIGITAL_CROP_CAPABILITY 127
+#define CCS_L_HDR_CAPABILITY_1 128
+#define CCS_L_MIN_HDR_BIT_DEPTH 129
+#define CCS_L_HDR_RESOLUTION_SUB_TYPES 130
+#define CCS_L_HDR_RESOLUTION_SUB_TYPE 131
+#define CCS_L_HDR_RESOLUTION_SUB_TYPE_OFFSET(n) (n)
+#define CCS_L_HDR_CAPABILITY_2 132
+#define CCS_L_MAX_HDR_BIT_DEPTH 133
+#define CCS_L_USL_SUPPORT_CAPABILITY 134
+#define CCS_L_USL_CLOCK_MODE_D_CAPABILITY 135
+#define CCS_L_MIN_OP_SYS_CLK_DIV_REV 136
+#define CCS_L_MAX_OP_SYS_CLK_DIV_REV 137
+#define CCS_L_MIN_OP_PIX_CLK_DIV_REV 138
+#define CCS_L_MAX_OP_PIX_CLK_DIV_REV 139
+#define CCS_L_MIN_OP_SYS_CLK_FREQ_REV_MHZ 140
+#define CCS_L_MAX_OP_SYS_CLK_FREQ_REV_MHZ 141
+#define CCS_L_MIN_OP_PIX_CLK_FREQ_REV_MHZ 142
+#define CCS_L_MAX_OP_PIX_CLK_FREQ_REV_MHZ 143
+#define CCS_L_MAX_BITRATE_REV_D_MODE_MBPS 144
+#define CCS_L_MAX_SYMRATE_REV_C_MODE_MSPS 145
+#define CCS_L_COMPRESSION_CAPABILITY 146
+#define CCS_L_TEST_MODE_CAPABILITY 147
+#define CCS_L_PN9_DATA_FORMAT1 148
+#define CCS_L_PN9_DATA_FORMAT2 149
+#define CCS_L_PN9_DATA_FORMAT3 150
+#define CCS_L_PN9_DATA_FORMAT4 151
+#define CCS_L_PN9_MISC_CAPABILITY 152
+#define CCS_L_TEST_PATTERN_CAPABILITY 153
+#define CCS_L_PATTERN_SIZE_DIV_M1 154
+#define CCS_L_FIFO_SUPPORT_CAPABILITY 155
+#define CCS_L_PHY_CTRL_CAPABILITY 156
+#define CCS_L_CSI_DPHY_LANE_MODE_CAPABILITY 157
+#define CCS_L_CSI_SIGNALING_MODE_CAPABILITY 158
+#define CCS_L_FAST_STANDBY_CAPABILITY 159
+#define CCS_L_CSI_ADDRESS_CONTROL_CAPABILITY 160
+#define CCS_L_DATA_TYPE_CAPABILITY 161
+#define CCS_L_CSI_CPHY_LANE_MODE_CAPABILITY 162
+#define CCS_L_EMB_DATA_CAPABILITY 163
+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS 164
+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_OFFSET(n) ((n) * 4)
+#define CCS_L_TEMP_SENSOR_CAPABILITY 165
+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS 166
+#define CCS_L_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_OFFSET(n) ((n) * 4)
+#define CCS_L_DPHY_EQUALIZATION_CAPABILITY 167
+#define CCS_L_CPHY_EQUALIZATION_CAPABILITY 168
+#define CCS_L_DPHY_PREAMBLE_CAPABILITY 169
+#define CCS_L_DPHY_SSC_CAPABILITY 170
+#define CCS_L_CPHY_CALIBRATION_CAPABILITY 171
+#define CCS_L_DPHY_CALIBRATION_CAPABILITY 172
+#define CCS_L_PHY_CTRL_CAPABILITY_2 173
+#define CCS_L_LRTE_CPHY_CAPABILITY 174
+#define CCS_L_LRTE_DPHY_CAPABILITY 175
+#define CCS_L_ALPS_CAPABILITY_DPHY 176
+#define CCS_L_ALPS_CAPABILITY_CPHY 177
+#define CCS_L_SCRAMBLING_CAPABILITY 178
+#define CCS_L_DPHY_MANUAL_CONSTANT 179
+#define CCS_L_CPHY_MANUAL_CONSTANT 180
+#define CCS_L_CSI2_INTERFACE_CAPABILITY_MISC 181
+#define CCS_L_PHY_CTRL_CAPABILITY_3 182
+#define CCS_L_DPHY_SF 183
+#define CCS_L_CPHY_SF 184
+#define CCS_L_DPHY_LIMITS_1 185
+#define CCS_L_DPHY_LIMITS_2 186
+#define CCS_L_DPHY_LIMITS_3 187
+#define CCS_L_DPHY_LIMITS_4 188
+#define CCS_L_DPHY_LIMITS_5 189
+#define CCS_L_DPHY_LIMITS_6 190
+#define CCS_L_CPHY_LIMITS_1 191
+#define CCS_L_CPHY_LIMITS_2 192
+#define CCS_L_CPHY_LIMITS_3 193
+#define CCS_L_MIN_FRAME_LENGTH_LINES_BIN 194
+#define CCS_L_MAX_FRAME_LENGTH_LINES_BIN 195
+#define CCS_L_MIN_LINE_LENGTH_PCK_BIN 196
+#define CCS_L_MAX_LINE_LENGTH_PCK_BIN 197
+#define CCS_L_MIN_LINE_BLANKING_PCK_BIN 198
+#define CCS_L_FINE_INTEGRATION_TIME_MIN_BIN 199
+#define CCS_L_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN 200
+#define CCS_L_BINNING_CAPABILITY 201
+#define CCS_L_BINNING_WEIGHTING_CAPABILITY 202
+#define CCS_L_BINNING_SUB_TYPES 203
+#define CCS_L_BINNING_SUB_TYPE 204
+#define CCS_L_BINNING_SUB_TYPE_OFFSET(n) (n)
+#define CCS_L_BINNING_WEIGHTING_MONO_CAPABILITY 205
+#define CCS_L_BINNING_SUB_TYPES_MONO 206
+#define CCS_L_BINNING_SUB_TYPE_MONO 207
+#define CCS_L_BINNING_SUB_TYPE_MONO_OFFSET(n) (n)
+#define CCS_L_DATA_TRANSFER_IF_CAPABILITY 208
+#define CCS_L_SHADING_CORRECTION_CAPABILITY 209
+#define CCS_L_GREEN_IMBALANCE_CAPABILITY 210
+#define CCS_L_MODULE_SPECIFIC_CORRECTION_CAPABILITY 211
+#define CCS_L_DEFECT_CORRECTION_CAPABILITY 212
+#define CCS_L_DEFECT_CORRECTION_CAPABILITY_2 213
+#define CCS_L_NF_CAPABILITY 214
+#define CCS_L_OB_READOUT_CAPABILITY 215
+#define CCS_L_COLOR_FEEDBACK_CAPABILITY 216
+#define CCS_L_CFA_PATTERN_CAPABILITY 217
+#define CCS_L_CFA_PATTERN_CONVERSION_CAPABILITY 218
+#define CCS_L_FLASH_MODE_CAPABILITY 219
+#define CCS_L_SA_STROBE_MODE_CAPABILITY 220
+#define CCS_L_RESET_MAX_DELAY 221
+#define CCS_L_RESET_MIN_TIME 222
+#define CCS_L_PDAF_CAPABILITY_1 223
+#define CCS_L_PDAF_CAPABILITY_2 224
+#define CCS_L_BRACKETING_LUT_CAPABILITY_1 225
+#define CCS_L_BRACKETING_LUT_CAPABILITY_2 226
+#define CCS_L_BRACKETING_LUT_SIZE 227
+#define CCS_L_LAST 228
+
+#endif /* __CCS_LIMITS_H__ */
diff --git a/drivers/media/i2c/ccs/ccs-quirk.c b/drivers/media/i2c/ccs/ccs-quirk.c
new file mode 100644
index 000000000..e3d4c7a27
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-quirk.c
@@ -0,0 +1,218 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * drivers/media/i2c/ccs/ccs-quirk.c
+ *
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
+ *
+ * Copyright (C) 2020 Intel Corporation
+ * Copyright (C) 2011--2012 Nokia Corporation
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
+ */
+
+#include <linux/delay.h>
+
+#include "ccs.h"
+#include "ccs-limits.h"
+
+static int ccs_write_addr_8s(struct ccs_sensor *sensor,
+ const struct ccs_reg_8 *regs, int len)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+
+ for (; len > 0; len--, regs++) {
+ rval = ccs_write_addr(sensor, regs->reg, regs->val);
+ if (rval < 0) {
+ dev_err(&client->dev,
+ "error %d writing reg 0x%4.4x, val 0x%2.2x",
+ rval, regs->reg, regs->val);
+ return rval;
+ }
+ }
+
+ return 0;
+}
+
+static int jt8ew9_limits(struct ccs_sensor *sensor)
+{
+ if (sensor->minfo.revision_number < 0x0300)
+ sensor->frame_skip = 1;
+
+ /* Below 24 gain doesn't have effect at all, */
+ /* but ~59 is needed for full dynamic range */
+ ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MIN, 0, 59);
+ ccs_replace_limit(sensor, CCS_L_ANALOG_GAIN_CODE_MAX, 0, 6000);
+
+ return 0;
+}
+
+static int jt8ew9_post_poweron(struct ccs_sensor *sensor)
+{
+ static const struct ccs_reg_8 regs[] = {
+ { 0x30a3, 0xd8 }, /* Output port control : LVDS ports only */
+ { 0x30ae, 0x00 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
+ { 0x30af, 0xd0 }, /* 0x0307 pll_multiplier maximum value on PLL input 9.6MHz ( 19.2MHz is divided on pre_pll_div) */
+ { 0x322d, 0x04 }, /* Adjusting Processing Image Size to Scaler Toshiba Recommendation Setting */
+ { 0x3255, 0x0f }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */
+ { 0x3256, 0x15 }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */
+ { 0x3258, 0x70 }, /* Analog Gain Control Toshiba Recommendation Setting */
+ { 0x3259, 0x70 }, /* Analog Gain Control Toshiba Recommendation Setting */
+ { 0x325f, 0x7c }, /* Analog Gain Control Toshiba Recommendation Setting */
+ { 0x3302, 0x06 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
+ { 0x3304, 0x00 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
+ { 0x3307, 0x22 }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
+ { 0x3308, 0x8d }, /* Pixel Reference Voltage Control Toshiba Recommendation Setting */
+ { 0x331e, 0x0f }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
+ { 0x3320, 0x30 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
+ { 0x3321, 0x11 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
+ { 0x3322, 0x98 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
+ { 0x3323, 0x64 }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
+ { 0x3325, 0x83 }, /* Read Out Timing Control Toshiba Recommendation Setting */
+ { 0x3330, 0x18 }, /* Read Out Timing Control Toshiba Recommendation Setting */
+ { 0x333c, 0x01 }, /* Read Out Timing Control Toshiba Recommendation Setting */
+ { 0x3345, 0x2f }, /* Black Hole Sun Correction Control Toshiba Recommendation Setting */
+ { 0x33de, 0x38 }, /* Horizontal Noise Reduction Control Toshiba Recommendation Setting */
+ /* Taken from v03. No idea what the rest are. */
+ { 0x32e0, 0x05 },
+ { 0x32e1, 0x05 },
+ { 0x32e2, 0x04 },
+ { 0x32e5, 0x04 },
+ { 0x32e6, 0x04 },
+
+ };
+
+ return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
+}
+
+const struct ccs_quirk smiapp_jt8ew9_quirk = {
+ .limits = jt8ew9_limits,
+ .post_poweron = jt8ew9_post_poweron,
+};
+
+static int imx125es_post_poweron(struct ccs_sensor *sensor)
+{
+ /* Taken from v02. No idea what the other two are. */
+ static const struct ccs_reg_8 regs[] = {
+ /*
+ * 0x3302: clk during frame blanking:
+ * 0x00 - HS mode, 0x01 - LP11
+ */
+ { 0x3302, 0x01 },
+ { 0x302d, 0x00 },
+ { 0x3b08, 0x8c },
+ };
+
+ return ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
+}
+
+const struct ccs_quirk smiapp_imx125es_quirk = {
+ .post_poweron = imx125es_post_poweron,
+};
+
+static int jt8ev1_limits(struct ccs_sensor *sensor)
+{
+ ccs_replace_limit(sensor, CCS_L_X_ADDR_MAX, 0, 4271);
+ ccs_replace_limit(sensor, CCS_L_MIN_LINE_BLANKING_PCK_BIN, 0, 184);
+
+ return 0;
+}
+
+static int jt8ev1_post_poweron(struct ccs_sensor *sensor)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ int rval;
+ static const struct ccs_reg_8 regs[] = {
+ { 0x3031, 0xcd }, /* For digital binning (EQ_MONI) */
+ { 0x30a3, 0xd0 }, /* FLASH STROBE enable */
+ { 0x3237, 0x00 }, /* For control of pulse timing for ADC */
+ { 0x3238, 0x43 },
+ { 0x3301, 0x06 }, /* For analog bias for sensor */
+ { 0x3302, 0x06 },
+ { 0x3304, 0x00 },
+ { 0x3305, 0x88 },
+ { 0x332a, 0x14 },
+ { 0x332c, 0x6b },
+ { 0x3336, 0x01 },
+ { 0x333f, 0x1f },
+ { 0x3355, 0x00 },
+ { 0x3356, 0x20 },
+ { 0x33bf, 0x20 }, /* Adjust the FBC speed */
+ { 0x33c9, 0x20 },
+ { 0x33ce, 0x30 }, /* Adjust the parameter for logic function */
+ { 0x33cf, 0xec }, /* For Black sun */
+ { 0x3328, 0x80 }, /* Ugh. No idea what's this. */
+ };
+ static const struct ccs_reg_8 regs_96[] = {
+ { 0x30ae, 0x00 }, /* For control of ADC clock */
+ { 0x30af, 0xd0 },
+ { 0x30b0, 0x01 },
+ };
+
+ rval = ccs_write_addr_8s(sensor, regs, ARRAY_SIZE(regs));
+ if (rval < 0)
+ return rval;
+
+ switch (sensor->hwcfg.ext_clk) {
+ case 9600000:
+ return ccs_write_addr_8s(sensor, regs_96,
+ ARRAY_SIZE(regs_96));
+ default:
+ dev_warn(&client->dev, "no MSRs for %d Hz ext_clk\n",
+ sensor->hwcfg.ext_clk);
+ return 0;
+ }
+}
+
+static int jt8ev1_pre_streamon(struct ccs_sensor *sensor)
+{
+ return ccs_write_addr(sensor, 0x3328, 0x00);
+}
+
+static int jt8ev1_post_streamoff(struct ccs_sensor *sensor)
+{
+ int rval;
+
+ /* Workaround: allows fast standby to work properly */
+ rval = ccs_write_addr(sensor, 0x3205, 0x04);
+ if (rval < 0)
+ return rval;
+
+ /* Wait for 1 ms + one line => 2 ms is likely enough */
+ usleep_range(2000, 2050);
+
+ /* Restore it */
+ rval = ccs_write_addr(sensor, 0x3205, 0x00);
+ if (rval < 0)
+ return rval;
+
+ return ccs_write_addr(sensor, 0x3328, 0x80);
+}
+
+static int jt8ev1_init(struct ccs_sensor *sensor)
+{
+ sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL |
+ CCS_PLL_FLAG_LINK_DECOUPLED;
+ sensor->pll.vt_lanes = 1;
+ sensor->pll.op_lanes = sensor->pll.csi2.lanes;
+
+ return 0;
+}
+
+const struct ccs_quirk smiapp_jt8ev1_quirk = {
+ .limits = jt8ev1_limits,
+ .post_poweron = jt8ev1_post_poweron,
+ .pre_streamon = jt8ev1_pre_streamon,
+ .post_streamoff = jt8ev1_post_streamoff,
+ .init = jt8ev1_init,
+};
+
+static int tcm8500md_limits(struct ccs_sensor *sensor)
+{
+ ccs_replace_limit(sensor, CCS_L_MIN_PLL_IP_CLK_FREQ_MHZ, 0, 2700000);
+
+ return 0;
+}
+
+const struct ccs_quirk smiapp_tcm8500md_quirk = {
+ .limits = tcm8500md_limits,
+};
diff --git a/drivers/media/i2c/ccs/ccs-quirk.h b/drivers/media/i2c/ccs/ccs-quirk.h
new file mode 100644
index 000000000..0b1a64958
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-quirk.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * drivers/media/i2c/ccs/ccs-quirk.h
+ *
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
+ *
+ * Copyright (C) 2020 Intel Corporation
+ * Copyright (C) 2011--2012 Nokia Corporation
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
+ */
+
+#ifndef __CCS_QUIRK__
+#define __CCS_QUIRK__
+
+struct ccs_sensor;
+
+/**
+ * struct ccs_quirk - quirks for sensors that deviate from SMIA++ standard
+ *
+ * @limits: Replace sensor->limits with values which can't be read from
+ * sensor registers. Called the first time the sensor is powered up.
+ * @post_poweron: Called always after the sensor has been fully powered on.
+ * @pre_streamon: Called just before streaming is enabled.
+ * @post_streamoff: Called right after stopping streaming.
+ * @pll_flags: Return flags for the PLL calculator.
+ * @init: Quirk initialisation, called the last in probe(). This is
+ * also appropriate for adding sensor specific controls, for instance.
+ * @reg_access: Register access quirk. The quirk may divert the access
+ * to another register, or no register at all.
+ *
+ * @write: Is this read (false) or write (true) access?
+ * @reg: Pointer to the register to access
+ * @value: Register value, set by the caller on write, or
+ * by the quirk on read
+ * @return: 0 on success, -ENOIOCTLCMD if no register
+ * access may be done by the caller (default read
+ * value is zero), else negative error code on error
+ * @flags: Quirk flags
+ */
+struct ccs_quirk {
+ int (*limits)(struct ccs_sensor *sensor);
+ int (*post_poweron)(struct ccs_sensor *sensor);
+ int (*pre_streamon)(struct ccs_sensor *sensor);
+ int (*post_streamoff)(struct ccs_sensor *sensor);
+ unsigned long (*pll_flags)(struct ccs_sensor *sensor);
+ int (*init)(struct ccs_sensor *sensor);
+ int (*reg_access)(struct ccs_sensor *sensor, bool write, u32 *reg,
+ u32 *val);
+ unsigned long flags;
+};
+
+#define CCS_QUIRK_FLAG_8BIT_READ_ONLY (1 << 0)
+
+struct ccs_reg_8 {
+ u16 reg;
+ u8 val;
+};
+
+#define CCS_MK_QUIRK_REG_8(_reg, _val) \
+ { \
+ .reg = (u16)_reg, \
+ .val = _val, \
+ }
+
+#define ccs_call_quirk(sensor, _quirk, ...) \
+ ((sensor)->minfo.quirk && \
+ (sensor)->minfo.quirk->_quirk ? \
+ (sensor)->minfo.quirk->_quirk(sensor, ##__VA_ARGS__) : 0)
+
+#define ccs_needs_quirk(sensor, _quirk) \
+ ((sensor)->minfo.quirk ? \
+ (sensor)->minfo.quirk->flags & _quirk : 0)
+
+extern const struct ccs_quirk smiapp_jt8ev1_quirk;
+extern const struct ccs_quirk smiapp_imx125es_quirk;
+extern const struct ccs_quirk smiapp_jt8ew9_quirk;
+extern const struct ccs_quirk smiapp_tcm8500md_quirk;
+
+#endif /* __CCS_QUIRK__ */
diff --git a/drivers/media/i2c/ccs/ccs-reg-access.c b/drivers/media/i2c/ccs/ccs-reg-access.c
new file mode 100644
index 000000000..25993445f
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-reg-access.c
@@ -0,0 +1,416 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * drivers/media/i2c/ccs/ccs-reg-access.c
+ *
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
+ *
+ * Copyright (C) 2020 Intel Corporation
+ * Copyright (C) 2011--2012 Nokia Corporation
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
+ */
+
+#include <asm/unaligned.h>
+
+#include <linux/delay.h>
+#include <linux/i2c.h>
+
+#include "ccs.h"
+#include "ccs-limits.h"
+
+static u32 float_to_u32_mul_1000000(struct i2c_client *client, u32 phloat)
+{
+ s32 exp;
+ u64 man;
+
+ if (phloat >= 0x80000000) {
+ dev_err(&client->dev, "this is a negative number\n");
+ return 0;
+ }
+
+ if (phloat == 0x7f800000)
+ return ~0; /* Inf. */
+
+ if ((phloat & 0x7f800000) == 0x7f800000) {
+ dev_err(&client->dev, "NaN or other special number\n");
+ return 0;
+ }
+
+ /* Valid cases begin here */
+ if (phloat == 0)
+ return 0; /* Valid zero */
+
+ if (phloat > 0x4f800000)
+ return ~0; /* larger than 4294967295 */
+
+ /*
+ * Unbias exponent (note how phloat is now guaranteed to
+ * have 0 in the high bit)
+ */
+ exp = ((int32_t)phloat >> 23) - 127;
+
+ /* Extract mantissa, add missing '1' bit and it's in MHz */
+ man = ((phloat & 0x7fffff) | 0x800000) * 1000000ULL;
+
+ if (exp < 0)
+ man >>= -exp;
+ else
+ man <<= exp;
+
+ man >>= 23; /* Remove mantissa bias */
+
+ return man & 0xffffffff;
+}
+
+
+/*
+ * Read a 8/16/32-bit i2c register. The value is returned in 'val'.
+ * Returns zero if successful, or non-zero otherwise.
+ */
+static int ____ccs_read_addr(struct ccs_sensor *sensor, u16 reg, u16 len,
+ u32 *val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ struct i2c_msg msg;
+ unsigned char data_buf[sizeof(u32)] = { 0 };
+ unsigned char offset_buf[sizeof(u16)];
+ int r;
+
+ if (len > sizeof(data_buf))
+ return -EINVAL;
+
+ msg.addr = client->addr;
+ msg.flags = 0;
+ msg.len = sizeof(offset_buf);
+ msg.buf = offset_buf;
+ put_unaligned_be16(reg, offset_buf);
+
+ r = i2c_transfer(client->adapter, &msg, 1);
+ if (r != 1) {
+ if (r >= 0)
+ r = -EBUSY;
+ goto err;
+ }
+
+ msg.len = len;
+ msg.flags = I2C_M_RD;
+ msg.buf = &data_buf[sizeof(data_buf) - len];
+
+ r = i2c_transfer(client->adapter, &msg, 1);
+ if (r != 1) {
+ if (r >= 0)
+ r = -EBUSY;
+ goto err;
+ }
+
+ *val = get_unaligned_be32(data_buf);
+
+ return 0;
+
+err:
+ dev_err(&client->dev, "read from offset 0x%x error %d\n", reg, r);
+
+ return r;
+}
+
+/* Read a register using 8-bit access only. */
+static int ____ccs_read_addr_8only(struct ccs_sensor *sensor, u16 reg,
+ u16 len, u32 *val)
+{
+ unsigned int i;
+ int rval;
+
+ *val = 0;
+
+ for (i = 0; i < len; i++) {
+ u32 val8;
+
+ rval = ____ccs_read_addr(sensor, reg + i, 1, &val8);
+ if (rval < 0)
+ return rval;
+ *val |= val8 << ((len - i - 1) << 3);
+ }
+
+ return 0;
+}
+
+unsigned int ccs_reg_width(u32 reg)
+{
+ if (reg & CCS_FL_16BIT)
+ return sizeof(u16);
+ if (reg & CCS_FL_32BIT)
+ return sizeof(u32);
+
+ return sizeof(u8);
+}
+
+static u32 ireal32_to_u32_mul_1000000(struct i2c_client *client, u32 val)
+{
+ if (val >> 10 > U32_MAX / 15625) {
+ dev_warn(&client->dev, "value %u overflows!\n", val);
+ return U32_MAX;
+ }
+
+ return ((val >> 10) * 15625) +
+ (val & GENMASK(9, 0)) * 15625 / 1024;
+}
+
+u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+
+ if (reg & CCS_FL_FLOAT_IREAL) {
+ if (CCS_LIM(sensor, CLOCK_CAPA_TYPE_CAPABILITY) &
+ CCS_CLOCK_CAPA_TYPE_CAPABILITY_IREAL)
+ val = ireal32_to_u32_mul_1000000(client, val);
+ else
+ val = float_to_u32_mul_1000000(client, val);
+ } else if (reg & CCS_FL_IREAL) {
+ val = ireal32_to_u32_mul_1000000(client, val);
+ }
+
+ return val;
+}
+
+/*
+ * Read a 8/16/32-bit i2c register. The value is returned in 'val'.
+ * Returns zero if successful, or non-zero otherwise.
+ */
+static int __ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val,
+ bool only8, bool conv)
+{
+ unsigned int len = ccs_reg_width(reg);
+ int rval;
+
+ if (!only8)
+ rval = ____ccs_read_addr(sensor, CCS_REG_ADDR(reg), len, val);
+ else
+ rval = ____ccs_read_addr_8only(sensor, CCS_REG_ADDR(reg), len,
+ val);
+ if (rval < 0)
+ return rval;
+
+ if (!conv)
+ return 0;
+
+ *val = ccs_reg_conv(sensor, reg, *val);
+
+ return 0;
+}
+
+static int __ccs_read_data(struct ccs_reg *regs, size_t num_regs,
+ u32 reg, u32 *val)
+{
+ unsigned int width = ccs_reg_width(reg);
+ size_t i;
+
+ for (i = 0; i < num_regs; i++, regs++) {
+ u8 *data;
+
+ if (regs->addr + regs->len < CCS_REG_ADDR(reg) + width)
+ continue;
+
+ if (regs->addr > CCS_REG_ADDR(reg))
+ break;
+
+ data = &regs->value[CCS_REG_ADDR(reg) - regs->addr];
+
+ switch (width) {
+ case sizeof(u8):
+ *val = *data;
+ break;
+ case sizeof(u16):
+ *val = get_unaligned_be16(data);
+ break;
+ case sizeof(u32):
+ *val = get_unaligned_be32(data);
+ break;
+ default:
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
+ return 0;
+ }
+
+ return -ENOENT;
+}
+
+static int ccs_read_data(struct ccs_sensor *sensor, u32 reg, u32 *val)
+{
+ if (!__ccs_read_data(sensor->sdata.sensor_read_only_regs,
+ sensor->sdata.num_sensor_read_only_regs,
+ reg, val))
+ return 0;
+
+ return __ccs_read_data(sensor->mdata.module_read_only_regs,
+ sensor->mdata.num_module_read_only_regs,
+ reg, val);
+}
+
+static int ccs_read_addr_raw(struct ccs_sensor *sensor, u32 reg, u32 *val,
+ bool force8, bool quirk, bool conv, bool data)
+{
+ int rval;
+
+ if (data) {
+ rval = ccs_read_data(sensor, reg, val);
+ if (!rval)
+ return 0;
+ }
+
+ if (quirk) {
+ *val = 0;
+ rval = ccs_call_quirk(sensor, reg_access, false, &reg, val);
+ if (rval == -ENOIOCTLCMD)
+ return 0;
+ if (rval < 0)
+ return rval;
+
+ if (force8)
+ return __ccs_read_addr(sensor, reg, val, true, conv);
+ }
+
+ return __ccs_read_addr(sensor, reg, val,
+ ccs_needs_quirk(sensor,
+ CCS_QUIRK_FLAG_8BIT_READ_ONLY),
+ conv);
+}
+
+int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val)
+{
+ return ccs_read_addr_raw(sensor, reg, val, false, true, true, true);
+}
+
+int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val)
+{
+ return ccs_read_addr_raw(sensor, reg, val, true, true, true, true);
+}
+
+int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val)
+{
+ return ccs_read_addr_raw(sensor, reg, val, false, true, false, true);
+}
+
+static int ccs_write_retry(struct i2c_client *client, struct i2c_msg *msg)
+{
+ unsigned int retries;
+ int r;
+
+ for (retries = 0; retries < 10; retries++) {
+ /*
+ * Due to unknown reason sensor stops responding. This
+ * loop is a temporaty solution until the root cause
+ * is found.
+ */
+ r = i2c_transfer(client->adapter, msg, 1);
+ if (r != 1) {
+ usleep_range(1000, 2000);
+ continue;
+ }
+
+ if (retries)
+ dev_err(&client->dev,
+ "sensor i2c stall encountered. retries: %d\n",
+ retries);
+ return 0;
+ }
+
+ return r;
+}
+
+int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ struct i2c_msg msg;
+ unsigned char data[6];
+ unsigned int len = ccs_reg_width(reg);
+ int r;
+
+ if (len > sizeof(data) - 2)
+ return -EINVAL;
+
+ msg.addr = client->addr;
+ msg.flags = 0; /* Write */
+ msg.len = 2 + len;
+ msg.buf = data;
+
+ put_unaligned_be16(CCS_REG_ADDR(reg), data);
+ put_unaligned_be32(val << (8 * (sizeof(val) - len)), data + 2);
+
+ dev_dbg(&client->dev, "writing reg 0x%4.4x value 0x%*.*x (%u)\n",
+ CCS_REG_ADDR(reg), ccs_reg_width(reg) << 1,
+ ccs_reg_width(reg) << 1, val, val);
+
+ r = ccs_write_retry(client, &msg);
+ if (r)
+ dev_err(&client->dev,
+ "wrote 0x%x to offset 0x%x error %d\n", val,
+ CCS_REG_ADDR(reg), r);
+
+ return r;
+}
+
+/*
+ * Write to a 8/16-bit register.
+ * Returns zero if successful, or non-zero otherwise.
+ */
+int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val)
+{
+ int rval;
+
+ rval = ccs_call_quirk(sensor, reg_access, true, &reg, &val);
+ if (rval == -ENOIOCTLCMD)
+ return 0;
+ if (rval < 0)
+ return rval;
+
+ return ccs_write_addr_no_quirk(sensor, reg, val);
+}
+
+#define MAX_WRITE_LEN 32U
+
+int ccs_write_data_regs(struct ccs_sensor *sensor, struct ccs_reg *regs,
+ size_t num_regs)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&sensor->src->sd);
+ unsigned char buf[2 + MAX_WRITE_LEN];
+ struct i2c_msg msg = {
+ .addr = client->addr,
+ .buf = buf,
+ };
+ size_t i;
+
+ for (i = 0; i < num_regs; i++, regs++) {
+ unsigned char *regdata = regs->value;
+ unsigned int j;
+
+ for (j = 0; j < regs->len;
+ j += msg.len - 2, regdata += msg.len - 2) {
+ char printbuf[(MAX_WRITE_LEN << 1) +
+ 1 /* \0 */] = { 0 };
+ int rval;
+
+ msg.len = min(regs->len - j, MAX_WRITE_LEN);
+
+ bin2hex(printbuf, regdata, msg.len);
+ dev_dbg(&client->dev,
+ "writing msr reg 0x%4.4x value 0x%s\n",
+ regs->addr + j, printbuf);
+
+ put_unaligned_be16(regs->addr + j, buf);
+ memcpy(buf + 2, regdata, msg.len);
+
+ msg.len += 2;
+
+ rval = ccs_write_retry(client, &msg);
+ if (rval) {
+ dev_err(&client->dev,
+ "error writing %u octets to address 0x%4.4x\n",
+ msg.len, regs->addr + j);
+ return rval;
+ }
+ }
+ }
+
+ return 0;
+}
diff --git a/drivers/media/i2c/ccs/ccs-reg-access.h b/drivers/media/i2c/ccs/ccs-reg-access.h
new file mode 100644
index 000000000..78c43f92d
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-reg-access.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * include/media/ccs/ccs-reg-access.h
+ *
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
+ *
+ * Copyright (C) 2020 Intel Corporation
+ * Copyright (C) 2011--2012 Nokia Corporation
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
+ */
+
+#ifndef SMIAPP_REGS_H
+#define SMIAPP_REGS_H
+
+#include <linux/i2c.h>
+#include <linux/types.h>
+
+#include "ccs-regs.h"
+
+#define CCS_REG_ADDR(reg) ((u16)reg)
+
+struct ccs_sensor;
+
+int ccs_read_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 *val);
+int ccs_read_addr(struct ccs_sensor *sensor, u32 reg, u32 *val);
+int ccs_read_addr_8only(struct ccs_sensor *sensor, u32 reg, u32 *val);
+int ccs_read_addr_noconv(struct ccs_sensor *sensor, u32 reg, u32 *val);
+int ccs_write_addr_no_quirk(struct ccs_sensor *sensor, u32 reg, u32 val);
+int ccs_write_addr(struct ccs_sensor *sensor, u32 reg, u32 val);
+int ccs_write_data_regs(struct ccs_sensor *sensor, struct ccs_reg *regs,
+ size_t num_regs);
+
+unsigned int ccs_reg_width(u32 reg);
+u32 ccs_reg_conv(struct ccs_sensor *sensor, u32 reg, u32 val);
+
+#define ccs_read(sensor, reg_name, val) \
+ ccs_read_addr(sensor, CCS_R_##reg_name, val)
+
+#define ccs_write(sensor, reg_name, val) \
+ ccs_write_addr(sensor, CCS_R_##reg_name, val)
+
+#endif
diff --git a/drivers/media/i2c/ccs/ccs-regs.h b/drivers/media/i2c/ccs/ccs-regs.h
new file mode 100644
index 000000000..6ce84c5ec
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs-regs.h
@@ -0,0 +1,958 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause */
+/* Copyright (C) 2019--2020 Intel Corporation */
+/*
+ * Generated by Documentation/driver-api/media/drivers/ccs/mk-ccs-regs;
+ * do not modify.
+ */
+
+#ifndef __CCS_REGS_H__
+#define __CCS_REGS_H__
+
+#include <linux/bits.h>
+
+#define CCS_FL_BASE 16
+#define CCS_FL_16BIT BIT(CCS_FL_BASE)
+#define CCS_FL_32BIT BIT(CCS_FL_BASE + 1)
+#define CCS_FL_FLOAT_IREAL BIT(CCS_FL_BASE + 2)
+#define CCS_FL_IREAL BIT(CCS_FL_BASE + 3)
+#define CCS_R_ADDR(r) ((r) & 0xffff)
+
+#define CCS_R_MODULE_MODEL_ID (0x0000 | CCS_FL_16BIT)
+#define CCS_R_MODULE_REVISION_NUMBER_MAJOR 0x0002
+#define CCS_R_FRAME_COUNT 0x0005
+#define CCS_R_PIXEL_ORDER 0x0006
+#define CCS_PIXEL_ORDER_GRBG 0U
+#define CCS_PIXEL_ORDER_RGGB 1U
+#define CCS_PIXEL_ORDER_BGGR 2U
+#define CCS_PIXEL_ORDER_GBRG 3U
+#define CCS_R_MIPI_CCS_VERSION 0x0007
+#define CCS_MIPI_CCS_VERSION_V1_0 0x10
+#define CCS_MIPI_CCS_VERSION_V1_1 0x11
+#define CCS_MIPI_CCS_VERSION_MAJOR_SHIFT 4U
+#define CCS_MIPI_CCS_VERSION_MAJOR_MASK 0xf0
+#define CCS_MIPI_CCS_VERSION_MINOR_SHIFT 0U
+#define CCS_MIPI_CCS_VERSION_MINOR_MASK 0xf
+#define CCS_R_DATA_PEDESTAL (0x0008 | CCS_FL_16BIT)
+#define CCS_R_MODULE_MANUFACTURER_ID (0x000e | CCS_FL_16BIT)
+#define CCS_R_MODULE_REVISION_NUMBER_MINOR 0x0010
+#define CCS_R_MODULE_DATE_YEAR 0x0012
+#define CCS_R_MODULE_DATE_MONTH 0x0013
+#define CCS_R_MODULE_DATE_DAY 0x0014
+#define CCS_R_MODULE_DATE_PHASE 0x0015
+#define CCS_MODULE_DATE_PHASE_SHIFT 0U
+#define CCS_MODULE_DATE_PHASE_MASK 0x7
+#define CCS_MODULE_DATE_PHASE_TS 0U
+#define CCS_MODULE_DATE_PHASE_ES 1U
+#define CCS_MODULE_DATE_PHASE_CS 2U
+#define CCS_MODULE_DATE_PHASE_MP 3U
+#define CCS_R_SENSOR_MODEL_ID (0x0016 | CCS_FL_16BIT)
+#define CCS_R_SENSOR_REVISION_NUMBER 0x0018
+#define CCS_R_SENSOR_FIRMWARE_VERSION 0x001a
+#define CCS_R_SERIAL_NUMBER (0x001c | CCS_FL_32BIT)
+#define CCS_R_SENSOR_MANUFACTURER_ID (0x0020 | CCS_FL_16BIT)
+#define CCS_R_SENSOR_REVISION_NUMBER_16 (0x0022 | CCS_FL_16BIT)
+#define CCS_R_FRAME_FORMAT_MODEL_TYPE 0x0040
+#define CCS_FRAME_FORMAT_MODEL_TYPE_2_BYTE 1U
+#define CCS_FRAME_FORMAT_MODEL_TYPE_4_BYTE 2U
+#define CCS_R_FRAME_FORMAT_MODEL_SUBTYPE 0x0041
+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U
+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf
+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT 4U
+#define CCS_FRAME_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0
+#define CCS_R_FRAME_FORMAT_DESCRIPTOR(n) ((0x0042 | CCS_FL_16BIT) + (n) * 2)
+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MIN_N 0U
+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_MAX_N 14U
+#define CCS_R_FRAME_FORMAT_DESCRIPTOR_4(n) ((0x0060 | CCS_FL_32BIT) + (n) * 4)
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_SHIFT 0U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PIXELS_MASK 0xfff
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_SHIFT 12U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MASK 0xf000
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_EMBEDDED 1U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DUMMY_PIXEL 2U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_BLACK_PIXEL 3U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_DARK_PIXEL 4U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_VISIBLE_PIXEL 5U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_0 8U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_1 9U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_2 10U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_3 11U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_4 12U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_5 13U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_PCODE_MANUF_SPECIFIC_6 14U
+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MIN_N 0U
+#define CCS_LIM_FRAME_FORMAT_DESCRIPTOR_4_MAX_N 7U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_SHIFT 0U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PIXELS_MASK 0xffff
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_SHIFT 28U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MASK 0xf0000000
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_EMBEDDED 1U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_DUMMY_PIXEL 2U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_BLACK_PIXEL 3U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_DARK_PIXEL 4U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_VISIBLE_PIXEL 5U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_0 8U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_1 9U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_2 10U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_3 11U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_4 12U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_5 13U
+#define CCS_FRAME_FORMAT_DESCRIPTOR_4_PCODE_MANUF_SPECIFIC_6 14U
+#define CCS_R_ANALOG_GAIN_CAPABILITY (0x0080 | CCS_FL_16BIT)
+#define CCS_ANALOG_GAIN_CAPABILITY_GLOBAL 0U
+#define CCS_ANALOG_GAIN_CAPABILITY_ALTERNATE_GLOBAL 2U
+#define CCS_R_ANALOG_GAIN_CODE_MIN (0x0084 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_CODE_MAX (0x0086 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_CODE_STEP (0x0088 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_TYPE (0x008a | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_M0 (0x008c | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_C0 (0x008e | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_M1 (0x0090 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_C1 (0x0092 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_LINEAR_GAIN_MIN (0x0094 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_LINEAR_GAIN_MAX (0x0096 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_LINEAR_GAIN_STEP_SIZE (0x0098 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MIN (0x009a | CCS_FL_16BIT)
+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_MAX (0x009c | CCS_FL_16BIT)
+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_STEP_SIZE (0x009e | CCS_FL_16BIT)
+#define CCS_R_DATA_FORMAT_MODEL_TYPE 0x00c0
+#define CCS_DATA_FORMAT_MODEL_TYPE_NORMAL 1U
+#define CCS_DATA_FORMAT_MODEL_TYPE_EXTENDED 2U
+#define CCS_R_DATA_FORMAT_MODEL_SUBTYPE 0x00c1
+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_SHIFT 0U
+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_ROWS_MASK 0xf
+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_SHIFT 4U
+#define CCS_DATA_FORMAT_MODEL_SUBTYPE_COLUMNS_MASK 0xf0
+#define CCS_R_DATA_FORMAT_DESCRIPTOR(n) ((0x00c2 | CCS_FL_16BIT) + (n) * 2)
+#define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MIN_N 0U
+#define CCS_LIM_DATA_FORMAT_DESCRIPTOR_MAX_N 15U
+#define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_SHIFT 0U
+#define CCS_DATA_FORMAT_DESCRIPTOR_COMPRESSED_MASK 0xff
+#define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_SHIFT 8U
+#define CCS_DATA_FORMAT_DESCRIPTOR_UNCOMPRESSED_MASK 0xff00
+#define CCS_R_MODE_SELECT 0x0100
+#define CCS_MODE_SELECT_SOFTWARE_STANDBY 0U
+#define CCS_MODE_SELECT_STREAMING 1U
+#define CCS_R_IMAGE_ORIENTATION 0x0101
+#define CCS_IMAGE_ORIENTATION_HORIZONTAL_MIRROR BIT(0)
+#define CCS_IMAGE_ORIENTATION_VERTICAL_FLIP BIT(1)
+#define CCS_R_SOFTWARE_RESET 0x0103
+#define CCS_SOFTWARE_RESET_OFF 0U
+#define CCS_SOFTWARE_RESET_ON 1U
+#define CCS_R_GROUPED_PARAMETER_HOLD 0x0104
+#define CCS_R_MASK_CORRUPTED_FRAMES 0x0105
+#define CCS_MASK_CORRUPTED_FRAMES_ALLOW 0U
+#define CCS_MASK_CORRUPTED_FRAMES_MASK 1U
+#define CCS_R_FAST_STANDBY_CTRL 0x0106
+#define CCS_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0U
+#define CCS_FAST_STANDBY_CTRL_FRAME_TRUNCATION 1U
+#define CCS_R_CCI_ADDRESS_CTRL 0x0107
+#define CCS_R_2ND_CCI_IF_CTRL 0x0108
+#define CCS_2ND_CCI_IF_CTRL_ENABLE BIT(0)
+#define CCS_2ND_CCI_IF_CTRL_ACK BIT(1)
+#define CCS_R_2ND_CCI_ADDRESS_CTRL 0x0109
+#define CCS_R_CSI_CHANNEL_IDENTIFIER 0x0110
+#define CCS_R_CSI_SIGNALING_MODE 0x0111
+#define CCS_CSI_SIGNALING_MODE_CSI_2_DPHY 2U
+#define CCS_CSI_SIGNALING_MODE_CSI_2_CPHY 3U
+#define CCS_R_CSI_DATA_FORMAT (0x0112 | CCS_FL_16BIT)
+#define CCS_R_CSI_LANE_MODE 0x0114
+#define CCS_R_DPCM_FRAME_DT 0x011d
+#define CCS_R_BOTTOM_EMBEDDED_DATA_DT 0x011e
+#define CCS_R_BOTTOM_EMBEDDED_DATA_VC 0x011f
+#define CCS_R_GAIN_MODE 0x0120
+#define CCS_GAIN_MODE_GLOBAL 0U
+#define CCS_GAIN_MODE_ALTERNATE 1U
+#define CCS_R_ADC_BIT_DEPTH 0x0121
+#define CCS_R_EMB_DATA_CTRL 0x0122
+#define CCS_EMB_DATA_CTRL_RAW8_PACKING_FOR_RAW16 BIT(0)
+#define CCS_EMB_DATA_CTRL_RAW10_PACKING_FOR_RAW20 BIT(1)
+#define CCS_EMB_DATA_CTRL_RAW12_PACKING_FOR_RAW24 BIT(2)
+#define CCS_R_GPIO_TRIG_MODE 0x0130
+#define CCS_R_EXTCLK_FREQUENCY_MHZ (0x0136 | (CCS_FL_16BIT | CCS_FL_IREAL))
+#define CCS_R_TEMP_SENSOR_CTRL 0x0138
+#define CCS_TEMP_SENSOR_CTRL_ENABLE BIT(0)
+#define CCS_R_TEMP_SENSOR_MODE 0x0139
+#define CCS_R_TEMP_SENSOR_OUTPUT 0x013a
+#define CCS_R_FINE_INTEGRATION_TIME (0x0200 | CCS_FL_16BIT)
+#define CCS_R_COARSE_INTEGRATION_TIME (0x0202 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_GAIN_CODE_GLOBAL (0x0204 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_LINEAR_GAIN_GLOBAL (0x0206 | CCS_FL_16BIT)
+#define CCS_R_ANALOG_EXPONENTIAL_GAIN_GLOBAL (0x0208 | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_GAIN_GLOBAL (0x020e | CCS_FL_16BIT)
+#define CCS_R_SHORT_ANALOG_GAIN_GLOBAL (0x0216 | CCS_FL_16BIT)
+#define CCS_R_SHORT_DIGITAL_GAIN_GLOBAL (0x0218 | CCS_FL_16BIT)
+#define CCS_R_HDR_MODE 0x0220
+#define CCS_HDR_MODE_ENABLED BIT(0)
+#define CCS_HDR_MODE_SEPARATE_ANALOG_GAIN BIT(1)
+#define CCS_HDR_MODE_UPSCALING BIT(2)
+#define CCS_HDR_MODE_RESET_SYNC BIT(3)
+#define CCS_HDR_MODE_TIMING_MODE BIT(4)
+#define CCS_HDR_MODE_EXPOSURE_CTRL_DIRECT BIT(5)
+#define CCS_HDR_MODE_SEPARATE_DIGITAL_GAIN BIT(6)
+#define CCS_R_HDR_RESOLUTION_REDUCTION 0x0221
+#define CCS_HDR_RESOLUTION_REDUCTION_ROW_SHIFT 0U
+#define CCS_HDR_RESOLUTION_REDUCTION_ROW_MASK 0xf
+#define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_SHIFT 4U
+#define CCS_HDR_RESOLUTION_REDUCTION_COLUMN_MASK 0xf0
+#define CCS_R_EXPOSURE_RATIO 0x0222
+#define CCS_R_HDR_INTERNAL_BIT_DEPTH 0x0223
+#define CCS_R_DIRECT_SHORT_INTEGRATION_TIME (0x0224 | CCS_FL_16BIT)
+#define CCS_R_SHORT_ANALOG_LINEAR_GAIN_GLOBAL (0x0226 | CCS_FL_16BIT)
+#define CCS_R_SHORT_ANALOG_EXPONENTIAL_GAIN_GLOBAL (0x0228 | CCS_FL_16BIT)
+#define CCS_R_VT_PIX_CLK_DIV (0x0300 | CCS_FL_16BIT)
+#define CCS_R_VT_SYS_CLK_DIV (0x0302 | CCS_FL_16BIT)
+#define CCS_R_PRE_PLL_CLK_DIV (0x0304 | CCS_FL_16BIT)
+#define CCS_R_PLL_MULTIPLIER (0x0306 | CCS_FL_16BIT)
+#define CCS_R_OP_PIX_CLK_DIV (0x0308 | CCS_FL_16BIT)
+#define CCS_R_OP_SYS_CLK_DIV (0x030a | CCS_FL_16BIT)
+#define CCS_R_OP_PRE_PLL_CLK_DIV (0x030c | CCS_FL_16BIT)
+#define CCS_R_OP_PLL_MULTIPLIER (0x030e | CCS_FL_16BIT)
+#define CCS_R_PLL_MODE 0x0310
+#define CCS_PLL_MODE_SHIFT 0U
+#define CCS_PLL_MODE_MASK 0x1
+#define CCS_PLL_MODE_SINGLE 0U
+#define CCS_PLL_MODE_DUAL 1U
+#define CCS_R_OP_PIX_CLK_DIV_REV (0x0312 | CCS_FL_16BIT)
+#define CCS_R_OP_SYS_CLK_DIV_REV (0x0314 | CCS_FL_16BIT)
+#define CCS_R_FRAME_LENGTH_LINES (0x0340 | CCS_FL_16BIT)
+#define CCS_R_LINE_LENGTH_PCK (0x0342 | CCS_FL_16BIT)
+#define CCS_R_X_ADDR_START (0x0344 | CCS_FL_16BIT)
+#define CCS_R_Y_ADDR_START (0x0346 | CCS_FL_16BIT)
+#define CCS_R_X_ADDR_END (0x0348 | CCS_FL_16BIT)
+#define CCS_R_Y_ADDR_END (0x034a | CCS_FL_16BIT)
+#define CCS_R_X_OUTPUT_SIZE (0x034c | CCS_FL_16BIT)
+#define CCS_R_Y_OUTPUT_SIZE (0x034e | CCS_FL_16BIT)
+#define CCS_R_FRAME_LENGTH_CTRL 0x0350
+#define CCS_FRAME_LENGTH_CTRL_AUTOMATIC BIT(0)
+#define CCS_R_TIMING_MODE_CTRL 0x0352
+#define CCS_TIMING_MODE_CTRL_MANUAL_READOUT BIT(0)
+#define CCS_TIMING_MODE_CTRL_DELAYED_EXPOSURE BIT(1)
+#define CCS_R_START_READOUT_RS 0x0353
+#define CCS_START_READOUT_RS_MANUAL_READOUT_START BIT(0)
+#define CCS_R_FRAME_MARGIN (0x0354 | CCS_FL_16BIT)
+#define CCS_R_X_EVEN_INC (0x0380 | CCS_FL_16BIT)
+#define CCS_R_X_ODD_INC (0x0382 | CCS_FL_16BIT)
+#define CCS_R_Y_EVEN_INC (0x0384 | CCS_FL_16BIT)
+#define CCS_R_Y_ODD_INC (0x0386 | CCS_FL_16BIT)
+#define CCS_R_MONOCHROME_EN 0x0390
+#define CCS_MONOCHROME_EN_ENABLED 0U
+#define CCS_R_SCALING_MODE (0x0400 | CCS_FL_16BIT)
+#define CCS_SCALING_MODE_NO_SCALING 0U
+#define CCS_SCALING_MODE_HORIZONTAL 1U
+#define CCS_R_SCALE_M (0x0404 | CCS_FL_16BIT)
+#define CCS_R_SCALE_N (0x0406 | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_CROP_X_OFFSET (0x0408 | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_CROP_Y_OFFSET (0x040a | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_CROP_IMAGE_WIDTH (0x040c | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_CROP_IMAGE_HEIGHT (0x040e | CCS_FL_16BIT)
+#define CCS_R_COMPRESSION_MODE (0x0500 | CCS_FL_16BIT)
+#define CCS_COMPRESSION_MODE_NONE 0U
+#define CCS_COMPRESSION_MODE_DPCM_PCM_SIMPLE 1U
+#define CCS_R_TEST_PATTERN_MODE (0x0600 | CCS_FL_16BIT)
+#define CCS_TEST_PATTERN_MODE_NONE 0U
+#define CCS_TEST_PATTERN_MODE_SOLID_COLOR 1U
+#define CCS_TEST_PATTERN_MODE_COLOR_BARS 2U
+#define CCS_TEST_PATTERN_MODE_FADE_TO_GREY 3U
+#define CCS_TEST_PATTERN_MODE_PN9 4U
+#define CCS_TEST_PATTERN_MODE_COLOR_TILE 5U
+#define CCS_R_TEST_DATA_RED (0x0602 | CCS_FL_16BIT)
+#define CCS_R_TEST_DATA_GREENR (0x0604 | CCS_FL_16BIT)
+#define CCS_R_TEST_DATA_BLUE (0x0606 | CCS_FL_16BIT)
+#define CCS_R_TEST_DATA_GREENB (0x0608 | CCS_FL_16BIT)
+#define CCS_R_VALUE_STEP_SIZE_SMOOTH 0x060a
+#define CCS_R_VALUE_STEP_SIZE_QUANTISED 0x060b
+#define CCS_R_TCLK_POST 0x0800
+#define CCS_R_THS_PREPARE 0x0801
+#define CCS_R_THS_ZERO_MIN 0x0802
+#define CCS_R_THS_TRAIL 0x0803
+#define CCS_R_TCLK_TRAIL_MIN 0x0804
+#define CCS_R_TCLK_PREPARE 0x0805
+#define CCS_R_TCLK_ZERO 0x0806
+#define CCS_R_TLPX 0x0807
+#define CCS_R_PHY_CTRL 0x0808
+#define CCS_PHY_CTRL_AUTO 0U
+#define CCS_PHY_CTRL_UI 1U
+#define CCS_PHY_CTRL_MANUAL 2U
+#define CCS_R_TCLK_POST_EX (0x080a | CCS_FL_16BIT)
+#define CCS_R_THS_PREPARE_EX (0x080c | CCS_FL_16BIT)
+#define CCS_R_THS_ZERO_MIN_EX (0x080e | CCS_FL_16BIT)
+#define CCS_R_THS_TRAIL_EX (0x0810 | CCS_FL_16BIT)
+#define CCS_R_TCLK_TRAIL_MIN_EX (0x0812 | CCS_FL_16BIT)
+#define CCS_R_TCLK_PREPARE_EX (0x0814 | CCS_FL_16BIT)
+#define CCS_R_TCLK_ZERO_EX (0x0816 | CCS_FL_16BIT)
+#define CCS_R_TLPX_EX (0x0818 | CCS_FL_16BIT)
+#define CCS_R_REQUESTED_LINK_RATE (0x0820 | CCS_FL_32BIT)
+#define CCS_R_DPHY_EQUALIZATION_MODE 0x0824
+#define CCS_DPHY_EQUALIZATION_MODE_EQ2 BIT(0)
+#define CCS_R_PHY_EQUALIZATION_CTRL 0x0825
+#define CCS_PHY_EQUALIZATION_CTRL_ENABLE BIT(0)
+#define CCS_R_DPHY_PREAMBLE_CTRL 0x0826
+#define CCS_DPHY_PREAMBLE_CTRL_ENABLE BIT(0)
+#define CCS_R_DPHY_PREAMBLE_LENGTH 0x0826
+#define CCS_R_PHY_SSC_CTRL 0x0828
+#define CCS_PHY_SSC_CTRL_ENABLE BIT(0)
+#define CCS_R_MANUAL_LP_CTRL 0x0829
+#define CCS_MANUAL_LP_CTRL_ENABLE BIT(0)
+#define CCS_R_TWAKEUP 0x082a
+#define CCS_R_TINIT 0x082b
+#define CCS_R_THS_EXIT 0x082c
+#define CCS_R_THS_EXIT_EX (0x082e | CCS_FL_16BIT)
+#define CCS_R_PHY_PERIODIC_CALIBRATION_CTRL 0x0830
+#define CCS_PHY_PERIODIC_CALIBRATION_CTRL_FRAME_BLANKING BIT(0)
+#define CCS_R_PHY_PERIODIC_CALIBRATION_INTERVAL 0x0831
+#define CCS_R_PHY_INIT_CALIBRATION_CTRL 0x0832
+#define CCS_PHY_INIT_CALIBRATION_CTRL_STREAM_START BIT(0)
+#define CCS_R_DPHY_CALIBRATION_MODE 0x0833
+#define CCS_DPHY_CALIBRATION_MODE_ALSO_ALTERNATE BIT(0)
+#define CCS_R_CPHY_CALIBRATION_MODE 0x0834
+#define CCS_CPHY_CALIBRATION_MODE_FORMAT_1 0U
+#define CCS_CPHY_CALIBRATION_MODE_FORMAT_2 1U
+#define CCS_CPHY_CALIBRATION_MODE_FORMAT_3 2U
+#define CCS_R_T3_CALPREAMBLE_LENGTH 0x0835
+#define CCS_R_T3_CALPREAMBLE_LENGTH_PER 0x0836
+#define CCS_R_T3_CALALTSEQ_LENGTH 0x0837
+#define CCS_R_T3_CALALTSEQ_LENGTH_PER 0x0838
+#define CCS_R_FM2_INIT_SEED (0x083a | CCS_FL_16BIT)
+#define CCS_R_T3_CALUDEFSEQ_LENGTH (0x083c | CCS_FL_16BIT)
+#define CCS_R_T3_CALUDEFSEQ_LENGTH_PER (0x083e | CCS_FL_16BIT)
+#define CCS_R_TGR_PREAMBLE_LENGTH 0x0841
+#define CCS_TGR_PREAMBLE_LENGTH_PREAMABLE_PROG_SEQ BIT(7)
+#define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_SHIFT 0U
+#define CCS_TGR_PREAMBLE_LENGTH_BEGIN_PREAMBLE_LENGTH_MASK 0x3f
+#define CCS_R_TGR_POST_LENGTH 0x0842
+#define CCS_TGR_POST_LENGTH_POST_LENGTH_SHIFT 0U
+#define CCS_TGR_POST_LENGTH_POST_LENGTH_MASK 0x1f
+#define CCS_R_TGR_PREAMBLE_PROG_SEQUENCE(n2) (0x0843 + (n2))
+#define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MIN_N2 0U
+#define CCS_LIM_TGR_PREAMBLE_PROG_SEQUENCE_MAX_N2 6U
+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_SHIFT 3U
+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_1_MASK 0x38
+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_SHIFT 0U
+#define CCS_TGR_PREAMBLE_PROG_SEQUENCE_SYMBOL_N_MASK 0x7
+#define CCS_R_T3_PREPARE (0x084e | CCS_FL_16BIT)
+#define CCS_R_T3_LPX (0x0850 | CCS_FL_16BIT)
+#define CCS_R_ALPS_CTRL 0x085a
+#define CCS_ALPS_CTRL_LVLP_DPHY BIT(0)
+#define CCS_ALPS_CTRL_LVLP_CPHY BIT(1)
+#define CCS_ALPS_CTRL_ALP_CPHY BIT(2)
+#define CCS_R_TX_REG_CSI_EPD_EN_SSP_CPHY (0x0860 | CCS_FL_16BIT)
+#define CCS_R_TX_REG_CSI_EPD_OP_SLP_CPHY (0x0862 | CCS_FL_16BIT)
+#define CCS_R_TX_REG_CSI_EPD_EN_SSP_DPHY (0x0864 | CCS_FL_16BIT)
+#define CCS_R_TX_REG_CSI_EPD_OP_SLP_DPHY (0x0866 | CCS_FL_16BIT)
+#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_CPHY 0x0868
+#define CCS_R_TX_REG_CSI_EPD_MISC_OPTION_DPHY 0x0869
+#define CCS_R_SCRAMBLING_CTRL 0x0870
+#define CCS_SCRAMBLING_CTRL_ENABLED BIT(0)
+#define CCS_SCRAMBLING_CTRL_SHIFT 2U
+#define CCS_SCRAMBLING_CTRL_MASK 0xc
+#define CCS_SCRAMBLING_CTRL_1_SEED_CPHY 0U
+#define CCS_SCRAMBLING_CTRL_4_SEED_CPHY 3U
+#define CCS_R_LANE_SEED_VALUE(seed, lane) ((0x0872 | CCS_FL_16BIT) + (seed) * 16 + (lane) * 2)
+#define CCS_LIM_LANE_SEED_VALUE_MIN_SEED 0U
+#define CCS_LIM_LANE_SEED_VALUE_MAX_SEED 3U
+#define CCS_LIM_LANE_SEED_VALUE_MIN_LANE 0U
+#define CCS_LIM_LANE_SEED_VALUE_MAX_LANE 7U
+#define CCS_R_TX_USL_REV_ENTRY (0x08c0 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_REV_CLOCK_COUNTER (0x08c2 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_REV_LP_COUNTER (0x08c4 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_REV_FRAME_COUNTER (0x08c6 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_REV_CHRONOLOGICAL_TIMER (0x08c8 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_FWD_ENTRY (0x08ca | CCS_FL_16BIT)
+#define CCS_R_TX_USL_GPIO (0x08cc | CCS_FL_16BIT)
+#define CCS_R_TX_USL_OPERATION (0x08ce | CCS_FL_16BIT)
+#define CCS_TX_USL_OPERATION_RESET BIT(0)
+#define CCS_R_TX_USL_ALP_CTRL (0x08d0 | CCS_FL_16BIT)
+#define CCS_TX_USL_ALP_CTRL_CLOCK_PAUSE BIT(0)
+#define CCS_R_TX_USL_APP_BTA_ACK_TIMEOUT (0x08d2 | CCS_FL_16BIT)
+#define CCS_R_TX_USL_SNS_BTA_ACK_TIMEOUT (0x08d2 | CCS_FL_16BIT)
+#define CCS_R_USL_CLOCK_MODE_D_CTRL 0x08d2
+#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_STANDBY BIT(0)
+#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_VBLANK BIT(1)
+#define CCS_USL_CLOCK_MODE_D_CTRL_CONT_CLOCK_HBLANK BIT(2)
+#define CCS_R_BINNING_MODE 0x0900
+#define CCS_R_BINNING_TYPE 0x0901
+#define CCS_R_BINNING_WEIGHTING 0x0902
+#define CCS_R_DATA_TRANSFER_IF_1_CTRL 0x0a00
+#define CCS_DATA_TRANSFER_IF_1_CTRL_ENABLE BIT(0)
+#define CCS_DATA_TRANSFER_IF_1_CTRL_WRITE BIT(1)
+#define CCS_DATA_TRANSFER_IF_1_CTRL_CLEAR_ERROR BIT(2)
+#define CCS_R_DATA_TRANSFER_IF_1_STATUS 0x0a01
+#define CCS_DATA_TRANSFER_IF_1_STATUS_READ_IF_READY BIT(0)
+#define CCS_DATA_TRANSFER_IF_1_STATUS_WRITE_IF_READY BIT(1)
+#define CCS_DATA_TRANSFER_IF_1_STATUS_DATA_CORRUPTED BIT(2)
+#define CCS_DATA_TRANSFER_IF_1_STATUS_IMPROPER_IF_USAGE BIT(3)
+#define CCS_R_DATA_TRANSFER_IF_1_PAGE_SELECT 0x0a02
+#define CCS_R_DATA_TRANSFER_IF_1_DATA(p) (0x0a04 + (p))
+#define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MIN_P 0U
+#define CCS_LIM_DATA_TRANSFER_IF_1_DATA_MAX_P 63U
+#define CCS_R_SHADING_CORRECTION_EN 0x0b00
+#define CCS_SHADING_CORRECTION_EN_ENABLE BIT(0)
+#define CCS_R_LUMINANCE_CORRECTION_LEVEL 0x0b01
+#define CCS_R_GREEN_IMBALANCE_FILTER_EN 0x0b02
+#define CCS_GREEN_IMBALANCE_FILTER_EN_ENABLE BIT(0)
+#define CCS_R_MAPPED_DEFECT_CORRECT_EN 0x0b05
+#define CCS_MAPPED_DEFECT_CORRECT_EN_ENABLE BIT(0)
+#define CCS_R_SINGLE_DEFECT_CORRECT_EN 0x0b06
+#define CCS_SINGLE_DEFECT_CORRECT_EN_ENABLE BIT(0)
+#define CCS_R_DYNAMIC_COUPLET_CORRECT_EN 0x0b08
+#define CCS_DYNAMIC_COUPLET_CORRECT_EN_ENABLE BIT(0)
+#define CCS_R_COMBINED_DEFECT_CORRECT_EN 0x0b0a
+#define CCS_COMBINED_DEFECT_CORRECT_EN_ENABLE BIT(0)
+#define CCS_R_MODULE_SPECIFIC_CORRECTION_EN 0x0b0c
+#define CCS_MODULE_SPECIFIC_CORRECTION_EN_ENABLE BIT(0)
+#define CCS_R_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN 0x0b13
+#define CCS_DYNAMIC_TRIPLET_DEFECT_CORRECT_EN_ENABLE BIT(0)
+#define CCS_R_NF_CTRL 0x0b15
+#define CCS_NF_CTRL_LUMA BIT(0)
+#define CCS_NF_CTRL_CHROMA BIT(1)
+#define CCS_NF_CTRL_COMBINED BIT(2)
+#define CCS_R_OB_READOUT_CONTROL 0x0b30
+#define CCS_OB_READOUT_CONTROL_ENABLE BIT(0)
+#define CCS_OB_READOUT_CONTROL_INTERLEAVING BIT(1)
+#define CCS_R_OB_VIRTUAL_CHANNEL 0x0b31
+#define CCS_R_OB_DT 0x0b32
+#define CCS_R_OB_DATA_FORMAT 0x0b33
+#define CCS_R_COLOR_TEMPERATURE (0x0b8c | CCS_FL_16BIT)
+#define CCS_R_ABSOLUTE_GAIN_GREENR (0x0b8e | CCS_FL_16BIT)
+#define CCS_R_ABSOLUTE_GAIN_RED (0x0b90 | CCS_FL_16BIT)
+#define CCS_R_ABSOLUTE_GAIN_BLUE (0x0b92 | CCS_FL_16BIT)
+#define CCS_R_ABSOLUTE_GAIN_GREENB (0x0b94 | CCS_FL_16BIT)
+#define CCS_R_CFA_CONVERSION_CTRL 0x0ba0
+#define CCS_CFA_CONVERSION_CTRL_BAYER_CONVERSION_ENABLE BIT(0)
+#define CCS_R_FLASH_STROBE_ADJUSTMENT 0x0c12
+#define CCS_R_FLASH_STROBE_START_POINT (0x0c14 | CCS_FL_16BIT)
+#define CCS_R_TFLASH_STROBE_DELAY_RS_CTRL (0x0c16 | CCS_FL_16BIT)
+#define CCS_R_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL (0x0c18 | CCS_FL_16BIT)
+#define CCS_R_FLASH_MODE_RS 0x0c1a
+#define CCS_FLASH_MODE_RS_CONTINUOUS BIT(0)
+#define CCS_FLASH_MODE_RS_TRUNCATE BIT(1)
+#define CCS_FLASH_MODE_RS_ASYNC BIT(3)
+#define CCS_R_FLASH_TRIGGER_RS 0x0c1b
+#define CCS_R_FLASH_STATUS 0x0c1c
+#define CCS_FLASH_STATUS_RETIMED BIT(0)
+#define CCS_R_SA_STROBE_MODE 0x0c1d
+#define CCS_SA_STROBE_MODE_CONTINUOUS BIT(0)
+#define CCS_SA_STROBE_MODE_TRUNCATE BIT(1)
+#define CCS_SA_STROBE_MODE_ASYNC BIT(3)
+#define CCS_SA_STROBE_MODE_ADJUST_EDGE BIT(4)
+#define CCS_R_SA_STROBE_START_POINT (0x0c1e | CCS_FL_16BIT)
+#define CCS_R_TSA_STROBE_DELAY_CTRL (0x0c20 | CCS_FL_16BIT)
+#define CCS_R_TSA_STROBE_WIDTH_CTRL (0x0c22 | CCS_FL_16BIT)
+#define CCS_R_SA_STROBE_TRIGGER 0x0c24
+#define CCS_R_SA_STROBE_STATUS 0x0c25
+#define CCS_SA_STROBE_STATUS_RETIMED BIT(0)
+#define CCS_R_TSA_STROBE_RE_DELAY_CTRL (0x0c30 | CCS_FL_16BIT)
+#define CCS_R_TSA_STROBE_FE_DELAY_CTRL (0x0c32 | CCS_FL_16BIT)
+#define CCS_R_PDAF_CTRL (0x0d00 | CCS_FL_16BIT)
+#define CCS_PDAF_CTRL_ENABLE BIT(0)
+#define CCS_PDAF_CTRL_PROCESSED BIT(1)
+#define CCS_PDAF_CTRL_INTERLEAVED BIT(2)
+#define CCS_PDAF_CTRL_VISIBLE_PDAF_CORRECTION BIT(3)
+#define CCS_R_PDAF_VC 0x0d02
+#define CCS_R_PDAF_DT 0x0d03
+#define CCS_R_PD_X_ADDR_START (0x0d04 | CCS_FL_16BIT)
+#define CCS_R_PD_Y_ADDR_START (0x0d06 | CCS_FL_16BIT)
+#define CCS_R_PD_X_ADDR_END (0x0d08 | CCS_FL_16BIT)
+#define CCS_R_PD_Y_ADDR_END (0x0d0a | CCS_FL_16BIT)
+#define CCS_R_BRACKETING_LUT_CTRL 0x0e00
+#define CCS_R_BRACKETING_LUT_MODE 0x0e01
+#define CCS_BRACKETING_LUT_MODE_CONTINUE_STREAMING BIT(0)
+#define CCS_BRACKETING_LUT_MODE_LOOP_MODE BIT(1)
+#define CCS_R_BRACKETING_LUT_ENTRY_CTRL 0x0e02
+#define CCS_R_BRACKETING_LUT_FRAME(n) (0x0e10 + (n))
+#define CCS_LIM_BRACKETING_LUT_FRAME_MIN_N 0U
+#define CCS_LIM_BRACKETING_LUT_FRAME_MAX_N 239U
+#define CCS_R_INTEGRATION_TIME_CAPABILITY (0x1000 | CCS_FL_16BIT)
+#define CCS_INTEGRATION_TIME_CAPABILITY_FINE BIT(0)
+#define CCS_R_COARSE_INTEGRATION_TIME_MIN (0x1004 | CCS_FL_16BIT)
+#define CCS_R_COARSE_INTEGRATION_TIME_MAX_MARGIN (0x1006 | CCS_FL_16BIT)
+#define CCS_R_FINE_INTEGRATION_TIME_MIN (0x1008 | CCS_FL_16BIT)
+#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN (0x100a | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_GAIN_CAPABILITY 0x1081
+#define CCS_DIGITAL_GAIN_CAPABILITY_NONE 0U
+#define CCS_DIGITAL_GAIN_CAPABILITY_GLOBAL 2U
+#define CCS_R_DIGITAL_GAIN_MIN (0x1084 | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_GAIN_MAX (0x1086 | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_GAIN_STEP_SIZE (0x1088 | CCS_FL_16BIT)
+#define CCS_R_PEDESTAL_CAPABILITY 0x10e0
+#define CCS_R_ADC_CAPABILITY 0x10f0
+#define CCS_ADC_CAPABILITY_BIT_DEPTH_CTRL BIT(0)
+#define CCS_R_ADC_BIT_DEPTH_CAPABILITY (0x10f4 | CCS_FL_32BIT)
+#define CCS_R_MIN_EXT_CLK_FREQ_MHZ (0x1100 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_EXT_CLK_FREQ_MHZ (0x1104 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_PRE_PLL_CLK_DIV (0x1108 | CCS_FL_16BIT)
+#define CCS_R_MAX_PRE_PLL_CLK_DIV (0x110a | CCS_FL_16BIT)
+#define CCS_R_MIN_PLL_IP_CLK_FREQ_MHZ (0x110c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_PLL_IP_CLK_FREQ_MHZ (0x1110 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_PLL_MULTIPLIER (0x1114 | CCS_FL_16BIT)
+#define CCS_R_MAX_PLL_MULTIPLIER (0x1116 | CCS_FL_16BIT)
+#define CCS_R_MIN_PLL_OP_CLK_FREQ_MHZ (0x1118 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_PLL_OP_CLK_FREQ_MHZ (0x111c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_VT_SYS_CLK_DIV (0x1120 | CCS_FL_16BIT)
+#define CCS_R_MAX_VT_SYS_CLK_DIV (0x1122 | CCS_FL_16BIT)
+#define CCS_R_MIN_VT_SYS_CLK_FREQ_MHZ (0x1124 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_VT_SYS_CLK_FREQ_MHZ (0x1128 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_VT_PIX_CLK_FREQ_MHZ (0x112c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_VT_PIX_CLK_FREQ_MHZ (0x1130 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_VT_PIX_CLK_DIV (0x1134 | CCS_FL_16BIT)
+#define CCS_R_MAX_VT_PIX_CLK_DIV (0x1136 | CCS_FL_16BIT)
+#define CCS_R_CLOCK_CALCULATION 0x1138
+#define CCS_CLOCK_CALCULATION_LANE_SPEED BIT(0)
+#define CCS_CLOCK_CALCULATION_LINK_DECOUPLED BIT(1)
+#define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_SYS_DDR BIT(2)
+#define CCS_CLOCK_CALCULATION_DUAL_PLL_OP_PIX_DDR BIT(3)
+#define CCS_R_NUM_OF_VT_LANES 0x1139
+#define CCS_R_NUM_OF_OP_LANES 0x113a
+#define CCS_R_OP_BITS_PER_LANE 0x113b
+#define CCS_R_MIN_FRAME_LENGTH_LINES (0x1140 | CCS_FL_16BIT)
+#define CCS_R_MAX_FRAME_LENGTH_LINES (0x1142 | CCS_FL_16BIT)
+#define CCS_R_MIN_LINE_LENGTH_PCK (0x1144 | CCS_FL_16BIT)
+#define CCS_R_MAX_LINE_LENGTH_PCK (0x1146 | CCS_FL_16BIT)
+#define CCS_R_MIN_LINE_BLANKING_PCK (0x1148 | CCS_FL_16BIT)
+#define CCS_R_MIN_FRAME_BLANKING_LINES (0x114a | CCS_FL_16BIT)
+#define CCS_R_MIN_LINE_LENGTH_PCK_STEP_SIZE 0x114c
+#define CCS_R_TIMING_MODE_CAPABILITY 0x114d
+#define CCS_TIMING_MODE_CAPABILITY_AUTO_FRAME_LENGTH BIT(0)
+#define CCS_TIMING_MODE_CAPABILITY_ROLLING_SHUTTER_MANUAL_READOUT BIT(2)
+#define CCS_TIMING_MODE_CAPABILITY_DELAYED_EXPOSURE_START BIT(3)
+#define CCS_TIMING_MODE_CAPABILITY_MANUAL_EXPOSURE_EMBEDDED_DATA BIT(4)
+#define CCS_R_FRAME_MARGIN_MAX_VALUE (0x114e | CCS_FL_16BIT)
+#define CCS_R_FRAME_MARGIN_MIN_VALUE 0x1150
+#define CCS_R_GAIN_DELAY_TYPE 0x1151
+#define CCS_GAIN_DELAY_TYPE_FIXED 0U
+#define CCS_GAIN_DELAY_TYPE_VARIABLE 1U
+#define CCS_R_MIN_OP_SYS_CLK_DIV (0x1160 | CCS_FL_16BIT)
+#define CCS_R_MAX_OP_SYS_CLK_DIV (0x1162 | CCS_FL_16BIT)
+#define CCS_R_MIN_OP_SYS_CLK_FREQ_MHZ (0x1164 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_SYS_CLK_FREQ_MHZ (0x1168 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_OP_PIX_CLK_DIV (0x116c | CCS_FL_16BIT)
+#define CCS_R_MAX_OP_PIX_CLK_DIV (0x116e | CCS_FL_16BIT)
+#define CCS_R_MIN_OP_PIX_CLK_FREQ_MHZ (0x1170 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_PIX_CLK_FREQ_MHZ (0x1174 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_X_ADDR_MIN (0x1180 | CCS_FL_16BIT)
+#define CCS_R_Y_ADDR_MIN (0x1182 | CCS_FL_16BIT)
+#define CCS_R_X_ADDR_MAX (0x1184 | CCS_FL_16BIT)
+#define CCS_R_Y_ADDR_MAX (0x1186 | CCS_FL_16BIT)
+#define CCS_R_MIN_X_OUTPUT_SIZE (0x1188 | CCS_FL_16BIT)
+#define CCS_R_MIN_Y_OUTPUT_SIZE (0x118a | CCS_FL_16BIT)
+#define CCS_R_MAX_X_OUTPUT_SIZE (0x118c | CCS_FL_16BIT)
+#define CCS_R_MAX_Y_OUTPUT_SIZE (0x118e | CCS_FL_16BIT)
+#define CCS_R_X_ADDR_START_DIV_CONSTANT 0x1190
+#define CCS_R_Y_ADDR_START_DIV_CONSTANT 0x1191
+#define CCS_R_X_ADDR_END_DIV_CONSTANT 0x1192
+#define CCS_R_Y_ADDR_END_DIV_CONSTANT 0x1193
+#define CCS_R_X_SIZE_DIV 0x1194
+#define CCS_R_Y_SIZE_DIV 0x1195
+#define CCS_R_X_OUTPUT_DIV 0x1196
+#define CCS_R_Y_OUTPUT_DIV 0x1197
+#define CCS_R_NON_FLEXIBLE_RESOLUTION_SUPPORT 0x1198
+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_PIX_ADDR BIT(0)
+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_NEW_OUTPUT_RES BIT(1)
+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_CROP_NO_PAD BIT(2)
+#define CCS_NON_FLEXIBLE_RESOLUTION_SUPPORT_OUTPUT_SIZE_LANE_DEP BIT(3)
+#define CCS_R_MIN_OP_PRE_PLL_CLK_DIV (0x11a0 | CCS_FL_16BIT)
+#define CCS_R_MAX_OP_PRE_PLL_CLK_DIV (0x11a2 | CCS_FL_16BIT)
+#define CCS_R_MIN_OP_PLL_IP_CLK_FREQ_MHZ (0x11a4 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_PLL_IP_CLK_FREQ_MHZ (0x11a8 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_OP_PLL_MULTIPLIER (0x11ac | CCS_FL_16BIT)
+#define CCS_R_MAX_OP_PLL_MULTIPLIER (0x11ae | CCS_FL_16BIT)
+#define CCS_R_MIN_OP_PLL_OP_CLK_FREQ_MHZ (0x11b0 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_PLL_OP_CLK_FREQ_MHZ (0x11b4 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_CLOCK_TREE_PLL_CAPABILITY 0x11b8
+#define CCS_CLOCK_TREE_PLL_CAPABILITY_DUAL_PLL BIT(0)
+#define CCS_CLOCK_TREE_PLL_CAPABILITY_SINGLE_PLL BIT(1)
+#define CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER BIT(2)
+#define CCS_CLOCK_TREE_PLL_CAPABILITY_FLEXIBLE_OP_PIX_CLK_DIV BIT(3)
+#define CCS_R_CLOCK_CAPA_TYPE_CAPABILITY 0x11b9
+#define CCS_CLOCK_CAPA_TYPE_CAPABILITY_IREAL BIT(0)
+#define CCS_R_MIN_EVEN_INC (0x11c0 | CCS_FL_16BIT)
+#define CCS_R_MIN_ODD_INC (0x11c2 | CCS_FL_16BIT)
+#define CCS_R_MAX_EVEN_INC (0x11c4 | CCS_FL_16BIT)
+#define CCS_R_MAX_ODD_INC (0x11c6 | CCS_FL_16BIT)
+#define CCS_R_AUX_SUBSAMP_CAPABILITY 0x11c8
+#define CCS_AUX_SUBSAMP_CAPABILITY_FACTOR_POWER_OF_2 BIT(1)
+#define CCS_R_AUX_SUBSAMP_MONO_CAPABILITY 0x11c9
+#define CCS_AUX_SUBSAMP_MONO_CAPABILITY_FACTOR_POWER_OF_2 BIT(1)
+#define CCS_R_MONOCHROME_CAPABILITY 0x11ca
+#define CCS_MONOCHROME_CAPABILITY_INC_ODD 0U
+#define CCS_MONOCHROME_CAPABILITY_INC_EVEN 1U
+#define CCS_R_PIXEL_READOUT_CAPABILITY 0x11cb
+#define CCS_PIXEL_READOUT_CAPABILITY_BAYER 0U
+#define CCS_PIXEL_READOUT_CAPABILITY_MONOCHROME 1U
+#define CCS_PIXEL_READOUT_CAPABILITY_BAYER_AND_MONO 2U
+#define CCS_R_MIN_EVEN_INC_MONO (0x11cc | CCS_FL_16BIT)
+#define CCS_R_MAX_EVEN_INC_MONO (0x11ce | CCS_FL_16BIT)
+#define CCS_R_MIN_ODD_INC_MONO (0x11d0 | CCS_FL_16BIT)
+#define CCS_R_MAX_ODD_INC_MONO (0x11d2 | CCS_FL_16BIT)
+#define CCS_R_MIN_EVEN_INC_BC2 (0x11d4 | CCS_FL_16BIT)
+#define CCS_R_MAX_EVEN_INC_BC2 (0x11d6 | CCS_FL_16BIT)
+#define CCS_R_MIN_ODD_INC_BC2 (0x11d8 | CCS_FL_16BIT)
+#define CCS_R_MAX_ODD_INC_BC2 (0x11da | CCS_FL_16BIT)
+#define CCS_R_MIN_EVEN_INC_MONO_BC2 (0x11dc | CCS_FL_16BIT)
+#define CCS_R_MAX_EVEN_INC_MONO_BC2 (0x11de | CCS_FL_16BIT)
+#define CCS_R_MIN_ODD_INC_MONO_BC2 (0x11f0 | CCS_FL_16BIT)
+#define CCS_R_MAX_ODD_INC_MONO_BC2 (0x11f2 | CCS_FL_16BIT)
+#define CCS_R_SCALING_CAPABILITY (0x1200 | CCS_FL_16BIT)
+#define CCS_SCALING_CAPABILITY_NONE 0U
+#define CCS_SCALING_CAPABILITY_HORIZONTAL 1U
+#define CCS_SCALING_CAPABILITY_RESERVED 2U
+#define CCS_R_SCALER_M_MIN (0x1204 | CCS_FL_16BIT)
+#define CCS_R_SCALER_M_MAX (0x1206 | CCS_FL_16BIT)
+#define CCS_R_SCALER_N_MIN (0x1208 | CCS_FL_16BIT)
+#define CCS_R_SCALER_N_MAX (0x120a | CCS_FL_16BIT)
+#define CCS_R_DIGITAL_CROP_CAPABILITY 0x120e
+#define CCS_DIGITAL_CROP_CAPABILITY_NONE 0U
+#define CCS_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1U
+#define CCS_R_HDR_CAPABILITY_1 0x1210
+#define CCS_HDR_CAPABILITY_1_2X2_BINNING BIT(0)
+#define CCS_HDR_CAPABILITY_1_COMBINED_ANALOG_GAIN BIT(1)
+#define CCS_HDR_CAPABILITY_1_SEPARATE_ANALOG_GAIN BIT(2)
+#define CCS_HDR_CAPABILITY_1_UPSCALING BIT(3)
+#define CCS_HDR_CAPABILITY_1_RESET_SYNC BIT(4)
+#define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_TIMING BIT(5)
+#define CCS_HDR_CAPABILITY_1_DIRECT_SHORT_EXP_SYNTHESIS BIT(6)
+#define CCS_R_MIN_HDR_BIT_DEPTH 0x1211
+#define CCS_R_HDR_RESOLUTION_SUB_TYPES 0x1212
+#define CCS_R_HDR_RESOLUTION_SUB_TYPE(n) (0x1213 + (n))
+#define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MIN_N 0U
+#define CCS_LIM_HDR_RESOLUTION_SUB_TYPE_MAX_N 1U
+#define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_SHIFT 0U
+#define CCS_HDR_RESOLUTION_SUB_TYPE_ROW_MASK 0xf
+#define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_SHIFT 4U
+#define CCS_HDR_RESOLUTION_SUB_TYPE_COLUMN_MASK 0xf0
+#define CCS_R_HDR_CAPABILITY_2 0x121b
+#define CCS_HDR_CAPABILITY_2_COMBINED_DIGITAL_GAIN BIT(0)
+#define CCS_HDR_CAPABILITY_2_SEPARATE_DIGITAL_GAIN BIT(1)
+#define CCS_HDR_CAPABILITY_2_TIMING_MODE BIT(3)
+#define CCS_HDR_CAPABILITY_2_SYNTHESIS_MODE BIT(4)
+#define CCS_R_MAX_HDR_BIT_DEPTH 0x121c
+#define CCS_R_USL_SUPPORT_CAPABILITY 0x1230
+#define CCS_USL_SUPPORT_CAPABILITY_CLOCK_TREE BIT(0)
+#define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_TREE BIT(1)
+#define CCS_USL_SUPPORT_CAPABILITY_REV_CLOCK_CALC BIT(2)
+#define CCS_R_USL_CLOCK_MODE_D_CAPABILITY 0x1231
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_STANDBY BIT(0)
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_VBLANK BIT(1)
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_CONT_CLOCK_HBLANK BIT(2)
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_STANDBY BIT(3)
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_VBLANK BIT(4)
+#define CCS_USL_CLOCK_MODE_D_CAPABILITY_NONCONT_CLOCK_HBLANK BIT(5)
+#define CCS_R_MIN_OP_SYS_CLK_DIV_REV 0x1234
+#define CCS_R_MAX_OP_SYS_CLK_DIV_REV 0x1236
+#define CCS_R_MIN_OP_PIX_CLK_DIV_REV 0x1238
+#define CCS_R_MAX_OP_PIX_CLK_DIV_REV 0x123a
+#define CCS_R_MIN_OP_SYS_CLK_FREQ_REV_MHZ (0x123c | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_SYS_CLK_FREQ_REV_MHZ (0x1240 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MIN_OP_PIX_CLK_FREQ_REV_MHZ (0x1244 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_OP_PIX_CLK_FREQ_REV_MHZ (0x1248 | (CCS_FL_32BIT | CCS_FL_FLOAT_IREAL))
+#define CCS_R_MAX_BITRATE_REV_D_MODE_MBPS (0x124c | (CCS_FL_32BIT | CCS_FL_IREAL))
+#define CCS_R_MAX_SYMRATE_REV_C_MODE_MSPS (0x1250 | (CCS_FL_32BIT | CCS_FL_IREAL))
+#define CCS_R_COMPRESSION_CAPABILITY 0x1300
+#define CCS_COMPRESSION_CAPABILITY_DPCM_PCM_SIMPLE BIT(0)
+#define CCS_R_TEST_MODE_CAPABILITY (0x1310 | CCS_FL_16BIT)
+#define CCS_TEST_MODE_CAPABILITY_SOLID_COLOR BIT(0)
+#define CCS_TEST_MODE_CAPABILITY_COLOR_BARS BIT(1)
+#define CCS_TEST_MODE_CAPABILITY_FADE_TO_GREY BIT(2)
+#define CCS_TEST_MODE_CAPABILITY_PN9 BIT(3)
+#define CCS_TEST_MODE_CAPABILITY_COLOR_TILE BIT(5)
+#define CCS_R_PN9_DATA_FORMAT1 0x1312
+#define CCS_R_PN9_DATA_FORMAT2 0x1313
+#define CCS_R_PN9_DATA_FORMAT3 0x1314
+#define CCS_R_PN9_DATA_FORMAT4 0x1315
+#define CCS_R_PN9_MISC_CAPABILITY 0x1316
+#define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_SHIFT 0U
+#define CCS_PN9_MISC_CAPABILITY_NUM_PIXELS_MASK 0x7
+#define CCS_PN9_MISC_CAPABILITY_COMPRESSION BIT(3)
+#define CCS_R_TEST_PATTERN_CAPABILITY 0x1317
+#define CCS_TEST_PATTERN_CAPABILITY_NO_REPEAT BIT(1)
+#define CCS_R_PATTERN_SIZE_DIV_M1 0x1318
+#define CCS_R_FIFO_SUPPORT_CAPABILITY 0x1502
+#define CCS_FIFO_SUPPORT_CAPABILITY_NONE 0U
+#define CCS_FIFO_SUPPORT_CAPABILITY_DERATING 1U
+#define CCS_FIFO_SUPPORT_CAPABILITY_DERATING_OVERRATING 2U
+#define CCS_R_PHY_CTRL_CAPABILITY 0x1600
+#define CCS_PHY_CTRL_CAPABILITY_AUTO_PHY_CTL BIT(0)
+#define CCS_PHY_CTRL_CAPABILITY_UI_PHY_CTL BIT(1)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_1_CTL BIT(2)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_UI_REG_2_CTL BIT(3)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_TIME_CTL BIT(4)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_1_CTL BIT(5)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_UI_REG_2_CTL BIT(6)
+#define CCS_PHY_CTRL_CAPABILITY_DPHY_EXT_TIME_CTL BIT(7)
+#define CCS_R_CSI_DPHY_LANE_MODE_CAPABILITY 0x1601
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_2_LANE BIT(1)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_3_LANE BIT(2)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_4_LANE BIT(3)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_5_LANE BIT(4)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_6_LANE BIT(5)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_7_LANE BIT(6)
+#define CCS_CSI_DPHY_LANE_MODE_CAPABILITY_8_LANE BIT(7)
+#define CCS_R_CSI_SIGNALING_MODE_CAPABILITY 0x1602
+#define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_DPHY BIT(2)
+#define CCS_CSI_SIGNALING_MODE_CAPABILITY_CSI_CPHY BIT(3)
+#define CCS_R_FAST_STANDBY_CAPABILITY 0x1603
+#define CCS_FAST_STANDBY_CAPABILITY_NO_FRAME_TRUNCATION 0U
+#define CCS_FAST_STANDBY_CAPABILITY_FRAME_TRUNCATION 1U
+#define CCS_R_CSI_ADDRESS_CONTROL_CAPABILITY 0x1604
+#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_CCI_ADDR_CHANGE BIT(0)
+#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_2ND_CCI_ADDR BIT(1)
+#define CCS_CSI_ADDRESS_CONTROL_CAPABILITY_SW_CHANGEABLE_2ND_CCI_ADDR BIT(2)
+#define CCS_R_DATA_TYPE_CAPABILITY 0x1605
+#define CCS_DATA_TYPE_CAPABILITY_DPCM_PROGRAMMABLE BIT(0)
+#define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_DT_PROGRAMMABLE BIT(1)
+#define CCS_DATA_TYPE_CAPABILITY_BOTTOM_EMBEDDED_VC_PROGRAMMABLE BIT(2)
+#define CCS_DATA_TYPE_CAPABILITY_EXT_VC_RANGE BIT(3)
+#define CCS_R_CSI_CPHY_LANE_MODE_CAPABILITY 0x1606
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_1_LANE BIT(0)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_2_LANE BIT(1)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_3_LANE BIT(2)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_4_LANE BIT(3)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_5_LANE BIT(4)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_6_LANE BIT(5)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_7_LANE BIT(6)
+#define CCS_CSI_CPHY_LANE_MODE_CAPABILITY_8_LANE BIT(7)
+#define CCS_R_EMB_DATA_CAPABILITY 0x1607
+#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW16 BIT(0)
+#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW20 BIT(1)
+#define CCS_EMB_DATA_CAPABILITY_TWO_BYTES_PER_RAW24 BIT(2)
+#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW16 BIT(3)
+#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW20 BIT(4)
+#define CCS_EMB_DATA_CAPABILITY_NO_ONE_BYTE_PER_RAW24 BIT(5)
+#define CCS_R_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS(n) ((0x1608 | (CCS_FL_32BIT | CCS_FL_IREAL)) + ((n) < 4 ? (n) * 4 : 0x32 + ((n) - 4) * 4))
+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MIN_N 0U
+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_D_MODE_MBPS_MAX_N 7U
+#define CCS_R_TEMP_SENSOR_CAPABILITY 0x1618
+#define CCS_TEMP_SENSOR_CAPABILITY_SUPPORTED BIT(0)
+#define CCS_TEMP_SENSOR_CAPABILITY_CCS_FORMAT BIT(1)
+#define CCS_TEMP_SENSOR_CAPABILITY_RESET_0X80 BIT(2)
+#define CCS_R_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS(n) ((0x161a | (CCS_FL_32BIT | CCS_FL_IREAL)) + ((n) < 4 ? (n) * 4 : 0x30 + ((n) - 4) * 4))
+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MIN_N 0U
+#define CCS_LIM_MAX_PER_LANE_BITRATE_LANE_C_MODE_MBPS_MAX_N 7U
+#define CCS_R_DPHY_EQUALIZATION_CAPABILITY 0x162b
+#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0)
+#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ1 BIT(1)
+#define CCS_DPHY_EQUALIZATION_CAPABILITY_EQ2 BIT(2)
+#define CCS_R_CPHY_EQUALIZATION_CAPABILITY 0x162c
+#define CCS_CPHY_EQUALIZATION_CAPABILITY_EQUALIZATION_CTRL BIT(0)
+#define CCS_R_DPHY_PREAMBLE_CAPABILITY 0x162d
+#define CCS_DPHY_PREAMBLE_CAPABILITY_PREAMBLE_SEQ_CTRL BIT(0)
+#define CCS_R_DPHY_SSC_CAPABILITY 0x162e
+#define CCS_DPHY_SSC_CAPABILITY_SUPPORTED BIT(0)
+#define CCS_R_CPHY_CALIBRATION_CAPABILITY 0x162f
+#define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0)
+#define CCS_CPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING BIT(1)
+#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_1_CTRL BIT(2)
+#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_2_CTRL BIT(3)
+#define CCS_CPHY_CALIBRATION_CAPABILITY_FORMAT_3_CTRL BIT(4)
+#define CCS_R_DPHY_CALIBRATION_CAPABILITY 0x1630
+#define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL BIT(0)
+#define CCS_DPHY_CALIBRATION_CAPABILITY_MANUAL_STREAMING BIT(1)
+#define CCS_DPHY_CALIBRATION_CAPABILITY_ALTERNATE_SEQ BIT(2)
+#define CCS_R_PHY_CTRL_CAPABILITY_2 0x1631
+#define CCS_PHY_CTRL_CAPABILITY_2_TGR_LENGTH BIT(0)
+#define CCS_PHY_CTRL_CAPABILITY_2_TGR_PREAMBLE_PROG_SEQ BIT(1)
+#define CCS_PHY_CTRL_CAPABILITY_2_EXTRA_CPHY_MANUAL_TIMING BIT(2)
+#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CDPHY BIT(3)
+#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_DPHY BIT(4)
+#define CCS_PHY_CTRL_CAPABILITY_2_CLOCK_BASED_MANUAL_CPHY BIT(5)
+#define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_DPHY BIT(6)
+#define CCS_PHY_CTRL_CAPABILITY_2_MANUAL_LP_CPHY BIT(7)
+#define CCS_R_LRTE_CPHY_CAPABILITY 0x1632
+#define CCS_LRTE_CPHY_CAPABILITY_PDQ_SHORT BIT(0)
+#define CCS_LRTE_CPHY_CAPABILITY_SPACER_SHORT BIT(1)
+#define CCS_LRTE_CPHY_CAPABILITY_PDQ_LONG BIT(2)
+#define CCS_LRTE_CPHY_CAPABILITY_SPACER_LONG BIT(3)
+#define CCS_LRTE_CPHY_CAPABILITY_SPACER_NO_PDQ BIT(4)
+#define CCS_R_LRTE_DPHY_CAPABILITY 0x1633
+#define CCS_LRTE_DPHY_CAPABILITY_PDQ_SHORT_OPT1 BIT(0)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT1 BIT(1)
+#define CCS_LRTE_DPHY_CAPABILITY_PDQ_LONG_OPT1 BIT(2)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT1 BIT(3)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_SHORT_OPT2 BIT(4)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_LONG_OPT2 BIT(5)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_NO_PDQ_OPT1 BIT(6)
+#define CCS_LRTE_DPHY_CAPABILITY_SPACER_VARIABLE_OPT2 BIT(7)
+#define CCS_R_ALPS_CAPABILITY_DPHY 0x1634
+#define CCS_ALPS_CAPABILITY_DPHY_LVLP_NOT_SUPPORTED 0U
+#define CCS_ALPS_CAPABILITY_DPHY_LVLP_SUPPORTED 1U
+#define CCS_ALPS_CAPABILITY_DPHY_CONTROLLABLE_LVLP 2U
+#define CCS_R_ALPS_CAPABILITY_CPHY 0x1635
+#define CCS_ALPS_CAPABILITY_CPHY_LVLP_NOT_SUPPORTED 0U
+#define CCS_ALPS_CAPABILITY_CPHY_LVLP_SUPPORTED 1U
+#define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_LVLP 2U
+#define CCS_ALPS_CAPABILITY_CPHY_ALP_NOT_SUPPORTED 0xc
+#define CCS_ALPS_CAPABILITY_CPHY_ALP_SUPPORTED 0xd
+#define CCS_ALPS_CAPABILITY_CPHY_CONTROLLABLE_ALP 0xe
+#define CCS_R_SCRAMBLING_CAPABILITY 0x1636
+#define CCS_SCRAMBLING_CAPABILITY_SCRAMBLING_SUPPORTED BIT(0)
+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_SHIFT 1U
+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_MASK 0x6
+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_1 0U
+#define CCS_SCRAMBLING_CAPABILITY_MAX_SEEDS_PER_LANE_C_4 3U
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_SHIFT 3U
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_MASK 0x38
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_0 0U
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_1 1U
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_REGS_4 4U
+#define CCS_SCRAMBLING_CAPABILITY_NUM_SEED_PER_LANE BIT(6)
+#define CCS_R_DPHY_MANUAL_CONSTANT 0x1637
+#define CCS_R_CPHY_MANUAL_CONSTANT 0x1638
+#define CCS_R_CSI2_INTERFACE_CAPABILITY_MISC 0x1639
+#define CCS_CSI2_INTERFACE_CAPABILITY_MISC_EOTP_SHORT_PKT_OPT2 BIT(0)
+#define CCS_R_PHY_CTRL_CAPABILITY_3 0x165c
+#define CCS_PHY_CTRL_CAPABILITY_3_DPHY_TIMING_NOT_MULTIPLE BIT(0)
+#define CCS_PHY_CTRL_CAPABILITY_3_DPHY_MIN_TIMING_VALUE_1 BIT(1)
+#define CCS_PHY_CTRL_CAPABILITY_3_TWAKEUP_SUPPORTED BIT(2)
+#define CCS_PHY_CTRL_CAPABILITY_3_TINIT_SUPPORTED BIT(3)
+#define CCS_PHY_CTRL_CAPABILITY_3_THS_EXIT_SUPPORTED BIT(4)
+#define CCS_PHY_CTRL_CAPABILITY_3_CPHY_TIMING_NOT_MULTIPLE BIT(5)
+#define CCS_PHY_CTRL_CAPABILITY_3_CPHY_MIN_TIMING_VALUE_1 BIT(6)
+#define CCS_R_DPHY_SF 0x165d
+#define CCS_R_CPHY_SF 0x165e
+#define CCS_CPHY_SF_TWAKEUP_SHIFT 0U
+#define CCS_CPHY_SF_TWAKEUP_MASK 0xf
+#define CCS_CPHY_SF_TINIT_SHIFT 4U
+#define CCS_CPHY_SF_TINIT_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_1 0x165f
+#define CCS_DPHY_LIMITS_1_THS_PREPARE_SHIFT 0U
+#define CCS_DPHY_LIMITS_1_THS_PREPARE_MASK 0xf
+#define CCS_DPHY_LIMITS_1_THS_ZERO_SHIFT 4U
+#define CCS_DPHY_LIMITS_1_THS_ZERO_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_2 0x1660
+#define CCS_DPHY_LIMITS_2_THS_TRAIL_SHIFT 0U
+#define CCS_DPHY_LIMITS_2_THS_TRAIL_MASK 0xf
+#define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_SHIFT 4U
+#define CCS_DPHY_LIMITS_2_TCLK_TRAIL_MIN_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_3 0x1661
+#define CCS_DPHY_LIMITS_3_TCLK_PREPARE_SHIFT 0U
+#define CCS_DPHY_LIMITS_3_TCLK_PREPARE_MASK 0xf
+#define CCS_DPHY_LIMITS_3_TCLK_ZERO_SHIFT 4U
+#define CCS_DPHY_LIMITS_3_TCLK_ZERO_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_4 0x1662
+#define CCS_DPHY_LIMITS_4_TCLK_POST_SHIFT 0U
+#define CCS_DPHY_LIMITS_4_TCLK_POST_MASK 0xf
+#define CCS_DPHY_LIMITS_4_TLPX_SHIFT 4U
+#define CCS_DPHY_LIMITS_4_TLPX_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_5 0x1663
+#define CCS_DPHY_LIMITS_5_THS_EXIT_SHIFT 0U
+#define CCS_DPHY_LIMITS_5_THS_EXIT_MASK 0xf
+#define CCS_DPHY_LIMITS_5_TWAKEUP_SHIFT 4U
+#define CCS_DPHY_LIMITS_5_TWAKEUP_MASK 0xf0
+#define CCS_R_DPHY_LIMITS_6 0x1664
+#define CCS_DPHY_LIMITS_6_TINIT_SHIFT 0U
+#define CCS_DPHY_LIMITS_6_TINIT_MASK 0xf
+#define CCS_R_CPHY_LIMITS_1 0x1665
+#define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_SHIFT 0U
+#define CCS_CPHY_LIMITS_1_T3_PREPARE_MAX_MASK 0xf
+#define CCS_CPHY_LIMITS_1_T3_LPX_MAX_SHIFT 4U
+#define CCS_CPHY_LIMITS_1_T3_LPX_MAX_MASK 0xf0
+#define CCS_R_CPHY_LIMITS_2 0x1666
+#define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_SHIFT 0U
+#define CCS_CPHY_LIMITS_2_THS_EXIT_MAX_MASK 0xf
+#define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_SHIFT 4U
+#define CCS_CPHY_LIMITS_2_TWAKEUP_MAX_MASK 0xf0
+#define CCS_R_CPHY_LIMITS_3 0x1667
+#define CCS_CPHY_LIMITS_3_TINIT_MAX_SHIFT 0U
+#define CCS_CPHY_LIMITS_3_TINIT_MAX_MASK 0xf
+#define CCS_R_MIN_FRAME_LENGTH_LINES_BIN (0x1700 | CCS_FL_16BIT)
+#define CCS_R_MAX_FRAME_LENGTH_LINES_BIN (0x1702 | CCS_FL_16BIT)
+#define CCS_R_MIN_LINE_LENGTH_PCK_BIN (0x1704 | CCS_FL_16BIT)
+#define CCS_R_MAX_LINE_LENGTH_PCK_BIN (0x1706 | CCS_FL_16BIT)
+#define CCS_R_MIN_LINE_BLANKING_PCK_BIN (0x1708 | CCS_FL_16BIT)
+#define CCS_R_FINE_INTEGRATION_TIME_MIN_BIN (0x170a | CCS_FL_16BIT)
+#define CCS_R_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN (0x170c | CCS_FL_16BIT)
+#define CCS_R_BINNING_CAPABILITY 0x1710
+#define CCS_BINNING_CAPABILITY_UNSUPPORTED 0U
+#define CCS_BINNING_CAPABILITY_BINNING_THEN_SUBSAMPLING 1U
+#define CCS_BINNING_CAPABILITY_SUBSAMPLING_THEN_BINNING 2U
+#define CCS_R_BINNING_WEIGHTING_CAPABILITY 0x1711
+#define CCS_BINNING_WEIGHTING_CAPABILITY_AVERAGED BIT(0)
+#define CCS_BINNING_WEIGHTING_CAPABILITY_SUMMED BIT(1)
+#define CCS_BINNING_WEIGHTING_CAPABILITY_BAYER_CORRECTED BIT(2)
+#define CCS_BINNING_WEIGHTING_CAPABILITY_MODULE_SPECIFIC_WEIGHT BIT(3)
+#define CCS_R_BINNING_SUB_TYPES 0x1712
+#define CCS_R_BINNING_SUB_TYPE(n) (0x1713 + (n))
+#define CCS_LIM_BINNING_SUB_TYPE_MIN_N 0U
+#define CCS_LIM_BINNING_SUB_TYPE_MAX_N 63U
+#define CCS_BINNING_SUB_TYPE_ROW_SHIFT 0U
+#define CCS_BINNING_SUB_TYPE_ROW_MASK 0xf
+#define CCS_BINNING_SUB_TYPE_COLUMN_SHIFT 4U
+#define CCS_BINNING_SUB_TYPE_COLUMN_MASK 0xf0
+#define CCS_R_BINNING_WEIGHTING_MONO_CAPABILITY 0x1771
+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_AVERAGED BIT(0)
+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_SUMMED BIT(1)
+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_BAYER_CORRECTED BIT(2)
+#define CCS_BINNING_WEIGHTING_MONO_CAPABILITY_MODULE_SPECIFIC_WEIGHT BIT(3)
+#define CCS_R_BINNING_SUB_TYPES_MONO 0x1772
+#define CCS_R_BINNING_SUB_TYPE_MONO(n) (0x1773 + (n))
+#define CCS_LIM_BINNING_SUB_TYPE_MONO_MIN_N 0U
+#define CCS_LIM_BINNING_SUB_TYPE_MONO_MAX_N 63U
+#define CCS_R_DATA_TRANSFER_IF_CAPABILITY 0x1800
+#define CCS_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0)
+#define CCS_DATA_TRANSFER_IF_CAPABILITY_POLLING BIT(2)
+#define CCS_R_SHADING_CORRECTION_CAPABILITY 0x1900
+#define CCS_SHADING_CORRECTION_CAPABILITY_COLOR_SHADING BIT(0)
+#define CCS_SHADING_CORRECTION_CAPABILITY_LUMINANCE_CORRECTION BIT(1)
+#define CCS_R_GREEN_IMBALANCE_CAPABILITY 0x1901
+#define CCS_GREEN_IMBALANCE_CAPABILITY_SUPPORTED BIT(0)
+#define CCS_R_MODULE_SPECIFIC_CORRECTION_CAPABILITY 0x1903
+#define CCS_R_DEFECT_CORRECTION_CAPABILITY (0x1904 | CCS_FL_16BIT)
+#define CCS_DEFECT_CORRECTION_CAPABILITY_MAPPED_DEFECT BIT(0)
+#define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_COUPLET BIT(2)
+#define CCS_DEFECT_CORRECTION_CAPABILITY_DYNAMIC_SINGLE BIT(5)
+#define CCS_DEFECT_CORRECTION_CAPABILITY_COMBINED_DYNAMIC BIT(8)
+#define CCS_R_DEFECT_CORRECTION_CAPABILITY_2 (0x1906 | CCS_FL_16BIT)
+#define CCS_DEFECT_CORRECTION_CAPABILITY_2_DYNAMIC_TRIPLET BIT(3)
+#define CCS_R_NF_CAPABILITY 0x1908
+#define CCS_NF_CAPABILITY_LUMA BIT(0)
+#define CCS_NF_CAPABILITY_CHROMA BIT(1)
+#define CCS_NF_CAPABILITY_COMBINED BIT(2)
+#define CCS_R_OB_READOUT_CAPABILITY 0x1980
+#define CCS_OB_READOUT_CAPABILITY_CONTROLLABLE_READOUT BIT(0)
+#define CCS_OB_READOUT_CAPABILITY_VISIBLE_PIXEL_READOUT BIT(1)
+#define CCS_OB_READOUT_CAPABILITY_DIFFERENT_VC_READOUT BIT(2)
+#define CCS_OB_READOUT_CAPABILITY_DIFFERENT_DT_READOUT BIT(3)
+#define CCS_OB_READOUT_CAPABILITY_PROG_DATA_FORMAT BIT(4)
+#define CCS_R_COLOR_FEEDBACK_CAPABILITY 0x1987
+#define CCS_COLOR_FEEDBACK_CAPABILITY_KELVIN BIT(0)
+#define CCS_COLOR_FEEDBACK_CAPABILITY_AWB_GAIN BIT(1)
+#define CCS_R_CFA_PATTERN_CAPABILITY 0x1990
+#define CCS_CFA_PATTERN_CAPABILITY_BAYER 0U
+#define CCS_CFA_PATTERN_CAPABILITY_MONOCHROME 1U
+#define CCS_CFA_PATTERN_CAPABILITY_4X4_QUAD_BAYER 2U
+#define CCS_CFA_PATTERN_CAPABILITY_VENDOR_SPECIFIC 3U
+#define CCS_R_CFA_PATTERN_CONVERSION_CAPABILITY 0x1991
+#define CCS_CFA_PATTERN_CONVERSION_CAPABILITY_BAYER BIT(0)
+#define CCS_R_FLASH_MODE_CAPABILITY 0x1a02
+#define CCS_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0)
+#define CCS_R_SA_STROBE_MODE_CAPABILITY 0x1a03
+#define CCS_SA_STROBE_MODE_CAPABILITY_FIXED_WIDTH BIT(0)
+#define CCS_SA_STROBE_MODE_CAPABILITY_EDGE_CTRL BIT(1)
+#define CCS_R_RESET_MAX_DELAY 0x1a10
+#define CCS_R_RESET_MIN_TIME 0x1a11
+#define CCS_R_PDAF_CAPABILITY_1 0x1b80
+#define CCS_PDAF_CAPABILITY_1_SUPPORTED BIT(0)
+#define CCS_PDAF_CAPABILITY_1_PROCESSED_BOTTOM_EMBEDDED BIT(1)
+#define CCS_PDAF_CAPABILITY_1_PROCESSED_INTERLEAVED BIT(2)
+#define CCS_PDAF_CAPABILITY_1_RAW_BOTTOM_EMBEDDED BIT(3)
+#define CCS_PDAF_CAPABILITY_1_RAW_INTERLEAVED BIT(4)
+#define CCS_PDAF_CAPABILITY_1_VISIBLE_PDAF_CORRECTION BIT(5)
+#define CCS_PDAF_CAPABILITY_1_VC_INTERLEAVING BIT(6)
+#define CCS_PDAF_CAPABILITY_1_DT_INTERLEAVING BIT(7)
+#define CCS_R_PDAF_CAPABILITY_2 0x1b81
+#define CCS_PDAF_CAPABILITY_2_ROI BIT(0)
+#define CCS_PDAF_CAPABILITY_2_AFTER_DIGITAL_CROP BIT(1)
+#define CCS_PDAF_CAPABILITY_2_CTRL_RETIMED BIT(2)
+#define CCS_R_BRACKETING_LUT_CAPABILITY_1 0x1c00
+#define CCS_BRACKETING_LUT_CAPABILITY_1_COARSE_INTEGRATION BIT(0)
+#define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_ANALOG_GAIN BIT(1)
+#define CCS_BRACKETING_LUT_CAPABILITY_1_FLASH BIT(4)
+#define CCS_BRACKETING_LUT_CAPABILITY_1_GLOBAL_DIGITAL_GAIN BIT(5)
+#define CCS_BRACKETING_LUT_CAPABILITY_1_ALTERNATE_GLOBAL_ANALOG_GAIN BIT(6)
+#define CCS_R_BRACKETING_LUT_CAPABILITY_2 0x1c01
+#define CCS_BRACKETING_LUT_CAPABILITY_2_SINGLE_BRACKETING_MODE BIT(0)
+#define CCS_BRACKETING_LUT_CAPABILITY_2_LOOPED_BRACKETING_MODE BIT(1)
+#define CCS_R_BRACKETING_LUT_SIZE 0x1c02
+
+#endif /* __CCS_REGS_H__ */
diff --git a/drivers/media/i2c/ccs/ccs.h b/drivers/media/i2c/ccs/ccs.h
new file mode 100644
index 000000000..6beac375c
--- /dev/null
+++ b/drivers/media/i2c/ccs/ccs.h
@@ -0,0 +1,290 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * drivers/media/i2c/smiapp/ccs.h
+ *
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
+ *
+ * Copyright (C) 2020 Intel Corporation
+ * Copyright (C) 2010--2012 Nokia Corporation
+ * Contact: Sakari Ailus <sakari.ailus@linux.intel.com>
+ */
+
+#ifndef __CCS_H__
+#define __CCS_H__
+
+#include <linux/mutex.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-subdev.h>
+
+#include "ccs-data.h"
+#include "ccs-limits.h"
+#include "ccs-quirk.h"
+#include "ccs-regs.h"
+#include "ccs-reg-access.h"
+#include "../ccs-pll.h"
+#include "smiapp-reg-defs.h"
+
+/*
+ * Standard SMIA++ constants
+ */
+#define SMIA_VERSION_1 10
+#define SMIAPP_VERSION_0_8 8 /* Draft 0.8 */
+#define SMIAPP_VERSION_0_9 9 /* Draft 0.9 */
+#define SMIAPP_VERSION_1 10
+
+#define SMIAPP_PROFILE_0 0
+#define SMIAPP_PROFILE_1 1
+#define SMIAPP_PROFILE_2 2
+
+#define SMIAPP_NVM_PAGE_SIZE 64 /* bytes */
+
+#define SMIAPP_RESET_DELAY_CLOCKS 2400
+#define SMIAPP_RESET_DELAY(clk) \
+ (1000 + (SMIAPP_RESET_DELAY_CLOCKS * 1000 \
+ + (clk) / 1000 - 1) / ((clk) / 1000))
+
+#define CCS_COLOUR_COMPONENTS 4
+
+#define SMIAPP_NAME "smiapp"
+#define CCS_NAME "ccs"
+
+#define CCS_DFL_I2C_ADDR (0x20 >> 1) /* Default I2C Address */
+#define CCS_ALT_I2C_ADDR (0x6e >> 1) /* Alternate I2C Address */
+
+#define CCS_LIM(sensor, limit) \
+ ccs_get_limit(sensor, CCS_L_##limit, 0)
+
+#define CCS_LIM_AT(sensor, limit, offset) \
+ ccs_get_limit(sensor, CCS_L_##limit, CCS_L_##limit##_OFFSET(offset))
+
+/*
+ * Sometimes due to board layout considerations the camera module can be
+ * mounted rotated. The typical rotation used is 180 degrees which can be
+ * corrected by giving a default H-FLIP and V-FLIP in the sensor readout.
+ * FIXME: rotation also changes the bayer pattern.
+ */
+enum ccs_module_board_orient {
+ CCS_MODULE_BOARD_ORIENT_0 = 0,
+ CCS_MODULE_BOARD_ORIENT_180,
+};
+
+struct ccs_flash_strobe_parms {
+ u8 mode;
+ u32 strobe_width_high_us;
+ u16 strobe_delay;
+ u16 stobe_start_point;
+ u8 trigger;
+};
+
+struct ccs_hwconfig {
+ /*
+ * Change the cci address if i2c_addr_alt is set.
+ * Both default and alternate cci addr need to be present
+ */
+ unsigned short i2c_addr_dfl; /* Default i2c addr */
+ unsigned short i2c_addr_alt; /* Alternate i2c addr */
+
+ u32 ext_clk; /* sensor external clk */
+
+ unsigned int lanes; /* Number of CSI-2 lanes */
+ u32 csi_signalling_mode; /* CCS_CSI_SIGNALLING_MODE_* */
+ u64 *op_sys_clock;
+
+ enum ccs_module_board_orient module_board_orient;
+
+ struct ccs_flash_strobe_parms *strobe_setup;
+};
+
+struct ccs_quirk;
+
+#define CCS_MODULE_IDENT_FLAG_REV_LE (1 << 0)
+
+struct ccs_module_ident {
+ u16 mipi_manufacturer_id;
+ u16 model_id;
+ u8 smia_manufacturer_id;
+ u8 revision_number_major;
+
+ u8 flags;
+
+ char *name;
+ const struct ccs_quirk *quirk;
+};
+
+struct ccs_module_info {
+ u32 smia_manufacturer_id;
+ u32 mipi_manufacturer_id;
+ u32 model_id;
+ u32 revision_number;
+
+ u32 module_year;
+ u32 module_month;
+ u32 module_day;
+
+ u32 sensor_smia_manufacturer_id;
+ u32 sensor_mipi_manufacturer_id;
+ u32 sensor_model_id;
+ u32 sensor_revision_number;
+ u32 sensor_firmware_version;
+
+ u32 smia_version;
+ u32 smiapp_version;
+ u32 ccs_version;
+
+ char *name;
+ const struct ccs_quirk *quirk;
+};
+
+#define CCS_IDENT_FQ(manufacturer, model, rev, fl, _name, _quirk) \
+ { .smia_manufacturer_id = manufacturer, \
+ .model_id = model, \
+ .revision_number_major = rev, \
+ .flags = fl, \
+ .name = _name, \
+ .quirk = _quirk, }
+
+#define CCS_IDENT_LQ(manufacturer, model, rev, _name, _quirk) \
+ { .smia_manufacturer_id = manufacturer, \
+ .model_id = model, \
+ .revision_number_major = rev, \
+ .flags = CCS_MODULE_IDENT_FLAG_REV_LE, \
+ .name = _name, \
+ .quirk = _quirk, }
+
+#define CCS_IDENT_L(manufacturer, model, rev, _name) \
+ { .smia_manufacturer_id = manufacturer, \
+ .model_id = model, \
+ .revision_number_major = rev, \
+ .flags = CCS_MODULE_IDENT_FLAG_REV_LE, \
+ .name = _name, }
+
+#define CCS_IDENT_Q(manufacturer, model, rev, _name, _quirk) \
+ { .smia_manufacturer_id = manufacturer, \
+ .model_id = model, \
+ .revision_number_major = rev, \
+ .flags = 0, \
+ .name = _name, \
+ .quirk = _quirk, }
+
+#define CCS_IDENT(manufacturer, model, rev, _name) \
+ { .smia_manufacturer_id = manufacturer, \
+ .model_id = model, \
+ .revision_number_major = rev, \
+ .flags = 0, \
+ .name = _name, }
+
+struct ccs_csi_data_format {
+ u32 code;
+ u8 width;
+ u8 compressed;
+ u8 pixel_order;
+};
+
+#define CCS_SUBDEVS 3
+
+#define CCS_PA_PAD_SRC 0
+#define CCS_PAD_SINK 0
+#define CCS_PAD_SRC 1
+#define CCS_PADS 2
+
+struct ccs_binning_subtype {
+ u8 horizontal:4;
+ u8 vertical:4;
+} __packed;
+
+struct ccs_subdev {
+ struct v4l2_subdev sd;
+ struct media_pad pads[CCS_PADS];
+ struct v4l2_rect sink_fmt;
+ struct v4l2_rect crop[CCS_PADS];
+ struct v4l2_rect compose; /* compose on sink */
+ unsigned short sink_pad;
+ unsigned short source_pad;
+ int npads;
+ struct ccs_sensor *sensor;
+ struct v4l2_ctrl_handler ctrl_handler;
+};
+
+/*
+ * struct ccs_sensor - Main device structure
+ */
+struct ccs_sensor {
+ /*
+ * "mutex" is used to serialise access to all fields here
+ * except v4l2_ctrls at the end of the struct. "mutex" is also
+ * used to serialise access to file handle specific
+ * information.
+ */
+ struct mutex mutex;
+ struct ccs_subdev ssds[CCS_SUBDEVS];
+ u32 ssds_used;
+ struct ccs_subdev *src;
+ struct ccs_subdev *binner;
+ struct ccs_subdev *scaler;
+ struct ccs_subdev *pixel_array;
+ struct ccs_hwconfig hwcfg;
+ struct regulator_bulk_data *regulators;
+ struct clk *ext_clk;
+ struct gpio_desc *xshutdown;
+ struct gpio_desc *reset;
+ void *ccs_limits;
+ u8 nbinning_subtypes;
+ struct ccs_binning_subtype binning_subtypes[CCS_LIM_BINNING_SUB_TYPE_MAX_N + 1];
+ u32 mbus_frame_fmts;
+ const struct ccs_csi_data_format *csi_format;
+ const struct ccs_csi_data_format *internal_csi_format;
+ u32 default_mbus_frame_fmts;
+ int default_pixel_order;
+ struct ccs_data_container sdata, mdata;
+
+ u8 binning_horizontal;
+ u8 binning_vertical;
+
+ u8 scale_m;
+ u8 scaling_mode;
+
+ u8 hvflip_inv_mask; /* H/VFLIP inversion due to sensor orientation */
+ u8 frame_skip;
+ u16 embedded_start; /* embedded data start line */
+ u16 embedded_end;
+ u16 image_start; /* image data start line */
+ u16 visible_pixel_start; /* start pixel of the visible image */
+
+ bool streaming;
+ bool dev_init_done;
+ u8 compressed_min_bpp;
+
+ struct ccs_module_info minfo;
+
+ struct ccs_pll pll;
+
+ /* Is a default format supported for a given BPP? */
+ unsigned long *valid_link_freqs;
+
+ /* Pixel array controls */
+ struct v4l2_ctrl *exposure;
+ struct v4l2_ctrl *hflip;
+ struct v4l2_ctrl *vflip;
+ struct v4l2_ctrl *vblank;
+ struct v4l2_ctrl *hblank;
+ struct v4l2_ctrl *pixel_rate_parray;
+ struct v4l2_ctrl *luminance_level;
+ /* src controls */
+ struct v4l2_ctrl *link_freq;
+ struct v4l2_ctrl *pixel_rate_csi;
+ /* test pattern colour components */
+ struct v4l2_ctrl *test_data[CCS_COLOUR_COMPONENTS];
+};
+
+#define to_ccs_subdev(_sd) \
+ container_of(_sd, struct ccs_subdev, sd)
+
+#define to_ccs_sensor(_sd) \
+ (to_ccs_subdev(_sd)->sensor)
+
+void ccs_replace_limit(struct ccs_sensor *sensor,
+ unsigned int limit, unsigned int offset, u32 val);
+u32 ccs_get_limit(struct ccs_sensor *sensor, unsigned int limit,
+ unsigned int offset);
+
+#endif /* __CCS_H__ */
diff --git a/drivers/media/i2c/ccs/smiapp-reg-defs.h b/drivers/media/i2c/ccs/smiapp-reg-defs.h
new file mode 100644
index 000000000..177e3e512
--- /dev/null
+++ b/drivers/media/i2c/ccs/smiapp-reg-defs.h
@@ -0,0 +1,582 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * drivers/media/i2c/smiapp/smiapp-reg-defs.h
+ *
+ * Generic driver for MIPI CCS/SMIA/SMIA++ compliant camera sensors
+ *
+ * Copyright (C) 2020 Intel Corporation
+ * Copyright (C) 2011--2012 Nokia Corporation
+ * Contact: Sakari Ailus <sakari.ailus@iki.fi>
+ */
+
+#ifndef __SMIAPP_REG_DEFS_H__
+#define __SMIAPP_REG_DEFS_H__
+
+/* Register addresses */
+#define SMIAPP_REG_U16_MODEL_ID (0x0000 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_REVISION_NUMBER_MAJOR 0x0002
+#define SMIAPP_REG_U8_MANUFACTURER_ID 0x0003
+#define SMIAPP_REG_U8_SMIA_VERSION 0x0004
+#define SMIAPP_REG_U8_FRAME_COUNT 0x0005
+#define SMIAPP_REG_U8_PIXEL_ORDER 0x0006
+#define SMIAPP_REG_U16_DATA_PEDESTAL (0x0008 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_PIXEL_DEPTH 0x000c
+#define SMIAPP_REG_U8_REVISION_NUMBER_MINOR 0x0010
+#define SMIAPP_REG_U8_SMIAPP_VERSION 0x0011
+#define SMIAPP_REG_U8_MODULE_DATE_YEAR 0x0012
+#define SMIAPP_REG_U8_MODULE_DATE_MONTH 0x0013
+#define SMIAPP_REG_U8_MODULE_DATE_DAY 0x0014
+#define SMIAPP_REG_U8_MODULE_DATE_PHASE 0x0015
+#define SMIAPP_REG_U16_SENSOR_MODEL_ID (0x0016 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_SENSOR_REVISION_NUMBER 0x0018
+#define SMIAPP_REG_U8_SENSOR_MANUFACTURER_ID 0x0019
+#define SMIAPP_REG_U8_SENSOR_FIRMWARE_VERSION 0x001a
+#define SMIAPP_REG_U32_SERIAL_NUMBER (0x001c | CCS_FL_32BIT)
+#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_TYPE 0x0040
+#define SMIAPP_REG_U8_FRAME_FORMAT_MODEL_SUBTYPE 0x0041
+#define SMIAPP_REG_U16_FRAME_FORMAT_DESCRIPTOR_2(n) ((0x0042 + ((n) << 1)) | CCS_FL_16BIT) /* 0 <= n <= 14 */
+#define SMIAPP_REG_U32_FRAME_FORMAT_DESCRIPTOR_4(n) ((0x0060 + ((n) << 2)) | CCS_FL_32BIT) /* 0 <= n <= 7 */
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CAPABILITY (0x0080 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MIN (0x0084 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_MAX (0x0086 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_STEP (0x0088 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_TYPE (0x008a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_M0 (0x008c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_C0 (0x008e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_M1 (0x0090 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_C1 (0x0092 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_TYPE 0x00c0
+#define SMIAPP_REG_U8_DATA_FORMAT_MODEL_SUBTYPE 0x00c1
+#define SMIAPP_REG_U16_DATA_FORMAT_DESCRIPTOR(n) ((0x00c2 + ((n) << 1)) | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_MODE_SELECT 0x0100
+#define SMIAPP_REG_U8_IMAGE_ORIENTATION 0x0101
+#define SMIAPP_REG_U8_SOFTWARE_RESET 0x0103
+#define SMIAPP_REG_U8_GROUPED_PARAMETER_HOLD 0x0104
+#define SMIAPP_REG_U8_MASK_CORRUPTED_FRAMES 0x0105
+#define SMIAPP_REG_U8_FAST_STANDBY_CTRL 0x0106
+#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL 0x0107
+#define SMIAPP_REG_U8_2ND_CCI_IF_CONTROL 0x0108
+#define SMIAPP_REG_U8_2ND_CCI_ADDRESS_CONTROL 0x0109
+#define SMIAPP_REG_U8_CSI_CHANNEL_IDENTIFIER 0x0110
+#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE 0x0111
+#define SMIAPP_REG_U16_CSI_DATA_FORMAT (0x0112 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_CSI_LANE_MODE 0x0114
+#define SMIAPP_REG_U8_CSI2_10_TO_8_DT 0x0115
+#define SMIAPP_REG_U8_CSI2_10_TO_7_DT 0x0116
+#define SMIAPP_REG_U8_CSI2_10_TO_6_DT 0x0117
+#define SMIAPP_REG_U8_CSI2_12_TO_8_DT 0x0118
+#define SMIAPP_REG_U8_CSI2_12_TO_7_DT 0x0119
+#define SMIAPP_REG_U8_CSI2_12_TO_6_DT 0x011a
+#define SMIAPP_REG_U8_CSI2_14_TO_10_DT 0x011b
+#define SMIAPP_REG_U8_CSI2_14_TO_8_DT 0x011c
+#define SMIAPP_REG_U8_CSI2_16_TO_10_DT 0x011d
+#define SMIAPP_REG_U8_CSI2_16_TO_8_DT 0x011e
+#define SMIAPP_REG_U8_GAIN_MODE 0x0120
+#define SMIAPP_REG_U16_VANA_VOLTAGE (0x0130 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VDIG_VOLTAGE (0x0132 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VIO_VOLTAGE (0x0134 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_EXTCLK_FREQUENCY_MHZ (0x0136 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_TEMP_SENSOR_CONTROL 0x0138
+#define SMIAPP_REG_U8_TEMP_SENSOR_MODE 0x0139
+#define SMIAPP_REG_U8_TEMP_SENSOR_OUTPUT 0x013a
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME (0x0200 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME (0x0202 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GLOBAL (0x0204 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENR (0x0206 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_RED (0x0208 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_BLUE (0x020a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ANALOGUE_GAIN_CODE_GREENB (0x020c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENR (0x020e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_RED (0x0210 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_BLUE (0x0212 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_GREENB (0x0214 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VT_PIX_CLK_DIV (0x0300 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VT_SYS_CLK_DIV (0x0302 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_PRE_PLL_CLK_DIV (0x0304 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_PLL_MULTIPLIER (0x0306 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_OP_PIX_CLK_DIV (0x0308 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_OP_SYS_CLK_DIV (0x030a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FRAME_LENGTH_LINES (0x0340 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_LINE_LENGTH_PCK (0x0342 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ADDR_START (0x0344 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_START (0x0346 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ADDR_END (0x0348 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_END (0x034a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_OUTPUT_SIZE (0x034c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_OUTPUT_SIZE (0x034e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_EVEN_INC (0x0380 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ODD_INC (0x0382 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_EVEN_INC (0x0384 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ODD_INC (0x0386 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALING_MODE (0x0400 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SPATIAL_SAMPLING (0x0402 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALE_M (0x0404 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALE_N (0x0406 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_X_OFFSET (0x0408 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_Y_OFFSET (0x040a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_WIDTH (0x040c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_CROP_IMAGE_HEIGHT (0x040e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COMPRESSION_MODE (0x0500 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_PATTERN_MODE (0x0600 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_RED (0x0602 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_GREENR (0x0604 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_BLUE (0x0606 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TEST_DATA_GREENB (0x0608 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_WIDTH (0x060a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_HORIZONTAL_CURSOR_POSITION (0x060c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VERTICAL_CURSOR_WIDTH (0x060e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_VERTICAL_CURSOR_POSITION (0x0610 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FIFO_WATER_MARK_PIXELS (0x0700 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_TCLK_POST 0x0800
+#define SMIAPP_REG_U8_THS_PREPARE 0x0801
+#define SMIAPP_REG_U8_THS_ZERO_MIN 0x0802
+#define SMIAPP_REG_U8_THS_TRAIL 0x0803
+#define SMIAPP_REG_U8_TCLK_TRAIL_MIN 0x0804
+#define SMIAPP_REG_U8_TCLK_PREPARE 0x0805
+#define SMIAPP_REG_U8_TCLK_ZERO 0x0806
+#define SMIAPP_REG_U8_TLPX 0x0807
+#define SMIAPP_REG_U8_DPHY_CTRL 0x0808
+#define SMIAPP_REG_U32_REQUESTED_LINK_BIT_RATE_MBPS (0x0820 | CCS_FL_32BIT)
+#define SMIAPP_REG_U8_BINNING_MODE 0x0900
+#define SMIAPP_REG_U8_BINNING_TYPE 0x0901
+#define SMIAPP_REG_U8_BINNING_WEIGHTING 0x0902
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_CTRL 0x0a00
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_STATUS 0x0a01
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_PAGE_SELECT 0x0a02
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_0 0x0a04
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_1 0x0a05
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_2 0x0a06
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_3 0x0a07
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_4 0x0a08
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_5 0x0a09
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_12 0x0a10
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_13 0x0a11
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_14 0x0a12
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_15 0x0a13
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_16 0x0a14
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_17 0x0a15
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_18 0x0a16
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_19 0x0a17
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_20 0x0a18
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_21 0x0a19
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_22 0x0a1a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_23 0x0a1b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_24 0x0a1c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_25 0x0a1d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_26 0x0a1e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_27 0x0a1f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_28 0x0a20
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_29 0x0a21
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_30 0x0a22
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_31 0x0a23
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_32 0x0a24
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_33 0x0a25
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_34 0x0a26
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_35 0x0a27
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_36 0x0a28
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_37 0x0a29
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_38 0x0a2a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_39 0x0a2b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_40 0x0a2c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_41 0x0a2d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_42 0x0a2e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_43 0x0a2f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_44 0x0a30
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_45 0x0a31
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_46 0x0a32
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_47 0x0a33
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_48 0x0a34
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_49 0x0a35
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_50 0x0a36
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_51 0x0a37
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_52 0x0a38
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_53 0x0a39
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_54 0x0a3a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_55 0x0a3b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_56 0x0a3c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_57 0x0a3d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_58 0x0a3e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_59 0x0a3f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_60 0x0a40
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_61 0x0a41
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_62 0x0a42
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_1_DATA_63 0x0a43
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_CTRL 0x0a44
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_STATUS 0x0a45
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_PAGE_SELECT 0x0a46
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_0 0x0a48
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_1 0x0a49
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_2 0x0a4a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_3 0x0a4b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_4 0x0a4c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_5 0x0a4d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_6 0x0a4e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_7 0x0a4f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_8 0x0a50
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_9 0x0a51
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_10 0x0a52
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_11 0x0a53
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_12 0x0a54
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_13 0x0a55
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_14 0x0a56
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_15 0x0a57
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_16 0x0a58
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_17 0x0a59
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_18 0x0a5a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_19 0x0a5b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_20 0x0a5c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_21 0x0a5d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_22 0x0a5e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_23 0x0a5f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_24 0x0a60
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_25 0x0a61
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_26 0x0a62
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_27 0x0a63
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_28 0x0a64
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_29 0x0a65
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_30 0x0a66
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_31 0x0a67
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_32 0x0a68
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_33 0x0a69
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_34 0x0a6a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_35 0x0a6b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_36 0x0a6c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_37 0x0a6d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_38 0x0a6e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_39 0x0a6f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_40 0x0a70
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_41 0x0a71
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_42 0x0a72
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_43 0x0a73
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_44 0x0a74
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_45 0x0a75
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_46 0x0a76
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_47 0x0a77
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_48 0x0a78
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_49 0x0a79
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_50 0x0a7a
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_51 0x0a7b
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_52 0x0a7c
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_53 0x0a7d
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_54 0x0a7e
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_55 0x0a7f
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_56 0x0a80
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_57 0x0a81
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_58 0x0a82
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_59 0x0a83
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_60 0x0a84
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_61 0x0a85
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_62 0x0a86
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_2_DATA_63 0x0a87
+#define SMIAPP_REG_U8_SHADING_CORRECTION_ENABLE 0x0b00
+#define SMIAPP_REG_U8_LUMINANCE_CORRECTION_LEVEL 0x0b01
+#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_ENABLE 0x0b02
+#define SMIAPP_REG_U8_GREEN_IMBALANCE_FILTER_WEIGHT 0x0b03
+#define SMIAPP_REG_U8_BLACK_LEVEL_CORRECTION_ENABLE 0x0b04
+#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ENABLE 0x0b05
+#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_ENABLE 0x0b06
+#define SMIAPP_REG_U8_SINGLE_DEFECT_CORRECT_WEIGHT 0x0b07
+#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_ENABLE 0x0b08
+#define SMIAPP_REG_U8_DYNAMIC_COUPLET_CORRECT_WEIGHT 0x0b09
+#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_ENABLE 0x0b0a
+#define SMIAPP_REG_U8_COMBINED_DEFECT_CORRECT_WEIGHT 0x0b0b
+#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_ENABLE 0x0b0c
+#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_WEIGHT 0x0b0d
+#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ENABLE 0x0b0e
+#define SMIAPP_REG_U8_MAPPED_LINE_DEFECT_CORRECT_ADJUST 0x0b0f
+#define SMIAPP_REG_U8_MAPPED_COUPLET_CORRECT_ADJUST 0x0b10
+#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ENABLE 0x0b11
+#define SMIAPP_REG_U8_MAPPED_TRIPLET_DEFECT_CORRECT_ADJUST 0x0b12
+#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ENABLE 0x0b13
+#define SMIAPP_REG_U8_DYNAMIC_TRIPLET_DEFECT_CORRECT_ADJUST 0x0b14
+#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ENABLE 0x0b15
+#define SMIAPP_REG_U8_DYNAMIC_LINE_DEFECT_CORRECT_ADJUST 0x0b16
+#define SMIAPP_REG_U8_EDOF_MODE 0x0b80
+#define SMIAPP_REG_U8_SHARPNESS 0x0b83
+#define SMIAPP_REG_U8_DENOISING 0x0b84
+#define SMIAPP_REG_U8_MODULE_SPECIFIC 0x0b85
+#define SMIAPP_REG_U16_DEPTH_OF_FIELD (0x0b86 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_DISTANCE (0x0b88 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_ESTIMATION_MODE_CTRL 0x0b8a
+#define SMIAPP_REG_U16_COLOUR_TEMPERATURE (0x0b8c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENR (0x0b8e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_RED (0x0b90 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_BLUE (0x0b92 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_ABSOLUTE_GAIN_GREENB (0x0b94 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_ESTIMATION_ZONE_MODE 0x0bc0
+#define SMIAPP_REG_U16_FIXED_ZONE_WEIGHTING (0x0bc2 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_X_START (0x0bc4 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_Y_START (0x0bc6 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_WIDTH (0x0bc8 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CUSTOM_ZONE_HEIGHT (0x0bca | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL1 0x0c00
+#define SMIAPP_REG_U8_GLOBAL_RESET_CTRL2 0x0c01
+#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_1 0x0c02
+#define SMIAPP_REG_U8_GLOBAL_RESET_MODE_CONFIG_2 0x0c03
+#define SMIAPP_REG_U16_TRDY_CTRL (0x0c04 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TRDOUT_CTRL (0x0c06 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSHUTTER_STROBE_DELAY_CTRL (0x0c08 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSHUTTER_STROBE_WIDTH_CTRL (0x0c0a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_CTRL (0x0c0c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_CTRL (0x0c0e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TGRST_INTERVAL_CTRL (0x0c10 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FLASH_STROBE_ADJUSTMENT 0x0c12
+#define SMIAPP_REG_U16_FLASH_STROBE_START_POINT (0x0c14 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_DELAY_RS_CTRL (0x0c16 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_HIGH_RS_CTRL (0x0c18 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FLASH_MODE_RS 0x0c1a
+#define SMIAPP_REG_U8_FLASH_TRIGGER_RS 0x0c1b
+#define SMIAPP_REG_U8_FLASH_STATUS 0x0c1c
+#define SMIAPP_REG_U8_SA_STROBE_MODE 0x0c1d
+#define SMIAPP_REG_U16_SA_STROBE_START_POINT (0x0c1e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSA_STROBE_DELAY_CTRL (0x0c20 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TSA_STROBE_WIDTH_CTRL (0x0c22 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_SA_STROBE_TRIGGER 0x0c24
+#define SMIAPP_REG_U8_SPECIAL_ACTUATOR_STATUS 0x0c25
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_RS_CTRL (0x0c26 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_RS_CTRL (0x0c28 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_RS_CTRL 0x0c2a
+#define SMIAPP_REG_U8_TFLASH_STROBE_COUNT_CTRL 0x0c2b
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH2_HIGH_CTRL (0x0c2c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_TFLASH_STROBE_WIDTH_LOW_CTRL (0x0c2e | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_LOW_LEVEL_CTRL 0x0c80
+#define SMIAPP_REG_U16_MAIN_TRIGGER_REF_POINT (0x0c82 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAIN_TRIGGER_T3 (0x0c84 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_MAIN_TRIGGER_COUNT 0x0c86
+#define SMIAPP_REG_U16_PHASE1_TRIGGER_T3 (0x0c88 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_PHASE1_TRIGGER_COUNT 0x0c8a
+#define SMIAPP_REG_U16_PHASE2_TRIGGER_T3 (0x0c8c | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_PHASE2_TRIGGER_COUNT 0x0c8e
+#define SMIAPP_REG_U8_MECH_SHUTTER_CTRL 0x0d00
+#define SMIAPP_REG_U8_OPERATION_MODE 0x0d01
+#define SMIAPP_REG_U8_ACT_STATE1 0x0d02
+#define SMIAPP_REG_U8_ACT_STATE2 0x0d03
+#define SMIAPP_REG_U16_FOCUS_CHANGE (0x0d80 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_CHANGE_CONTROL (0x0d82 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE1 (0x0d84 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FOCUS_CHANGE_NUMBER_PHASE2 (0x0d86 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_STROBE_COUNT_PHASE1 0x0d88
+#define SMIAPP_REG_U8_STROBE_COUNT_PHASE2 0x0d89
+#define SMIAPP_REG_U8_POSITION 0x0d8a
+#define SMIAPP_REG_U8_BRACKETING_LUT_CONTROL 0x0e00
+#define SMIAPP_REG_U8_BRACKETING_LUT_MODE 0x0e01
+#define SMIAPP_REG_U8_BRACKETING_LUT_ENTRY_CONTROL 0x0e02
+#define SMIAPP_REG_U8_LUT_PARAMETERS_START 0x0e10
+#define SMIAPP_REG_U8_LUT_PARAMETERS_END 0x0eff
+#define SMIAPP_REG_U16_INTEGRATION_TIME_CAPABILITY (0x1000 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MIN (0x1004 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_COARSE_INTEGRATION_TIME_MAX_MARGIN (0x1006 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN (0x1008 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN (0x100a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_CAPABILITY (0x1080 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_MIN (0x1084 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_MAX (0x1086 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DIGITAL_GAIN_STEP_SIZE (0x1088 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_EXT_CLK_FREQ_HZ (0x1100 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_EXT_CLK_FREQ_HZ (0x1104 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_PRE_PLL_CLK_DIV (0x1108 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_PRE_PLL_CLK_DIV (0x110a | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_PLL_IP_FREQ_HZ (0x110c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_PLL_IP_FREQ_HZ (0x1110 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_PLL_MULTIPLIER (0x1114 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_PLL_MULTIPLIER (0x1116 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_PLL_OP_FREQ_HZ (0x1118 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_PLL_OP_FREQ_HZ (0x111c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_VT_SYS_CLK_DIV (0x1120 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_VT_SYS_CLK_DIV (0x1122 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_VT_SYS_CLK_FREQ_HZ (0x1124 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_VT_SYS_CLK_FREQ_HZ (0x1128 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MIN_VT_PIX_CLK_FREQ_HZ (0x112c | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_VT_PIX_CLK_FREQ_HZ (0x1130 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_VT_PIX_CLK_DIV (0x1134 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_VT_PIX_CLK_DIV (0x1136 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES (0x1140 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES (0x1142 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK (0x1144 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK (0x1146 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK (0x1148 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_FRAME_BLANKING_LINES (0x114a | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_MIN_LINE_LENGTH_PCK_STEP_SIZE 0x114c
+#define SMIAPP_REG_U16_MIN_OP_SYS_CLK_DIV (0x1160 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_OP_SYS_CLK_DIV (0x1162 | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_OP_SYS_CLK_FREQ_HZ (0x1164 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_OP_SYS_CLK_FREQ_HZ (0x1168 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_MIN_OP_PIX_CLK_DIV (0x116c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_OP_PIX_CLK_DIV (0x116e | CCS_FL_16BIT)
+#define SMIAPP_REG_F32_MIN_OP_PIX_CLK_FREQ_HZ (0x1170 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_F32_MAX_OP_PIX_CLK_FREQ_HZ (0x1174 | CCS_FL_FLOAT_IREAL | CCS_FL_32BIT)
+#define SMIAPP_REG_U16_X_ADDR_MIN (0x1180 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_MIN (0x1182 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_X_ADDR_MAX (0x1184 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_Y_ADDR_MAX (0x1186 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_X_OUTPUT_SIZE (0x1188 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_Y_OUTPUT_SIZE (0x118a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_X_OUTPUT_SIZE (0x118c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_Y_OUTPUT_SIZE (0x118e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_EVEN_INC (0x11c0 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_EVEN_INC (0x11c2 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_ODD_INC (0x11c4 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_ODD_INC (0x11c6 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALING_CAPABILITY (0x1200 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_M_MIN (0x1204 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_M_MAX (0x1206 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_N_MIN (0x1208 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SCALER_N_MAX (0x120a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_SPATIAL_SAMPLING_CAPABILITY (0x120c | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_DIGITAL_CROP_CAPABILITY 0x120e
+#define SMIAPP_REG_U16_COMPRESSION_CAPABILITY (0x1300 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINRED (0x1400 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINRED (0x1402 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINRED (0x1404 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINGREEN (0x1406 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINGREEN (0x1408 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINGREEN (0x140a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_REDINBLUE (0x140c | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_GREENINBLUE (0x140e | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MATRIX_ELEMENT_BLUEINBLUE (0x1410 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FIFO_SIZE_PIXELS (0x1500 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FIFO_SUPPORT_CAPABILITY 0x1502
+#define SMIAPP_REG_U8_DPHY_CTRL_CAPABILITY 0x1600
+#define SMIAPP_REG_U8_CSI_LANE_MODE_CAPABILITY 0x1601
+#define SMIAPP_REG_U8_CSI_SIGNALLING_MODE_CAPABILITY 0x1602
+#define SMIAPP_REG_U8_FAST_STANDBY_CAPABILITY 0x1603
+#define SMIAPP_REG_U8_CCI_ADDRESS_CONTROL_CAPABILITY 0x1604
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_1_LANE_MODE_MBPS (0x1608 | CCS_FL_32BIT)
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_2_LANE_MODE_MBPS (0x160c | CCS_FL_32BIT)
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_3_LANE_MODE_MBPS (0x1610 | CCS_FL_32BIT)
+#define SMIAPP_REG_U32_MAX_PER_LANE_BITRATE_4_LANE_MODE_MBPS (0x1614 | CCS_FL_32BIT)
+#define SMIAPP_REG_U8_TEMP_SENSOR_CAPABILITY 0x1618
+#define SMIAPP_REG_U16_MIN_FRAME_LENGTH_LINES_BIN (0x1700 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_FRAME_LENGTH_LINES_BIN (0x1702 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_LENGTH_PCK_BIN (0x1704 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MAX_LINE_LENGTH_PCK_BIN (0x1706 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_MIN_LINE_BLANKING_PCK_BIN (0x1708 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MIN_BIN (0x170a | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_FINE_INTEGRATION_TIME_MAX_MARGIN_BIN (0x170c | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_BINNING_CAPABILITY 0x1710
+#define SMIAPP_REG_U8_BINNING_WEIGHTING_CAPABILITY 0x1711
+#define SMIAPP_REG_U8_BINNING_SUBTYPES 0x1712
+#define SMIAPP_REG_U8_BINNING_TYPE_n(n) (0x1713 + (n)) /* 1 <= n <= 237 */
+#define SMIAPP_REG_U8_DATA_TRANSFER_IF_CAPABILITY 0x1800
+#define SMIAPP_REG_U8_SHADING_CORRECTION_CAPABILITY 0x1900
+#define SMIAPP_REG_U8_GREEN_IMBALANCE_CAPABILITY 0x1901
+#define SMIAPP_REG_U8_BLACK_LEVEL_CAPABILITY 0x1902
+#define SMIAPP_REG_U8_MODULE_SPECIFIC_CORRECTION_CAPABILITY 0x1903
+#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY (0x1904 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_DEFECT_CORRECTION_CAPABILITY_2 (0x1906 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_EDOF_CAPABILITY 0x1980
+#define SMIAPP_REG_U8_ESTIMATION_FRAMES 0x1981
+#define SMIAPP_REG_U8_SUPPORTS_SHARPNESS_ADJ 0x1982
+#define SMIAPP_REG_U8_SUPPORTS_DENOISING_ADJ 0x1983
+#define SMIAPP_REG_U8_SUPPORTS_MODULE_SPECIFIC_ADJ 0x1984
+#define SMIAPP_REG_U8_SUPPORTS_DEPTH_OF_FIELD_ADJ 0x1985
+#define SMIAPP_REG_U8_SUPPORTS_FOCUS_DISTANCE_ADJ 0x1986
+#define SMIAPP_REG_U8_COLOUR_FEEDBACK_CAPABILITY 0x1987
+#define SMIAPP_REG_U8_EDOF_SUPPORT_AB_NXM 0x1988
+#define SMIAPP_REG_U8_ESTIMATION_MODE_CAPABILITY 0x19c0
+#define SMIAPP_REG_U8_ESTIMATION_ZONE_CAPABILITY 0x19c1
+#define SMIAPP_REG_U16_EST_DEPTH_OF_FIELD (0x19c2 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_EST_FOCUS_DISTANCE (0x19c4 | CCS_FL_16BIT)
+#define SMIAPP_REG_U16_CAPABILITY_TRDY_MIN (0x1a00 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_FLASH_MODE_CAPABILITY 0x1a02
+#define SMIAPP_REG_U16_MECH_SHUT_AND_ACT_START_ADDR (0x1b02 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_ACTUATOR_CAPABILITY 0x1b04
+#define SMIAPP_REG_U16_ACTUATOR_TYPE (0x1b40 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_AF_DEVICE_ADDRESS 0x1b42
+#define SMIAPP_REG_U16_FOCUS_CHANGE_ADDRESS (0x1b44 | CCS_FL_16BIT)
+#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_1 0x1c00
+#define SMIAPP_REG_U8_BRACKETING_LUT_CAPABILITY_2 0x1c01
+#define SMIAPP_REG_U8_BRACKETING_LUT_SIZE 0x1c02
+
+/* Register bit definitions */
+#define SMIAPP_IMAGE_ORIENTATION_HFLIP BIT(0)
+#define SMIAPP_IMAGE_ORIENTATION_VFLIP BIT(1)
+
+#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_EN BIT(0)
+#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_WR_EN BIT(1)
+#define SMIAPP_DATA_TRANSFER_IF_1_CTRL_ERR_CLEAR BIT(2)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_RD_READY BIT(0)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_WR_READY BIT(1)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EDATA BIT(2)
+#define SMIAPP_DATA_TRANSFER_IF_1_STATUS_EUSAGE BIT(3)
+
+#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_SUPPORTED BIT(0)
+#define SMIAPP_DATA_TRANSFER_IF_CAPABILITY_POLL BIT(2)
+
+#define SMIAPP_SOFTWARE_RESET BIT(0)
+
+#define SMIAPP_FLASH_MODE_CAPABILITY_SINGLE_STROBE BIT(0)
+#define SMIAPP_FLASH_MODE_CAPABILITY_MULTIPLE_STROBE BIT(1)
+
+#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_CLOCK 0
+#define SMIAPP_CSI_SIGNALLING_MODE_CCP2_DATA_STROBE 1
+#define SMIAPP_CSI_SIGNALLING_MODE_CSI2 2
+
+#define SMIAPP_DPHY_CTRL_AUTOMATIC 0
+/* DPHY control based on REQUESTED_LINK_BIT_RATE_MBPS */
+#define SMIAPP_DPHY_CTRL_UI 1
+#define SMIAPP_DPHY_CTRL_REGISTER 2
+
+#define SMIAPP_COMPRESSION_MODE_SIMPLE_PREDICTOR 1
+#define SMIAPP_COMPRESSION_MODE_ADVANCED_PREDICTOR 2
+
+#define SMIAPP_MODE_SELECT_SOFTWARE_STANDBY 0
+#define SMIAPP_MODE_SELECT_STREAMING 1
+
+#define SMIAPP_SCALING_MODE_NONE 0
+#define SMIAPP_SCALING_MODE_HORIZONTAL 1
+#define SMIAPP_SCALING_MODE_BOTH 2
+
+#define SMIAPP_SCALING_CAPABILITY_NONE 0
+#define SMIAPP_SCALING_CAPABILITY_HORIZONTAL 1
+#define SMIAPP_SCALING_CAPABILITY_BOTH 2 /* horizontal/both */
+
+/* digital crop right before scaler */
+#define SMIAPP_DIGITAL_CROP_CAPABILITY_NONE 0
+#define SMIAPP_DIGITAL_CROP_CAPABILITY_INPUT_CROP 1
+
+#define SMIAPP_DIGITAL_GAIN_CAPABILITY_PER_CHANNEL 1
+
+#define SMIAPP_BINNING_CAPABILITY_NO 0
+#define SMIAPP_BINNING_CAPABILITY_YES 1
+
+/* Maximum number of binning subtypes */
+#define SMIAPP_BINNING_SUBTYPES 253
+
+#define SMIAPP_PIXEL_ORDER_GRBG 0
+#define SMIAPP_PIXEL_ORDER_RGGB 1
+#define SMIAPP_PIXEL_ORDER_BGGR 2
+#define SMIAPP_PIXEL_ORDER_GBRG 3
+
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL 1
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED 2
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_NORMAL_N 8
+#define SMIAPP_DATA_FORMAT_MODEL_TYPE_EXTENDED_N 16
+
+#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_2BYTE 0x01
+#define SMIAPP_FRAME_FORMAT_MODEL_TYPE_4BYTE 0x02
+#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NROWS_MASK 0x0f
+#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_MASK 0xf0
+#define SMIAPP_FRAME_FORMAT_MODEL_SUBTYPE_NCOLS_SHIFT 4
+
+#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_MASK 0xf000
+#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELCODE_SHIFT 12
+#define SMIAPP_FRAME_FORMAT_DESC_2_PIXELS_MASK 0x0fff
+
+#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_MASK 0xf0000000
+#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELCODE_SHIFT 28
+#define SMIAPP_FRAME_FORMAT_DESC_4_PIXELS_MASK 0x0000ffff
+
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_EMBEDDED 1
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DUMMY 2
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_BLACK 3
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_DARK 4
+#define SMIAPP_FRAME_FORMAT_DESC_PIXELCODE_VISIBLE 5
+
+#define SMIAPP_FAST_STANDBY_CTRL_COMPLETE_FRAMES 0
+#define SMIAPP_FAST_STANDBY_CTRL_IMMEDIATE 1
+
+/* Scaling N factor */
+#define SMIAPP_SCALE_N 16
+
+#endif /* __SMIAPP_REG_DEFS_H__ */
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-25 18:05:54 +0000