1 files changed, 91 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
new file mode 100644
index 000000000..21fe5fe22
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
@@ -0,0 +1,91 @@
+[
+    {
+        "BriefDescription": "BACLEARS asserted.",
+        "Counter": "0,1",
+        "EventCode": "0xE6",
+        "EventName": "BACLEARS.ANY",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Cycles during which instruction fetches are  stalled.",
+        "Counter": "0,1",
+        "EventCode": "0x86",
+        "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Decode stall due to IQ full",
+        "Counter": "0,1",
+        "EventCode": "0x87",
+        "EventName": "DECODE_STALL.IQ_FULL",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Decode stall due to PFB empty",
+        "Counter": "0,1",
+        "EventCode": "0x87",
+        "EventName": "DECODE_STALL.PFB_EMPTY",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Instruction fetches.",
+        "Counter": "0,1",
+        "EventCode": "0x80",
+        "EventName": "ICACHE.ACCESSES",
+        "SampleAfterValue": "200000",
+        "UMask": "0x3"
+    },
+    {
+        "BriefDescription": "Icache hit",
+        "Counter": "0,1",
+        "EventCode": "0x80",
+        "EventName": "ICACHE.HIT",
+        "SampleAfterValue": "200000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Icache miss",
+        "Counter": "0,1",
+        "EventCode": "0x80",
+        "EventName": "ICACHE.MISSES",
+        "SampleAfterValue": "200000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "All Instructions decoded",
+        "Counter": "0,1",
+        "EventCode": "0xAA",
+        "EventName": "MACRO_INSTS.ALL_DECODED",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x3"
+    },
+    {
+        "BriefDescription": "CISC macro instructions decoded",
+        "Counter": "0,1",
+        "EventCode": "0xAA",
+        "EventName": "MACRO_INSTS.CISC_DECODED",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Non-CISC nacro instructions decoded",
+        "Counter": "0,1",
+        "EventCode": "0xAA",
+        "EventName": "MACRO_INSTS.NON_CISC_DECODED",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
+        "Counter": "0,1",
+        "CounterMask": "1",
+        "EventCode": "0xA9",
+        "EventName": "UOPS.MS_CYCLES",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    }
+]