From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- arch/arm/mach-aspeed/Kconfig | 46 +++++++++++++++++++++++++++++++ arch/arm/mach-aspeed/Makefile | 5 ++++ arch/arm/mach-aspeed/platsmp.c | 61 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 112 insertions(+) create mode 100644 arch/arm/mach-aspeed/Kconfig create mode 100644 arch/arm/mach-aspeed/Makefile create mode 100644 arch/arm/mach-aspeed/platsmp.c (limited to 'arch/arm/mach-aspeed') diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig new file mode 100644 index 000000000..080019aa6 --- /dev/null +++ b/arch/arm/mach-aspeed/Kconfig @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only +menuconfig ARCH_ASPEED + bool "Aspeed BMC architectures" + depends on (CPU_LITTLE_ENDIAN && ARCH_MULTI_V5) || ARCH_MULTI_V6 || ARCH_MULTI_V7 + select SRAM + select WATCHDOG + select ASPEED_WATCHDOG + select MFD_SYSCON + select PINCTRL + help + Say Y here if you want to run your kernel on an ASpeed BMC SoC. + +if ARCH_ASPEED + +config MACH_ASPEED_G4 + bool "Aspeed SoC 4th Generation" + depends on ARCH_MULTI_V5 + select CPU_ARM926T + select PINCTRL_ASPEED_G4 + select FTTMR010_TIMER + help + Say yes if you intend to run on an Aspeed ast2400 or similar + fourth generation BMCs, such as those used by OpenPower Power8 + systems. + +config MACH_ASPEED_G5 + bool "Aspeed SoC 5th Generation" + depends on ARCH_MULTI_V6 + select PINCTRL_ASPEED_G5 + select FTTMR010_TIMER + help + Say yes if you intend to run on an Aspeed ast2500 or similar + fifth generation Aspeed BMCs. + +config MACH_ASPEED_G6 + bool "Aspeed SoC 6th Generation" + depends on ARCH_MULTI_V7 + select CPU_V7 + select PINCTRL_ASPEED_G6 + select ARM_GIC + select HAVE_ARM_ARCH_TIMER + help + Say yes if you intend to run on an Aspeed ast2600 or similar + sixth generation Aspeed BMCs. + +endif diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile new file mode 100644 index 000000000..1951b3317 --- /dev/null +++ b/arch/arm/mach-aspeed/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# Copyright (C) ASPEED Technology Inc. +# Copyright IBM Corp. + +obj-$(CONFIG_SMP) += platsmp.o diff --git a/arch/arm/mach-aspeed/platsmp.c b/arch/arm/mach-aspeed/platsmp.c new file mode 100644 index 000000000..2324becf7 --- /dev/null +++ b/arch/arm/mach-aspeed/platsmp.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (C) ASPEED Technology Inc. +// Copyright IBM Corp. + +#include +#include +#include +#include + +#define BOOT_ADDR 0x00 +#define BOOT_SIG 0x04 + +static struct device_node *secboot_node; + +static int aspeed_g6_boot_secondary(unsigned int cpu, struct task_struct *idle) +{ + void __iomem *base; + + base = of_iomap(secboot_node, 0); + if (!base) { + pr_err("could not map the secondary boot base!"); + return -ENODEV; + } + + writel_relaxed(0, base + BOOT_ADDR); + writel_relaxed(__pa_symbol(secondary_startup_arm), base + BOOT_ADDR); + writel_relaxed((0xABBAAB00 | (cpu & 0xff)), base + BOOT_SIG); + + dsb_sev(); + + iounmap(base); + + return 0; +} + +static void __init aspeed_g6_smp_prepare_cpus(unsigned int max_cpus) +{ + void __iomem *base; + + secboot_node = of_find_compatible_node(NULL, NULL, "aspeed,ast2600-smpmem"); + if (!secboot_node) { + pr_err("secboot device node found!!\n"); + return; + } + + base = of_iomap(secboot_node, 0); + if (!base) { + pr_err("could not map the secondary boot base!"); + return; + } + __raw_writel(0xBADABABA, base + BOOT_SIG); + + iounmap(base); +} + +static const struct smp_operations aspeed_smp_ops __initconst = { + .smp_prepare_cpus = aspeed_g6_smp_prepare_cpus, + .smp_boot_secondary = aspeed_g6_boot_secondary, +}; + +CPU_METHOD_OF_DECLARE(aspeed_smp, "aspeed,ast2600-smp", &aspeed_smp_ops); -- cgit v1.2.3