From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- arch/arm/mach-shmobile/headsmp-scu.S | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 arch/arm/mach-shmobile/headsmp-scu.S (limited to 'arch/arm/mach-shmobile/headsmp-scu.S') diff --git a/arch/arm/mach-shmobile/headsmp-scu.S b/arch/arm/mach-shmobile/headsmp-scu.S new file mode 100644 index 000000000..d0234296a --- /dev/null +++ b/arch/arm/mach-shmobile/headsmp-scu.S @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Shared SCU setup for mach-shmobile + * + * Copyright (C) 2012 Bastian Hecht + */ + +#include +#include +#include + +/* + * Boot code for secondary CPUs. + * + * First we turn on L1 cache coherency for our CPU. Then we jump to + * secondary_startup that invalidates the cache and hands over control + * to the common ARM startup code. + */ +ENTRY(shmobile_boot_scu) + @ r0 = SCU base address + mrc p15, 0, r1, c0, c0, 5 @ read MPIDR + and r1, r1, #3 @ mask out cpu ID + lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits + ldr r2, [r0, #8] @ SCU Power Status Register + mov r3, #3 + lsl r3, r3, r1 + bic r2, r2, r3 @ Clear bits of our CPU (Run Mode) + str r2, [r0, #8] @ write back + + b secondary_startup +ENDPROC(shmobile_boot_scu) -- cgit v1.2.3