From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 283 ++++++++++++++++++++++ 1 file changed, 283 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi (limited to 'arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi') diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi new file mode 100644 index 000000000..5ff66aa6f --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/G2LC SMARC SOM common parts + * + * Copyright (C) 2021 Renesas Electronics Corp. + */ + +#include +#include + +/ { + aliases { + ethernet0 = ð0; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_1p1v: regulator-vdd-core { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <3300000 1>, <1800000 0>; + regulator-boot-on; + gpios = <&pinctrl RZG2L_GPIO(39, 0) GPIO_ACTIVE_HIGH>; + regulator-always-on; + }; +}; + +ð0 { + pinctrl-0 = <ð0_pins>; + pinctrl-names = "default"; + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; + + phy0: ethernet-phy@7 { + compatible = "ethernet-phy-id0022.1640", + "ethernet-phy-ieee802.3-c22"; + reg = <7>; + rxc-skew-psec = <2400>; + txc-skew-psec = <2400>; + rxdv-skew-psec = <0>; + txen-skew-psec = <0>; + rxd0-skew-psec = <0>; + rxd1-skew-psec = <0>; + rxd2-skew-psec = <0>; + rxd3-skew-psec = <0>; + txd0-skew-psec = <0>; + txd1-skew-psec = <0>; + txd2-skew-psec = <0>; + txd3-skew-psec = <0>; + }; +}; + +&extal_clk { + clock-frequency = <24000000>; +}; + +&gpu { + mali-supply = <®_1p1v>; +}; + +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + +&pinctrl { + eth0_pins: eth0 { + pinmux = , /* ET0_LINKSTA */ + , /* ET0_MDC */ + , /* ET0_MDIO */ + , /* ET0_TXC */ + , /* ET0_TX_CTL */ + , /* ET0_TXD0 */ + , /* ET0_TXD1 */ + , /* ET0_TXD2 */ + , /* ET0_TXD3 */ + , /* ET0_RXC */ + , /* ET0_RX_CTL */ + , /* ET0_RXD0 */ + , /* ET0_RXD1 */ + , /* ET0_RXD2 */ + ; /* ET0_RXD3 */ + }; + + gpio-sd0-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "gpio_sd0_pwr_en"; + }; + + qspi0_pins: qspi0 { + qspi0-data { + pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3"; + power-source = <1800>; + }; + + qspi0-ctrl { + pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#"; + power-source = <1800>; + }; + }; + + /* + * SD0 device selection is XOR between GPIO_SD0_DEV_SEL and SW1[2] + * The below switch logic can be used to select the device between + * eMMC and microSD, after setting GPIO_SD0_DEV_SEL to high in DT. + * SW1[2] should be at OFF position to enable 64 GB eMMC + * SW1[2] should be at position ON to enable uSD card CN3 + */ + gpio-sd0-dev-sel-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "gpio_sd0_dev_sel"; + }; + + sdhi0_emmc_pins: sd0emmc { + sd0_emmc_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3", + "SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7"; + power-source = <1800>; + }; + + sd0_emmc_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_emmc_rst { + pins = "SD0_RST#"; + power-source = <1800>; + }; + }; + + sdhi0_pins: sd0 { + sd0_data { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <3300>; + }; + + sd0_ctrl { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <3300>; + }; + + sd0_mux { + pinmux = ; /* SD0_CD */ + }; + }; + + sdhi0_pins_uhs: sd0_uhs { + sd0_data_uhs { + pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3"; + power-source = <1800>; + }; + + sd0_ctrl_uhs { + pins = "SD0_CLK", "SD0_CMD"; + power-source = <1800>; + }; + + sd0_mux_uhs { + pinmux = ; /* SD0_CD */ + }; + }; +}; + +&sbc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + status = "okay"; + + flash@0 { + compatible = "micron,mt25qu512a", "jedec,spi-nor"; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + boot@0 { + reg = <0x00000000 0x2000000>; + read-only; + }; + user@2000000 { + reg = <0x2000000 0x2000000>; + }; + }; + }; +}; + +#if (!SW_SD0_DEV_SEL) +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; +#endif + +#if SW_SD0_DEV_SEL +&sdhi0 { + pinctrl-0 = <&sdhi0_emmc_pins>; + pinctrl-1 = <&sdhi0_emmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + mmc-hs200-1_8v; + non-removable; + fixed-emmc-driver-type = <1>; + status = "okay"; +}; +#endif + +&wdt0 { + status = "okay"; + timeout-sec = <60>; +}; + +&wdt1 { + status = "okay"; + timeout-sec = <60>; +}; + +&wdt2 { + status = "okay"; + timeout-sec = <60>; +}; -- cgit v1.2.3