From 2c3c1048746a4622d8c89a29670120dc8fab93c4 Mon Sep 17 00:00:00 2001 From: Daniel Baumann Date: Sun, 7 Apr 2024 20:49:45 +0200 Subject: Adding upstream version 6.1.76. Signed-off-by: Daniel Baumann --- drivers/pci/pci-mid.c | 56 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 drivers/pci/pci-mid.c (limited to 'drivers/pci/pci-mid.c') diff --git a/drivers/pci/pci-mid.c b/drivers/pci/pci-mid.c new file mode 100644 index 000000000..fbfd78127 --- /dev/null +++ b/drivers/pci/pci-mid.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Intel MID platform PM support + * + * Copyright (C) 2016, Intel Corporation + * + * Author: Andy Shevchenko + */ + +#include +#include + +#include +#include +#include + +#include "pci.h" + +static bool pci_mid_pm_enabled __read_mostly; + +bool pci_use_mid_pm(void) +{ + return pci_mid_pm_enabled; +} + +int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) +{ + return intel_mid_pci_set_power_state(pdev, state); +} + +pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) +{ + return intel_mid_pci_get_power_state(pdev); +} + +/* + * This table should be in sync with the one in + * arch/x86/platform/intel-mid/pwr.c. + */ +static const struct x86_cpu_id lpss_cpu_ids[] = { + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_MID, NULL), + X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, NULL), + {} +}; + +static int __init mid_pci_init(void) +{ + const struct x86_cpu_id *id; + + id = x86_match_cpu(lpss_cpu_ids); + if (id) + pci_mid_pm_enabled = true; + + return 0; +} +arch_initcall(mid_pci_init); -- cgit v1.2.3