path: root/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Google Gru-scarlet board device tree source
 *
 * Copyright 2018 Google, Inc
 */

#include "rk3399-gru.dtsi"

/{
	chassis-type = "tablet";

	/* Power tree */

	/* ppvar_sys children, sorted by name */
	pp1250_s3: pp1250-s3 {
		compatible = "regulator-fixed";
		regulator-name = "pp1250_s3";

		/* EC turns on w/ pp1250_s3_en; always on for AP */
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <1250000>;
		regulator-max-microvolt = <1250000>;

		vin-supply = <&ppvar_sys>;
	};

	pp1250_cam: pp1250-dvdd {
		compatible = "regulator-fixed";
		regulator-name = "pp1250_dvdd";
		pinctrl-names = "default";
		pinctrl-0 = <&pp1250_cam_en>;

		enable-active-high;
		gpio = <&gpio2 4 GPIO_ACTIVE_HIGH>;

		/* 740us delay from gpio output high to pp1250 stable,
		 * rounding up to 1ms for safety.
		 */
		startup-delay-us = <1000>;
		vin-supply = <&pp1250_s3>;
	};

	pp900_s0: pp900-s0 {
		compatible = "regulator-fixed";
		regulator-name = "pp900_s0";

		/* EC turns on w/ pp900_s0_en; always on for AP */
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <900000>;

		vin-supply = <&ppvar_sys>;
	};

	ppvarn_lcd: ppvarn-lcd {
		compatible = "regulator-fixed";
		regulator-name = "ppvarn_lcd";
		pinctrl-names = "default";
		pinctrl-0 = <&ppvarn_lcd_en>;

		enable-active-high;
		gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
		vin-supply = <&ppvar_sys>;
	};

	ppvarp_lcd: ppvarp-lcd {
		compatible = "regulator-fixed";
		regulator-name = "ppvarp_lcd";
		pinctrl-names = "default";
		pinctrl-0 = <&ppvarp_lcd_en>;

		enable-active-high;
		gpio = <&gpio4 27 GPIO_ACTIVE_HIGH>;
		vin-supply = <&ppvar_sys>;
	};

	/* pp1800 children, sorted by name */
	pp900_s3: pp900-s3 {
		compatible = "regulator-fixed";
		regulator-name = "pp900_s3";

		/* EC turns on w/ pp900_s3_en; always on for AP */
		regulator-always-on;
		regulator-boot-on;
		regulator-min-microvolt = <900000>;
		regulator-max-microvolt = <900000>;

		vin-supply = <&pp1800>;
	};

	/* EC turns on pp1800_s3_en */
	pp1800_s3: pp1800 {
	};

	/* pp3300 children, sorted by name */
	pp2800_cam: pp2800-avdd {
		compatible = "regulator-fixed";
		regulator-name = "pp2800_avdd";
		pinctrl-names = "default";
		pinctrl-0 = <&pp2800_cam_en>;

		enable-active-high;
		gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>;
		startup-delay-us = <100>;
		vin-supply = <&pp3300>;
	};

	/* EC turns on pp3300_s0_en */
	pp3300_s0: pp3300 {
	};

	/* EC turns on pp3300_s3_en */
	pp3300_s3: pp3300 {
	};

	/*
	 * See b/66922012
	 *
	 * This is a hack to make sure the Bluetooth part of the QCA6174A
	 * is reset at boot by toggling BT_EN. At boot BT_EN is first set
	 * to low when the bt_3v3 regulator is registered (in disabled
	 * state). The fake regulator is configured as a supply of the
	 * wlan_3v3 regulator below. When wlan_3v3 is enabled early in
	 * the boot process it also enables its supply regulator bt_3v3,
	 * which changes BT_EN to high.
	 */
	bt_3v3: bt-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "bt_3v3";
		pinctrl-names = "default";
		pinctrl-0 = <&bt_en_1v8_l>;

		enable-active-high;
		gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
		vin-supply = <&pp3300_s3>;
	};

	wlan_3v3: wlan-3v3 {
		compatible = "regulator-fixed";
		regulator-name = "wlan_3v3";
		pinctrl-names = "default";
		pinctrl-0 = <&wlan_pd_1v8_l>;

		/*
		 * The WL_EN pin is driven low when the regulator is
		 * registered, and transitions to high when the PCIe bus
		 * is powered up.
		 */
		enable-active-high;
		gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;

		/*
		 * Require minimum 10ms from power-on (e.g., PD#) to init PCIe.
		 * TODO (b/64444991): how long to assert PD#?
		 */
		regulator-enable-ramp-delay = <10000>;
		/* See bt_3v3 hack above */
		vin-supply = <&bt_3v3>;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		enable-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&bl_en>;
		pwms = <&pwm1 0 1000000 0>;
		pwm-delay-us = <10000>;
	};

	dmic: dmic {
		compatible = "dmic-codec";
		dmicen-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&dmic_en>;
		wakeup-delay-ms = <250>;
	};

	gpio_keys: gpio-keys {
		compatible = "gpio-keys";
		pinctrl-names = "default";
		pinctrl-0 = <&pen_eject_odl>;

		switch-pen-insert {
			label = "Pen Insert";
			/* Insert = low, eject = high */
			gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
			linux,code = <SW_PEN_INSERTED>;
			linux,input-type = <EV_SW>;
			wakeup-source;
		};
	};
};

/* pp900_s0 aliases */
pp900_ddrpll_ap: &pp900_s0 {
};
pp900_pcie: &pp900_s0 {
};
pp900_usb: &pp900_s0 {
};

/* pp900_s3 aliases */
pp900_emmcpll: &pp900_s3 {
};

/* EC turns on; alias for pp1800_s0 */
pp1800_pcie: &pp1800_s0 {
};

/* On scarlet PPVAR(big_cpu, lit_cpu, gpu) need to adjust voltage ranges */
&ppvar_bigcpu {
	ctrl-voltage-range = <800074 1299226>;
	regulator-min-microvolt = <800074>;
	regulator-max-microvolt = <1299226>;
};

&ppvar_bigcpu_pwm {
	/* On scarlet ppvar big cpu use pwm3 */
	pwms = <&pwm3 0 3337 0>;
	regulator-min-microvolt = <800074>;
	regulator-max-microvolt = <1299226>;
};

&ppvar_litcpu {
	ctrl-voltage-range = <802122 1199620>;
	regulator-min-microvolt = <802122>;
	regulator-max-microvolt = <1199620>;
};

&ppvar_litcpu_pwm {
	regulator-min-microvolt = <802122>;
	regulator-max-microvolt = <1199620>;
};

&ppvar_gpu {
	ctrl-voltage-range = <799600 1099600>;
	regulator-min-microvolt = <799600>;
	regulator-max-microvolt = <1099600>;
};

&ppvar_gpu_pwm {
	regulator-min-microvolt = <799600>;
	regulator-max-microvolt = <1099600>;
};

&ppvar_sd_card_io {
	states = <1800000 0x0>, <3300000 0x1>;
	regulator-max-microvolt = <3300000>;
};

&pp3000_sd_slot {
	vin-supply = <&pp3300>;
};

ap_i2c_dig: &i2c2 {
	status = "okay";

	clock-frequency = <400000>;

	/* These are relatively safe rise/fall times. */
	i2c-scl-falling-time-ns = <50>;
	i2c-scl-rising-time-ns = <300>;

	digitizer: digitizer@9 {
		compatible = "hid-over-i2c";
		reg = <0x9>;
		interrupt-parent = <&gpio1>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
		hid-descr-addr = <0x1>;
		pinctrl-names = "default";
		pinctrl-0 = <&pen_int_odl &pen_reset_l>;
	};
};

&ap_i2c_ts {
	touchscreen: touchscreen@10 {
		compatible = "elan,ekth3500";
		reg = <0x10>;
		interrupt-parent = <&gpio1>;
		interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
		pinctrl-names = "default";
		pinctrl-0 = <&touch_int_l &touch_reset_l>;
		reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
	};
};

camera: &i2c7 {
	status = "okay";

	clock-frequency = <400000>;

	/* These are relatively safe rise/fall times; TODO: measure */
	i2c-scl-falling-time-ns = <50>;
	i2c-scl-rising-time-ns = <300>;

	/* 24M mclk is shared between world and user cameras */
	pinctrl-0 = <&i2c7_xfer &test_clkout1>;

	/* Rear-facing camera */
	wcam: camera@36 {
		compatible = "ovti,ov5695";
		reg = <0x36>;
		pinctrl-names = "default";
		pinctrl-0 = <&wcam_rst>;

		clocks = <&cru SCLK_TESTCLKOUT1>;
		clock-names = "xvclk";

		avdd-supply = <&pp2800_cam>;
		dvdd-supply = <&pp1250_cam>;
		dovdd-supply = <&pp1800_s0>;
		reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;

		port {
			wcam_out: endpoint {
				remote-endpoint = <&mipi_in_wcam>;
				data-lanes = <1 2>;
			};
		};
	};

	/* Front-facing camera */
	ucam: camera@3c {
		compatible = "ovti,ov2685";
		reg = <0x3c>;
		pinctrl-names = "default";
		pinctrl-0 = <&ucam_rst>;

		clocks = <&cru SCLK_TESTCLKOUT1>;
		clock-names = "xvclk";

		avdd-supply = <&pp2800_cam>;
		dovdd-supply = <&pp1800_s0>;
		dvdd-supply = <&pp1800_s0>;
		reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;

		port {
			ucam_out: endpoint {
				remote-endpoint = <&mipi_in_ucam>;
				data-lanes = <1>;
			};
		};
	};
};

&cdn_dp {
	extcon = <&usbc_extcon0>;
	phys = <&tcphy0_dp>;
};

&cpu_alert0 {
	temperature = <66000>;
};

&cpu_alert1 {
	temperature = <71000>;
};

&cros_ec {
	interrupt-parent = <&gpio1>;
	interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
};

&cru {
	assigned-clocks =
		<&cru PLL_GPLL>, <&cru PLL_CPLL>,
		<&cru PLL_NPLL>,
		<&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
		<&cru PCLK_PERIHP>,
		<&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
		<&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
		<&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
		<&cru ACLK_VIO>,
		<&cru ACLK_GIC_PRE>,
		<&cru PCLK_DDR>,
		<&cru ACLK_HDCP>,
		<&cru ACLK_VDU>;
	assigned-clock-rates =
		<600000000>, <1600000000>,
		<1000000000>,
		<150000000>, <75000000>,
		<37500000>,
		<100000000>, <100000000>,
		<50000000>, <800000000>,
		<100000000>, <50000000>,
		<400000000>,
		<200000000>,
		<200000000>,
		<400000000>,
		<400000000>;
};

/* The center supply is fixed to .9V on scarlet */
&dmc {
	center-supply = <&pp900_s0>;
};

/* We don't need .925 V for 928 MHz on scarlet */
&dmc_opp_table {
	opp03 {
		opp-microvolt = <900000>;
	};
};

&gpio0 {
	gpio-line-names = /* GPIO0 A 0-7 */
			  "CLK_32K_AP",
			  "EC_IN_RW_OD",
			  "SPK_PA_EN",
			  "WLAN_PERST_1V8_L",
			  "WLAN_PD_1V8_L",
			  "WLAN_RF_KILL_1V8_L",
			  "BIGCPU_DVS_PWM",
			  "SD_CD_L_JTAG_EN",

			  /* GPIO0 B 0-5 */
			  "BT_EN_BT_RF_KILL_1V8_L",
			  "PMUIO2_33_18_L_PP3300_S0_EN",
			  "TOUCH_RESET_L",
			  "AP_EC_WARM_RESET_REQ",
			  "PEN_RESET_L",
			  /*
			   * AP_FLASH_WP_L is crossystem ABI. Schematics call
			   * it AP_FLASH_WP_R_ODL.
			   */
			  "AP_FLASH_WP_L";
};

&gpio1 {
	gpio-line-names = /* GPIO1 A 0-7 */
			  "PEN_INT_ODL",
			  "PEN_EJECT_ODL",
			  "BT_HOST_WAKE_1V8_L",
			  "WLAN_HOST_WAKE_1V8_L",
			  "TOUCH_INT_ODL",
			  "AP_EC_S3_S0_L",
			  "AP_EC_OVERTEMP",
			  "AP_SPI_FLASH_MISO",

			  /* GPIO1 B 0-7 */
			  "AP_SPI_FLASH_MOSI_R",
			  "AP_SPI_FLASH_CLK_R",
			  "AP_SPI_FLASH_CS_L_R",
			  "SD_CARD_DET_ODL",
			  "",
			  "AP_EXPANSION_IO1",
			  "AP_EXPANSION_IO2",
			  "AP_I2C_DISP_SDA",

			  /* GPIO1 C 0-7 */
			  "AP_I2C_DISP_SCL",
			  "H1_INT_ODL",
			  "EC_AP_INT_ODL",
			  "LITCPU_DVS_PWM",
			  "AP_I2C_AUDIO_SDA",
			  "AP_I2C_AUDIO_SCL",
			  "AP_EXPANSION_IO3",
			  "HEADSET_INT_ODL",

			  /* GPIO1 D0 */
			  "AP_EXPANSION_IO4";
};

&gpio2 {
	gpio-line-names = /* GPIO2 A 0-7 */
			  "AP_I2C_PEN_SDA",
			  "AP_I2C_PEN_SCL",
			  "SD_IO_PWR_EN",
			  "UCAM_RST_L",
			  "PP1250_CAM_EN",
			  "WCAM_RST_L",
			  "AP_EXPANSION_IO5",
			  "AP_I2C_CAM_SDA",

			  /* GPIO2 B 0-7 */
			  "AP_I2C_CAM_SCL",
			  "AP_H1_SPI_MISO",
			  "AP_H1_SPI_MOSI",
			  "AP_H1_SPI_CLK",
			  "AP_H1_SPI_CS_L",
			  "",
			  "",
			  "",

			  /* GPIO2 C 0-7 */
			  "UART_EXPANSION_TX_AP_RX",
			  "UART_AP_TX_EXPANSION_RX",
			  "UART_EXPANSION_RTS_AP_CTS",
			  "UART_AP_RTS_EXPANSION_CTS",
			  "AP_SPI_EC_MISO",
			  "AP_SPI_EC_MOSI",
			  "AP_SPI_EC_CLK",
			  "AP_SPI_EC_CS_L",

			  /* GPIO2 D 0-4 */
			  "PP2800_CAM_EN",
			  "CLK_24M_CAM",
			  "WLAN_PCIE_CLKREQ_1V8_L",
			  "",
			  "SD_PWR_3000_1800_L";
};

&gpio3 {
	gpio-line-names = /* GPIO3 A 0-7 */
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  /* GPIO3 B 0-7 */
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  /* GPIO3 C 0-7 */
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  /* GPIO3 D 0-7 */
			  "I2S0_SCLK",
			  "I2S0_LRCK_RX",
			  "I2S0_LRCK_TX",
			  "I2S0_SDI_0",
			  "STRAP_LCDBIAS_L",
			  "STRAP_FEATURE_1",
			  "STRAP_FEATURE_2",
			  "I2S0_SDO_0";
};

&gpio4 {
	gpio-line-names = /* GPIO4 A 0-7 */
			  "I2S_MCLK",
			  "AP_I2C_EXPANSION_SDA",
			  "AP_I2C_EXPANSION_SCL",
			  "DMIC_EN",
			  "",
			  "",
			  "",
			  "",

			  /* GPIO4 B 0-7 */
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",
			  "",

			  /* GPIO4 C 0-7 */
			  "AP_I2C_TS_SDA",
			  "AP_I2C_TS_SCL",
			  "GPU_DVS_PWM",
			  "UART_DBG_TX_AP_RX",
			  "UART_AP_TX_DBG_RX",
			  "BL_EN",
			  "BL_PWM",
			  "",

			  /* GPIO4 D 0-5 */
			  "",
			  "DISPLAY_RST_L",
			  "",
			  "PPVARP_LCD_EN",
			  "PPVARN_LCD_EN",
			  "SD_SLOT_PWR_EN";
};

&i2c_tunnel {
	google,remote-bus = <0>;
};

&io_domains {
	bt656-supply = <&pp1800_s0>;		/* APIO2_VDD;  2a 2b */
	audio-supply = <&pp1800_s0>;		/* APIO5_VDD;  3d 4a */
	gpio1830-supply = <&pp1800_s0>;		/* APIO4_VDD;  4c 4d */
};

&isp0 {
	status = "okay";

	ports {
		port@0 {
			mipi_in_wcam: endpoint@0 {
				reg = <0>;
				remote-endpoint = <&wcam_out>;
				data-lanes = <1 2>;
			};

			mipi_in_ucam: endpoint@1 {
				reg = <1>;
				remote-endpoint = <&ucam_out>;
				data-lanes = <1>;
			};
		};
	};
};

&isp0_mmu {
	status = "okay";
};

&max98357a {
	sdmode-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
};

&mipi_dphy_rx0 {
	status = "okay";
};

&mipi_dsi {
	status = "okay";
	clock-master;

	ports {
		mipi_out: port@1 {
			reg = <1>;

			mipi_out_panel: endpoint {
				remote-endpoint = <&mipi_in_panel>;
			};
		};
	};

	mipi_panel: panel@0 {
		/* 2 different panels are used, compatibles are in dts files */
		reg = <0>;
		backlight = <&backlight>;
		enable-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&display_rst_l>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;

				mipi_in_panel: endpoint {
					remote-endpoint = <&mipi_out_panel>;
				};
			};

			port@1 {
				reg = <1>;

				mipi1_in_panel: endpoint@1 {
					remote-endpoint = <&mipi1_out_panel>;
				};
			};
		};
	};
};

&mipi_dsi1 {
	status = "okay";

	ports {
		mipi1_out: port@1 {
			reg = <1>;

			mipi1_out_panel: endpoint {
				remote-endpoint = <&mipi1_in_panel>;
			};
		};
	};
};

&pcie0 {
	ep-gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;

	/* PERST# asserted in S3 */
	pcie-reset-suspend = <1>;

	vpcie3v3-supply = <&wlan_3v3>;
	vpcie1v8-supply = <&pp1800_pcie>;
};

&sdmmc {
	cd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
};

&sound {
	rockchip,codec = <&max98357a &dmic &codec &cdn_dp>;
};

&spi2 {
	status = "okay";

	cr50@0 {
		compatible = "google,cr50";
		reg = <0>;
		interrupt-parent = <&gpio1>;
		interrupts = <17 IRQ_TYPE_EDGE_RISING>;
		pinctrl-names = "default";
		pinctrl-0 = <&h1_int_od_l>;
		spi-max-frequency = <800000>;
	};
};

&usb_host0_ohci {
	#address-cells = <1>;
	#size-cells = <0>;

	qca_bt: bluetooth@1 {
		compatible = "usbcf3,e300", "usb4ca,301a";
		reg = <1>;
		pinctrl-names = "default";
		pinctrl-0 = <&bt_host_wake_l>;
		interrupt-parent = <&gpio1>;
		interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "wakeup";
	};
};

/* PINCTRL OVERRIDES */
&ap_fw_wp {
	rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
};

&bl_en {
	rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
};

&bt_host_wake_l {
	rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};

&ec_ap_int_l {
	rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
};

&headset_int_l {
	rockchip,pins = <1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
};

&i2s0_8ch_bus {
	rockchip,pins =
		<3 RK_PD0 1 &pcfg_pull_none_6ma>,
		<3 RK_PD1 1 &pcfg_pull_none_6ma>,
		<3 RK_PD2 1 &pcfg_pull_none_6ma>,
		<3 RK_PD3 1 &pcfg_pull_none_6ma>,
		<3 RK_PD7 1 &pcfg_pull_none_6ma>,
		<4 RK_PA0 1 &pcfg_pull_none_6ma>;
};

&i2s0_8ch_bus_bclk_off {
	rockchip,pins =
		<3 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none_6ma>,
		<3 RK_PD1 1 &pcfg_pull_none_6ma>,
		<3 RK_PD2 1 &pcfg_pull_none_6ma>,
		<3 RK_PD3 1 &pcfg_pull_none_6ma>,
		<3 RK_PD7 1 &pcfg_pull_none_6ma>,
		<4 RK_PA0 1 &pcfg_pull_none_6ma>;
};

/* there is no external pull up, so need to set this pin pull up */
&sdmmc_cd_pin {
	rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
};

&sd_pwr_1800_sel {
	rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
};

&sdmode_en {
	rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_down>;
};

&touch_reset_l {
	rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
};

&touch_int_l {
	rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
};

&pinctrl {
	pinctrl-0 = <
		&ap_pwroff	/* AP will auto-assert this when in S3 */
		&clk_32k	/* This pin is always 32k on gru boards */
		&wlan_rf_kill_1v8_l
	>;

	pcfg_pull_none_6ma: pcfg-pull-none-6ma {
		bias-disable;
		drive-strength = <6>;
	};

	camera {
		pp1250_cam_en: pp1250-dvdd {
			rockchip,pins = <2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		pp2800_cam_en: pp2800-avdd {
			rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		ucam_rst: ucam_rst {
			rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		wcam_rst: wcam_rst {
			rockchip,pins = <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	digitizer {
		pen_int_odl: pen-int-odl {
			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
		};

		pen_reset_l: pen-reset-l {
			rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	discrete-regulators {
		display_rst_l: display-rst-l {
			rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_down>;
		};

		ppvarp_lcd_en: ppvarp-lcd-en {
			rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
		};

		ppvarn_lcd_en: ppvarn-lcd-en {
			rockchip,pins = <4 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	dmic {
		dmic_en: dmic-en {
			rockchip,pins = <4 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
		};
	};

	pen {
		pen_eject_odl: pen-eject-odl {
			rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};

	tpm {
		h1_int_od_l: h1-int-od-l {
			rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
		};
	};
};

&wifi {
	bt_en_1v8_l: bt-en-1v8-l {
		rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	wlan_pd_1v8_l: wlan-pd-1v8-l {
		rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	/* Default pull-up, but just to be clear */
	wlan_rf_kill_1v8_l: wlan-rf-kill-1v8-l {
		rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
	};

	wifi_perst_l: wifi-perst-l {
		rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
	};

	wlan_host_wake_l: wlan-host-wake-l {
		rockchip,pins = <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
	};
};