1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
|
/*
* Copyright (c) 2017 Redpine Signals Inc.
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
#ifndef __RSI_HAL_H__
#define __RSI_HAL_H__
/* Device Operating modes */
#define DEV_OPMODE_WIFI_ALONE 1
#define DEV_OPMODE_BT_ALONE 4
#define DEV_OPMODE_BT_LE_ALONE 8
#define DEV_OPMODE_BT_DUAL 12
#define DEV_OPMODE_STA_BT 5
#define DEV_OPMODE_STA_BT_LE 9
#define DEV_OPMODE_STA_BT_DUAL 13
#define DEV_OPMODE_AP_BT 6
#define DEV_OPMODE_AP_BT_DUAL 14
#define DEV_OPMODE_PARAM_DESC \
__stringify(DEV_OPMODE_WIFI_ALONE) "[Wi-Fi alone], " \
__stringify(DEV_OPMODE_BT_ALONE) "[BT classic alone], " \
__stringify(DEV_OPMODE_BT_LE_ALONE) "[BT LE alone], " \
__stringify(DEV_OPMODE_BT_DUAL) "[BT classic + BT LE alone], " \
__stringify(DEV_OPMODE_STA_BT) "[Wi-Fi STA + BT classic], " \
__stringify(DEV_OPMODE_STA_BT_LE) "[Wi-Fi STA + BT LE], " \
__stringify(DEV_OPMODE_STA_BT_DUAL) "[Wi-Fi STA + BT classic + BT LE], " \
__stringify(DEV_OPMODE_AP_BT) "[Wi-Fi AP + BT classic], " \
__stringify(DEV_OPMODE_AP_BT_DUAL) "[Wi-Fi AP + BT classic + BT LE]"
#define FLASH_WRITE_CHUNK_SIZE (4 * 1024)
#define FLASH_SECTOR_SIZE (4 * 1024)
#define FLASH_SIZE_ADDR 0x04000016
#define PING_BUFFER_ADDRESS 0x19000
#define PONG_BUFFER_ADDRESS 0x1a000
#define SWBL_REGIN 0x41050034
#define SWBL_REGOUT 0x4105003c
#define PING_WRITE 0x1
#define PONG_WRITE 0x2
#define BL_CMD_TIMEOUT 2000
#define BL_BURN_TIMEOUT (50 * 1000)
#define REGIN_VALID 0xA
#define REGIN_INPUT 0xA0
#define REGOUT_VALID 0xAB
#define REGOUT_INVALID (~0xAB)
#define CMD_PASS 0xAA
#define CMD_FAIL 0xCC
#define LOAD_HOSTED_FW 'A'
#define BURN_HOSTED_FW 'B'
#define PING_VALID 'I'
#define PONG_VALID 'O'
#define PING_AVAIL 'I'
#define PONG_AVAIL 'O'
#define EOF_REACHED 'E'
#define CHECK_CRC 'K'
#define POLLING_MODE 'P'
#define CONFIG_AUTO_READ_MODE 'R'
#define JUMP_TO_ZERO_PC 'J'
#define FW_LOADING_SUCCESSFUL 'S'
#define LOADING_INITIATED '1'
#define RSI_ULP_RESET_REG 0x161
#define RSI_WATCH_DOG_TIMER_1 0x16c
#define RSI_WATCH_DOG_TIMER_2 0x16d
#define RSI_WATCH_DOG_DELAY_TIMER_1 0x16e
#define RSI_WATCH_DOG_DELAY_TIMER_2 0x16f
#define RSI_WATCH_DOG_TIMER_ENABLE 0x170
/* Watchdog timer addresses for 9116 */
#define NWP_AHB_BASE_ADDR 0x41300000
#define NWP_WWD_INTERRUPT_TIMER (NWP_AHB_BASE_ADDR + 0x300)
#define NWP_WWD_SYSTEM_RESET_TIMER (NWP_AHB_BASE_ADDR + 0x304)
#define NWP_WWD_WINDOW_TIMER (NWP_AHB_BASE_ADDR + 0x308)
#define NWP_WWD_TIMER_SETTINGS (NWP_AHB_BASE_ADDR + 0x30C)
#define NWP_WWD_MODE_AND_RSTART (NWP_AHB_BASE_ADDR + 0x310)
#define NWP_WWD_RESET_BYPASS (NWP_AHB_BASE_ADDR + 0x314)
#define NWP_FSM_INTR_MASK_REG (NWP_AHB_BASE_ADDR + 0x104)
/* Watchdog timer values */
#define NWP_WWD_INT_TIMER_CLKS 5
#define NWP_WWD_SYS_RESET_TIMER_CLKS 4
#define NWP_WWD_TIMER_DISABLE 0xAA0001
#define RSI_ULP_WRITE_0 00
#define RSI_ULP_WRITE_2 02
#define RSI_ULP_WRITE_50 50
#define RSI_RESTART_WDT BIT(11)
#define RSI_BYPASS_ULP_ON_WDT BIT(1)
#define RSI_ULP_TIMER_ENABLE ((0xaa000) | RSI_RESTART_WDT | \
RSI_BYPASS_ULP_ON_WDT)
#define RSI_RF_SPI_PROG_REG_BASE_ADDR 0x40080000
#define RSI_GSPI_CTRL_REG0 (RSI_RF_SPI_PROG_REG_BASE_ADDR)
#define RSI_GSPI_CTRL_REG1 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x2)
#define RSI_GSPI_DATA_REG0 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x4)
#define RSI_GSPI_DATA_REG1 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x6)
#define RSI_GSPI_DATA_REG2 (RSI_RF_SPI_PROG_REG_BASE_ADDR + 0x8)
#define RSI_GSPI_CTRL_REG0_VALUE 0x340
#define RSI_GSPI_DMA_MODE BIT(13)
#define RSI_GSPI_2_ULP BIT(12)
#define RSI_GSPI_TRIG BIT(7)
#define RSI_GSPI_READ BIT(6)
#define RSI_GSPI_RF_SPI_ACTIVE BIT(8)
/* Boot loader commands */
#define SEND_RPS_FILE '2'
#define FW_IMAGE_MIN_ADDRESS (68 * 1024)
#define MAX_FLASH_FILE_SIZE (400 * 1024) //400K
#define FLASH_START_ADDRESS 16
#define COMMON_HAL_CARD_READY_IND 0x0
#define COMMAN_HAL_WAIT_FOR_CARD_READY 1
#define RSI_DEV_OPMODE_WIFI_ALONE 1
#define RSI_DEV_COEX_MODE_WIFI_ALONE 1
#define BBP_INFO_40MHZ 0x6
#define FW_FLASH_OFFSET 0x820
#define LMAC_VER_OFFSET_9113 (FW_FLASH_OFFSET + 0x200)
#define LMAC_VER_OFFSET_9116 0x22C2
#define MAX_DWORD_ALIGN_BYTES 64
#define RSI_COMMON_REG_SIZE 2
#define RSI_9116_REG_SIZE 4
#define FW_ALIGN_SIZE 4
#define RSI_9116_FW_MAGIC_WORD 0x5aa5
#define MEM_ACCESS_CTRL_FROM_HOST 0x41300000
#define RAM_384K_ACCESS_FROM_TA (BIT(2) | BIT(3) | BIT(4) | BIT(5) | \
BIT(20) | BIT(21) | BIT(22) | \
BIT(23) | BIT(24) | BIT(25))
struct bl_header {
__le32 flags;
__le32 image_no;
__le32 check_sum;
__le32 flash_start_address;
__le32 flash_len;
} __packed;
struct ta_metadata {
char *name;
unsigned int address;
};
#define RSI_BL_CTRL_LEN_MASK 0xFFFFFF
#define RSI_BL_CTRL_SPI_32BIT_MODE BIT(27)
#define RSI_BL_CTRL_REL_TA_SOFTRESET BIT(28)
#define RSI_BL_CTRL_START_FROM_ROM_PC BIT(29)
#define RSI_BL_CTRL_SPI_8BIT_MODE BIT(30)
#define RSI_BL_CTRL_LAST_ENTRY BIT(31)
struct bootload_entry {
__le32 control;
__le32 dst_addr;
} __packed;
struct bootload_ds {
__le16 fixed_pattern;
__le16 offset;
__le32 reserved;
struct bootload_entry bl_entry[7];
} __packed;
struct rsi_mgmt_desc {
__le16 len_qno;
u8 frame_type;
u8 misc_flags;
u8 xtend_desc_size;
u8 header_len;
__le16 frame_info;
__le16 rate_info;
__le16 bbp_info;
__le16 seq_ctrl;
u8 reserved2;
u8 sta_id;
} __packed;
struct rsi_data_desc {
__le16 len_qno;
u8 cfm_frame_type;
u8 misc_flags;
u8 xtend_desc_size;
u8 header_len;
__le16 frame_info;
__le16 rate_info;
__le16 bbp_info;
__le16 mac_flags;
u8 qid_tid;
u8 sta_id;
} __packed;
struct rsi_bt_desc {
__le16 len_qno;
__le16 reserved1;
__le32 reserved2;
__le32 reserved3;
__le16 reserved4;
__le16 bt_pkt_type;
} __packed;
int rsi_hal_device_init(struct rsi_hw *adapter);
int rsi_prepare_mgmt_desc(struct rsi_common *common, struct sk_buff *skb);
int rsi_prepare_data_desc(struct rsi_common *common, struct sk_buff *skb);
int rsi_prepare_beacon(struct rsi_common *common, struct sk_buff *skb);
int rsi_send_pkt_to_bus(struct rsi_common *common, struct sk_buff *skb);
int rsi_send_bt_pkt(struct rsi_common *common, struct sk_buff *skb);
#endif
|
