1 2 3 4 5 6 7 8 9 10 11 12 13 14
[ { "ArchStdEvent": "MEM_ACCESS" }, { "ArchStdEvent": "MEM_ACCESS_RD" }, { "ArchStdEvent": "MEM_ACCESS_WR" }, { "ArchStdEvent": "UNALIGNED_LDST_SPEC" } ]