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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
commit | 2c3c1048746a4622d8c89a29670120dc8fab93c4 (patch) | |
tree | 848558de17fb3008cdf4d861b01ac7781903ce39 /Documentation/devicetree/bindings/interrupt-controller/samsung,exynos4210-combiner.yaml | |
parent | Initial commit. (diff) | |
download | linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.tar.xz linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.zip |
Adding upstream version 6.1.76.upstream/6.1.76
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'Documentation/devicetree/bindings/interrupt-controller/samsung,exynos4210-combiner.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/samsung,exynos4210-combiner.yaml | 96 |
1 files changed, 96 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/samsung,exynos4210-combiner.yaml b/Documentation/devicetree/bindings/interrupt-controller/samsung,exynos4210-combiner.yaml new file mode 100644 index 000000000..72456a07d --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/samsung,exynos4210-combiner.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC Interrupt Combiner Controller + +maintainers: + - Krzysztof Kozlowski <krzk@kernel.org> + +description: | + Samsung's Exynos4 architecture includes a interrupt combiner controller which + can combine interrupt sources as a group and provide a single interrupt + request for the group. The interrupt request from each group are connected to + a parent interrupt controller, such as GIC in case of Exynos4210. + + The interrupt combiner controller consists of multiple combiners. Up to eight + interrupt sources can be connected to a combiner. The combiner outputs one + combined interrupt for its eight interrupt sources. The combined interrupt is + usually connected to a parent interrupt controller. + + A single node in the device tree is used to describe the interrupt combiner + controller module (which includes multiple combiners). A combiner in the + interrupt controller module shares config/control registers with other + combiners. For example, a 32-bit interrupt enable/disable config register can + accommodate up to 4 interrupt combiners (with each combiner supporting up to + 8 interrupt sources). + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + const: samsung,exynos4210-combiner + + interrupt-controller: true + + interrupts: + minItems: 8 + maxItems: 32 + + "#interrupt-cells": + description: | + The meaning of the cells are: + * First Cell: Combiner Group Number. + * Second Cell: Interrupt number within the group. + const: 2 + + reg: + maxItems: 1 + + samsung,combiner-nr: + description: | + The number of interrupt combiners supported. Should match number + of interrupts set in "interrupts" property. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 8 + maximum: 32 + default: 16 + +required: + - compatible + - interrupt-controller + - interrupts + - "#interrupt-cells" + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + interrupt-controller@10440000 { + compatible = "samsung,exynos4210-combiner"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x10440000 0x1000>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + }; |