summaryrefslogtreecommitdiffstats
path: root/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
diff options
context:
space:
mode:
authorDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-07 18:49:45 +0000
committerDaniel Baumann <daniel.baumann@progress-linux.org>2024-04-07 18:49:45 +0000
commit2c3c1048746a4622d8c89a29670120dc8fab93c4 (patch)
tree848558de17fb3008cdf4d861b01ac7781903ce39 /Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
parentInitial commit. (diff)
downloadlinux-2c3c1048746a4622d8c89a29670120dc8fab93c4.tar.xz
linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.zip
Adding upstream version 6.1.76.upstream/6.1.76
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'Documentation/devicetree/bindings/mailbox/fsl,mu.yaml')
-rw-r--r--Documentation/devicetree/bindings/mailbox/fsl,mu.yaml135
1 files changed, 135 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
new file mode 100644
index 000000000..191c1ce15
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX Messaging Unit (MU)
+
+maintainers:
+ - Dong Aisheng <aisheng.dong@nxp.com>
+
+description: |
+ The Messaging Unit module enables two processors within the SoC to
+ communicate and coordinate by passing messages (e.g. data, status
+ and control) through the MU interface. The MU also provides the ability
+ for one processor to signal the other processor using interrupts.
+
+ Because the MU manages the messaging between processors, the MU uses
+ different clocks (from each side of the different peripheral buses).
+ Therefore, the MU must synchronize the accesses from one side to the
+ other. The MU accomplishes synchronization using two sets of matching
+ registers (Processor A-facing, Processor B-facing).
+
+properties:
+ compatible:
+ oneOf:
+ - const: fsl,imx6sx-mu
+ - const: fsl,imx7ulp-mu
+ - const: fsl,imx8ulp-mu
+ - const: fsl,imx8-mu-scu
+ - const: fsl,imx8-mu-seco
+ - const: fsl,imx93-mu-s4
+ - const: fsl,imx8ulp-mu-s4
+ - items:
+ - const: fsl,imx93-mu
+ - const: fsl,imx8ulp-mu
+ - items:
+ - enum:
+ - fsl,imx7s-mu
+ - fsl,imx8mq-mu
+ - fsl,imx8mm-mu
+ - fsl,imx8mn-mu
+ - fsl,imx8mp-mu
+ - fsl,imx8qm-mu
+ - fsl,imx8qxp-mu
+ - const: fsl,imx6sx-mu
+ - description: To communicate with i.MX8 SCU with fast IPC
+ items:
+ - const: fsl,imx8-mu-scu
+ - enum:
+ - fsl,imx8qm-mu
+ - fsl,imx8qxp-mu
+ - const: fsl,imx6sx-mu
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+
+ interrupt-names:
+ minItems: 1
+ items:
+ - const: tx
+ - const: rx
+
+ "#mbox-cells":
+ description: |
+ <&phandle type channel>
+ phandle : Label name of controller
+ type : Channel type
+ channel : Channel number
+
+ This MU support 5 type of unidirectional channels, each type
+ has 4 channels except RST channel which only has 1 channel.
+ A total of 17 channels. Following types are
+ supported:
+ 0 - TX channel with 32bit transmit register and IRQ transmit
+ acknowledgment support.
+ 1 - RX channel with 32bit receive register and IRQ support
+ 2 - TX doorbell channel. Without own register and no ACK support.
+ 3 - RX doorbell channel.
+ 4 - RST channel
+ const: 2
+
+ clocks:
+ maxItems: 1
+
+ fsl,mu-side-b:
+ description: boolean, if present, means it is for side B MU.
+ type: boolean
+
+ power-domains:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#mbox-cells"
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx93-mu-s4
+ then:
+ properties:
+ interrupt-names:
+ minItems: 2
+ interrupts:
+ minItems: 2
+
+ else:
+ properties:
+ interrupts:
+ maxItems: 1
+ not:
+ required:
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ mailbox@5d1b0000 {
+ compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+ reg = <0x5d1b0000 0x10000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <2>;
+ };