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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
commit | 2c3c1048746a4622d8c89a29670120dc8fab93c4 (patch) | |
tree | 848558de17fb3008cdf4d861b01ac7781903ce39 /Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml | |
parent | Initial commit. (diff) | |
download | linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.tar.xz linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.zip |
Adding upstream version 6.1.76.upstream/6.1.76
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml new file mode 100644 index 000000000..80a923853 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale(NXP) IMX8 DDR performance monitor + +maintainers: + - Frank Li <frank.li@nxp.com> + +properties: + compatible: + oneOf: + - enum: + - fsl,imx8-ddr-pmu + - fsl,imx8m-ddr-pmu + - fsl,imx8mq-ddr-pmu + - fsl,imx8mm-ddr-pmu + - fsl,imx8mn-ddr-pmu + - fsl,imx8mp-ddr-pmu + - items: + - enum: + - fsl,imx8mm-ddr-pmu + - fsl,imx8mn-ddr-pmu + - fsl,imx8mq-ddr-pmu + - fsl,imx8mp-ddr-pmu + - const: fsl,imx8m-ddr-pmu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + ddr-pmu@5c020000 { + compatible = "fsl,imx8-ddr-pmu"; + reg = <0x5c020000 0x10000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + }; |