Documentation/devicetree/bindings/dma/altr,msgdma.yaml


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63

# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/dma/altr,msgdma.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Altera mSGDMA IP core

maintainers:
  - Olivier Dautricourt <olivierdautricourt@gmail.com>

description: |
  Altera / Intel modular Scatter-Gather Direct Memory Access (mSGDMA)
  intellectual property (IP)

allOf:
  - $ref: "dma-controller.yaml#"

properties:
  compatible:
    const: altr,socfpga-msgdma

  reg:
    items:
      - description: Control and Status Register Slave Port
      - description: Descriptor Slave Port
      - description: Response Slave Port (Optional)
    minItems: 2

  reg-names:
    items:
      - const: csr
      - const: desc
      - const: resp
    minItems: 2

  interrupts:
    maxItems: 1

  "#dma-cells":
    const: 1
    description:
      The cell identifies the channel id (must be 0)

required:
  - compatible
  - reg
  - reg-names
  - interrupts

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    msgdma_controller: dma-controller@ff200b00 {
        compatible = "altr,socfpga-msgdma";
        reg = <0xff200b00 0x100>, <0xff200c00 0x100>, <0xff200d00 0x100>;
        reg-names = "csr", "desc", "resp";
        interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
        #dma-cells = <1>;
    };