diff options
Diffstat (limited to 'src/spdk/intel-ipsec-mb/no-aesni/aes256_cntr_by4_sse_no_aesni.asm')
-rw-r--r-- | src/spdk/intel-ipsec-mb/no-aesni/aes256_cntr_by4_sse_no_aesni.asm | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/spdk/intel-ipsec-mb/no-aesni/aes256_cntr_by4_sse_no_aesni.asm b/src/spdk/intel-ipsec-mb/no-aesni/aes256_cntr_by4_sse_no_aesni.asm new file mode 100644 index 000000000..a99faff80 --- /dev/null +++ b/src/spdk/intel-ipsec-mb/no-aesni/aes256_cntr_by4_sse_no_aesni.asm @@ -0,0 +1,31 @@ +;; +;; Copyright (c) 2018, Intel Corporation +;; +;; Redistribution and use in source and binary forms, with or without +;; modification, are permitted provided that the following conditions are met: +;; +;; * Redistributions of source code must retain the above copyright notice, +;; this list of conditions and the following disclaimer. +;; * Redistributions in binary form must reproduce the above copyright +;; notice, this list of conditions and the following disclaimer in the +;; documentation and/or other materials provided with the distribution. +;; * Neither the name of Intel Corporation nor the names of its contributors +;; may be used to endorse or promote products derived from this software +;; without specific prior written permission. +;; +;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE +;; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;; + +%include "include/aesni_emu.inc" +%define AES_CNTR_256 aes_cntr_256_sse_no_aesni +%define AES_CNTR_BIT_256 aes_cntr_bit_256_sse_no_aesni +%include "sse/aes256_cntr_by4_sse.asm" |