1 files changed, 266 insertions, 0 deletions
diff --git a/src/spdk/isa-l/Makefile.nmake b/src/spdk/isa-l/Makefile.nmake
new file mode 100644
index 000000000..fc72aa126
--- /dev/null
+++ b/src/spdk/isa-l/Makefile.nmake
@@ -0,0 +1,266 @@
+########################################################################
+#  Copyright(c) 2011-2016 Intel Corporation All rights reserved.
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions
+#  are met:
+#    * Redistributions of source code must retain the above copyright
+#      notice, this list of conditions and the following disclaimer.
+#    * Redistributions in binary form must reproduce the above copyright
+#      notice, this list of conditions and the following disclaimer in
+#      the documentation and/or other materials provided with the
+#      distribution.
+#    * Neither the name of Intel Corporation nor the names of its
+#      contributors may be used to endorse or promote products derived
+#      from this software without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+########################################################################
+
+objs =  \
+	bin\ec_base.obj \
+	bin\ec_highlevel_func.obj \
+	bin\ec_multibinary.obj \
+	bin\gf_2vect_dot_prod_avx.obj \
+	bin\gf_2vect_dot_prod_avx2.obj \
+	bin\gf_2vect_dot_prod_avx512.obj \
+	bin\gf_2vect_dot_prod_sse.obj \
+	bin\gf_2vect_mad_avx.obj \
+	bin\gf_2vect_mad_avx2.obj \
+	bin\gf_2vect_mad_avx512.obj \
+	bin\gf_2vect_mad_sse.obj \
+	bin\gf_3vect_dot_prod_avx.obj \
+	bin\gf_3vect_dot_prod_avx2.obj \
+	bin\gf_3vect_dot_prod_avx512.obj \
+	bin\gf_3vect_dot_prod_sse.obj \
+	bin\gf_3vect_mad_avx.obj \
+	bin\gf_3vect_mad_avx2.obj \
+	bin\gf_3vect_mad_avx512.obj \
+	bin\gf_3vect_mad_sse.obj \
+	bin\gf_4vect_dot_prod_avx.obj \
+	bin\gf_4vect_dot_prod_avx2.obj \
+	bin\gf_4vect_dot_prod_avx512.obj \
+	bin\gf_4vect_dot_prod_sse.obj \
+	bin\gf_4vect_mad_avx.obj \
+	bin\gf_4vect_mad_avx2.obj \
+	bin\gf_4vect_mad_avx512.obj \
+	bin\gf_4vect_mad_sse.obj \
+	bin\gf_5vect_dot_prod_avx.obj \
+	bin\gf_5vect_dot_prod_avx2.obj \
+	bin\gf_5vect_dot_prod_sse.obj \
+	bin\gf_5vect_mad_avx.obj \
+	bin\gf_5vect_mad_avx2.obj \
+	bin\gf_5vect_mad_sse.obj \
+	bin\gf_6vect_dot_prod_avx.obj \
+	bin\gf_6vect_dot_prod_avx2.obj \
+	bin\gf_6vect_dot_prod_sse.obj \
+	bin\gf_6vect_mad_avx.obj \
+	bin\gf_6vect_mad_avx2.obj \
+	bin\gf_6vect_mad_sse.obj \
+	bin\gf_vect_dot_prod_avx.obj \
+	bin\gf_vect_dot_prod_avx2.obj \
+	bin\gf_vect_dot_prod_avx512.obj \
+	bin\gf_vect_dot_prod_sse.obj \
+	bin\gf_vect_mad_avx.obj \
+	bin\gf_vect_mad_avx2.obj \
+	bin\gf_vect_mad_avx512.obj \
+	bin\gf_vect_mad_sse.obj \
+	bin\gf_vect_mul_avx.obj \
+	bin\gf_vect_mul_sse.obj \
+	bin\pq_check_sse.obj \
+	bin\pq_gen_avx.obj \
+	bin\pq_gen_avx2.obj \
+	bin\pq_gen_avx512.obj \
+	bin\pq_gen_sse.obj \
+	bin\raid_base.obj \
+	bin\raid_multibinary.obj \
+	bin\xor_check_sse.obj \
+	bin\xor_gen_avx.obj \
+	bin\xor_gen_avx512.obj \
+	bin\xor_gen_sse.obj \
+	bin\crc16_t10dif_01.obj \
+	bin\crc16_t10dif_by4.obj \
+	bin\crc16_t10dif_copy_by4.obj \
+	bin\crc32_ieee_01.obj \
+	bin\crc32_ieee_by4.obj \
+	bin\crc32_iscsi_00.obj \
+	bin\crc32_iscsi_01.obj \
+	bin\crc64_base.obj \
+	bin\crc64_ecma_norm_by8.obj \
+	bin\crc64_ecma_refl_by8.obj \
+	bin\crc64_iso_norm_by8.obj \
+	bin\crc64_iso_refl_by8.obj \
+	bin\crc64_jones_norm_by8.obj \
+	bin\crc64_jones_refl_by8.obj \
+	bin\crc64_multibinary.obj \
+	bin\crc_base.obj \
+	bin\adler32_base.obj \
+	bin\crc_multibinary.obj \
+	bin\huff_codes.obj \
+	bin\hufftables_c.obj \
+	bin\igzip.obj \
+	bin\igzip_base.obj \
+	bin\igzip_body.obj \
+	bin\igzip_decode_block_stateless_01.obj \
+	bin\igzip_decode_block_stateless_04.obj \
+	bin\igzip_finish.obj \
+	bin\flatten_ll.obj \
+	bin\encode_df.obj \
+	bin\encode_df_04.obj \
+	bin\proc_heap.obj \
+	bin\igzip_icf_body_h1_gr_bt.obj \
+	bin\igzip_icf_finish.obj \
+	bin\igzip_icf_base.obj \
+	bin\igzip_inflate.obj \
+	bin\igzip_inflate_multibinary.obj \
+	bin\igzip_multibinary.obj \
+	bin\igzip_update_histogram_01.obj \
+	bin\igzip_update_histogram_04.obj \
+	bin\rfc1951_lookup.obj \
+	bin\crc32_gzip_refl_by8.obj \
+	bin\adler32_sse.obj \
+	bin\adler32_avx2_4.obj \
+	bin\igzip_deflate_hash.obj \
+	bin\igzip_gen_icf_map_lh1_04.obj \
+	bin\igzip_gen_icf_map_lh1_06.obj \
+	bin\igzip_set_long_icf_fg_04.obj \
+	bin\igzip_set_long_icf_fg_06.obj \
+	bin\igzip_icf_body.obj \
+	bin\mem_zero_detect_avx.obj \
+	bin\mem_zero_detect_base.obj \
+	bin\mem_multibinary.obj \
+	bin\mem_zero_detect_sse.obj
+
+INCLUDES  = -I./ -Ierasure_code/ -Iraid/ -Icrc/ -Iigzip/ -Iinclude/ -Imem/
+LINKFLAGS = /nologo
+CFLAGS   = -O2 -D NDEBUG /nologo -D_USE_MATH_DEFINES -Qstd=c99 $(INCLUDES) $(D)
+AFLAGS   = -f win64 $(INCLUDES) $(D)
+CC       = icl
+AS       = yasm
+
+lib: bin static dll
+static: bin isa-l_static.lib
+dll: bin isa-l.dll
+
+bin: ; -mkdir $@
+
+isa-l_static.lib: $(objs)
+	lib -out:$@ @<<
+$?
+<<
+
+isa-l.dll: $(objs)
+	link -out:$@ -dll -def:isa-l.def @<<
+$?
+<<
+
+{erasure_code}.c.obj:
+	$(CC) $(CFLAGS) /c -Fo$@ $?
+{erasure_code}.asm.obj:
+	$(AS) $(AFLAGS) -o $@ $?
+
+{raid}.c.obj:
+	$(CC) $(CFLAGS) /c -Fo$@ $?
+{raid}.asm.obj:
+	$(AS) $(AFLAGS) -o $@ $?
+
+{crc}.c.obj:
+	$(CC) $(CFLAGS) /c -Fo$@ $?
+{crc}.asm.obj:
+	$(AS) $(AFLAGS) -o $@ $?
+
+{igzip}.c.obj:
+	$(CC) $(CFLAGS) /c -Fo$@ $?
+{igzip}.asm.obj:
+	$(AS) $(AFLAGS) -o $@ $?
+
+{mem}.c.obj:
+	$(CC) $(CFLAGS) /c -Fo$@ $?
+{mem}.asm.obj:
+	$(AS) $(AFLAGS) -o $@ $?
+
+# Examples
+ex = xor_example.exe crc_simple_test.exe crc64_example.exe igzip_example.exe igzip_sync_flush_example.exe
+ex: lib $(ex)
+
+$(ex): $(@B).obj
+
+.obj.exe:
+	link /out:$@ $(LINKFLAGS) isa-l.lib $?
+
+# Check tests
+checks = \
+	gf_vect_mul_test.exe \
+	erasure_code_test.exe \
+	gf_inverse_test.exe \
+	erasure_code_update_test.exe \
+	xor_gen_test.exe \
+	pq_gen_test.exe \
+	xor_check_test.exe \
+	pq_check_test.exe \
+	crc16_t10dif_test.exe \
+	crc16_t10dif_copy_test.exe \
+	crc32_funcs_test.exe \
+	crc64_funcs_test.exe \
+	igzip_wrapper_hdr_test.exe \
+	igzip_rand_test.exe \
+	mem_zero_detect_test.exe
+
+checks: lib $(checks)
+$(checks): $(@B).obj
+check: $(checks)
+	!$?
+
+# Unit tests
+tests = \
+	gf_vect_mul_base_test.exe \
+	gf_vect_dot_prod_base_test.exe \
+	gf_vect_dot_prod_test.exe \
+	gf_vect_mad_test.exe \
+	erasure_code_base_test.exe
+
+tests: lib $(tests)
+$(tests): $(@B).obj
+
+# Performance tests
+perfs = \
+	gf_vect_mul_perf.exe \
+	gf_vect_dot_prod_perf.exe \
+	gf_vect_dot_prod_1tbl.exe \
+	erasure_code_perf.exe \
+	erasure_code_base_perf.exe \
+	erasure_code_sse_perf.exe \
+	erasure_code_update_perf.exe \
+	xor_gen_perf.exe \
+	pq_gen_perf.exe \
+	crc16_t10dif_perf.exe \
+	crc32_ieee_perf.exe \
+	crc32_iscsi_perf.exe \
+	igzip_perf.exe \
+	igzip_sync_flush_perf.exe \
+	crc32_gzip_refl_perf.exe \
+	mem_zero_detect_perf.exe
+
+perfs: lib $(perfs)
+$(perfs): $(@B).obj
+
+clean:
+	-if exist *.obj del *.obj
+	-if exist bin\*.obj del bin\*.obj
+	-if exist isa-l_static.lib del isa-l_static.lib
+	-if exist *.exe del *.exe
+	-if exist isa-l.lib del isa-l.lib
+	-if exist isa-l.dll del isa-l.dll
+
+zlib.lib:
+igzip_inflate_test.exe:  zlib.lib