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Diffstat (limited to 'third_party/rust/cache-padded')
| -rw-r--r-- | third_party/rust/cache-padded/.cargo-checksum.json | 1 | ||||
| -rw-r--r-- | third_party/rust/cache-padded/CHANGELOG.md | 15 | ||||
| -rw-r--r-- | third_party/rust/cache-padded/Cargo.toml | 22 | ||||
| -rw-r--r-- | third_party/rust/cache-padded/LICENSE-APACHE | 201 | ||||
| -rw-r--r-- | third_party/rust/cache-padded/LICENSE-MIT | 23 | ||||
| -rw-r--r-- | third_party/rust/cache-padded/README.md | 79 | ||||
| -rw-r--r-- | third_party/rust/cache-padded/src/lib.rs | 187 | ||||
| -rw-r--r-- | third_party/rust/cache-padded/tests/padding.rs | 107 |
8 files changed, 635 insertions, 0 deletions
diff --git a/third_party/rust/cache-padded/.cargo-checksum.json b/third_party/rust/cache-padded/.cargo-checksum.json new file mode 100644 index 0000000000..fe13a97d87 --- /dev/null +++ b/third_party/rust/cache-padded/.cargo-checksum.json @@ -0,0 +1 @@ +{"files":{"CHANGELOG.md":"01efe9c9a75e5a305dac0e12676ed451f746049a825aa86acef0d8ee90742f71","Cargo.toml":"ea55c73cacac2dcc3bdcb2c657e057d9b73214e76f8654799236b13c853e97bd","LICENSE-APACHE":"a60eea817514531668d7e00765731449fe14d059d3249e0bc93b36de45f759f2","LICENSE-MIT":"23f18e03dc49df91622fe2a76176497404e46ced8a715d9d2b67a7446571cca3","README.md":"61d450a57f8699dfc1c39e3bb69236f7d10f31f4503b03aa8b2b37b2448b8b69","src/lib.rs":"4bcb45fe37cdca78ba0e403d9e531102c521ad42e9ffd2ecbb154b4509864978","tests/padding.rs":"120cc65d1fcebbdb0ed8b0c287680ede2483e3ab040746e1a3616ffb39d8f414"},"package":"c1db59621ec70f09c5e9b597b220c7a2b43611f4710dc03ceb8748637775692c"}
\ No newline at end of file diff --git a/third_party/rust/cache-padded/CHANGELOG.md b/third_party/rust/cache-padded/CHANGELOG.md new file mode 100644 index 0000000000..7ed155bb86 --- /dev/null +++ b/third_party/rust/cache-padded/CHANGELOG.md @@ -0,0 +1,15 @@ +# Version 1.2.0 + +- Improve implementation of `CachePadded`. + +# Version 1.1.1 + +- Forbid unsafe code. + +# Version 1.1.0 + +- Mark `CachePadded::new()` as const fn. + +# Version 1.0.0 + +- Initial version diff --git a/third_party/rust/cache-padded/Cargo.toml b/third_party/rust/cache-padded/Cargo.toml new file mode 100644 index 0000000000..cac57bfbb3 --- /dev/null +++ b/third_party/rust/cache-padded/Cargo.toml @@ -0,0 +1,22 @@ +# THIS FILE IS AUTOMATICALLY GENERATED BY CARGO +# +# When uploading crates to the registry Cargo will automatically +# "normalize" Cargo.toml files for maximal compatibility +# with all versions of Cargo and also rewrite `path` dependencies +# to registry (e.g., crates.io) dependencies. +# +# If you are reading this file be aware that the original Cargo.toml +# will likely look very different (and much more reasonable). +# See Cargo.toml.orig for the original contents. + +[package] +edition = "2018" +name = "cache-padded" +version = "1.2.0" +authors = ["Stjepan Glavina <stjepang@gmail.com>"] +description = "Prevent false sharing by padding and aligning to the length of a cache line" +homepage = "https://github.com/smol-rs/cache-padded" +keywords = ["cache", "padding", "lock-free", "atomic"] +categories = ["concurrency", "no-std"] +license = "Apache-2.0 OR MIT" +repository = "https://github.com/smol-rs/cache-padded" diff --git a/third_party/rust/cache-padded/LICENSE-APACHE b/third_party/rust/cache-padded/LICENSE-APACHE new file mode 100644 index 0000000000..16fe87b06e --- /dev/null +++ b/third_party/rust/cache-padded/LICENSE-APACHE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + +TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + +1. 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IN NO EVENT +SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY +CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION +OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR +IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER +DEALINGS IN THE SOFTWARE. diff --git a/third_party/rust/cache-padded/README.md b/third_party/rust/cache-padded/README.md new file mode 100644 index 0000000000..6dd2b36929 --- /dev/null +++ b/third_party/rust/cache-padded/README.md @@ -0,0 +1,79 @@ +# cache-padded + +[]( +https://github.com/smol-rs/cache-padded/actions) +[]( +https://github.com/smol-rs/cache-padded) +[]( +https://crates.io/crates/cache-padded) +[]( +https://docs.rs/cache-padded) + +Prevent false sharing by padding and aligning to the length of a cache line. + +In concurrent programming, sometimes it is desirable to make sure commonly accessed shared data +is not all placed into the same cache line. Updating an atomic value invalides the whole cache +line it belongs to, which makes the next access to the same cache line slower for other CPU +cores. Use `CachePadded` to ensure updating one piece of data doesn't invalidate other cached +data. + +## Size and alignment + +Cache lines are assumed to be N bytes long, depending on the architecture: + +* On x86-64 and aarch64, N = 128. +* On all others, N = 64. + +Note that N is just a reasonable guess and is not guaranteed to match the actual cache line +length of the machine the program is running on. + +The size of `CachePadded<T>` is the smallest multiple of N bytes large enough to accommodate +a value of type `T`. + +The alignment of `CachePadded<T>` is the maximum of N bytes and the alignment of `T`. + +## Examples + +Alignment and padding: + +```rust +use cache_padded::CachePadded; + +let array = [CachePadded::new(1i8), CachePadded::new(2i8)]; +let addr1 = &*array[0] as *const i8 as usize; +let addr2 = &*array[1] as *const i8 as usize; + +assert!(addr2 - addr1 >= 64); +assert_eq!(addr1 % 64, 0); +assert_eq!(addr2 % 64, 0); +``` + +When building a concurrent queue with a head and a tail index, it is wise to place indices in +different cache lines so that concurrent threads pushing and popping elements don't invalidate +each other's cache lines: + +```rust +use cache_padded::CachePadded; +use std::sync::atomic::AtomicUsize; + +struct Queue<T> { + head: CachePadded<AtomicUsize>, + tail: CachePadded<AtomicUsize>, + buffer: *mut T, +} +``` + +## License + +Licensed under either of + + * Apache License, Version 2.0 ([LICENSE-APACHE](LICENSE-APACHE) or http://www.apache.org/licenses/LICENSE-2.0) + * MIT license ([LICENSE-MIT](LICENSE-MIT) or http://opensource.org/licenses/MIT) + +at your option. + +#### Contribution + +Unless you explicitly state otherwise, any contribution intentionally submitted +for inclusion in the work by you, as defined in the Apache-2.0 license, shall be +dual licensed as above, without any additional terms or conditions. diff --git a/third_party/rust/cache-padded/src/lib.rs b/third_party/rust/cache-padded/src/lib.rs new file mode 100644 index 0000000000..4d602cb667 --- /dev/null +++ b/third_party/rust/cache-padded/src/lib.rs @@ -0,0 +1,187 @@ +//! Prevent false sharing by padding and aligning to the length of a cache line. +//! +//! In concurrent programming, sometimes it is desirable to make sure commonly accessed shared data +//! is not all placed into the same cache line. Updating an atomic value invalidates the whole cache +//! line it belongs to, which makes the next access to the same cache line slower for other CPU +//! cores. Use [`CachePadded`] to ensure updating one piece of data doesn't invalidate other cached +//! data. +//! +//! # Size and alignment +//! +//! Cache lines are assumed to be N bytes long, depending on the architecture: +//! +//! * On x86-64, aarch64, and powerpc64, N = 128. +//! * On arm, mips, mips64, and riscv64, N = 32. +//! * On s390x, N = 256. +//! +//! Note that N is just a reasonable guess and is not guaranteed to match the actual cache line +//! length of the machine the program is running on. +//! +//! The size of `CachePadded<T>` is the smallest multiple of N bytes large enough to accommodate +//! a value of type `T`. +//! +//! The alignment of `CachePadded<T>` is the maximum of N bytes and the alignment of `T`. +//! +//! # Examples +//! +//! Alignment and padding: +//! +//! ``` +//! use cache_padded::CachePadded; +//! +//! let array = [CachePadded::new(1i8), CachePadded::new(2i8)]; +//! let addr1 = &*array[0] as *const i8 as usize; +//! let addr2 = &*array[1] as *const i8 as usize; +//! +//! assert!(addr2 - addr1 >= 64); +//! assert_eq!(addr1 % 64, 0); +//! assert_eq!(addr2 % 64, 0); +//! ``` +//! +//! When building a concurrent queue with a head and a tail index, it is wise to place indices in +//! different cache lines so that concurrent threads pushing and popping elements don't invalidate +//! each other's cache lines: +//! +//! ``` +//! use cache_padded::CachePadded; +//! use std::sync::atomic::AtomicUsize; +//! +//! struct Queue<T> { +//! head: CachePadded<AtomicUsize>, +//! tail: CachePadded<AtomicUsize>, +//! buffer: *mut T, +//! } +//! ``` + +#![no_std] +#![forbid(unsafe_code)] +#![warn(missing_docs, missing_debug_implementations, rust_2018_idioms)] + +use core::fmt; +use core::ops::{Deref, DerefMut}; + +/// Pads and aligns data to the length of a cache line. +// Starting from Intel's Sandy Bridge, spatial prefetcher is now pulling pairs of 64-byte cache +// lines at a time, so we have to align to 128 bytes rather than 64. +// +// Sources: +// - https://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-optimization-manual.pdf +// - https://github.com/facebook/folly/blob/1b5288e6eea6df074758f877c849b6e73bbb9fbb/folly/lang/Align.h#L107 +// +// ARM's big.LITTLE architecture has asymmetric cores and "big" cores have 128-byte cache line size. +// +// Sources: +// - https://www.mono-project.com/news/2016/09/12/arm64-icache/ +// +// powerpc64 has 128-byte cache line size. +// +// Sources: +// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_ppc64x.go#L9 +#[cfg_attr( + any( + target_arch = "x86_64", + target_arch = "aarch64", + target_arch = "powerpc64", + ), + repr(align(128)) +)] +// arm, mips, mips64, and riscv64 have 32-byte cache line size. +// +// Sources: +// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7 +// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7 +// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7 +// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9 +// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_riscv64.go#L7 +#[cfg_attr( + any( + target_arch = "arm", + target_arch = "mips", + target_arch = "mips64", + target_arch = "riscv64", + ), + repr(align(32)) +)] +// s390x has 256-byte cache line size. +// +// Sources: +// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_s390x.go#L7 +#[cfg_attr(target_arch = "s390x", repr(align(256)))] +// x86 and wasm have 64-byte cache line size. +// +// Sources: +// - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9 +// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7 +// +// All others are assumed to have 64-byte cache line size. +#[cfg_attr( + not(any( + target_arch = "x86_64", + target_arch = "aarch64", + target_arch = "powerpc64", + target_arch = "arm", + target_arch = "mips", + target_arch = "mips64", + target_arch = "riscv64", + target_arch = "s390x", + )), + repr(align(64)) +)] +#[derive(Clone, Copy, Default, Hash, PartialEq, Eq)] +pub struct CachePadded<T>(T); + +impl<T> CachePadded<T> { + /// Pads and aligns a piece of data to the length of a cache line. + /// + /// # Examples + /// + /// ``` + /// use cache_padded::CachePadded; + /// + /// let padded = CachePadded::new(1); + /// ``` + pub const fn new(t: T) -> CachePadded<T> { + CachePadded(t) + } + + /// Returns the inner data. + /// + /// # Examples + /// + /// ``` + /// use cache_padded::CachePadded; + /// + /// let padded = CachePadded::new(7); + /// let data = padded.into_inner(); + /// assert_eq!(data, 7); + /// ``` + pub fn into_inner(self) -> T { + self.0 + } +} + +impl<T> Deref for CachePadded<T> { + type Target = T; + + fn deref(&self) -> &T { + &self.0 + } +} + +impl<T> DerefMut for CachePadded<T> { + fn deref_mut(&mut self) -> &mut T { + &mut self.0 + } +} + +impl<T: fmt::Debug> fmt::Debug for CachePadded<T> { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + f.debug_tuple("CachePadded").field(&self.0).finish() + } +} + +impl<T> From<T> for CachePadded<T> { + fn from(t: T) -> Self { + CachePadded::new(t) + } +} diff --git a/third_party/rust/cache-padded/tests/padding.rs b/third_party/rust/cache-padded/tests/padding.rs new file mode 100644 index 0000000000..6125854cd9 --- /dev/null +++ b/third_party/rust/cache-padded/tests/padding.rs @@ -0,0 +1,107 @@ +use std::cell::Cell; +use std::mem; + +use cache_padded::CachePadded; + +#[test] +fn default() { + let x: CachePadded<u64> = Default::default(); + assert_eq!(*x, 0); +} + +#[test] +fn store_u64() { + let x: CachePadded<u64> = CachePadded::new(17); + assert_eq!(*x, 17); +} + +#[test] +fn store_pair() { + let x: CachePadded<(u64, u64)> = CachePadded::new((17, 37)); + assert_eq!(x.0, 17); + assert_eq!(x.1, 37); +} + +#[test] +fn distance() { + let arr = [CachePadded::new(17u8), CachePadded::new(37u8)]; + let a = &*arr[0] as *const u8; + let b = &*arr[1] as *const u8; + assert!(unsafe { a.offset(64) } <= b); +} + +#[test] +fn different_sizes() { + CachePadded::new(17u8); + CachePadded::new(17u16); + CachePadded::new(17u32); + CachePadded::new([17u64; 0]); + CachePadded::new([17u64; 1]); + CachePadded::new([17u64; 2]); + CachePadded::new([17u64; 3]); + CachePadded::new([17u64; 4]); + CachePadded::new([17u64; 5]); + CachePadded::new([17u64; 6]); + CachePadded::new([17u64; 7]); + CachePadded::new([17u64; 8]); +} + +#[test] +fn large() { + let a = [17u64; 9]; + let b = CachePadded::new(a); + assert!(mem::size_of_val(&a) <= mem::size_of_val(&b)); +} + +#[test] +fn debug() { + assert_eq!(format!("{:?}", CachePadded::new(17u64)), "CachePadded(17)"); +} + +#[test] +fn drops() { + let count = Cell::new(0); + + struct Foo<'a>(&'a Cell<usize>); + + impl<'a> Drop for Foo<'a> { + fn drop(&mut self) { + self.0.set(self.0.get() + 1); + } + } + + let a = CachePadded::new(Foo(&count)); + let b = CachePadded::new(Foo(&count)); + + assert_eq!(count.get(), 0); + drop(a); + assert_eq!(count.get(), 1); + drop(b); + assert_eq!(count.get(), 2); +} + +#[test] +fn clone() { + let a = CachePadded::new(17); + let b = a.clone(); + assert_eq!(*a, *b); +} + +#[test] +fn runs_custom_clone() { + let count = Cell::new(0); + + struct Foo<'a>(&'a Cell<usize>); + + impl<'a> Clone for Foo<'a> { + fn clone(&self) -> Foo<'a> { + self.0.set(self.0.get() + 1); + Foo::<'a>(self.0) + } + } + + let a = CachePadded::new(Foo(&count)); + let _ = a.clone(); + + assert_eq!(count.get(), 1); +} |