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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 16:29:51 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 16:29:51 +0000 |
| commit | 6e7a315eb67cb6c113cf37e1d66c4f11a51a2b3e (patch) | |
| tree | 32451fa3cdd9321fb2591fada9891b2cb70a9cd1 /grub-core/kern/powerpc/cache_flush.S | |
| parent | Initial commit. (diff) | |
| download | grub2-6e7a315eb67cb6c113cf37e1d66c4f11a51a2b3e.tar.xz grub2-6e7a315eb67cb6c113cf37e1d66c4f11a51a2b3e.zip | |
Adding upstream version 2.06.upstream/2.06upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'grub-core/kern/powerpc/cache_flush.S')
| -rw-r--r-- | grub-core/kern/powerpc/cache_flush.S | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/grub-core/kern/powerpc/cache_flush.S b/grub-core/kern/powerpc/cache_flush.S new file mode 100644 index 0000000..1410f78 --- /dev/null +++ b/grub-core/kern/powerpc/cache_flush.S @@ -0,0 +1,43 @@ +/* cache.S - Flush the processor cache for a specific region. */ +/* + * GRUB -- GRand Unified Bootloader + * Copyright (C) 2004,2007,2010 Free Software Foundation, Inc. + * + * GRUB is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * GRUB is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with GRUB. If not, see <http://www.gnu.org/licenses/>. + */ + +#undef CACHE_LINE_BYTES +#define CACHE_LINE_BYTES 32 + + /* `address' may not be CACHE_LINE_BYTES-aligned. */ + andi. 6, 3, CACHE_LINE_BYTES - 1 /* Find the misalignment. */ + add 4, 4, 6 /* Adjust `size' to compensate. */ + + /* Force the dcache lines to memory. */ + li 5, 0 +1: dcbst 5, 3 + addi 5, 5, CACHE_LINE_BYTES + cmpw 5, 4 + blt 1b + sync /* Force all dcbsts to complete. */ + + /* Invalidate the icache lines. */ + li 5, 0 +1: icbi 5, 3 + addi 5, 5, CACHE_LINE_BYTES + cmpw 5, 4 + blt 1b + sync /* Force all icbis to complete. */ + isync /* Discard partially executed instructions that were + loaded from the invalid icache. */ |