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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:59 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:59 +0000 |
| commit | 01997497f915e8f79871f3f2acb55ac465051d24 (patch) | |
| tree | 1ce1afd7246e1014199e15cbf854bf7924458e5d /debian/patches/features/arm64 | |
| parent | Adding upstream version 6.1.76. (diff) | |
| download | linux-debian.tar.xz linux-debian.zip | |
Adding debian version 6.1.76-1.debian/6.1.76-1debian
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to '')
21 files changed, 2159 insertions, 0 deletions
diff --git a/debian/patches/features/arm64/arm64-dts-rockchip-Add-Hardkernel-ODROID-M1-board.patch b/debian/patches/features/arm64/arm64-dts-rockchip-Add-Hardkernel-ODROID-M1-board.patch new file mode 100644 index 000000000..18b3218ee --- /dev/null +++ b/debian/patches/features/arm64/arm64-dts-rockchip-Add-Hardkernel-ODROID-M1-board.patch @@ -0,0 +1,454 @@ +From: Dongjin Kim <tobetter@gmail.com> +Date: Fri, 30 Sep 2022 07:12:35 +0200 +Subject: [02/13] arm64: dts: rockchip: Add Hardkernel ODROID-M1 board +Origin: https://git.kernel.org/linus/fd35832677032980df230f02509d6c016664cc89 + +This patch is to add a device tree for new board Hardkernel ODROID-M1 +based on Rockchip RK3568, includes basic peripherals - +uart/eMMC/uSD/i2c and on-board ethernet. + +Signed-off-by: Dongjin Kim <tobetter@gmail.com> +[aurelien@aurel32.net: addressed issues from initial review] +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> +Tested-by: Dan Johansen <strit@manjaro.org> +Link: https://lore.kernel.org/r/20220930051246.391614-3-aurelien@aurel32.net +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../boot/dts/rockchip/rk3568-odroid-m1.dts | 414 ++++++++++++++++++ + 2 files changed, 415 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index a5a6262936f0..68cc720a623a 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -72,4 +72,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +new file mode 100644 +index 000000000000..b3016437640b +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +@@ -0,0 +1,414 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++/* ++ * Copyright (c) 2022 Hardkernel Co., Ltd. ++ * ++ */ ++ ++/dts-v1/; ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/leds/common.h> ++#include <dt-bindings/pinctrl/rockchip.h> ++#include "rk3568.dtsi" ++ ++/ { ++ model = "Hardkernel ODROID-M1"; ++ compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568"; ++ ++ aliases { ++ ethernet0 = &gmac0; ++ i2c0 = &i2c3; ++ i2c3 = &i2c0; ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; ++ serial0 = &uart1; ++ serial1 = &uart0; ++ }; ++ ++ chosen { ++ stdout-path = "serial2:1500000n8"; ++ }; ++ ++ dc_12v: dc-12v-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "dc_12v"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_power: led-0 { ++ gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; ++ function = LED_FUNCTION_POWER; ++ color = <LED_COLOR_ID_RED>; ++ default-state = "keep"; ++ linux,default-trigger = "default-on"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_power_pin>; ++ }; ++ led_work: led-1 { ++ gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; ++ function = LED_FUNCTION_HEARTBEAT; ++ color = <LED_COLOR_ID_BLUE>; ++ linux,default-trigger = "heartbeat"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&led_work_pin>; ++ }; ++ }; ++ ++ vcc3v3_sys: vcc3v3-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&dc_12v>; ++ }; ++}; ++ ++&cpu0 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu1 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu2 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&cpu3 { ++ cpu-supply = <&vdd_cpu>; ++}; ++ ++&gmac0 { ++ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; ++ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>; ++ assigned-clock-rates = <0>, <125000000>; ++ clock_in_out = "output"; ++ phy-handle = <&rgmii_phy0>; ++ phy-mode = "rgmii"; ++ phy-supply = <&vcc3v3_sys>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&gmac0_miim ++ &gmac0_tx_bus2 ++ &gmac0_rx_bus2 ++ &gmac0_rgmii_clk ++ &gmac0_rgmii_bus>; ++ status = "okay"; ++ ++ tx_delay = <0x4f>; ++ rx_delay = <0x2d>; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ ++ vdd_cpu: regulator@1c { ++ compatible = "tcs,tcs4525"; ++ reg = <0x1c>; ++ fcs,suspend-voltage-selector = <1>; ++ regulator-name = "vdd_cpu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1150000>; ++ regulator-ramp-delay = <2300>; ++ vin-supply = <&vcc3v3_sys>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ rk809: pmic@20 { ++ compatible = "rockchip,rk809"; ++ reg = <0x20>; ++ interrupt-parent = <&gpio0>; ++ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; ++ #clock-cells = <1>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pmic_int_l>; ++ rockchip,system-power-controller; ++ vcc1-supply = <&vcc3v3_sys>; ++ vcc2-supply = <&vcc3v3_sys>; ++ vcc3-supply = <&vcc3v3_sys>; ++ vcc4-supply = <&vcc3v3_sys>; ++ vcc5-supply = <&vcc3v3_sys>; ++ vcc6-supply = <&vcc3v3_sys>; ++ vcc7-supply = <&vcc3v3_sys>; ++ vcc8-supply = <&vcc3v3_sys>; ++ vcc9-supply = <&vcc3v3_sys>; ++ wakeup-source; ++ ++ regulators { ++ vdd_logic: DCDC_REG1 { ++ regulator-name = "vdd_logic"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdd_gpu: DCDC_REG2 { ++ regulator-name = "vdd_gpu"; ++ regulator-always-on; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_ddr: DCDC_REG3 { ++ regulator-name = "vcc_ddr"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-initial-mode = <0x2>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ }; ++ }; ++ ++ vdd_npu: DCDC_REG4 { ++ regulator-name = "vdd_npu"; ++ regulator-init-microvolt = <900000>; ++ regulator-initial-mode = <0x2>; ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1350000>; ++ regulator-ramp-delay = <6001>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_1v8: DCDC_REG5 { ++ regulator-name = "vcc_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_image: LDO_REG1 { ++ regulator-name = "vdda0v9_image"; ++ regulator-always-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda_0v9: LDO_REG2 { ++ regulator-name = "vdda_0v9"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vdda0v9_pmu: LDO_REG3 { ++ regulator-name = "vdda0v9_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <900000>; ++ regulator-max-microvolt = <900000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <900000>; ++ }; ++ }; ++ ++ vccio_acodec: LDO_REG4 { ++ regulator-name = "vccio_acodec"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vccio_sd: LDO_REG5 { ++ regulator-name = "vccio_sd"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_pmu: LDO_REG6 { ++ regulator-name = "vcc3v3_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <3300000>; ++ }; ++ }; ++ ++ vcca_1v8: LDO_REG7 { ++ regulator-name = "vcca_1v8"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcca1v8_pmu: LDO_REG8 { ++ regulator-name = "vcca1v8_pmu"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-on-in-suspend; ++ regulator-suspend-microvolt = <1800000>; ++ }; ++ }; ++ ++ vcca1v8_image: LDO_REG9 { ++ regulator-name = "vcca1v8_image"; ++ regulator-always-on; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc_3v3: SWITCH_REG1 { ++ regulator-name = "vcc_3v3"; ++ regulator-always-on; ++ regulator-boot-on; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ ++ vcc3v3_sd: SWITCH_REG2 { ++ regulator-name = "vcc3v3_sd"; ++ ++ regulator-state-mem { ++ regulator-off-in-suspend; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++&mdio0 { ++ rgmii_phy0: ethernet-phy@0 { ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0x0>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; ++ }; ++}; ++ ++&pinctrl { ++ leds { ++ led_power_pin: led-power-pin { ++ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ led_work_pin: led-work-pin { ++ rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ ++ pmic { ++ pmic_int_l: pmic-int-l { ++ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; ++ }; ++ }; ++}; ++ ++&pmu_io_domains { ++ pmuio1-supply = <&vcc3v3_pmu>; ++ pmuio2-supply = <&vcc3v3_pmu>; ++ vccio1-supply = <&vccio_acodec>; ++ vccio2-supply = <&vcc_1v8>; ++ vccio3-supply = <&vccio_sd>; ++ vccio4-supply = <&vcc_1v8>; ++ vccio5-supply = <&vcc_3v3>; ++ vccio6-supply = <&vcc_3v3>; ++ vccio7-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ ++&saradc { ++ vref-supply = <&vcca_1v8>; ++ status = "okay"; ++}; ++ ++&sdhci { ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>; ++ vmmc-supply = <&vcc_3v3>; ++ vqmmc-supply = <&vcc_1v8>; ++ status = "okay"; ++}; ++ ++&sdmmc0 { ++ bus-width = <4>; ++ cap-sd-highspeed; ++ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>; ++ disable-wp; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>; ++ sd-uhs-sdr50; ++ vmmc-supply = <&vcc3v3_sd>; ++ vqmmc-supply = <&vccio_sd>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ status = "okay"; ++}; +-- +2.35.1 + diff --git a/debian/patches/features/arm64/arm64-dts-rockchip-Add-IR-receiver-node-to-ODROID-M1.patch b/debian/patches/features/arm64/arm64-dts-rockchip-Add-IR-receiver-node-to-ODROID-M1.patch new file mode 100644 index 000000000..c94e717a5 --- /dev/null +++ b/debian/patches/features/arm64/arm64-dts-rockchip-Add-IR-receiver-node-to-ODROID-M1.patch @@ -0,0 +1,51 @@ +From: Aurelien Jarno <aurelien@aurel32.net> +Date: Fri, 30 Sep 2022 07:12:46 +0200 +Subject: [13/13] arm64: dts: rockchip: Add IR receiver node to ODROID-M1 +Origin: https://git.kernel.org/linus/d6882992fe8182e3122be34af3f491948a8b9069 + +Add the infrared receiver and its associated pinctrl entry. Note that +there is an external pullup to VCC3V3_SYS. + +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> +Tested-by: Dan Johansen <strit@manjaro.org> +Link: https://lore.kernel.org/r/20220930051246.391614-14-aurelien@aurel32.net +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 14 ++++++++++++++ + 1 file changed, 14 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +index 2f685c606bb9..59ecf868dbd0 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +@@ -49,6 +49,13 @@ hdmi_con_in: endpoint { + }; + }; + ++ ir-receiver { ++ compatible = "gpio-ir-receiver"; ++ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ir_receiver_pin>; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -519,6 +526,13 @@ fspi_dual_io_pins: fspi-dual-io-pins { + }; + }; + ++ ir-receiver { ++ ir_receiver_pin: ir-receiver-pin { ++ /* external pullup to VCC3V3_SYS */ ++ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + leds { + led_power_pin: led-power-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +-- +2.35.1 + diff --git a/debian/patches/features/arm64/arm64-dts-rockchip-Add-NOR-flash-to-ODROID-M1.patch b/debian/patches/features/arm64/arm64-dts-rockchip-Add-NOR-flash-to-ODROID-M1.patch new file mode 100644 index 000000000..ebc21afec --- /dev/null +++ b/debian/patches/features/arm64/arm64-dts-rockchip-Add-NOR-flash-to-ODROID-M1.patch @@ -0,0 +1,100 @@ +From: Aurelien Jarno <aurelien@aurel32.net> +Date: Fri, 30 Sep 2022 07:12:37 +0200 +Subject: [04/13] arm64: dts: rockchip: Add NOR flash to ODROID-M1 +Origin: https://git.kernel.org/linus/9f96204b7dcf94d03cad41194447c665d10675b7 + +Enable the Rockchip Serial Flash Controller for the ODROID-M1 and add +the corresponding SPI NOR flash entry. The SFC is used in dual I/O mode +and not quad I/O mode, as the FSPI_D2 pin is shared with the EMMC_RSTn +pin. + +The partitions addresses and sizes are taken from the ODROID-M1 +Partition Table page on the ODROID wiki. + +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> +Tested-by: Dan Johansen <strit@manjaro.org> +Link: https://lore.kernel.org/r/20220930051246.391614-5-aurelien@aurel32.net +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + .../boot/dts/rockchip/rk3568-odroid-m1.dts | 58 +++++++++++++++++++ + 1 file changed, 58 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +index 112c65af3f55..94e839c9afab 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +@@ -351,6 +351,20 @@ rgmii_phy0: ethernet-phy@0 { + }; + + &pinctrl { ++ fspi { ++ fspi_dual_io_pins: fspi-dual-io-pins { ++ rockchip,pins = ++ /* fspi_clk */ ++ <1 RK_PD0 1 &pcfg_pull_none>, ++ /* fspi_cs0n */ ++ <1 RK_PD3 1 &pcfg_pull_none>, ++ /* fspi_d0 */ ++ <1 RK_PD1 1 &pcfg_pull_none>, ++ /* fspi_d1 */ ++ <1 RK_PD2 1 &pcfg_pull_none>; ++ }; ++ }; ++ + leds { + led_power_pin: led-power-pin { + rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; +@@ -409,6 +423,50 @@ &sdmmc0 { + status = "okay"; + }; + ++&sfc { ++ /* Dual I/O mode as the D2 pin conflicts with the eMMC */ ++ pinctrl-0 = <&fspi_dual_io_pins>; ++ pinctrl-names = "default"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ flash@0 { ++ compatible = "jedec,spi-nor"; ++ reg = <0>; ++ spi-max-frequency = <100000000>; ++ spi-rx-bus-width = <2>; ++ spi-tx-bus-width = <1>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "SPL"; ++ reg = <0x0 0xe0000>; ++ }; ++ partition@e0000 { ++ label = "U-Boot Env"; ++ reg = <0xe0000 0x20000>; ++ }; ++ partition@100000 { ++ label = "U-Boot"; ++ reg = <0x100000 0x200000>; ++ }; ++ partition@300000 { ++ label = "splash"; ++ reg = <0x300000 0x100000>; ++ }; ++ partition@400000 { ++ label = "Filesystem"; ++ reg = <0x400000 0xc00000>; ++ }; ++ }; ++ }; ++}; ++ + &tsadc { + rockchip,hw-tshut-mode = <1>; + rockchip,hw-tshut-polarity = <0>; +-- +2.35.1 + diff --git a/debian/patches/features/arm64/arm64-dts-rockchip-Add-PCIEe-v3-nodes-to-ODROID-M1.patch b/debian/patches/features/arm64/arm64-dts-rockchip-Add-PCIEe-v3-nodes-to-ODROID-M1.patch new file mode 100644 index 000000000..94c7d7952 --- /dev/null +++ b/debian/patches/features/arm64/arm64-dts-rockchip-Add-PCIEe-v3-nodes-to-ODROID-M1.patch @@ -0,0 +1,77 @@ +From: Aurelien Jarno <aurelien@aurel32.net> +Date: Fri, 30 Sep 2022 07:12:45 +0200 +Subject: [12/13] arm64: dts: rockchip: Add PCIEe v3 nodes to ODROID-M1 +Origin: https://git.kernel.org/linus/35b28582aa3dfd7b6861b7ebc72798b0ff50ed41 + +Add nodes to ODROID-M1 to support PCIe v3 on the M2 slot. + +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> +Tested-by: Dan Johansen <strit@manjaro.org> +Link: https://lore.kernel.org/r/20220930051246.391614-13-aurelien@aurel32.net +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + .../boot/dts/rockchip/rk3568-odroid-m1.dts | 34 +++++++++++++++++++ + 1 file changed, 34 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +index bd24ccf94e76..2f685c606bb9 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +@@ -96,6 +96,19 @@ simple-audio-card,codec { + }; + }; + ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie"; ++ enable-active-high; ++ gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc3v3_pcie_en_pin>; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ startup-delay-us = <5000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; +@@ -479,6 +492,18 @@ rgmii_phy0: ethernet-phy@0 { + }; + }; + ++&pcie30phy { ++ status = "okay"; ++}; ++ ++&pcie3x2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_reset_pin>; ++ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ + &pinctrl { + fspi { + fspi_dual_io_pins: fspi-dual-io-pins { +@@ -503,6 +528,15 @@ led_work_pin: led-work-pin { + }; + }; + ++ pcie { ++ pcie_reset_pin: pcie-reset-pin { ++ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin { ++ rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; +-- +2.35.1 + diff --git a/debian/patches/features/arm64/arm64-dts-rockchip-Add-SATA-support-to-ODROID-M1.patch b/debian/patches/features/arm64/arm64-dts-rockchip-Add-SATA-support-to-ODROID-M1.patch new file mode 100644 index 000000000..2025079e1 --- /dev/null +++ b/debian/patches/features/arm64/arm64-dts-rockchip-Add-SATA-support-to-ODROID-M1.patch @@ -0,0 +1,45 @@ +From: Aurelien Jarno <aurelien@aurel32.net> +Date: Fri, 30 Sep 2022 07:12:44 +0200 +Subject: [11/13] arm64: dts: rockchip: Add SATA support to ODROID-M1 +Origin: https://git.kernel.org/linus/6a5a04d52ccc42e0e59ff69fca9c1db7e08ba44b + +Enable the Combo PHY and SATA nodes in ODROID-M1. + +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> +Tested-by: Dan Johansen <strit@manjaro.org> +Link: https://lore.kernel.org/r/20220930051246.391614-12-aurelien@aurel32.net +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +index 9a84a7e76d7a..bd24ccf94e76 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +@@ -153,6 +153,11 @@ &combphy1 { + status = "okay"; + }; + ++&combphy2 { ++ /* used for SATA */ ++ status = "okay"; ++}; ++ + &cpu0 { + cpu-supply = <&vdd_cpu>; + }; +@@ -538,6 +543,10 @@ &saradc { + status = "okay"; + }; + ++&sata2 { ++ status = "okay"; ++}; ++ + &sdhci { + bus-width = <8>; + max-frequency = <200000000>; +-- +2.35.1 + diff --git a/debian/patches/features/arm64/arm64-dts-rockchip-Add-analog-audio-on-ODROID-M1.patch b/debian/patches/features/arm64/arm64-dts-rockchip-Add-analog-audio-on-ODROID-M1.patch new file mode 100644 index 000000000..03cb99ff1 --- /dev/null +++ b/debian/patches/features/arm64/arm64-dts-rockchip-Add-analog-audio-on-ODROID-M1.patch @@ -0,0 +1,99 @@ +From: Aurelien Jarno <aurelien@aurel32.net> +Date: Fri, 30 Sep 2022 07:12:38 +0200 +Subject: [05/13] arm64: dts: rockchip: Add analog audio on ODROID-M1 +Origin: https://git.kernel.org/linus/78f858447cb78cac7259093d095fb783328b835c + +On the ODROID-M1, the I2S1 TDM controller is connected to the rk809 +codec in I2S mode. It is used to provide a stereo headphones output and +a mono speaker output. A GPIO with an external pullup is used as an +headphone detection input. + +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> +Tested-by: Dan Johansen <strit@manjaro.org> +Link: https://lore.kernel.org/r/20220930051246.391614-6-aurelien@aurel32.net +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + .../boot/dts/rockchip/rk3568-odroid-m1.dts | 43 ++++++++++++++++++- + 1 file changed, 42 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +index 94e839c9afab..634c1bd80b4e 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +@@ -59,6 +59,31 @@ led_work: led-1 { + }; + }; + ++ rk809-sound { ++ compatible = "simple-audio-card"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&hp_det_pin>; ++ simple-audio-card,name = "Analog RK817"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>; ++ simple-audio-card,mclk-fs = <256>; ++ simple-audio-card,widgets = ++ "Headphone", "Headphones", ++ "Speaker", "Speaker"; ++ simple-audio-card,routing = ++ "Headphones", "HPOL", ++ "Headphones", "HPOR", ++ "Speaker", "SPKO"; ++ ++ simple-audio-card,cpu { ++ sound-dai = <&i2s1_8ch>; ++ }; ++ ++ simple-audio-card,codec { ++ sound-dai = <&rk809>; ++ }; ++ }; ++ + vcc3v3_sys: vcc3v3-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3_sys"; +@@ -131,10 +156,15 @@ rk809: pmic@20 { + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>; ++ assigned-clocks = <&cru I2S1_MCLKOUT_TX>; ++ assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>; + #clock-cells = <1>; ++ clock-names = "mclk"; ++ clocks = <&cru I2S1_MCLKOUT_TX>; + pinctrl-names = "default"; +- pinctrl-0 = <&pmic_int_l>; ++ pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>; + rockchip,system-power-controller; ++ #sound-dai-cells = <0>; + vcc1-supply = <&vcc3v3_sys>; + vcc2-supply = <&vcc3v3_sys>; + vcc3-supply = <&vcc3v3_sys>; +@@ -340,6 +370,11 @@ regulator-state-mem { + }; + }; + ++&i2s1_8ch { ++ rockchip,trcm-sync-tx-only; ++ status = "okay"; ++}; ++ + &mdio0 { + rgmii_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; +@@ -379,6 +414,12 @@ pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; ++ ++ rk809 { ++ hp_det_pin: hp-det-pin { ++ rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; + }; + + &pmu_io_domains { +-- +2.35.1 + diff --git a/debian/patches/features/arm64/arm64-dts-rockchip-Enable-HDMI-audio-on-ODROID-M1.patch b/debian/patches/features/arm64/arm64-dts-rockchip-Enable-HDMI-audio-on-ODROID-M1.patch new file mode 100644 index 000000000..0dff4d2b7 --- /dev/null +++ b/debian/patches/features/arm64/arm64-dts-rockchip-Enable-HDMI-audio-on-ODROID-M1.patch @@ -0,0 +1,45 @@ +From: Aurelien Jarno <aurelien@aurel32.net> +Date: Fri, 30 Sep 2022 07:12:40 +0200 +Subject: [07/13] arm64: dts: rockchip: Enable HDMI audio on ODROID-M1. +Origin: https://git.kernel.org/linus/1ca7ddddf36494f0f6afd4f35d37827323271f39 + +This enables the i2s0 controller and the hdmi-sound node on the +ODROID-M1. + +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> +Tested-by: Dan Johansen <strit@manjaro.org> +Link: https://lore.kernel.org/r/20220930051246.391614-8-aurelien@aurel32.net +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +index 126b893048fe..ac4e94d18feb 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +@@ -161,6 +161,10 @@ hdmi_out_con: endpoint { + }; + }; + ++&hdmi_sound { ++ status = "okay"; ++}; ++ + &i2c0 { + status = "okay"; + +@@ -400,6 +404,10 @@ regulator-state-mem { + }; + }; + ++&i2s0_8ch { ++ status = "okay"; ++}; ++ + &i2s1_8ch { + rockchip,trcm-sync-tx-only; + status = "okay"; +-- +2.35.1 + diff --git a/debian/patches/features/arm64/arm64-dts-rockchip-Enable-the-GPU-on-ODROID-M1.patch b/debian/patches/features/arm64/arm64-dts-rockchip-Enable-the-GPU-on-ODROID-M1.patch new file mode 100644 index 000000000..faed83fca --- /dev/null +++ b/debian/patches/features/arm64/arm64-dts-rockchip-Enable-the-GPU-on-ODROID-M1.patch @@ -0,0 +1,34 @@ +From: Aurelien Jarno <aurelien@aurel32.net> +Date: Fri, 30 Sep 2022 07:12:41 +0200 +Subject: [08/13] arm64: dts: rockchip: Enable the GPU on ODROID-M1 +Origin: https://git.kernel.org/linus/cb80b3455c7cadc4c1157879930e919f607d557c + +Enable the GPU core on the Rockchip RK3568 ODROID-M1. + +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> +Tested-by: Dan Johansen <strit@manjaro.org> +Link: https://lore.kernel.org/r/20220930051246.391614-9-aurelien@aurel32.net +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +index ac4e94d18feb..e4b7699d3eea 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +@@ -143,6 +143,11 @@ &gmac0_rgmii_clk + rx_delay = <0x2d>; + }; + ++&gpu { ++ mali-supply = <&vdd_gpu>; ++ status = "okay"; ++}; ++ + &hdmi { + avdd-0v9-supply = <&vdda0v9_image>; + avdd-1v8-supply = <&vcca1v8_image>; +-- +2.35.1 + diff --git a/debian/patches/features/arm64/arm64-dts-rockchip-Enable-the-USB-2.0-ports-on-ODROI.patch b/debian/patches/features/arm64/arm64-dts-rockchip-Enable-the-USB-2.0-ports-on-ODROI.patch new file mode 100644 index 000000000..c27944417 --- /dev/null +++ b/debian/patches/features/arm64/arm64-dts-rockchip-Enable-the-USB-2.0-ports-on-ODROI.patch @@ -0,0 +1,108 @@ +From: Aurelien Jarno <aurelien@aurel32.net> +Date: Fri, 30 Sep 2022 07:12:42 +0200 +Subject: [09/13] arm64: dts: rockchip: Enable the USB 2.0 ports on ODROID-M1 +Origin: https://git.kernel.org/linus/4685d7b68aaac199ab0d950d2047405bf551f964 + +The Rockchip RK3568 has two USB OHCI/EHCI controllers connected to a PHY +providing one host-only port and one OTG port. On the ODROID-M1, they +are both used in host mode. The USB ports are powered by a DC/DC +converter providing 5V and named VCC5V0_SYS on the schematics, followed +by a power switch. + +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> +Tested-by: Dan Johansen <strit@manjaro.org> +Link: https://lore.kernel.org/r/20220930051246.391614-10-aurelien@aurel32.net +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + .../boot/dts/rockchip/rk3568-odroid-m1.dts | 61 +++++++++++++++++++ + 1 file changed, 61 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +index e4b7699d3eea..2e4cc20bd676 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +@@ -105,6 +105,28 @@ vcc3v3_sys: vcc3v3-sys-regulator { + regulator-max-microvolt = <3300000>; + vin-supply = <&dc_12v>; + }; ++ ++ vcc5v0_sys: vcc5v0-sys-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_sys"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&dc_12v>; ++ }; ++ ++ vcc5v0_usb_host: vcc5v0-usb-host-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb_host"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_host_en_pin>; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; + }; + + &cpu0 { +@@ -463,6 +485,15 @@ hp_det_pin: hp-det-pin { + rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; ++ ++ usb { ++ vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin { ++ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ vcc5v0_usb_otg_en_pin: vcc5v0-usb-otg-en-pin { ++ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; + }; + + &pmu_io_domains { +@@ -561,6 +592,36 @@ &uart2 { + status = "okay"; + }; + ++&usb_host0_ehci { ++ status = "okay"; ++}; ++ ++&usb_host0_ohci { ++ status = "okay"; ++}; ++ ++&usb_host1_ehci { ++ status = "okay"; ++}; ++ ++&usb_host1_ohci { ++ status = "okay"; ++}; ++ ++&usb2phy1 { ++ status = "okay"; ++}; ++ ++&usb2phy1_host { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&usb2phy1_otg { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ + &vop { + assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; + assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; +-- +2.35.1 + diff --git a/debian/patches/features/arm64/arm64-dts-rockchip-Enable-the-USB-3.0-ports-on-ODROI.patch b/debian/patches/features/arm64/arm64-dts-rockchip-Enable-the-USB-3.0-ports-on-ODROI.patch new file mode 100644 index 000000000..bfcf9c523 --- /dev/null +++ b/debian/patches/features/arm64/arm64-dts-rockchip-Enable-the-USB-3.0-ports-on-ODROI.patch @@ -0,0 +1,111 @@ +From: Aurelien Jarno <aurelien@aurel32.net> +Date: Fri, 30 Sep 2022 07:12:43 +0200 +Subject: [10/13] arm64: dts: rockchip: Enable the USB 3.0 ports on ODROID-M1 +Origin: https://git.kernel.org/linus/9984ef562653c8d0beb51021fc286706b6ec4802 + +The Rockchip RK3568 has two USB XHCI controllers. The USB 2.0 signals +are connected to a PHY providing one host-only port and one OTG port. +The USB 3.0 signals are connected to two USB3.0/PCIE/SATA combo PHY. + +The ODROID M1 has 2 type A USB 3.0 connectors, with the USB 3.0 signals +connected to the two combo PHYs. For the USB 2.0 signals, one connector +is connected to the host-only PHY and uses the same power switch as the +USB 2.0 ports. The other connector has its own power switch and is +connected to the OTG PHY, which is also connected to a device only +micro-USB connector. The purpose of this micro-USB connector is for +firmware update using the Rockusb vendor specific USB class. Therefore +it does not make sense to enable this port on Linux, and the PHY is +forced to host mode. + +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> +Tested-by: Dan Johansen <strit@manjaro.org> +Link: https://lore.kernel.org/r/20220930051246.391614-11-aurelien@aurel32.net +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + .../boot/dts/rockchip/rk3568-odroid-m1.dts | 49 ++++++++++++++++++- + 1 file changed, 48 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +index 2e4cc20bd676..9a84a7e76d7a 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +@@ -127,6 +127,30 @@ vcc5v0_usb_host: vcc5v0-usb-host-regulator { + regulator-max-microvolt = <5000000>; + vin-supply = <&vcc5v0_sys>; + }; ++ ++ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb_otg"; ++ enable-active-high; ++ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&vcc5v0_usb_otg_en_pin>; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc5v0_sys>; ++ }; ++}; ++ ++&combphy0 { ++ /* Used for USB3 */ ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&combphy1 { ++ /* Used for USB3 */ ++ phy-supply = <&vcc5v0_usb_otg>; ++ status = "okay"; + }; + + &cpu0 { +@@ -490,7 +514,7 @@ usb { + vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin { + rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; + }; +- vcc5v0_usb_otg_en_pin: vcc5v0-usb-otg-en-pin { ++ vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin { + rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +@@ -600,6 +624,11 @@ &usb_host0_ohci { + status = "okay"; + }; + ++&usb_host0_xhci { ++ dr_mode = "host"; ++ status = "okay"; ++}; ++ + &usb_host1_ehci { + status = "okay"; + }; +@@ -608,6 +637,24 @@ &usb_host1_ohci { + status = "okay"; + }; + ++&usb_host1_xhci { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_host { ++ phy-supply = <&vcc5v0_usb_host>; ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ phy-supply = <&vcc5v0_usb_otg>; ++ status = "okay"; ++}; ++ + &usb2phy1 { + status = "okay"; + }; +-- +2.35.1 + diff --git a/debian/patches/features/arm64/arm64-dts-rockchip-Enable-vop2-and-hdmi-tx-on-ODROID.patch b/debian/patches/features/arm64/arm64-dts-rockchip-Enable-vop2-and-hdmi-tx-on-ODROID.patch new file mode 100644 index 000000000..48d1b3642 --- /dev/null +++ b/debian/patches/features/arm64/arm64-dts-rockchip-Enable-vop2-and-hdmi-tx-on-ODROID.patch @@ -0,0 +1,94 @@ +From: Aurelien Jarno <aurelien@aurel32.net> +Date: Fri, 30 Sep 2022 07:12:39 +0200 +Subject: [06/13] arm64: dts: rockchip: Enable vop2 and hdmi tx on ODROID-M1 +Origin: https://git.kernel.org/linus/913404aa2e60610f9cae375069dae97e11d726ed + +Enable the RK356x Video Output Processor (VOP) 2 on ODROID M1. + +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> +Tested-by: Dan Johansen <strit@manjaro.org> +Link: https://lore.kernel.org/r/20220930051246.391614-7-aurelien@aurel32.net +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + .../boot/dts/rockchip/rk3568-odroid-m1.dts | 47 +++++++++++++++++++ + 1 file changed, 47 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +index 634c1bd80b4e..126b893048fe 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +@@ -8,6 +8,7 @@ + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/leds/common.h> + #include <dt-bindings/pinctrl/rockchip.h> ++#include <dt-bindings/soc/rockchip,vop2.h> + #include "rk3568.dtsi" + + / { +@@ -37,6 +38,17 @@ dc_12v: dc-12v-regulator { + regulator-max-microvolt = <12000000>; + }; + ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -131,6 +143,24 @@ &gmac0_rgmii_clk + rx_delay = <0x2d>; + }; + ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &i2c0 { + status = "okay"; + +@@ -517,3 +547,20 @@ &tsadc { + &uart2 { + status = "okay"; + }; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = <ROCKCHIP_VOP2_EP_HDMI0>; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; +-- +2.35.1 + diff --git a/debian/patches/features/arm64/arm64-dts-rockchip-add-thermal-support-to-ODROID-M1.patch b/debian/patches/features/arm64/arm64-dts-rockchip-add-thermal-support-to-ODROID-M1.patch new file mode 100644 index 000000000..5e0970dba --- /dev/null +++ b/debian/patches/features/arm64/arm64-dts-rockchip-add-thermal-support-to-ODROID-M1.patch @@ -0,0 +1,35 @@ +From: Aurelien Jarno <aurelien@aurel32.net> +Date: Fri, 30 Sep 2022 07:12:36 +0200 +Subject: [03/13] arm64: dts: rockchip: add thermal support to ODROID-M1 +Origin: https://git.kernel.org/linus/f5511bd8498da222b6455038a0cf3e7d2b2dfc7e + +Add the thermal nodes for the ODROID-M1. + +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> +Tested-by: Dan Johansen <strit@manjaro.org> +Link: https://lore.kernel.org/r/20220930051246.391614-4-aurelien@aurel32.net +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 6 ++++++ + 1 file changed, 6 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +index b3016437640b..112c65af3f55 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts +@@ -409,6 +409,12 @@ &sdmmc0 { + status = "okay"; + }; + ++&tsadc { ++ rockchip,hw-tshut-mode = <1>; ++ rockchip,hw-tshut-polarity = <0>; ++ status = "okay"; ++}; ++ + &uart2 { + status = "okay"; + }; +-- +2.35.1 + diff --git a/debian/patches/features/arm64/dt-bindings-rockchip-Add-Hardkernel-ODROID-M1-board.patch b/debian/patches/features/arm64/dt-bindings-rockchip-Add-Hardkernel-ODROID-M1-board.patch new file mode 100644 index 000000000..54d0c6c20 --- /dev/null +++ b/debian/patches/features/arm64/dt-bindings-rockchip-Add-Hardkernel-ODROID-M1-board.patch @@ -0,0 +1,37 @@ +From: Dongjin Kim <tobetter@gmail.com> +Date: Fri, 30 Sep 2022 07:12:34 +0200 +Subject: [01/13] dt-bindings: rockchip: Add Hardkernel ODROID-M1 board +Origin: https://git.kernel.org/linus/19cc53eb2ce63c0e5adc2fd89494fb16f383ac10 + +Add device tree binding for Hardkernel ODROID-M1 board based on RK3568 +SoC. + +Signed-off-by: Dongjin Kim <tobetter@gmail.com> +Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> +Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> +Tested-by: Dan Johansen <strit@manjaro.org> +Link: https://lore.kernel.org/r/20220930051246.391614-2-aurelien@aurel32.net +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ + 1 file changed, 5 insertions(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index eee1e6b3f9cb..72bf2fbfe99d 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -468,6 +468,11 @@ properties: + - const: hardkernel,rk3326-odroid-go2 + - const: rockchip,rk3326 + ++ - description: Hardkernel Odroid M1 ++ items: ++ - const: rockchip,rk3568-odroid-m1 ++ - const: rockchip,rk3568 ++ + - description: Hugsun X99 TV Box + items: + - const: hugsun,x99 +-- +2.35.1 + diff --git a/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Add-SOQuartz-Model-A-baseboard.patch b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Add-SOQuartz-Model-A-baseboard.patch new file mode 100644 index 000000000..ae644e05f --- /dev/null +++ b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Add-SOQuartz-Model-A-baseboard.patch @@ -0,0 +1,279 @@ +From: Andrew Powers-Holmes <aholmes@omnom.net> +Date: Wed, 16 Nov 2022 12:53:37 +0100 +Subject: [4/4] arm64: dts: rockchip: Add SOQuartz Model A baseboard +Origin: https://git.kernel.org/linus/afbaed737fb45bcae91e4606025fb31da71b9dfe + +This patch adds the device tree for the "Model A" baseboard for +the SOQuartz CM4 SoM, which is not to be confused with the +Quartz64 Model A, which is the same form factor and SoC, but is +not a CM4 carrier board. + +The board features a PCIe 2 x1 slot, USB 2 host ports, CSI/DSI +connectors, an eDP FFC connector, gigabit ethernet, HDMI, and a +12V DC barrel jack. Also present is a microSD card slot, 40-pin +GPIO, and a power and reset button. + +Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net> +[rebase, misc fixes, reword] +Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> +Link: https://lore.kernel.org/r/20221116115337.541601-5-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../dts/rockchip/rk3566-soquartz-model-a.dts | 232 ++++++++++++++++++ + 2 files changed, 233 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index 071284a46bf7..0a76a2ebb5f6 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts +new file mode 100644 +index 000000000000..2208dbfb7f0a +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts +@@ -0,0 +1,232 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include "rk3566-soquartz.dtsi" ++ ++/ { ++ model = "PINE64 RK3566 SOQuartz on Model A carrier board"; ++ compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566"; ++ ++ /* labeled DCIN_12V in schematic */ ++ vcc12v_dcin: vcc12v-dcin-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc12v_dcin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ }; ++ ++ vcc5v0_usb: vcc5v0-usb-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v0_usb"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ vin-supply = <&vcc12v_dcin>; ++ }; ++ ++ /* ++ * Labelled VCC3V0_SD in schematic to not conflict with PMIC ++ * regulator, it's 3.3v in actuality ++ */ ++ vcc3v0_sd: vcc3v0-sd-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v0_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ vcc3v3_pcie: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc12v_dcin>; ++ }; ++ ++ vcc12v_pcie: vcc12v-pcie-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc12v_pcie"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ vin-supply = <&vcc12v_dcin>; ++ }; ++}; ++ ++/* phy for pcie */ ++&combphy2 { ++ phy-supply = <&vcc3v3_sys>; ++ status = "okay"; ++}; ++ ++&gmac1 { ++ status = "okay"; ++}; ++ ++/* ++ * i2c1 is exposed on CM1 / Module1A ++ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu ++ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu ++ */ ++&i2c1 { ++ status = "okay"; ++ ++ /* ++ * the rtc interrupt is tied to PMIC_PWRON, ++ * it will force reset the board if triggered. ++ */ ++ pcf85063: rtc@51 { ++ compatible = "nxp,pcf85063"; ++ reg = <0x51>; ++ }; ++}; ++ ++/* ++ * i2c2 is exposed on CM1 / Module1A - to PI40 ++ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch ++ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 ++ */ ++&i2c2 { ++ status = "disabled"; ++}; ++ ++/* ++ * i2c3 is exposed on CM1 / Module1A - to PI40 ++ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 ++ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 ++ */ ++&i2c3 { ++ status = "disabled"; ++}; ++ ++/* ++ * i2c4 is exposed on CM2 / Module1B - to PI40 ++ * pin 45 - GPIO24 - i2c4_scl_m1 ++ * pin 47 - GPIO23 - i2c4_sda_m1 ++ */ ++&i2c4 { ++ status = "disabled"; ++}; ++ ++/* ++ * i2s1_8ch is exposed on CM1 / Module1A - to PI40 ++ * pin 24 - GPIO26 - i2s1_sdi1_m1 ++ * pin 25 - GPIO21 - i2s1_sdo0_m1 ++ * pin 26 - GPIO19 - i2s1_lrck_tx_m1 ++ * pin 27 - GPIO20 - i2s1_sdi0_m1 ++ * pin 29 - GPIO16 - i2s1_sdi3_m1 ++ * pin 30 - GPIO6 - i2s1_sdi2_m1 ++ * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 ++ * pin 41 - GPIO25 - i2s1_sdo2_m1 ++ * pin 49 - GPIO18 - i2s1_sclk_tx_m1 ++ * pin 50 - GPIO17 - i2s1_mclk_m1 ++ * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 ++ */ ++&i2s1_8ch { ++ status = "disabled"; ++}; ++ ++&led_diy { ++ status = "okay"; ++}; ++ ++&led_work { ++ status = "okay"; ++}; ++ ++&pcie2x1 { ++ vpcie3v3-supply = <&vcc3v3_pcie>; ++ status = "okay"; ++}; ++ ++&rgmii_phy1 { ++ status = "okay"; ++}; ++ ++&rgmii_phy1 { ++ status = "okay"; ++}; ++ ++/* ++ * saradc is exposed on CM1 / Module1A - to J2 ++ * pin 94 - AIN1 - saradc_vin3 ++ * pin 96 - AIN0 - saradc_vin2 ++ */ ++&saradc { ++ status = "disabled"; ++}; ++ ++/* ++ * vmmc-supply is vcc3v3_sd on v1.0 and vcc3v0_sd on v1.1+ ++ * the soquartz SoM has SDMMC_PWR (CM1 pin 75) hardwired to vcc3v3_sys, ++ * so we use vcc3v3_sd here to ensure the regulator is enabled on older boards. ++ */ ++&sdmmc0 { ++ vmmc-supply = <&vcc3v3_sd>; ++ status = "okay"; ++}; ++ ++/* ++ * spi3 is exposed on CM1 / Module1A - to PI40 ++ * pin 37 - GPIO7 - spi3_cs1_m0 ++ * pin 38 - GPIO11 - spi3_clk_m0 ++ * pin 39 - GPIO8 - spi3_cs0_m0 ++ * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch ++ * pin 44 - GPIO10 - spi3_mosi_m0 ++ */ ++&spi3 { ++ status = "disabled"; ++}; ++ ++/* ++ * uart2 is exposed on CM1 / Module1A - to PI40 ++ * pin 51 - GPIO15 - uart2_rx_m0 ++ * pin 55 - GPIO14 - uart2_tx_m0 ++ */ ++&uart2 { ++ status = "okay"; ++}; ++ ++/* ++ * uart7 is exposed on CM1 / Module1A - to PI40 ++ * pin 46 - GPIO22 - uart7_tx_m2 ++ * pin 47 - GPIO23 - uart7_rx_m2 ++ */ ++&uart7 { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ phy-supply = <&vcc5v0_usb>; ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ status = "okay"; ++}; ++ ++&vbus { ++ vin-supply = <&vcc5v0_usb>; ++}; ++ ++&vcc3v3_sd { ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ status = "okay"; ++}; +-- +2.39.0 + diff --git a/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Add-SOQuartz-blade-board.patch b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Add-SOQuartz-blade-board.patch new file mode 100644 index 000000000..246d62c12 --- /dev/null +++ b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Add-SOQuartz-blade-board.patch @@ -0,0 +1,242 @@ +From: Andrew Powers-Holmes <aholmes@omnom.net> +Date: Wed, 16 Nov 2022 12:53:35 +0100 +Subject: [2/4] arm64: dts: rockchip: Add SOQuartz blade board +Origin: https://git.kernel.org/linus/a5c826ecde5222f755e7d8a0c8d795189c5c1228 + +This adds a device tree for the PINE64 SOQuartz blade baseboard, +a 1U rack mountable baseboard for the CM4 form factor with PoE +support designed for the SOQuartz CM4 System-on-Module. + +The board takes power from either PoE or a 5V DC input, and allows +for mounting an M.2 SSD. + +The board also features one USB 2.0 host port, one HDMI output, +a 3.5mm jack for UART, and the aforementioned gigabit networking +port. + +Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net> +[rebase, squash, reword, misc fixes] +Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> +Link: https://lore.kernel.org/r/20221116115337.541601-3-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + arch/arm64/boot/dts/rockchip/Makefile | 1 + + .../dts/rockchip/rk3566-soquartz-blade.dts | 194 ++++++++++++++++++ + 2 files changed, 195 insertions(+) + create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts + +diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile +index e14390277739..071284a46bf7 100644 +--- a/arch/arm64/boot/dts/rockchip/Makefile ++++ b/arch/arm64/boot/dts/rockchip/Makefile +@@ -68,6 +68,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb ++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb + dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts +new file mode 100644 +index 000000000000..4e49bebf548b +--- /dev/null ++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts +@@ -0,0 +1,194 @@ ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT) ++ ++/dts-v1/; ++ ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/input.h> ++#include <dt-bindings/leds/common.h> ++#include <dt-bindings/pinctrl/rockchip.h> ++ ++#include "rk3566-soquartz.dtsi" ++ ++/ { ++ model = "PINE64 RK3566 SOQuartz on Blade carrier board"; ++ compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566"; ++ ++ /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */ ++ vcc3v0_sd: vcc3v0-sd-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v0_sd"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vcc3v3_sys>; ++ }; ++ ++ /* labeled VCC_SSD in schematic */ ++ vcc3v3_pcie_p: vcc3v3-pcie-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc3v3_pcie_p"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ vin-supply = <&vbus>; ++ }; ++ ++ vcc5v_dcin: vcc5v-dcin-regulator { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc5v_dcin"; ++ regulator-always-on; ++ regulator-boot-on; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ }; ++}; ++ ++&combphy2 { ++ phy-supply = <&vcc3v3_sys>; ++ status = "okay"; ++}; ++ ++&gmac1 { ++ status = "okay"; ++}; ++ ++/* ++ * i2c1 is exposed on CM1 / Module1A ++ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu ++ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu ++ */ ++&i2c1 { ++ status = "okay"; ++ ++}; ++ ++/* ++ * i2c2 is exposed on CM1 / Module1A - to PI40 ++ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch ++ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3 ++ */ ++&i2c2 { ++ status = "disabled"; ++}; ++ ++/* ++ * i2c3 is exposed on CM1 / Module1A - to PI40 ++ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3 ++ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3 ++ */ ++&i2c3 { ++ status = "disabled"; ++}; ++ ++/* ++ * i2c4 is exposed on CM2 / Module1B - to PI40 ++ * pin 45 - GPIO24 - i2c4_scl_m1 ++ * pin 47 - GPIO23 - i2c4_sda_m1 ++ */ ++&i2c4 { ++ status = "disabled"; ++}; ++ ++/* ++ * i2s1_8ch is exposed on CM1 / Module1A - to PI40 ++ * pin 24 - GPIO26 - i2s1_sdi1_m1 ++ * pin 25 - GPIO21 - i2s1_sdo0_m1 ++ * pin 26 - GPIO19 - i2s1_lrck_tx_m1 ++ * pin 27 - GPIO20 - i2s1_sdi0_m1 ++ * pin 29 - GPIO16 - i2s1_sdi3_m1 ++ * pin 30 - GPIO6 - i2s1_sdi2_m1 ++ * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3 ++ * pin 41 - GPIO25 - i2s1_sdo2_m1 ++ * pin 49 - GPIO18 - i2s1_sclk_tx_m1 ++ * pin 50 - GPIO17 - i2s1_mclk_m1 ++ * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2 ++ */ ++&i2s1_8ch { ++ status = "disabled"; ++}; ++ ++&led_diy { ++ color = <LED_COLOR_ID_RED>; ++ function = LED_FUNCTION_DISK_ACTIVITY; ++ linux,default-trigger = "disk-activity"; ++ status = "okay"; ++}; ++ ++&led_work { ++ color = <LED_COLOR_ID_GREEN>; ++ function = LED_FUNCTION_STATUS; ++ linux,default-trigger = "heartbeat"; ++ status = "okay"; ++}; ++ ++&pcie2x1 { ++ vpcie3v3-supply = <&vcc3v3_pcie_p>; ++ status = "okay"; ++}; ++ ++&rgmii_phy1 { ++ status = "okay"; ++}; ++ ++/* ++ * saradc is exposed on CM1 / Module1A - to J2 ++ * pin 94 - AIN1 - saradc_vin3 ++ * pin 96 - AIN0 - saradc_vin2 ++ */ ++&saradc { ++ status = "disabled"; ++}; ++ ++&sdmmc0 { ++ vmmc-supply = <&vcc3v0_sd>; ++ status = "okay"; ++}; ++ ++/* ++ * spi3 is exposed on CM1 / Module1A - to PI40 ++ * pin 37 - GPIO7 - spi3_cs1_m0 ++ * pin 38 - GPIO11 - spi3_clk_m0 ++ * pin 39 - GPIO8 - spi3_cs0_m0 ++ * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch ++ * pin 44 - GPIO10 - spi3_mosi_m0 ++ */ ++&spi3 { ++ status = "disabled"; ++}; ++ ++/* ++ * uart2 is exposed on CM1 / Module1A - to PI40 ++ * pin 51 - GPIO15 - uart2_rx_m0 ++ * pin 55 - GPIO14 - uart2_tx_m0 ++ */ ++&uart2 { ++ status = "okay"; ++}; ++ ++/* ++ * uart7 is exposed on CM1 / Module1A - to PI40 ++ * pin 46 - GPIO22 - uart7_tx_m2 ++ * pin 47 - GPIO23 - uart7_rx_m2 ++ */ ++&uart7 { ++ status = "okay"; ++}; ++ ++&usb2phy0 { ++ status = "okay"; ++}; ++ ++&usb2phy0_otg { ++ phy-supply = <&vbus>; ++ status = "okay"; ++}; ++ ++&usb_host0_xhci { ++ status = "okay"; ++}; ++ ++&vbus { ++ vin-supply = <&vcc5v_dcin>; ++}; +-- +2.39.0 + diff --git a/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-HDMI-sound-on-SOQuartz.patch b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-HDMI-sound-on-SOQuartz.patch new file mode 100644 index 000000000..d4df69e16 --- /dev/null +++ b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-HDMI-sound-on-SOQuartz.patch @@ -0,0 +1,44 @@ +From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> +Date: Sat, 12 Nov 2022 17:04:00 +0100 +Subject: arm64: dts: rockchip: Enable HDMI sound on SOQuartz +Origin: https://git.kernel.org/linus/70b620c4ba919a87c607b8d98b08478b213877bd + +This patch enables the i2s0 node on SOQuartz, which is responsible +for hdmi audio, and adds an hdmi-sound node to enable said audio. + +Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> +Link: https://lore.kernel.org/r/20221112160404.70868-4-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +index 0bfb0cea7d6b..1b975822effa 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +@@ -178,6 +178,10 @@ + }; + }; + ++&hdmi_sound { ++ status = "okay"; ++}; ++ + &i2c0 { + status = "okay"; + +@@ -446,6 +450,10 @@ + status = "disabled"; + }; + ++&i2s0_8ch { ++ status = "okay"; ++}; ++ + /* + * i2s1_8ch is exposed on CM1 / Module1A + * pin 24 - i2s1_sdi1_m1 +-- +2.39.0 + diff --git a/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch new file mode 100644 index 000000000..1a8063e0f --- /dev/null +++ b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch @@ -0,0 +1,82 @@ +From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> +Date: Sat, 12 Nov 2022 17:04:01 +0100 +Subject: arm64: dts: rockchip: Enable PCIe 2 on SOQuartz CM4IO +Origin: https://git.kernel.org/linus/3736aa7ecc4cd9b4abce30052bad00aba4f0362f + +This patch enables the PCIe2 on the CM4IO board when paired with +a SOQuartz CM4 System-on-Module board. combphy2 also needs to be +enabled in this case to make the PHY work for this. + +Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> +Link: https://lore.kernel.org/r/20221112160404.70868-5-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + .../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 11 +++++++++++ + arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 15 +++++++++++++++ + 2 files changed, 26 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts +index e00568a6be5c..263ce40770dd 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts ++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts +@@ -30,6 +30,12 @@ + }; + }; + ++/* phy for pcie */ ++&combphy2 { ++ phy-supply = <&vcc3v3_sys>; ++ status = "okay"; ++}; ++ + &gmac1 { + status = "okay"; + }; +@@ -105,6 +111,11 @@ + status = "okay"; + }; + ++&pcie2x1 { ++ vpcie3v3-supply = <&vcc_3v3>; ++ status = "okay"; ++}; ++ + &rgmii_phy1 { + status = "okay"; + }; +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +index 1b975822effa..ce7165d7f1a1 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +@@ -487,6 +487,12 @@ + }; + }; + ++&pcie2x1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie_reset_h>; ++ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; ++}; ++ + &pinctrl { + bt { + bt_enable_h: bt-enable-h { +@@ -512,6 +518,15 @@ + }; + }; + ++ pcie { ++ pcie_clkreq_h: pcie-clkreq-h { ++ rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ pcie_reset_h: pcie-reset-h { ++ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; ++ }; ++ }; ++ + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>; +-- +2.39.0 + diff --git a/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-video-output-and-HDMI-on-S.patch b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-video-output-and-HDMI-on-S.patch new file mode 100644 index 000000000..37cfbdb23 --- /dev/null +++ b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-video-output-and-HDMI-on-S.patch @@ -0,0 +1,94 @@ +From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> +Date: Sat, 12 Nov 2022 17:03:59 +0100 +Subject: arm64: dts: rockchip: Enable video output and HDMI on SOQuartz +Origin: https://git.kernel.org/linus/36d7a605706d9648526a0574b8e7b0e02fa70c2a + +This patch adds and enables the necessary device tree nodes to +enable video output and HDMI functionality on the SOQuartz module. + +Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> +Link: https://lore.kernel.org/r/20221112160404.70868-3-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + .../boot/dts/rockchip/rk3566-soquartz.dtsi | 47 +++++++++++++++++++ + 1 file changed, 47 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +index 6e99f049501c..0bfb0cea7d6b 100644 +--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi +@@ -4,6 +4,7 @@ + + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/pinctrl/rockchip.h> ++#include <dt-bindings/soc/rockchip,vop2.h> + #include "rk3566.dtsi" + + / { +@@ -28,6 +29,17 @@ + #clock-cells = <0>; + }; + ++ hdmi-con { ++ compatible = "hdmi-connector"; ++ type = "a"; ++ ++ port { ++ hdmi_con_in: endpoint { ++ remote-endpoint = <&hdmi_out_con>; ++ }; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -148,6 +160,24 @@ + status = "okay"; + }; + ++&hdmi { ++ avdd-0v9-supply = <&vdda0v9_image>; ++ avdd-1v8-supply = <&vcca1v8_image>; ++ status = "okay"; ++}; ++ ++&hdmi_in { ++ hdmi_in_vp0: endpoint { ++ remote-endpoint = <&vp0_out_hdmi>; ++ }; ++}; ++ ++&hdmi_out { ++ hdmi_out_con: endpoint { ++ remote-endpoint = <&hdmi_con_in>; ++ }; ++}; ++ + &i2c0 { + status = "okay"; + +@@ -619,3 +649,20 @@ + &usb_host0_xhci { + status = "disabled"; + }; ++ ++&vop { ++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>; ++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>; ++ status = "okay"; ++}; ++ ++&vop_mmu { ++ status = "okay"; ++}; ++ ++&vp0 { ++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { ++ reg = <ROCKCHIP_VOP2_EP_HDMI0>; ++ remote-endpoint = <&hdmi_in_vp0>; ++ }; ++}; +-- +2.39.0 + diff --git a/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-RK356x-Add-I2S2-device-node.patch b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-RK356x-Add-I2S2-device-node.patch new file mode 100644 index 000000000..55c6af80b --- /dev/null +++ b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-RK356x-Add-I2S2-device-node.patch @@ -0,0 +1,50 @@ +From: Shengyu Qu <wiagn233@outlook.com> +Date: Sun, 30 Oct 2022 01:09:04 +0800 +Subject: arm64: dts: rockchip: RK356x: Add I2S2 device node +Origin: https://git.kernel.org/linus/755f37010f3eac0bdfa41bdf2308e8380a93f10c + +This patch adds I2S2 device tree node for RK3566/RK3568. + +Signed-off-by: Shengyu Qu <wiagn233@outlook.com> +Link: https://lore.kernel.org/r/OS3P286MB259771C12F2B15A4DDF435FE98359@OS3P286MB2597.JPNP286.PROD.OUTLOOK.COM +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + arch/arm64/boot/dts/rockchip/rk356x.dtsi | 22 ++++++++++++++++++++++ + 1 file changed, 22 insertions(+) + +diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +index 10e3a0862602..5706c3e24f0a 100644 +--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi ++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi +@@ -1091,6 +1091,28 @@ + status = "disabled"; + }; + ++ i2s2_2ch: i2s@fe420000 { ++ compatible = "rockchip,rk3568-i2s-tdm"; ++ reg = <0x0 0xfe420000 0x0 0x1000>; ++ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; ++ assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; ++ assigned-clock-rates = <1188000000>; ++ clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; ++ clock-names = "mclk_tx", "mclk_rx", "hclk"; ++ dmas = <&dmac1 4>, <&dmac1 5>; ++ dma-names = "tx", "rx"; ++ resets = <&cru SRST_M_I2S2_2CH>; ++ reset-names = "m"; ++ rockchip,grf = <&grf>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2s2m0_sclktx ++ &i2s2m0_lrcktx ++ &i2s2m0_sdi ++ &i2s2m0_sdo>; ++ #sound-dai-cells = <0>; ++ status = "disabled"; ++ }; ++ + i2s3_2ch: i2s@fe430000 { + compatible = "rockchip,rk3568-i2s-tdm"; + reg = <0x0 0xfe430000 0x0 0x1000>; +-- +2.39.0 + diff --git a/debian/patches/features/arm64/quartz64/dt-bindings-arm-rockchip-Add-SOQuartz-Blade.patch b/debian/patches/features/arm64/quartz64/dt-bindings-arm-rockchip-Add-SOQuartz-Blade.patch new file mode 100644 index 000000000..52fdca25d --- /dev/null +++ b/debian/patches/features/arm64/quartz64/dt-bindings-arm-rockchip-Add-SOQuartz-Blade.patch @@ -0,0 +1,39 @@ +From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> +Date: Wed, 16 Nov 2022 12:53:34 +0100 +Subject: [1/4] dt-bindings: arm: rockchip: Add SOQuartz Blade +Origin: https://git.kernel.org/linus/8c84c2e51f3ee39b40e8078ebe3ad9c01fb17aff + +Add a compatible for the SOQuartz Blade base board to the rockchip +platforms binding. + +The SOQuartz Blade is a PoE-capable carrier board for the CM4 SoM +form factor, designed around the SOQuartz CM4 System-on-Module. + +The board features the usual connectivity (GPIO, USB, HDMI, +Ethernet) and an M.2 slot for SSDs. It may also be powered from +a 5V barrel jack input, and has a 3.5mm jack for UART debug +output. + +Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> +Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> +Link: https://lore.kernel.org/r/20221116115337.541601-2-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index 3f31115ee99a..42f33240ade8 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -593,6 +593,7 @@ properties: + - description: Pine64 SoQuartz SoM + items: + - enum: ++ - pine64,soquartz-blade + - pine64,soquartz-cm4io + - const: pine64,soquartz + - const: rockchip,rk3566 +-- +2.39.0 + diff --git a/debian/patches/features/arm64/quartz64/dt-bindings-arm-rockchip-Add-SOQuartz-Model-A.patch b/debian/patches/features/arm64/quartz64/dt-bindings-arm-rockchip-Add-SOQuartz-Model-A.patch new file mode 100644 index 000000000..2983e8a88 --- /dev/null +++ b/debian/patches/features/arm64/quartz64/dt-bindings-arm-rockchip-Add-SOQuartz-Model-A.patch @@ -0,0 +1,39 @@ +From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> +Date: Wed, 16 Nov 2022 12:53:36 +0100 +Subject: [3/4] dt-bindings: arm: rockchip: Add SOQuartz Model A +Origin: https://git.kernel.org/linus/7441d8c437883581dddfb616a087b399338244f0 + +The SOQuartz Model A base board is a carrier board for the CM4 +form factor, designed around the PINE64 SOQuartz CM4 SoM. + +The board sports "Model A" dimensions like the Quartz64 Model A, +but is not to be confused with that. + +As for I/O, it features USB 2 ports, Gigabit Ethernet, a PCIe 2 +x1 slot, HDMI, a 40-pin GPIO header, CSI/DSI connectors, an eDP +flat-flex cable connector, a 12V DC barrel jack for power input +and power/reset buttons as well as a microSD card slot. + +Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> +Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> +Link: https://lore.kernel.org/r/20221116115337.541601-4-frattaroli.nicolas@gmail.com +Signed-off-by: Heiko Stuebner <heiko@sntech.de> +--- + Documentation/devicetree/bindings/arm/rockchip.yaml | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml +index 42f33240ade8..88ff4422a8c1 100644 +--- a/Documentation/devicetree/bindings/arm/rockchip.yaml ++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml +@@ -595,6 +595,7 @@ properties: + - enum: + - pine64,soquartz-blade + - pine64,soquartz-cm4io ++ - pine64,soquartz-model-a + - const: pine64,soquartz + - const: rockchip,rk3566 + +-- +2.39.0 + |