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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
commit | 2c3c1048746a4622d8c89a29670120dc8fab93c4 (patch) | |
tree | 848558de17fb3008cdf4d861b01ac7781903ce39 /drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h | |
parent | Initial commit. (diff) | |
download | linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.tar.xz linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.zip |
Adding upstream version 6.1.76.upstream/6.1.76upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to 'drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h')
-rw-r--r-- | drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h | 95 |
1 files changed, 95 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h new file mode 100644 index 000000000..f73e76c8f --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_edma0_core_ctx_regs.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ +#define ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ + +/* + ***************************************** + * DCORE0_EDMA0_CORE_CTX + * (Prototype: DMA_CORE_CTX) + ***************************************** + */ + +#define mmDCORE0_EDMA0_CORE_CTX_RATE_LIM_TKN 0x41CB860 + +#define mmDCORE0_EDMA0_CORE_CTX_PWRLP 0x41CB864 + +#define mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS 0x41CB868 + +#define mmDCORE0_EDMA0_CORE_CTX_IDX 0x41CB86C + +#define mmDCORE0_EDMA0_CORE_CTX_IDX_INC 0x41CB870 + +#define mmDCORE0_EDMA0_CORE_CTX_CTRL 0x41CB874 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0 0x41CB878 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1 0x41CB87C + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1 0x41CB880 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2 0x41CB884 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2 0x41CB888 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3 0x41CB88C + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3 0x41CB890 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4 0x41CB894 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4 0x41CB898 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1 0x41CB89C + +#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1 0x41CB8A0 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2 0x41CB8A4 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2 0x41CB8A8 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3 0x41CB8AC + +#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3 0x41CB8B0 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4 0x41CB8B4 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4 0x41CB8B8 + +#define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI 0x41CB8BC + +#define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO 0x41CB8C0 + +#define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA 0x41CB8C4 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO 0x41CB8C8 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI 0x41CB8CC + +#define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO 0x41CB8D0 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI 0x41CB8D4 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO 0x41CB8D8 + +#define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI 0x41CB8DC + +#define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO 0x41CB8E0 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI 0x41CB8E4 + +#define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0 0x41CB8E8 + +#define mmDCORE0_EDMA0_CORE_CTX_COMMIT 0x41CB8EC + +#endif /* ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ */ |