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author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
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committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
commit | 2c3c1048746a4622d8c89a29670120dc8fab93c4 (patch) | |
tree | 848558de17fb3008cdf4d861b01ac7781903ce39 /drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h | |
parent | Initial commit. (diff) | |
download | linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.tar.xz linux-2c3c1048746a4622d8c89a29670120dc8fab93c4.zip |
Adding upstream version 6.1.76.upstream/6.1.76upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to '')
-rw-r--r-- | drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h | 129 |
1 files changed, 129 insertions, 0 deletions
diff --git a/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h new file mode 100644 index 000000000..4cd9e26a1 --- /dev/null +++ b/drivers/misc/habanalabs/include/gaudi2/asic_reg/dcore0_tpc0_cfg_qm_regs.h @@ -0,0 +1,129 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright 2016-2020 HabanaLabs, Ltd. + * All Rights Reserved. + * + */ + +/************************************ + ** This is an auto-generated file ** + ** DO NOT EDIT BELOW ** + ************************************/ + +#ifndef ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ +#define ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ + +/* + ***************************************** + * DCORE0_TPC0_CFG_QM + * (Prototype: TPC_NON_TENSOR_DESCRIPTOR) + ***************************************** + */ + +#define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0x400BAE4 + +#define mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0x400BAE8 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0 0x400BAEC + +#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0 0x400BAF0 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1 0x400BAF4 + +#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1 0x400BAF8 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2 0x400BAFC + +#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2 0x400BB00 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3 0x400BB04 + +#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3 0x400BB08 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4 0x400BB0C + +#define mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4 0x400BB10 + +#define mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG 0x400BB14 + +#define mmDCORE0_TPC0_CFG_QM_KERNEL_ID 0x400BB18 + +#define mmDCORE0_TPC0_CFG_QM_POWER_LOOP 0x400BB1C + +#define mmDCORE0_TPC0_CFG_QM_SRF_0 0x400BB20 + +#define mmDCORE0_TPC0_CFG_QM_SRF_1 0x400BB24 + +#define mmDCORE0_TPC0_CFG_QM_SRF_2 0x400BB28 + +#define mmDCORE0_TPC0_CFG_QM_SRF_3 0x400BB2C + +#define mmDCORE0_TPC0_CFG_QM_SRF_4 0x400BB30 + +#define mmDCORE0_TPC0_CFG_QM_SRF_5 0x400BB34 + +#define mmDCORE0_TPC0_CFG_QM_SRF_6 0x400BB38 + +#define mmDCORE0_TPC0_CFG_QM_SRF_7 0x400BB3C + +#define mmDCORE0_TPC0_CFG_QM_SRF_8 0x400BB40 + +#define mmDCORE0_TPC0_CFG_QM_SRF_9 0x400BB44 + +#define mmDCORE0_TPC0_CFG_QM_SRF_10 0x400BB48 + +#define mmDCORE0_TPC0_CFG_QM_SRF_11 0x400BB4C + +#define mmDCORE0_TPC0_CFG_QM_SRF_12 0x400BB50 + +#define mmDCORE0_TPC0_CFG_QM_SRF_13 0x400BB54 + +#define mmDCORE0_TPC0_CFG_QM_SRF_14 0x400BB58 + +#define mmDCORE0_TPC0_CFG_QM_SRF_15 0x400BB5C + +#define mmDCORE0_TPC0_CFG_QM_SRF_16 0x400BB60 + +#define mmDCORE0_TPC0_CFG_QM_SRF_17 0x400BB64 + +#define mmDCORE0_TPC0_CFG_QM_SRF_18 0x400BB68 + +#define mmDCORE0_TPC0_CFG_QM_SRF_19 0x400BB6C + +#define mmDCORE0_TPC0_CFG_QM_SRF_20 0x400BB70 + +#define mmDCORE0_TPC0_CFG_QM_SRF_21 0x400BB74 + +#define mmDCORE0_TPC0_CFG_QM_SRF_22 0x400BB78 + +#define mmDCORE0_TPC0_CFG_QM_SRF_23 0x400BB7C + +#define mmDCORE0_TPC0_CFG_QM_SRF_24 0x400BB80 + +#define mmDCORE0_TPC0_CFG_QM_SRF_25 0x400BB84 + +#define mmDCORE0_TPC0_CFG_QM_SRF_26 0x400BB88 + +#define mmDCORE0_TPC0_CFG_QM_SRF_27 0x400BB8C + +#define mmDCORE0_TPC0_CFG_QM_SRF_28 0x400BB90 + +#define mmDCORE0_TPC0_CFG_QM_SRF_29 0x400BB94 + +#define mmDCORE0_TPC0_CFG_QM_SRF_30 0x400BB98 + +#define mmDCORE0_TPC0_CFG_QM_SRF_31 0x400BB9C + +#define mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC 0x400BBA0 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0 0x400BBA4 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1 0x400BBA8 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2 0x400BBAC + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3 0x400BBB0 + +#define mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4 0x400BBB4 + +#endif /* ASIC_REG_DCORE0_TPC0_CFG_QM_REGS_H_ */ |