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| author | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
|---|---|---|
| committer | Daniel Baumann <daniel.baumann@progress-linux.org> | 2024-04-07 18:49:45 +0000 |
| commit | 2c3c1048746a4622d8c89a29670120dc8fab93c4 (patch) | |
| tree | 848558de17fb3008cdf4d861b01ac7781903ce39 /include/sound | |
| parent | Initial commit. (diff) | |
| download | linux-upstream.tar.xz linux-upstream.zip | |
Adding upstream version 6.1.76.upstream/6.1.76upstream
Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>
Diffstat (limited to '')
182 files changed, 29571 insertions, 0 deletions
diff --git a/include/sound/ac97/codec.h b/include/sound/ac97/codec.h new file mode 100644 index 000000000..9792d25fa --- /dev/null +++ b/include/sound/ac97/codec.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016 Robert Jarzmik <robert.jarzmik@free.fr> + */ + +#ifndef __SOUND_AC97_CODEC2_H +#define __SOUND_AC97_CODEC2_H + +#include <linux/device.h> + +#define AC97_ID(vendor_id1, vendor_id2) \ + ((((vendor_id1) & 0xffff) << 16) | ((vendor_id2) & 0xffff)) +#define AC97_DRIVER_ID(vendor_id1, vendor_id2, mask_id1, mask_id2, _data) \ + { .id = (((vendor_id1) & 0xffff) << 16) | ((vendor_id2) & 0xffff), \ + .mask = (((mask_id1) & 0xffff) << 16) | ((mask_id2) & 0xffff), \ + .data = (_data) } + +struct ac97_controller; +struct clk; + +/** + * struct ac97_id - matches a codec device and driver on an ac97 bus + * @id: The significant bits if the codec vendor ID1 and ID2 + * @mask: Bitmask specifying which bits of the id field are significant when + * matching. A driver binds to a device when : + * ((vendorID1 << 8 | vendorID2) & (mask_id1 << 8 | mask_id2)) == id. + * @data: Private data used by the driver. + */ +struct ac97_id { + unsigned int id; + unsigned int mask; + void *data; +}; + +/** + * ac97_codec_device - a ac97 codec + * @dev: the core device + * @vendor_id: the vendor_id of the codec, as sensed on the AC-link + * @num: the codec number, 0 is primary, 1 is first slave, etc ... + * @clk: the clock BIT_CLK provided by the codec + * @ac97_ctrl: ac97 digital controller on the same AC-link + * + * This is the device instantiated for each codec living on a AC-link. There are + * normally 0 to 4 codec devices per AC-link, and all of them are controlled by + * an AC97 digital controller. + */ +struct ac97_codec_device { + struct device dev; + unsigned int vendor_id; + unsigned int num; + struct clk *clk; + struct ac97_controller *ac97_ctrl; +}; + +/** + * ac97_codec_driver - a ac97 codec driver + * @driver: the device driver structure + * @probe: the function called when a ac97_codec_device is matched + * @remove: the function called when the device is unbound/removed + * @shutdown: shutdown function (might be NULL) + * @id_table: ac97 vendor_id match table, { } member terminated + */ +struct ac97_codec_driver { + struct device_driver driver; + int (*probe)(struct ac97_codec_device *); + int (*remove)(struct ac97_codec_device *); + void (*shutdown)(struct ac97_codec_device *); + const struct ac97_id *id_table; +}; + +static inline struct ac97_codec_device *to_ac97_device(struct device *d) +{ + return container_of(d, struct ac97_codec_device, dev); +} + +static inline struct ac97_codec_driver *to_ac97_driver(struct device_driver *d) +{ + return container_of(d, struct ac97_codec_driver, driver); +} + +#if IS_ENABLED(CONFIG_AC97_BUS_NEW) +int snd_ac97_codec_driver_register(struct ac97_codec_driver *drv); +void snd_ac97_codec_driver_unregister(struct ac97_codec_driver *drv); +#else +static inline int +snd_ac97_codec_driver_register(struct ac97_codec_driver *drv) +{ + return 0; +} +static inline void +snd_ac97_codec_driver_unregister(struct ac97_codec_driver *drv) +{ +} +#endif + + +static inline struct device * +ac97_codec_dev2dev(struct ac97_codec_device *adev) +{ + return &adev->dev; +} + +static inline void *ac97_get_drvdata(struct ac97_codec_device *adev) +{ + return dev_get_drvdata(ac97_codec_dev2dev(adev)); +} + +static inline void ac97_set_drvdata(struct ac97_codec_device *adev, + void *data) +{ + dev_set_drvdata(ac97_codec_dev2dev(adev), data); +} + +void *snd_ac97_codec_get_platdata(const struct ac97_codec_device *adev); + +#endif diff --git a/include/sound/ac97/compat.h b/include/sound/ac97/compat.h new file mode 100644 index 000000000..57e19afa3 --- /dev/null +++ b/include/sound/ac97/compat.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016 Robert Jarzmik <robert.jarzmik@free.fr> + * + * This file is for backward compatibility with snd_ac97 structure and its + * multiple usages, such as the snd_ac97_bus and snd_ac97_build_ops. + */ + +#ifndef AC97_COMPAT_H +#define AC97_COMPAT_H + +#include <sound/ac97_codec.h> + +struct snd_ac97 *snd_ac97_compat_alloc(struct ac97_codec_device *adev); +void snd_ac97_compat_release(struct snd_ac97 *ac97); + +#endif diff --git a/include/sound/ac97/controller.h b/include/sound/ac97/controller.h new file mode 100644 index 000000000..06b5afb7f --- /dev/null +++ b/include/sound/ac97/controller.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016 Robert Jarzmik <robert.jarzmik@free.fr> + */ + +#ifndef AC97_CONTROLLER_H +#define AC97_CONTROLLER_H + +#include <linux/device.h> +#include <linux/list.h> + +#define AC97_BUS_MAX_CODECS 4 +#define AC97_SLOTS_AVAILABLE_ALL 0xf + +struct ac97_controller_ops; + +/** + * struct ac97_controller - The AC97 controller of the AC-Link + * @ops: the AC97 operations. + * @controllers: linked list of all existing controllers. + * @adap: the shell device ac97-%d, ie. ac97 adapter + * @nr: the number of the shell device + * @slots_available: the mask of accessible/scanable codecs. + * @parent: the device providing the AC97 controller. + * @codecs: the 4 possible AC97 codecs (NULL if none found). + * @codecs_pdata: platform_data for each codec (NULL if no pdata). + * + * This structure is internal to AC97 bus, and should not be used by the + * controllers themselves, excepting for using @dev. + */ +struct ac97_controller { + const struct ac97_controller_ops *ops; + struct list_head controllers; + struct device adap; + int nr; + unsigned short slots_available; + struct device *parent; + struct ac97_codec_device *codecs[AC97_BUS_MAX_CODECS]; + void *codecs_pdata[AC97_BUS_MAX_CODECS]; +}; + +/** + * struct ac97_controller_ops - The AC97 operations + * @reset: Cold reset of the AC97 AC-Link. + * @warm_reset: Warm reset of the AC97 AC-Link. + * @read: Read of a single AC97 register. + * Returns the register value or a negative error code. + * @write: Write of a single AC97 register. + * + * These are the basic operation an AC97 controller must provide for an AC97 + * access functions. Amongst these, all but the last 2 are mandatory. + * The slot number is also known as the AC97 codec number, between 0 and 3. + */ +struct ac97_controller_ops { + void (*reset)(struct ac97_controller *adrv); + void (*warm_reset)(struct ac97_controller *adrv); + int (*write)(struct ac97_controller *adrv, int slot, + unsigned short reg, unsigned short val); + int (*read)(struct ac97_controller *adrv, int slot, unsigned short reg); +}; + +#if IS_ENABLED(CONFIG_AC97_BUS_NEW) +struct ac97_controller *snd_ac97_controller_register( + const struct ac97_controller_ops *ops, struct device *dev, + unsigned short slots_available, void **codecs_pdata); +void snd_ac97_controller_unregister(struct ac97_controller *ac97_ctrl); +#else +static inline struct ac97_controller * +snd_ac97_controller_register(const struct ac97_controller_ops *ops, + struct device *dev, + unsigned short slots_available, + void **codecs_pdata) +{ + return ERR_PTR(-ENODEV); +} + +static inline void +snd_ac97_controller_unregister(struct ac97_controller *ac97_ctrl) +{ +} +#endif + +#endif diff --git a/include/sound/ac97/regs.h b/include/sound/ac97/regs.h new file mode 100644 index 000000000..843f73f37 --- /dev/null +++ b/include/sound/ac97/regs.h @@ -0,0 +1,246 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + * Universal interface for Audio Codec '97 + * + * For more details look to AC '97 component specification revision 2.1 + * by Intel Corporation (http://developer.intel.com). + */ +/* + * AC'97 codec registers + */ + +#define AC97_RESET 0x00 /* Reset */ +#define AC97_MASTER 0x02 /* Master Volume */ +#define AC97_HEADPHONE 0x04 /* Headphone Volume (optional) */ +#define AC97_MASTER_MONO 0x06 /* Master Volume Mono (optional) */ +#define AC97_MASTER_TONE 0x08 /* Master Tone (Bass & Treble) (optional) */ +#define AC97_PC_BEEP 0x0a /* PC Beep Volume (optional) */ +#define AC97_PHONE 0x0c /* Phone Volume (optional) */ +#define AC97_MIC 0x0e /* MIC Volume */ +#define AC97_LINE 0x10 /* Line In Volume */ +#define AC97_CD 0x12 /* CD Volume */ +#define AC97_VIDEO 0x14 /* Video Volume (optional) */ +#define AC97_AUX 0x16 /* AUX Volume (optional) */ +#define AC97_PCM 0x18 /* PCM Volume */ +#define AC97_REC_SEL 0x1a /* Record Select */ +#define AC97_REC_GAIN 0x1c /* Record Gain */ +#define AC97_REC_GAIN_MIC 0x1e /* Record Gain MIC (optional) */ +#define AC97_GENERAL_PURPOSE 0x20 /* General Purpose (optional) */ +#define AC97_3D_CONTROL 0x22 /* 3D Control (optional) */ +#define AC97_INT_PAGING 0x24 /* Audio Interrupt & Paging (AC'97 2.3) */ +#define AC97_POWERDOWN 0x26 /* Powerdown control / status */ +/* range 0x28-0x3a - AUDIO AC'97 2.0 extensions */ +#define AC97_EXTENDED_ID 0x28 /* Extended Audio ID */ +#define AC97_EXTENDED_STATUS 0x2a /* Extended Audio Status and Control */ +#define AC97_PCM_FRONT_DAC_RATE 0x2c /* PCM Front DAC Rate */ +#define AC97_PCM_SURR_DAC_RATE 0x2e /* PCM Surround DAC Rate */ +#define AC97_PCM_LFE_DAC_RATE 0x30 /* PCM LFE DAC Rate */ +#define AC97_PCM_LR_ADC_RATE 0x32 /* PCM LR ADC Rate */ +#define AC97_PCM_MIC_ADC_RATE 0x34 /* PCM MIC ADC Rate */ +#define AC97_CENTER_LFE_MASTER 0x36 /* Center + LFE Master Volume */ +#define AC97_SURROUND_MASTER 0x38 /* Surround (Rear) Master Volume */ +#define AC97_SPDIF 0x3a /* S/PDIF control */ +/* range 0x3c-0x58 - MODEM */ +#define AC97_EXTENDED_MID 0x3c /* Extended Modem ID */ +#define AC97_EXTENDED_MSTATUS 0x3e /* Extended Modem Status and Control */ +#define AC97_LINE1_RATE 0x40 /* Line1 DAC/ADC Rate */ +#define AC97_LINE2_RATE 0x42 /* Line2 DAC/ADC Rate */ +#define AC97_HANDSET_RATE 0x44 /* Handset DAC/ADC Rate */ +#define AC97_LINE1_LEVEL 0x46 /* Line1 DAC/ADC Level */ +#define AC97_LINE2_LEVEL 0x48 /* Line2 DAC/ADC Level */ +#define AC97_HANDSET_LEVEL 0x4a /* Handset DAC/ADC Level */ +#define AC97_GPIO_CFG 0x4c /* GPIO Configuration */ +#define AC97_GPIO_POLARITY 0x4e /* GPIO Pin Polarity/Type, 0=low, 1=high active */ +#define AC97_GPIO_STICKY 0x50 /* GPIO Pin Sticky, 0=not, 1=sticky */ +#define AC97_GPIO_WAKEUP 0x52 /* GPIO Pin Wakeup, 0=no int, 1=yes int */ +#define AC97_GPIO_STATUS 0x54 /* GPIO Pin Status, slot 12 */ +#define AC97_MISC_AFE 0x56 /* Miscellaneous Modem AFE Status and Control */ +/* range 0x5a-0x7b - Vendor Specific */ +#define AC97_VENDOR_ID1 0x7c /* Vendor ID1 */ +#define AC97_VENDOR_ID2 0x7e /* Vendor ID2 / revision */ +/* range 0x60-0x6f (page 1) - extended codec registers */ +#define AC97_CODEC_CLASS_REV 0x60 /* Codec Class/Revision */ +#define AC97_PCI_SVID 0x62 /* PCI Subsystem Vendor ID */ +#define AC97_PCI_SID 0x64 /* PCI Subsystem ID */ +#define AC97_FUNC_SELECT 0x66 /* Function Select */ +#define AC97_FUNC_INFO 0x68 /* Function Information */ +#define AC97_SENSE_INFO 0x6a /* Sense Details */ + +/* volume controls */ +#define AC97_MUTE_MASK_MONO 0x8000 +#define AC97_MUTE_MASK_STEREO 0x8080 + +/* slot allocation */ +#define AC97_SLOT_TAG 0 +#define AC97_SLOT_CMD_ADDR 1 +#define AC97_SLOT_CMD_DATA 2 +#define AC97_SLOT_PCM_LEFT 3 +#define AC97_SLOT_PCM_RIGHT 4 +#define AC97_SLOT_MODEM_LINE1 5 +#define AC97_SLOT_PCM_CENTER 6 +#define AC97_SLOT_MIC 6 /* input */ +#define AC97_SLOT_SPDIF_LEFT1 6 +#define AC97_SLOT_PCM_SLEFT 7 /* surround left */ +#define AC97_SLOT_PCM_LEFT_0 7 /* double rate operation */ +#define AC97_SLOT_SPDIF_LEFT 7 +#define AC97_SLOT_PCM_SRIGHT 8 /* surround right */ +#define AC97_SLOT_PCM_RIGHT_0 8 /* double rate operation */ +#define AC97_SLOT_SPDIF_RIGHT 8 +#define AC97_SLOT_LFE 9 +#define AC97_SLOT_SPDIF_RIGHT1 9 +#define AC97_SLOT_MODEM_LINE2 10 +#define AC97_SLOT_PCM_LEFT_1 10 /* double rate operation */ +#define AC97_SLOT_SPDIF_LEFT2 10 +#define AC97_SLOT_HANDSET 11 /* output */ +#define AC97_SLOT_PCM_RIGHT_1 11 /* double rate operation */ +#define AC97_SLOT_SPDIF_RIGHT2 11 +#define AC97_SLOT_MODEM_GPIO 12 /* modem GPIO */ +#define AC97_SLOT_PCM_CENTER_1 12 /* double rate operation */ + +/* basic capabilities (reset register) */ +#define AC97_BC_DEDICATED_MIC 0x0001 /* Dedicated Mic PCM In Channel */ +#define AC97_BC_RESERVED1 0x0002 /* Reserved (was Modem Line Codec support) */ +#define AC97_BC_BASS_TREBLE 0x0004 /* Bass & Treble Control */ +#define AC97_BC_SIM_STEREO 0x0008 /* Simulated stereo */ +#define AC97_BC_HEADPHONE 0x0010 /* Headphone Out Support */ +#define AC97_BC_LOUDNESS 0x0020 /* Loudness (bass boost) Support */ +#define AC97_BC_16BIT_DAC 0x0000 /* 16-bit DAC resolution */ +#define AC97_BC_18BIT_DAC 0x0040 /* 18-bit DAC resolution */ +#define AC97_BC_20BIT_DAC 0x0080 /* 20-bit DAC resolution */ +#define AC97_BC_DAC_MASK 0x00c0 +#define AC97_BC_16BIT_ADC 0x0000 /* 16-bit ADC resolution */ +#define AC97_BC_18BIT_ADC 0x0100 /* 18-bit ADC resolution */ +#define AC97_BC_20BIT_ADC 0x0200 /* 20-bit ADC resolution */ +#define AC97_BC_ADC_MASK 0x0300 +#define AC97_BC_3D_TECH_ID_MASK 0x7c00 /* Per-vendor ID of 3D enhancement */ + +/* general purpose */ +#define AC97_GP_DRSS_MASK 0x0c00 /* double rate slot select */ +#define AC97_GP_DRSS_1011 0x0000 /* LR(C) 10+11(+12) */ +#define AC97_GP_DRSS_78 0x0400 /* LR 7+8 */ + +/* powerdown bits */ +#define AC97_PD_ADC_STATUS 0x0001 /* ADC status (RO) */ +#define AC97_PD_DAC_STATUS 0x0002 /* DAC status (RO) */ +#define AC97_PD_MIXER_STATUS 0x0004 /* Analog mixer status (RO) */ +#define AC97_PD_VREF_STATUS 0x0008 /* Vref status (RO) */ +#define AC97_PD_PR0 0x0100 /* Power down PCM ADCs and input MUX */ +#define AC97_PD_PR1 0x0200 /* Power down PCM front DAC */ +#define AC97_PD_PR2 0x0400 /* Power down Mixer (Vref still on) */ +#define AC97_PD_PR3 0x0800 /* Power down Mixer (Vref off) */ +#define AC97_PD_PR4 0x1000 /* Power down AC-Link */ +#define AC97_PD_PR5 0x2000 /* Disable internal clock usage */ +#define AC97_PD_PR6 0x4000 /* Headphone amplifier */ +#define AC97_PD_EAPD 0x8000 /* External Amplifer Power Down (EAPD) */ + +/* extended audio ID bit defines */ +#define AC97_EI_VRA 0x0001 /* Variable bit rate supported */ +#define AC97_EI_DRA 0x0002 /* Double rate supported */ +#define AC97_EI_SPDIF 0x0004 /* S/PDIF out supported */ +#define AC97_EI_VRM 0x0008 /* Variable bit rate supported for MIC */ +#define AC97_EI_DACS_SLOT_MASK 0x0030 /* DACs slot assignment */ +#define AC97_EI_DACS_SLOT_SHIFT 4 +#define AC97_EI_CDAC 0x0040 /* PCM Center DAC available */ +#define AC97_EI_SDAC 0x0080 /* PCM Surround DACs available */ +#define AC97_EI_LDAC 0x0100 /* PCM LFE DAC available */ +#define AC97_EI_AMAP 0x0200 /* indicates optional slot/DAC mapping based on codec ID */ +#define AC97_EI_REV_MASK 0x0c00 /* AC'97 revision mask */ +#define AC97_EI_REV_22 0x0400 /* AC'97 revision 2.2 */ +#define AC97_EI_REV_23 0x0800 /* AC'97 revision 2.3 */ +#define AC97_EI_REV_SHIFT 10 +#define AC97_EI_ADDR_MASK 0xc000 /* physical codec ID (address) */ +#define AC97_EI_ADDR_SHIFT 14 + +/* extended audio status and control bit defines */ +#define AC97_EA_VRA 0x0001 /* Variable bit rate enable bit */ +#define AC97_EA_DRA 0x0002 /* Double-rate audio enable bit */ +#define AC97_EA_SPDIF 0x0004 /* S/PDIF out enable bit */ +#define AC97_EA_VRM 0x0008 /* Variable bit rate for MIC enable bit */ +#define AC97_EA_SPSA_SLOT_MASK 0x0030 /* Mask for slot assignment bits */ +#define AC97_EA_SPSA_SLOT_SHIFT 4 +#define AC97_EA_SPSA_3_4 0x0000 /* Slot assigned to 3 & 4 */ +#define AC97_EA_SPSA_7_8 0x0010 /* Slot assigned to 7 & 8 */ +#define AC97_EA_SPSA_6_9 0x0020 /* Slot assigned to 6 & 9 */ +#define AC97_EA_SPSA_10_11 0x0030 /* Slot assigned to 10 & 11 */ +#define AC97_EA_CDAC 0x0040 /* PCM Center DAC is ready (Read only) */ +#define AC97_EA_SDAC 0x0080 /* PCM Surround DACs are ready (Read only) */ +#define AC97_EA_LDAC 0x0100 /* PCM LFE DAC is ready (Read only) */ +#define AC97_EA_MDAC 0x0200 /* MIC ADC is ready (Read only) */ +#define AC97_EA_SPCV 0x0400 /* S/PDIF configuration valid (Read only) */ +#define AC97_EA_PRI 0x0800 /* Turns the PCM Center DAC off */ +#define AC97_EA_PRJ 0x1000 /* Turns the PCM Surround DACs off */ +#define AC97_EA_PRK 0x2000 /* Turns the PCM LFE DAC off */ +#define AC97_EA_PRL 0x4000 /* Turns the MIC ADC off */ + +/* S/PDIF control bit defines */ +#define AC97_SC_PRO 0x0001 /* Professional status */ +#define AC97_SC_NAUDIO 0x0002 /* Non audio stream */ +#define AC97_SC_COPY 0x0004 /* Copyright status */ +#define AC97_SC_PRE 0x0008 /* Preemphasis status */ +#define AC97_SC_CC_MASK 0x07f0 /* Category Code mask */ +#define AC97_SC_CC_SHIFT 4 +#define AC97_SC_L 0x0800 /* Generation Level status */ +#define AC97_SC_SPSR_MASK 0x3000 /* S/PDIF Sample Rate bits */ +#define AC97_SC_SPSR_SHIFT 12 +#define AC97_SC_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */ +#define AC97_SC_SPSR_48K 0x2000 /* Use 48kHz Sample rate */ +#define AC97_SC_SPSR_32K 0x3000 /* Use 32kHz Sample rate */ +#define AC97_SC_DRS 0x4000 /* Double Rate S/PDIF */ +#define AC97_SC_V 0x8000 /* Validity status */ + +/* Interrupt and Paging bit defines (AC'97 2.3) */ +#define AC97_PAGE_MASK 0x000f /* Page Selector */ +#define AC97_PAGE_VENDOR 0 /* Vendor-specific registers */ +#define AC97_PAGE_1 1 /* Extended Codec Registers page 1 */ +#define AC97_INT_ENABLE 0x0800 /* Interrupt Enable */ +#define AC97_INT_SENSE 0x1000 /* Sense Cycle */ +#define AC97_INT_CAUSE_SENSE 0x2000 /* Sense Cycle Completed (RO) */ +#define AC97_INT_CAUSE_GPIO 0x4000 /* GPIO bits changed (RO) */ +#define AC97_INT_STATUS 0x8000 /* Interrupt Status */ + +/* extended modem ID bit defines */ +#define AC97_MEI_LINE1 0x0001 /* Line1 present */ +#define AC97_MEI_LINE2 0x0002 /* Line2 present */ +#define AC97_MEI_HANDSET 0x0004 /* Handset present */ +#define AC97_MEI_CID1 0x0008 /* caller ID decode for Line1 is supported */ +#define AC97_MEI_CID2 0x0010 /* caller ID decode for Line2 is supported */ +#define AC97_MEI_ADDR_MASK 0xc000 /* physical codec ID (address) */ +#define AC97_MEI_ADDR_SHIFT 14 + +/* extended modem status and control bit defines */ +#define AC97_MEA_GPIO 0x0001 /* GPIO is ready (ro) */ +#define AC97_MEA_MREF 0x0002 /* Vref is up to nominal level (ro) */ +#define AC97_MEA_ADC1 0x0004 /* ADC1 operational (ro) */ +#define AC97_MEA_DAC1 0x0008 /* DAC1 operational (ro) */ +#define AC97_MEA_ADC2 0x0010 /* ADC2 operational (ro) */ +#define AC97_MEA_DAC2 0x0020 /* DAC2 operational (ro) */ +#define AC97_MEA_HADC 0x0040 /* HADC operational (ro) */ +#define AC97_MEA_HDAC 0x0080 /* HDAC operational (ro) */ +#define AC97_MEA_PRA 0x0100 /* GPIO power down (high) */ +#define AC97_MEA_PRB 0x0200 /* reserved */ +#define AC97_MEA_PRC 0x0400 /* ADC1 power down (high) */ +#define AC97_MEA_PRD 0x0800 /* DAC1 power down (high) */ +#define AC97_MEA_PRE 0x1000 /* ADC2 power down (high) */ +#define AC97_MEA_PRF 0x2000 /* DAC2 power down (high) */ +#define AC97_MEA_PRG 0x4000 /* HADC power down (high) */ +#define AC97_MEA_PRH 0x8000 /* HDAC power down (high) */ + +/* modem gpio status defines */ +#define AC97_GPIO_LINE1_OH 0x0001 /* Off Hook Line1 */ +#define AC97_GPIO_LINE1_RI 0x0002 /* Ring Detect Line1 */ +#define AC97_GPIO_LINE1_CID 0x0004 /* Caller ID path enable Line1 */ +#define AC97_GPIO_LINE1_LCS 0x0008 /* Loop Current Sense Line1 */ +#define AC97_GPIO_LINE1_PULSE 0x0010 /* Opt./ Pulse Dial Line1 (out) */ +#define AC97_GPIO_LINE1_HL1R 0x0020 /* Opt./ Handset to Line1 relay control (out) */ +#define AC97_GPIO_LINE1_HOHD 0x0040 /* Opt./ Handset off hook detect Line1 (in) */ +#define AC97_GPIO_LINE12_AC 0x0080 /* Opt./ Int.bit 1 / Line1/2 AC (out) */ +#define AC97_GPIO_LINE12_DC 0x0100 /* Opt./ Int.bit 2 / Line1/2 DC (out) */ +#define AC97_GPIO_LINE12_RS 0x0200 /* Opt./ Int.bit 3 / Line1/2 RS (out) */ +#define AC97_GPIO_LINE2_OH 0x0400 /* Off Hook Line2 */ +#define AC97_GPIO_LINE2_RI 0x0800 /* Ring Detect Line2 */ +#define AC97_GPIO_LINE2_CID 0x1000 /* Caller ID path enable Line2 */ +#define AC97_GPIO_LINE2_LCS 0x2000 /* Loop Current Sense Line2 */ +#define AC97_GPIO_LINE2_PULSE 0x4000 /* Opt./ Pulse Dial Line2 (out) */ +#define AC97_GPIO_LINE2_HL1R 0x8000 /* Opt./ Handset to Line2 relay control (out) */ + diff --git a/include/sound/ac97_codec.h b/include/sound/ac97_codec.h new file mode 100644 index 000000000..49200ec26 --- /dev/null +++ b/include/sound/ac97_codec.h @@ -0,0 +1,418 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + * Universal interface for Audio Codec '97 + * + * For more details look to AC '97 component specification revision 2.1 + * by Intel Corporation (http://developer.intel.com). + */ + +#ifndef __SOUND_AC97_CODEC_H +#define __SOUND_AC97_CODEC_H + +#include <linux/bitops.h> +#include <linux/device.h> +#include <linux/workqueue.h> +#include <sound/ac97/regs.h> +#include <sound/pcm.h> +#include <sound/control.h> +#include <sound/info.h> + +/* maximum number of devices on the AC97 bus */ +#define AC97_BUS_MAX_DEVICES 4 + +/* specific - SigmaTel */ +#define AC97_SIGMATEL_OUTSEL 0x64 /* Output Select, STAC9758 */ +#define AC97_SIGMATEL_INSEL 0x66 /* Input Select, STAC9758 */ +#define AC97_SIGMATEL_IOMISC 0x68 /* STAC9758 */ +#define AC97_SIGMATEL_ANALOG 0x6c /* Analog Special */ +#define AC97_SIGMATEL_DAC2INVERT 0x6e +#define AC97_SIGMATEL_BIAS1 0x70 +#define AC97_SIGMATEL_BIAS2 0x72 +#define AC97_SIGMATEL_VARIOUS 0x72 /* STAC9758 */ +#define AC97_SIGMATEL_MULTICHN 0x74 /* Multi-Channel programming */ +#define AC97_SIGMATEL_CIC1 0x76 +#define AC97_SIGMATEL_CIC2 0x78 + +/* specific - Analog Devices */ +#define AC97_AD_TEST 0x5a /* test register */ +#define AC97_AD_TEST2 0x5c /* undocumented test register 2 */ +#define AC97_AD_HPFD_SHIFT 12 /* High Pass Filter Disable */ +#define AC97_AD_CODEC_CFG 0x70 /* codec configuration */ +#define AC97_AD_JACK_SPDIF 0x72 /* Jack Sense & S/PDIF */ +#define AC97_AD_SERIAL_CFG 0x74 /* Serial Configuration */ +#define AC97_AD_MISC 0x76 /* Misc Control Bits */ +#define AC97_AD_VREFD_SHIFT 2 /* V_REFOUT Disable (AD1888) */ + +/* specific - Cirrus Logic */ +#define AC97_CSR_ACMODE 0x5e /* AC Mode Register */ +#define AC97_CSR_MISC_CRYSTAL 0x60 /* Misc Crystal Control */ +#define AC97_CSR_SPDIF 0x68 /* S/PDIF Register */ +#define AC97_CSR_SERIAL 0x6a /* Serial Port Control */ +#define AC97_CSR_SPECF_ADDR 0x6c /* Special Feature Address */ +#define AC97_CSR_SPECF_DATA 0x6e /* Special Feature Data */ +#define AC97_CSR_BDI_STATUS 0x7a /* BDI Status */ + +/* specific - Conexant */ +#define AC97_CXR_AUDIO_MISC 0x5c +#define AC97_CXR_SPDIFEN (1<<3) +#define AC97_CXR_COPYRGT (1<<2) +#define AC97_CXR_SPDIF_MASK (3<<0) +#define AC97_CXR_SPDIF_PCM 0x0 +#define AC97_CXR_SPDIF_AC3 0x2 + +/* specific - ALC */ +#define AC97_ALC650_SPDIF_INPUT_STATUS1 0x60 +/* S/PDIF input status 1 bit defines */ +#define AC97_ALC650_PRO 0x0001 /* Professional status */ +#define AC97_ALC650_NAUDIO 0x0002 /* Non audio stream */ +#define AC97_ALC650_COPY 0x0004 /* Copyright status */ +#define AC97_ALC650_PRE 0x0038 /* Preemphasis status */ +#define AC97_ALC650_PRE_SHIFT 3 +#define AC97_ALC650_MODE 0x00C0 /* Preemphasis status */ +#define AC97_ALC650_MODE_SHIFT 6 +#define AC97_ALC650_CC_MASK 0x7f00 /* Category Code mask */ +#define AC97_ALC650_CC_SHIFT 8 +#define AC97_ALC650_L 0x8000 /* Generation Level status */ + +#define AC97_ALC650_SPDIF_INPUT_STATUS2 0x62 +/* S/PDIF input status 2 bit defines */ +#define AC97_ALC650_SOUCE_MASK 0x000f /* Source number */ +#define AC97_ALC650_CHANNEL_MASK 0x00f0 /* Channel number */ +#define AC97_ALC650_CHANNEL_SHIFT 4 +#define AC97_ALC650_SPSR_MASK 0x0f00 /* S/PDIF Sample Rate bits */ +#define AC97_ALC650_SPSR_SHIFT 8 +#define AC97_ALC650_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */ +#define AC97_ALC650_SPSR_48K 0x0200 /* Use 48kHz Sample rate */ +#define AC97_ALC650_SPSR_32K 0x0300 /* Use 32kHz Sample rate */ +#define AC97_ALC650_CLOCK_ACCURACY 0x3000 /* Clock accuracy */ +#define AC97_ALC650_CLOCK_SHIFT 12 +#define AC97_ALC650_CLOCK_LOCK 0x4000 /* Clock locked status */ +#define AC97_ALC650_V 0x8000 /* Validity status */ + +#define AC97_ALC650_SURR_DAC_VOL 0x64 +#define AC97_ALC650_LFE_DAC_VOL 0x66 +#define AC97_ALC650_UNKNOWN1 0x68 +#define AC97_ALC650_MULTICH 0x6a +#define AC97_ALC650_UNKNOWN2 0x6c +#define AC97_ALC650_REVISION 0x6e +#define AC97_ALC650_UNKNOWN3 0x70 +#define AC97_ALC650_UNKNOWN4 0x72 +#define AC97_ALC650_MISC 0x74 +#define AC97_ALC650_GPIO_SETUP 0x76 +#define AC97_ALC650_GPIO_STATUS 0x78 +#define AC97_ALC650_CLOCK 0x7a + +/* specific - Yamaha YMF7x3 */ +#define AC97_YMF7X3_DIT_CTRL 0x66 /* DIT Control (YMF743) / 2 (YMF753) */ +#define AC97_YMF7X3_3D_MODE_SEL 0x68 /* 3D Mode Select */ + +/* specific - C-Media */ +#define AC97_CM9738_VENDOR_CTRL 0x5a +#define AC97_CM9739_MULTI_CHAN 0x64 +#define AC97_CM9739_SPDIF_IN_STATUS 0x68 /* 32bit */ +#define AC97_CM9739_SPDIF_CTRL 0x6c + +/* specific - wolfson */ +#define AC97_WM97XX_FMIXER_VOL 0x72 +#define AC97_WM9704_RMIXER_VOL 0x74 +#define AC97_WM9704_TEST 0x5a +#define AC97_WM9704_RPCM_VOL 0x70 +#define AC97_WM9711_OUT3VOL 0x16 + + +/* ac97->scaps */ +#define AC97_SCAP_AUDIO (1<<0) /* audio codec 97 */ +#define AC97_SCAP_MODEM (1<<1) /* modem codec 97 */ +#define AC97_SCAP_SURROUND_DAC (1<<2) /* surround L&R DACs are present */ +#define AC97_SCAP_CENTER_LFE_DAC (1<<3) /* center and LFE DACs are present */ +#define AC97_SCAP_SKIP_AUDIO (1<<4) /* skip audio part of codec */ +#define AC97_SCAP_SKIP_MODEM (1<<5) /* skip modem part of codec */ +#define AC97_SCAP_INDEP_SDIN (1<<6) /* independent SDIN */ +#define AC97_SCAP_INV_EAPD (1<<7) /* inverted EAPD */ +#define AC97_SCAP_DETECT_BY_VENDOR (1<<8) /* use vendor registers for read tests */ +#define AC97_SCAP_NO_SPDIF (1<<9) /* don't build SPDIF controls */ +#define AC97_SCAP_EAPD_LED (1<<10) /* EAPD as mute LED */ +#define AC97_SCAP_POWER_SAVE (1<<11) /* capable for aggressive power-saving */ + +/* ac97->flags */ +#define AC97_HAS_PC_BEEP (1<<0) /* force PC Speaker usage */ +#define AC97_AD_MULTI (1<<1) /* Analog Devices - multi codecs */ +#define AC97_CS_SPDIF (1<<2) /* Cirrus Logic uses funky SPDIF */ +#define AC97_CX_SPDIF (1<<3) /* Conexant's spdif interface */ +#define AC97_STEREO_MUTES (1<<4) /* has stereo mute bits */ +#define AC97_DOUBLE_RATE (1<<5) /* supports double rate playback */ +#define AC97_HAS_NO_MASTER_VOL (1<<6) /* no Master volume */ +#define AC97_HAS_NO_PCM_VOL (1<<7) /* no PCM volume */ +#define AC97_DEFAULT_POWER_OFF (1<<8) /* no RESET write */ +#define AC97_MODEM_PATCH (1<<9) /* modem patch */ +#define AC97_HAS_NO_REC_GAIN (1<<10) /* no Record gain */ +#define AC97_HAS_NO_PHONE (1<<11) /* no PHONE volume */ +#define AC97_HAS_NO_PC_BEEP (1<<12) /* no PC Beep volume */ +#define AC97_HAS_NO_VIDEO (1<<13) /* no Video volume */ +#define AC97_HAS_NO_CD (1<<14) /* no CD volume */ +#define AC97_HAS_NO_MIC (1<<15) /* no MIC volume */ +#define AC97_HAS_NO_TONE (1<<16) /* no Tone volume */ +#define AC97_HAS_NO_STD_PCM (1<<17) /* no standard AC97 PCM volume and mute */ +#define AC97_HAS_NO_AUX (1<<18) /* no standard AC97 AUX volume and mute */ +#define AC97_HAS_8CH (1<<19) /* supports 8-channel output */ + +/* rates indexes */ +#define AC97_RATES_FRONT_DAC 0 +#define AC97_RATES_SURR_DAC 1 +#define AC97_RATES_LFE_DAC 2 +#define AC97_RATES_ADC 3 +#define AC97_RATES_MIC_ADC 4 +#define AC97_RATES_SPDIF 5 + +#define AC97_NUM_GPIOS 16 +/* + * + */ + +struct snd_ac97; +struct snd_ac97_gpio_priv; +struct snd_pcm_chmap; + +struct snd_ac97_build_ops { + int (*build_3d) (struct snd_ac97 *ac97); + int (*build_specific) (struct snd_ac97 *ac97); + int (*build_spdif) (struct snd_ac97 *ac97); + int (*build_post_spdif) (struct snd_ac97 *ac97); +#ifdef CONFIG_PM + void (*suspend) (struct snd_ac97 *ac97); + void (*resume) (struct snd_ac97 *ac97); +#endif + void (*update_jacks) (struct snd_ac97 *ac97); /* for jack-sharing */ +}; + +struct snd_ac97_bus_ops { + void (*reset) (struct snd_ac97 *ac97); + void (*warm_reset)(struct snd_ac97 *ac97); + void (*write) (struct snd_ac97 *ac97, unsigned short reg, unsigned short val); + unsigned short (*read) (struct snd_ac97 *ac97, unsigned short reg); + void (*wait) (struct snd_ac97 *ac97); + void (*init) (struct snd_ac97 *ac97); +}; + +struct snd_ac97_bus { + /* -- lowlevel (hardware) driver specific -- */ + const struct snd_ac97_bus_ops *ops; + void *private_data; + void (*private_free) (struct snd_ac97_bus *bus); + /* --- */ + struct snd_card *card; + unsigned short num; /* bus number */ + unsigned short no_vra: 1, /* bridge doesn't support VRA */ + dra: 1, /* bridge supports double rate */ + isdin: 1;/* independent SDIN */ + unsigned int clock; /* AC'97 base clock (usually 48000Hz) */ + spinlock_t bus_lock; /* used mainly for slot allocation */ + unsigned short used_slots[2][4]; /* actually used PCM slots */ + unsigned short pcms_count; /* count of PCMs */ + struct ac97_pcm *pcms; + struct snd_ac97 *codec[4]; + struct snd_info_entry *proc; +}; + +/* static resolution table */ +struct snd_ac97_res_table { + unsigned short reg; /* register */ + unsigned short bits; /* resolution bitmask */ +}; + +struct snd_ac97_template { + void *private_data; + void (*private_free) (struct snd_ac97 *ac97); + struct pci_dev *pci; /* assigned PCI device - used for quirks */ + unsigned short num; /* number of codec: 0 = primary, 1 = secondary */ + unsigned short addr; /* physical address of codec [0-3] */ + unsigned int scaps; /* driver capabilities */ + const struct snd_ac97_res_table *res_table; /* static resolution */ +}; + +struct snd_ac97 { + /* -- lowlevel (hardware) driver specific -- */ + const struct snd_ac97_build_ops *build_ops; + void *private_data; + void (*private_free) (struct snd_ac97 *ac97); + /* --- */ + struct snd_ac97_bus *bus; + struct pci_dev *pci; /* assigned PCI device - used for quirks */ + struct snd_info_entry *proc; + struct snd_info_entry *proc_regs; + unsigned short subsystem_vendor; + unsigned short subsystem_device; + struct mutex reg_mutex; + struct mutex page_mutex; /* mutex for AD18xx multi-codecs and paging (2.3) */ + unsigned short num; /* number of codec: 0 = primary, 1 = secondary */ + unsigned short addr; /* physical address of codec [0-3] */ + unsigned int id; /* identification of codec */ + unsigned short caps; /* capabilities (register 0) */ + unsigned short ext_id; /* extended feature identification (register 28) */ + unsigned short ext_mid; /* extended modem ID (register 3C) */ + const struct snd_ac97_res_table *res_table; /* static resolution */ + unsigned int scaps; /* driver capabilities */ + unsigned int flags; /* specific code */ + unsigned int rates[6]; /* see AC97_RATES_* defines */ + unsigned int spdif_status; + unsigned short regs[0x80]; /* register cache */ + DECLARE_BITMAP(reg_accessed, 0x80); /* bit flags */ + union { /* vendor specific code */ + struct { + unsigned short unchained[3]; // 0 = C34, 1 = C79, 2 = C69 + unsigned short chained[3]; // 0 = C34, 1 = C79, 2 = C69 + unsigned short id[3]; // codec IDs (lower 16-bit word) + unsigned short pcmreg[3]; // PCM registers + unsigned short codec_cfg[3]; // CODEC_CFG bits + unsigned char swap_mic_linein; // AD1986/AD1986A only + unsigned char lo_as_master; /* LO as master */ + } ad18xx; + unsigned int dev_flags; /* device specific */ + } spec; + /* jack-sharing info */ + unsigned char indep_surround; + unsigned char channel_mode; + +#ifdef CONFIG_SND_AC97_POWER_SAVE + unsigned int power_up; /* power states */ + struct delayed_work power_work; +#endif + struct device dev; + struct snd_ac97_gpio_priv *gpio_priv; + + struct snd_pcm_chmap *chmaps[2]; /* channel-maps (optional) */ +}; + +#define to_ac97_t(d) container_of(d, struct snd_ac97, dev) + +/* conditions */ +static inline int ac97_is_audio(struct snd_ac97 * ac97) +{ + return (ac97->scaps & AC97_SCAP_AUDIO); +} +static inline int ac97_is_modem(struct snd_ac97 * ac97) +{ + return (ac97->scaps & AC97_SCAP_MODEM); +} +static inline int ac97_is_rev22(struct snd_ac97 * ac97) +{ + return (ac97->ext_id & AC97_EI_REV_MASK) >= AC97_EI_REV_22; +} +static inline int ac97_can_amap(struct snd_ac97 * ac97) +{ + return (ac97->ext_id & AC97_EI_AMAP) != 0; +} +static inline int ac97_can_spdif(struct snd_ac97 * ac97) +{ + return (ac97->ext_id & AC97_EI_SPDIF) != 0; +} + +/* functions */ +/* create new AC97 bus */ +int snd_ac97_bus(struct snd_card *card, int num, + const struct snd_ac97_bus_ops *ops, + void *private_data, struct snd_ac97_bus **rbus); +/* create mixer controls */ +int snd_ac97_mixer(struct snd_ac97_bus *bus, struct snd_ac97_template *template, + struct snd_ac97 **rac97); +const char *snd_ac97_get_short_name(struct snd_ac97 *ac97); + +void snd_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short value); +unsigned short snd_ac97_read(struct snd_ac97 *ac97, unsigned short reg); +void snd_ac97_write_cache(struct snd_ac97 *ac97, unsigned short reg, unsigned short value); +int snd_ac97_update(struct snd_ac97 *ac97, unsigned short reg, unsigned short value); +int snd_ac97_update_bits(struct snd_ac97 *ac97, unsigned short reg, unsigned short mask, unsigned short value); +#ifdef CONFIG_SND_AC97_POWER_SAVE +int snd_ac97_update_power(struct snd_ac97 *ac97, int reg, int powerup); +#else +static inline int snd_ac97_update_power(struct snd_ac97 *ac97, int reg, + int powerup) +{ + return 0; +} +#endif +#ifdef CONFIG_PM +void snd_ac97_suspend(struct snd_ac97 *ac97); +void snd_ac97_resume(struct snd_ac97 *ac97); +#endif +int snd_ac97_reset(struct snd_ac97 *ac97, bool try_warm, unsigned int id, + unsigned int id_mask); + +/* quirk types */ +enum { + AC97_TUNE_DEFAULT = -1, /* use default from quirk list (not valid in list) */ + AC97_TUNE_NONE = 0, /* nothing extra to do */ + AC97_TUNE_HP_ONLY, /* headphone (true line-out) control as master only */ + AC97_TUNE_SWAP_HP, /* swap headphone and master controls */ + AC97_TUNE_SWAP_SURROUND, /* swap master and surround controls */ + AC97_TUNE_AD_SHARING, /* for AD1985, turn on OMS bit and use headphone */ + AC97_TUNE_ALC_JACK, /* for Realtek, enable JACK detection */ + AC97_TUNE_INV_EAPD, /* inverted EAPD implementation */ + AC97_TUNE_MUTE_LED, /* EAPD bit works as mute LED */ + AC97_TUNE_HP_MUTE_LED, /* EAPD bit works as mute LED, use headphone control as master */ +}; + +struct ac97_quirk { + unsigned short subvendor; /* PCI subsystem vendor id */ + unsigned short subdevice; /* PCI subsystem device id */ + unsigned short mask; /* device id bit mask, 0 = accept all */ + unsigned int codec_id; /* codec id (if any), 0 = accept all */ + const char *name; /* name shown as info */ + int type; /* quirk type above */ +}; + +int snd_ac97_tune_hardware(struct snd_ac97 *ac97, + const struct ac97_quirk *quirk, + const char *override); +int snd_ac97_set_rate(struct snd_ac97 *ac97, int reg, unsigned int rate); + +/* + * PCM allocation + */ + +enum ac97_pcm_cfg { + AC97_PCM_CFG_FRONT = 2, + AC97_PCM_CFG_REAR = 10, /* alias surround */ + AC97_PCM_CFG_LFE = 11, /* center + lfe */ + AC97_PCM_CFG_40 = 4, /* front + rear */ + AC97_PCM_CFG_51 = 6, /* front + rear + center/lfe */ + AC97_PCM_CFG_SPDIF = 20 +}; + +struct ac97_pcm { + struct snd_ac97_bus *bus; + unsigned int stream: 1, /* stream type: 1 = capture */ + exclusive: 1, /* exclusive mode, don't override with other pcms */ + copy_flag: 1, /* lowlevel driver must fill all entries */ + spdif: 1; /* spdif pcm */ + unsigned short aslots; /* active slots */ + unsigned short cur_dbl; /* current double-rate state */ + unsigned int rates; /* available rates */ + struct { + unsigned short slots; /* driver input: requested AC97 slot numbers */ + unsigned short rslots[4]; /* allocated slots per codecs */ + unsigned char rate_table[4]; + struct snd_ac97 *codec[4]; /* allocated codecs */ + } r[2]; /* 0 = standard rates, 1 = double rates */ + unsigned long private_value; /* used by the hardware driver */ +}; + +int snd_ac97_pcm_assign(struct snd_ac97_bus *ac97, + unsigned short pcms_count, + const struct ac97_pcm *pcms); +int snd_ac97_pcm_open(struct ac97_pcm *pcm, unsigned int rate, + enum ac97_pcm_cfg cfg, unsigned short slots); +int snd_ac97_pcm_close(struct ac97_pcm *pcm); +int snd_ac97_pcm_double_rate_rules(struct snd_pcm_runtime *runtime); + +/* ad hoc AC97 device driver access */ +extern struct bus_type ac97_bus_type; + +/* AC97 platform_data adding function */ +static inline void snd_ac97_dev_add_pdata(struct snd_ac97 *ac97, void *data) +{ + ac97->dev.platform_data = data; +} + +#endif /* __SOUND_AC97_CODEC_H */ diff --git a/include/sound/aci.h b/include/sound/aci.h new file mode 100644 index 000000000..6ebbd4223 --- /dev/null +++ b/include/sound/aci.h @@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ACI_H_ +#define _ACI_H_ + +#define ACI_REG_COMMAND 0 /* write register offset */ +#define ACI_REG_STATUS 1 /* read register offset */ +#define ACI_REG_BUSY 2 /* busy register offset */ +#define ACI_REG_RDS 2 /* PCM20: RDS register offset */ +#define ACI_MINTIME 500 /* ACI time out limit */ + +#define ACI_SET_MUTE 0x0d +#define ACI_SET_POWERAMP 0x0f +#define ACI_SET_TUNERMUTE 0xa3 +#define ACI_SET_TUNERMONO 0xa4 +#define ACI_SET_IDE 0xd0 +#define ACI_SET_WSS 0xd1 +#define ACI_SET_SOLOMODE 0xd2 +#define ACI_SET_PREAMP 0x03 +#define ACI_GET_PREAMP 0x21 +#define ACI_WRITE_TUNE 0xa7 +#define ACI_READ_TUNERSTEREO 0xa8 +#define ACI_READ_TUNERSTATION 0xa9 +#define ACI_READ_VERSION 0xf1 +#define ACI_READ_IDCODE 0xf2 +#define ACI_INIT 0xff +#define ACI_STATUS 0xf0 +#define ACI_S_GENERAL 0x00 +#define ACI_ERROR_OP 0xdf + +/* ACI Mixer */ + +/* These are the values for the right channel GET registers. + Add an offset of 0x01 for the left channel register. + (left=right+0x01) */ + +#define ACI_GET_MASTER 0x03 +#define ACI_GET_MIC 0x05 +#define ACI_GET_LINE 0x07 +#define ACI_GET_CD 0x09 +#define ACI_GET_SYNTH 0x0b +#define ACI_GET_PCM 0x0d +#define ACI_GET_LINE1 0x10 /* Radio on PCM20 */ +#define ACI_GET_LINE2 0x12 + +#define ACI_GET_EQ1 0x22 /* from Bass ... */ +#define ACI_GET_EQ2 0x24 +#define ACI_GET_EQ3 0x26 +#define ACI_GET_EQ4 0x28 +#define ACI_GET_EQ5 0x2a +#define ACI_GET_EQ6 0x2c +#define ACI_GET_EQ7 0x2e /* ... to Treble */ + +/* And these are the values for the right channel SET registers. + For left channel access you have to add an offset of 0x08. + MASTER is an exception, which needs an offset of 0x01 */ + +#define ACI_SET_MASTER 0x00 +#define ACI_SET_MIC 0x30 +#define ACI_SET_LINE 0x31 +#define ACI_SET_CD 0x34 +#define ACI_SET_SYNTH 0x33 +#define ACI_SET_PCM 0x32 +#define ACI_SET_LINE1 0x35 /* Radio on PCM20 */ +#define ACI_SET_LINE2 0x36 + +#define ACI_SET_EQ1 0x40 /* from Bass ... */ +#define ACI_SET_EQ2 0x41 +#define ACI_SET_EQ3 0x42 +#define ACI_SET_EQ4 0x43 +#define ACI_SET_EQ5 0x44 +#define ACI_SET_EQ6 0x45 +#define ACI_SET_EQ7 0x46 /* ... to Treble */ + +struct snd_miro_aci { + unsigned long aci_port; + int aci_vendor; + int aci_product; + int aci_version; + int aci_amp; + int aci_preamp; + int aci_solomode; + + struct mutex aci_mutex; +}; + +int snd_aci_cmd(struct snd_miro_aci *aci, int write1, int write2, int write3); + +struct snd_miro_aci *snd_aci_get_aci(void); + +#endif /* _ACI_H_ */ + diff --git a/include/sound/acp63_chip_offset_byte.h b/include/sound/acp63_chip_offset_byte.h new file mode 100644 index 000000000..b02d0467c --- /dev/null +++ b/include/sound/acp63_chip_offset_byte.h @@ -0,0 +1,444 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * AMD ACP 6.3 Register Documentation + * + * Copyright 2022 Advanced Micro Devices, Inc. + */ + +#ifndef _acp_ip_OFFSET_HEADER +#define _acp_ip_OFFSET_HEADER + +/* Registers from ACP_DMA block */ +#define ACP_DMA_CNTL_0 0x0000000 +#define ACP_DMA_CNTL_1 0x0000004 +#define ACP_DMA_CNTL_2 0x0000008 +#define ACP_DMA_CNTL_3 0x000000C +#define ACP_DMA_CNTL_4 0x0000010 +#define ACP_DMA_CNTL_5 0x0000014 +#define ACP_DMA_CNTL_6 0x0000018 +#define ACP_DMA_CNTL_7 0x000001C +#define ACP_DMA_DSCR_STRT_IDX_0 0x0000020 +#define ACP_DMA_DSCR_STRT_IDX_1 0x0000024 +#define ACP_DMA_DSCR_STRT_IDX_2 0x0000028 +#define ACP_DMA_DSCR_STRT_IDX_3 0x000002C +#define ACP_DMA_DSCR_STRT_IDX_4 0x0000030 +#define ACP_DMA_DSCR_STRT_IDX_5 0x0000034 +#define ACP_DMA_DSCR_STRT_IDX_6 0x0000038 +#define ACP_DMA_DSCR_STRT_IDX_7 0x000003C +#define ACP_DMA_DSCR_CNT_0 0x0000040 +#define ACP_DMA_DSCR_CNT_1 0x0000044 +#define ACP_DMA_DSCR_CNT_2 0x0000048 +#define ACP_DMA_DSCR_CNT_3 0x000004C +#define ACP_DMA_DSCR_CNT_4 0x0000050 +#define ACP_DMA_DSCR_CNT_5 0x0000054 +#define ACP_DMA_DSCR_CNT_6 0x0000058 +#define ACP_DMA_DSCR_CNT_7 0x000005C +#define ACP_DMA_PRIO_0 0x0000060 +#define ACP_DMA_PRIO_1 0x0000064 +#define ACP_DMA_PRIO_2 0x0000068 +#define ACP_DMA_PRIO_3 0x000006C +#define ACP_DMA_PRIO_4 0x0000070 +#define ACP_DMA_PRIO_5 0x0000074 +#define ACP_DMA_PRIO_6 0x0000078 +#define ACP_DMA_PRIO_7 0x000007C +#define ACP_DMA_CUR_DSCR_0 0x0000080 +#define ACP_DMA_CUR_DSCR_1 0x0000084 +#define ACP_DMA_CUR_DSCR_2 0x0000088 +#define ACP_DMA_CUR_DSCR_3 0x000008C +#define ACP_DMA_CUR_DSCR_4 0x0000090 +#define ACP_DMA_CUR_DSCR_5 0x0000094 +#define ACP_DMA_CUR_DSCR_6 0x0000098 +#define ACP_DMA_CUR_DSCR_7 0x000009C +#define ACP_DMA_CUR_TRANS_CNT_0 0x00000A0 +#define ACP_DMA_CUR_TRANS_CNT_1 0x00000A4 +#define ACP_DMA_CUR_TRANS_CNT_2 0x00000A8 +#define ACP_DMA_CUR_TRANS_CNT_3 0x00000AC +#define ACP_DMA_CUR_TRANS_CNT_4 0x00000B0 +#define ACP_DMA_CUR_TRANS_CNT_5 0x00000B4 +#define ACP_DMA_CUR_TRANS_CNT_6 0x00000B8 +#define ACP_DMA_CUR_TRANS_CNT_7 0x00000BC +#define ACP_DMA_ERR_STS_0 0x00000C0 +#define ACP_DMA_ERR_STS_1 0x00000C4 +#define ACP_DMA_ERR_STS_2 0x00000C8 +#define ACP_DMA_ERR_STS_3 0x00000CC +#define ACP_DMA_ERR_STS_4 0x00000D0 +#define ACP_DMA_ERR_STS_5 0x00000D4 +#define ACP_DMA_ERR_STS_6 0x00000D8 +#define ACP_DMA_ERR_STS_7 0x00000DC +#define ACP_DMA_DESC_BASE_ADDR 0x00000E0 +#define ACP_DMA_DESC_MAX_NUM_DSCR 0x00000E4 +#define ACP_DMA_CH_STS 0x00000E8 +#define ACP_DMA_CH_GROUP 0x00000EC +#define ACP_DMA_CH_RST_STS 0x00000F0 + +/* Registers from ACP_AXI2AXIATU block */ +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_1 0x0000C00 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_1 0x0000C04 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_2 0x0000C08 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_2 0x0000C0C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_3 0x0000C10 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_3 0x0000C14 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_4 0x0000C18 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_4 0x0000C1C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_5 0x0000C20 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_5 0x0000C24 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_6 0x0000C28 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_6 0x0000C2C +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_7 0x0000C30 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_7 0x0000C34 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_8 0x0000C38 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_8 0x0000C3C +#define ACPAXI2AXI_ATU_CTRL 0x0000C40 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_9 0x0000C44 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_9 0x0000C48 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_10 0x0000C4C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_10 0x0000C50 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_11 0x0000C54 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_11 0x0000C58 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_12 0x0000C5C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_12 0x0000C60 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_13 0x0000C64 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_13 0x0000C68 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_14 0x0000C6C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_14 0x0000C70 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_15 0x0000C74 +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_15 0x0000C78 +#define ACPAXI2AXI_ATU_PAGE_SIZE_GRP_16 0x0000C7C +#define ACPAXI2AXI_ATU_BASE_ADDR_GRP_16 0x0000C80 + +/* Registers from ACP_CLKRST block */ +#define ACP_SOFT_RESET 0x0001000 +#define ACP_CONTROL 0x0001004 +#define ACP_STATUS 0x0001008 +#define ACP_DYNAMIC_CG_MASTER_CONTROL 0x0001010 +#define ACP_ZSC_DSP_CTRL 0x0001014 +#define ACP_ZSC_STS 0x0001018 +#define ACP_PGFSM_CONTROL 0x0001024 +#define ACP_PGFSM_STATUS 0x0001028 +#define ACP_CLKMUX_SEL 0x000102C + +/* Registers from ACP_AON block */ +#define ACP_PME_EN 0x0001400 +#define ACP_DEVICE_STATE 0x0001404 +#define AZ_DEVICE_STATE 0x0001408 +#define ACP_PIN_CONFIG 0x0001440 +#define ACP_PAD_PULLUP_CTRL 0x0001444 +#define ACP_PAD_PULLDOWN_CTRL 0x0001448 +#define ACP_PAD_DRIVE_STRENGTH_CTRL 0x000144C +#define ACP_PAD_SCHMEN_CTRL 0x0001450 +#define ACP_SW_PAD_KEEPER_EN 0x0001454 +#define ACP_SW_WAKE_EN 0x0001458 +#define ACP_I2S_WAKE_EN 0x000145C +#define ACP_SW1_WAKE_EN 0x0001460 + +/* Registers from ACP_P1_MISC block */ +#define ACP_EXTERNAL_INTR_ENB 0x0001A00 +#define ACP_EXTERNAL_INTR_CNTL 0x0001A04 +#define ACP_EXTERNAL_INTR_CNTL1 0x0001A08 +#define ACP_EXTERNAL_INTR_STAT 0x0001A0C +#define ACP_EXTERNAL_INTR_STAT1 0x0001A10 +#define ACP_ERROR_STATUS 0x0001A4C +#define ACP_P1_SW_I2S_ERROR_REASON 0x0001A50 +#define ACP_P1_SW_POS_TRACK_I2S_TX_CTRL 0x0001A6C +#define ACP_P1_SW_I2S_TX_DMA_POS 0x0001A70 +#define ACP_P1_SW_POS_TRACK_I2S_RX_CTRL 0x0001A74 +#define ACP_P1_SW_I2S_RX_DMA_POS 0x0001A78 +#define ACP_P1_DMIC_I2S_GPIO_INTR_CTRL 0x0001A7C +#define ACP_P1_DMIC_I2S_GPIO_INTR_STATUS 0x0001A80 +#define ACP_SCRATCH_REG_BASE_ADDR 0x0001A84 +#define ACP_P1_SW_POS_TRACK_BT_TX_CTRL 0x0001A88 +#define ACP_P1_SW_BT_TX_DMA_POS 0x0001A8C +#define ACP_P1_SW_POS_TRACK_HS_TX_CTRL 0x0001A90 +#define ACP_P1_SW_HS_TX_DMA_POS 0x0001A94 +#define ACP_P1_SW_POS_TRACK_BT_RX_CTRL 0x0001A98 +#define ACP_P1_SW_BT_RX_DMA_POS 0x0001A9C +#define ACP_P1_SW_POS_TRACK_HS_RX_CTRL 0x0001AA0 +#define ACP_P1_SW_HS_RX_DMA_POS 0x0001AA4 + +/* Registers from ACP_AUDIO_BUFFERS block */ +#define ACP_I2S_RX_RINGBUFADDR 0x0002000 +#define ACP_I2S_RX_RINGBUFSIZE 0x0002004 +#define ACP_I2S_RX_LINKPOSITIONCNTR 0x0002008 +#define ACP_I2S_RX_FIFOADDR 0x000200C +#define ACP_I2S_RX_FIFOSIZE 0x0002010 +#define ACP_I2S_RX_DMA_SIZE 0x0002014 +#define ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x0002018 +#define ACP_I2S_RX_LINEARPOSITIONCNTR_LOW 0x000201C +#define ACP_I2S_RX_INTR_WATERMARK_SIZE 0x0002020 +#define ACP_I2S_TX_RINGBUFADDR 0x0002024 +#define ACP_I2S_TX_RINGBUFSIZE 0x0002028 +#define ACP_I2S_TX_LINKPOSITIONCNTR 0x000202C +#define ACP_I2S_TX_FIFOADDR 0x0002030 +#define ACP_I2S_TX_FIFOSIZE 0x0002034 +#define ACP_I2S_TX_DMA_SIZE 0x0002038 +#define ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x000203C +#define ACP_I2S_TX_LINEARPOSITIONCNTR_LOW 0x0002040 +#define ACP_I2S_TX_INTR_WATERMARK_SIZE 0x0002044 +#define ACP_BT_RX_RINGBUFADDR 0x0002048 +#define ACP_BT_RX_RINGBUFSIZE 0x000204C +#define ACP_BT_RX_LINKPOSITIONCNTR 0x0002050 +#define ACP_BT_RX_FIFOADDR 0x0002054 +#define ACP_BT_RX_FIFOSIZE 0x0002058 +#define ACP_BT_RX_DMA_SIZE 0x000205C +#define ACP_BT_RX_LINEARPOSITIONCNTR_HIGH 0x0002060 +#define ACP_BT_RX_LINEARPOSITIONCNTR_LOW 0x0002064 +#define ACP_BT_RX_INTR_WATERMARK_SIZE 0x0002068 +#define ACP_BT_TX_RINGBUFADDR 0x000206C +#define ACP_BT_TX_RINGBUFSIZE 0x0002070 +#define ACP_BT_TX_LINKPOSITIONCNTR 0x0002074 +#define ACP_BT_TX_FIFOADDR 0x0002078 +#define ACP_BT_TX_FIFOSIZE 0x000207C +#define ACP_BT_TX_DMA_SIZE 0x0002080 +#define ACP_BT_TX_LINEARPOSITIONCNTR_HIGH 0x0002084 +#define ACP_BT_TX_LINEARPOSITIONCNTR_LOW 0x0002088 +#define ACP_BT_TX_INTR_WATERMARK_SIZE 0x000208C +#define ACP_HS_RX_RINGBUFADDR 0x0002090 +#define ACP_HS_RX_RINGBUFSIZE 0x0002094 +#define ACP_HS_RX_LINKPOSITIONCNTR 0x0002098 +#define ACP_HS_RX_FIFOADDR 0x000209C +#define ACP_HS_RX_FIFOSIZE 0x00020A0 +#define ACP_HS_RX_DMA_SIZE 0x00020A4 +#define ACP_HS_RX_LINEARPOSITIONCNTR_HIGH 0x00020A8 +#define ACP_HS_RX_LINEARPOSITIONCNTR_LOW 0x00020AC +#define ACP_HS_RX_INTR_WATERMARK_SIZE 0x00020B0 +#define ACP_HS_TX_RINGBUFADDR 0x00020B4 +#define ACP_HS_TX_RINGBUFSIZE 0x00020B8 +#define ACP_HS_TX_LINKPOSITIONCNTR 0x00020BC +#define ACP_HS_TX_FIFOADDR 0x00020C0 +#define ACP_HS_TX_FIFOSIZE 0x00020C4 +#define ACP_HS_TX_DMA_SIZE 0x00020C8 +#define ACP_HS_TX_LINEARPOSITIONCNTR_HIGH 0x00020CC +#define ACP_HS_TX_LINEARPOSITIONCNTR_LOW 0x00020D0 +#define ACP_HS_TX_INTR_WATERMARK_SIZE 0x00020D4 + +/* Registers from ACP_I2S_TDM block */ +#define ACP_I2STDM_IER 0x0002400 +#define ACP_I2STDM_IRER 0x0002404 +#define ACP_I2STDM_RXFRMT 0x0002408 +#define ACP_I2STDM_ITER 0x000240C +#define ACP_I2STDM_TXFRMT 0x0002410 +#define ACP_I2STDM0_MSTRCLKGEN 0x0002414 +#define ACP_I2STDM1_MSTRCLKGEN 0x0002418 +#define ACP_I2STDM2_MSTRCLKGEN 0x000241C +#define ACP_I2STDM_REFCLKGEN 0x0002420 + +/* Registers from ACP_BT_TDM block */ +#define ACP_BTTDM_IER 0x0002800 +#define ACP_BTTDM_IRER 0x0002804 +#define ACP_BTTDM_RXFRMT 0x0002808 +#define ACP_BTTDM_ITER 0x000280C +#define ACP_BTTDM_TXFRMT 0x0002810 +#define ACP_HSTDM_IER 0x0002814 +#define ACP_HSTDM_IRER 0x0002818 +#define ACP_HSTDM_RXFRMT 0x000281C +#define ACP_HSTDM_ITER 0x0002820 +#define ACP_HSTDM_TXFRMT 0x0002824 + +/* Registers from ACP_WOV block */ +#define ACP_WOV_PDM_ENABLE 0x0002C04 +#define ACP_WOV_PDM_DMA_ENABLE 0x0002C08 +#define ACP_WOV_RX_RINGBUFADDR 0x0002C0C +#define ACP_WOV_RX_RINGBUFSIZE 0x0002C10 +#define ACP_WOV_RX_LINKPOSITIONCNTR 0x0002C14 +#define ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH 0x0002C18 +#define ACP_WOV_RX_LINEARPOSITIONCNTR_LOW 0x0002C1C +#define ACP_WOV_RX_INTR_WATERMARK_SIZE 0x0002C20 +#define ACP_WOV_PDM_FIFO_FLUSH 0x0002C24 +#define ACP_WOV_PDM_NO_OF_CHANNELS 0x0002C28 +#define ACP_WOV_PDM_DECIMATION_FACTOR 0x0002C2C +#define ACP_WOV_PDM_VAD_CTRL 0x0002C30 +#define ACP_WOV_WAKE 0x0002C54 +#define ACP_WOV_BUFFER_STATUS 0x0002C58 +#define ACP_WOV_MISC_CTRL 0x0002C5C +#define ACP_WOV_CLK_CTRL 0x0002C60 +#define ACP_PDM_VAD_DYNAMIC_CLK_GATING_EN 0x0002C64 +#define ACP_WOV_ERROR_STATUS_REGISTER 0x0002C68 +#define ACP_PDM_CLKDIV 0x0002C6C + +/* Registers from ACP_P1_AUDIO_BUFFERS block */ +#define ACP_P1_I2S_RX_RINGBUFADDR 0x0003A00 +#define ACP_P1_I2S_RX_RINGBUFSIZE 0x0003A04 +#define ACP_P1_I2S_RX_LINKPOSITIONCNTR 0x0003A08 +#define ACP_P1_I2S_RX_FIFOADDR 0x0003A0C +#define ACP_P1_I2S_RX_FIFOSIZE 0x0003A10 +#define ACP_P1_I2S_RX_DMA_SIZE 0x0003A14 +#define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_HIGH 0x0003A18 +#define ACP_P1_I2S_RX_LINEARPOSITIONCNTR_LOW 0x0003A1C +#define ACP_P1_I2S_RX_INTR_WATERMARK_SIZE 0x0003A20 +#define ACP_P1_I2S_TX_RINGBUFADDR 0x0003A24 +#define ACP_P1_I2S_TX_RINGBUFSIZE 0x0003A28 +#define ACP_P1_I2S_TX_LINKPOSITIONCNTR 0x0003A2C +#define ACP_P1_I2S_TX_FIFOADDR 0x0003A30 +#define ACP_P1_I2S_TX_FIFOSIZE 0x0003A34 +#define ACP_P1_I2S_TX_DMA_SIZE 0x0003A38 +#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_HIGH 0x0003A3C +#define ACP_P1_I2S_TX_LINEARPOSITIONCNTR_LOW 0x0003A40 +#define ACP_P1_I2S_TX_INTR_WATERMARK_SIZE 0x0003A44 +#define ACP_P1_BT_RX_RINGBUFADDR 0x0003A48 +#define ACP_P1_BT_RX_RINGBUFSIZE 0x0003A4C +#define ACP_P1_BT_RX_LINKPOSITIONCNTR 0x0003A50 +#define ACP_P1_BT_RX_FIFOADDR 0x0003A54 +#define ACP_P1_BT_RX_FIFOSIZE 0x0003A58 +#define ACP_P1_BT_RX_DMA_SIZE 0x0003A5C +#define ACP_P1_BT_RX_LINEARPOSITIONCNTR_HIGH 0x0003A60 +#define ACP_P1_BT_RX_LINEARPOSITIONCNTR_LOW 0x0003A64 +#define ACP_P1_BT_RX_INTR_WATERMARK_SIZE 0x0003A68 +#define ACP_P1_BT_TX_RINGBUFADDR 0x0003A6C +#define ACP_P1_BT_TX_RINGBUFSIZE 0x0003A70 +#define ACP_P1_BT_TX_LINKPOSITIONCNTR 0x0003A74 +#define ACP_P1_BT_TX_FIFOADDR 0x0003A78 +#define ACP_P1_BT_TX_FIFOSIZE 0x0003A7C +#define ACP_P1_BT_TX_DMA_SIZE 0x0003A80 +#define ACP_P1_BT_TX_LINEARPOSITIONCNTR_HIGH 0x0003A84 +#define ACP_P1_BT_TX_LINEARPOSITIONCNTR_LOW 0x0003A88 +#define ACP_P1_BT_TX_INTR_WATERMARK_SIZE 0x0003A8C +#define ACP_P1_HS_RX_RINGBUFADDR 0x0003A90 +#define ACP_P1_HS_RX_RINGBUFSIZE 0x0003A94 +#define ACP_P1_HS_RX_LINKPOSITIONCNTR 0x0003A98 +#define ACP_P1_HS_RX_FIFOADDR 0x0003A9C +#define ACP_P1_HS_RX_FIFOSIZE 0x0003AA0 +#define ACP_P1_HS_RX_DMA_SIZE 0x0003AA4 +#define ACP_P1_HS_RX_LINEARPOSITIONCNTR_HIGH 0x0003AA8 +#define ACP_P1_HS_RX_LINEARPOSITIONCNTR_LOW 0x0003AAC +#define ACP_P1_HS_RX_INTR_WATERMARK_SIZE 0x0003AB0 +#define ACP_P1_HS_TX_RINGBUFADDR 0x0003AB4 +#define ACP_P1_HS_TX_RINGBUFSIZE 0x0003AB8 +#define ACP_P1_HS_TX_LINKPOSITIONCNTR 0x0003ABC +#define ACP_P1_HS_TX_FIFOADDR 0x0003AC0 +#define ACP_P1_HS_TX_FIFOSIZE 0x0003AC4 +#define ACP_P1_HS_TX_DMA_SIZE 0x0003AC8 +#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_HIGH 0x0003ACC +#define ACP_P1_HS_TX_LINEARPOSITIONCNTR_LOW 0x0003AD0 +#define ACP_P1_HS_TX_INTR_WATERMARK_SIZE 0x0003AD4 + +/* Registers from ACP_SCRATCH block */ +#define ACP_SCRATCH_REG_0 0x0010000 +#define ACP_SCRATCH_REG_1 0x0010004 +#define ACP_SCRATCH_REG_2 0x0010008 +#define ACP_SCRATCH_REG_3 0x001000C +#define ACP_SCRATCH_REG_4 0x0010010 +#define ACP_SCRATCH_REG_5 0x0010014 +#define ACP_SCRATCH_REG_6 0x0010018 +#define ACP_SCRATCH_REG_7 0x001001C +#define ACP_SCRATCH_REG_8 0x0010020 +#define ACP_SCRATCH_REG_9 0x0010024 +#define ACP_SCRATCH_REG_10 0x0010028 +#define ACP_SCRATCH_REG_11 0x001002C +#define ACP_SCRATCH_REG_12 0x0010030 +#define ACP_SCRATCH_REG_13 0x0010034 +#define ACP_SCRATCH_REG_14 0x0010038 +#define ACP_SCRATCH_REG_15 0x001003C +#define ACP_SCRATCH_REG_16 0x0010040 +#define ACP_SCRATCH_REG_17 0x0010044 +#define ACP_SCRATCH_REG_18 0x0010048 +#define ACP_SCRATCH_REG_19 0x001004C +#define ACP_SCRATCH_REG_20 0x0010050 +#define ACP_SCRATCH_REG_21 0x0010054 +#define ACP_SCRATCH_REG_22 0x0010058 +#define ACP_SCRATCH_REG_23 0x001005C +#define ACP_SCRATCH_REG_24 0x0010060 +#define ACP_SCRATCH_REG_25 0x0010064 +#define ACP_SCRATCH_REG_26 0x0010068 +#define ACP_SCRATCH_REG_27 0x001006C +#define ACP_SCRATCH_REG_28 0x0010070 +#define ACP_SCRATCH_REG_29 0x0010074 +#define ACP_SCRATCH_REG_30 0x0010078 +#define ACP_SCRATCH_REG_31 0x001007C +#define ACP_SCRATCH_REG_32 0x0010080 +#define ACP_SCRATCH_REG_33 0x0010084 +#define ACP_SCRATCH_REG_34 0x0010088 +#define ACP_SCRATCH_REG_35 0x001008C +#define ACP_SCRATCH_REG_36 0x0010090 +#define ACP_SCRATCH_REG_37 0x0010094 +#define ACP_SCRATCH_REG_38 0x0010098 +#define ACP_SCRATCH_REG_39 0x001009C +#define ACP_SCRATCH_REG_40 0x00100A0 +#define ACP_SCRATCH_REG_41 0x00100A4 +#define ACP_SCRATCH_REG_42 0x00100A8 +#define ACP_SCRATCH_REG_43 0x00100AC +#define ACP_SCRATCH_REG_44 0x00100B0 +#define ACP_SCRATCH_REG_45 0x00100B4 +#define ACP_SCRATCH_REG_46 0x00100B8 +#define ACP_SCRATCH_REG_47 0x00100BC +#define ACP_SCRATCH_REG_48 0x00100C0 +#define ACP_SCRATCH_REG_49 0x00100C4 +#define ACP_SCRATCH_REG_50 0x00100C8 +#define ACP_SCRATCH_REG_51 0x00100CC +#define ACP_SCRATCH_REG_52 0x00100D0 +#define ACP_SCRATCH_REG_53 0x00100D4 +#define ACP_SCRATCH_REG_54 0x00100D8 +#define ACP_SCRATCH_REG_55 0x00100DC +#define ACP_SCRATCH_REG_56 0x00100E0 +#define ACP_SCRATCH_REG_57 0x00100E4 +#define ACP_SCRATCH_REG_58 0x00100E8 +#define ACP_SCRATCH_REG_59 0x00100EC +#define ACP_SCRATCH_REG_60 0x00100F0 +#define ACP_SCRATCH_REG_61 0x00100F4 +#define ACP_SCRATCH_REG_62 0x00100F8 +#define ACP_SCRATCH_REG_63 0x00100FC +#define ACP_SCRATCH_REG_64 0x0010100 +#define ACP_SCRATCH_REG_65 0x0010104 +#define ACP_SCRATCH_REG_66 0x0010108 +#define ACP_SCRATCH_REG_67 0x001010C +#define ACP_SCRATCH_REG_68 0x0010110 +#define ACP_SCRATCH_REG_69 0x0010114 +#define ACP_SCRATCH_REG_70 0x0010118 +#define ACP_SCRATCH_REG_71 0x001011C +#define ACP_SCRATCH_REG_72 0x0010120 +#define ACP_SCRATCH_REG_73 0x0010124 +#define ACP_SCRATCH_REG_74 0x0010128 +#define ACP_SCRATCH_REG_75 0x001012C +#define ACP_SCRATCH_REG_76 0x0010130 +#define ACP_SCRATCH_REG_77 0x0010134 +#define ACP_SCRATCH_REG_78 0x0010138 +#define ACP_SCRATCH_REG_79 0x001013C +#define ACP_SCRATCH_REG_80 0x0010140 +#define ACP_SCRATCH_REG_81 0x0010144 +#define ACP_SCRATCH_REG_82 0x0010148 +#define ACP_SCRATCH_REG_83 0x001014C +#define ACP_SCRATCH_REG_84 0x0010150 +#define ACP_SCRATCH_REG_85 0x0010154 +#define ACP_SCRATCH_REG_86 0x0010158 +#define ACP_SCRATCH_REG_87 0x001015C +#define ACP_SCRATCH_REG_88 0x0010160 +#define ACP_SCRATCH_REG_89 0x0010164 +#define ACP_SCRATCH_REG_90 0x0010168 +#define ACP_SCRATCH_REG_91 0x001016C +#define ACP_SCRATCH_REG_92 0x0010170 +#define ACP_SCRATCH_REG_93 0x0010174 +#define ACP_SCRATCH_REG_94 0x0010178 +#define ACP_SCRATCH_REG_95 0x001017C +#define ACP_SCRATCH_REG_96 0x0010180 +#define ACP_SCRATCH_REG_97 0x0010184 +#define ACP_SCRATCH_REG_98 0x0010188 +#define ACP_SCRATCH_REG_99 0x001018C +#define ACP_SCRATCH_REG_100 0x0010190 +#define ACP_SCRATCH_REG_101 0x0010194 +#define ACP_SCRATCH_REG_102 0x0010198 +#define ACP_SCRATCH_REG_103 0x001019C +#define ACP_SCRATCH_REG_104 0x00101A0 +#define ACP_SCRATCH_REG_105 0x00101A4 +#define ACP_SCRATCH_REG_106 0x00101A8 +#define ACP_SCRATCH_REG_107 0x00101AC +#define ACP_SCRATCH_REG_108 0x00101B0 +#define ACP_SCRATCH_REG_109 0x00101B4 +#define ACP_SCRATCH_REG_110 0x00101B8 +#define ACP_SCRATCH_REG_111 0x00101BC +#define ACP_SCRATCH_REG_112 0x00101C0 +#define ACP_SCRATCH_REG_113 0x00101C4 +#define ACP_SCRATCH_REG_114 0x00101C8 +#define ACP_SCRATCH_REG_115 0x00101CC +#define ACP_SCRATCH_REG_116 0x00101D0 +#define ACP_SCRATCH_REG_117 0x00101D4 +#define ACP_SCRATCH_REG_118 0x00101D8 +#define ACP_SCRATCH_REG_119 0x00101DC +#define ACP_SCRATCH_REG_120 0x00101E0 +#define ACP_SCRATCH_REG_121 0x00101E4 +#define ACP_SCRATCH_REG_122 0x00101E8 +#define ACP_SCRATCH_REG_123 0x00101EC +#define ACP_SCRATCH_REG_124 0x00101F0 +#define ACP_SCRATCH_REG_125 0x00101F4 +#define ACP_SCRATCH_REG_126 0x00101F8 +#define ACP_SCRATCH_REG_127 0x00101FC +#define ACP_SCRATCH_REG_128 0x0010200 +#endif diff --git a/include/sound/ad1816a.h b/include/sound/ad1816a.h new file mode 100644 index 000000000..283477e86 --- /dev/null +++ b/include/sound/ad1816a.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_AD1816A_H +#define __SOUND_AD1816A_H + +/* + ad1816a.h - definitions for ADI SoundPort AD1816A chip. + Copyright (C) 1999-2000 by Massimo Piccioni <dafastidio@libero.it> + +*/ + +#include <sound/control.h> +#include <sound/pcm.h> +#include <sound/timer.h> + +#define AD1816A_REG(r) (chip->port + r) + +#define AD1816A_CHIP_STATUS 0x00 +#define AD1816A_INDIR_ADDR 0x00 +#define AD1816A_INTERRUPT_STATUS 0x01 +#define AD1816A_INDIR_DATA_LOW 0x02 +#define AD1816A_INDIR_DATA_HIGH 0x03 +#define AD1816A_PIO_DEBUG 0x04 +#define AD1816A_PIO_STATUS 0x05 +#define AD1816A_PIO_DATA 0x06 +#define AD1816A_RESERVED_7 0x07 +#define AD1816A_PLAYBACK_CONFIG 0x08 +#define AD1816A_CAPTURE_CONFIG 0x09 +#define AD1816A_RESERVED_10 0x0a +#define AD1816A_RESERVED_11 0x0b +#define AD1816A_JOYSTICK_RAW_DATA 0x0c +#define AD1816A_JOYSTICK_CTRL 0x0d +#define AD1816A_JOY_POS_DATA_LOW 0x0e +#define AD1816A_JOY_POS_DATA_HIGH 0x0f + +#define AD1816A_LOW_BYTE_TMP 0x00 +#define AD1816A_INTERRUPT_ENABLE 0x01 +#define AD1816A_EXTERNAL_CTRL 0x01 +#define AD1816A_PLAYBACK_SAMPLE_RATE 0x02 +#define AD1816A_CAPTURE_SAMPLE_RATE 0x03 +#define AD1816A_VOICE_ATT 0x04 +#define AD1816A_FM_ATT 0x05 +#define AD1816A_I2S_1_ATT 0x06 +#define AD1816A_I2S_0_ATT 0x07 +#define AD1816A_PLAYBACK_BASE_COUNT 0x08 +#define AD1816A_PLAYBACK_CURR_COUNT 0x09 +#define AD1816A_CAPTURE_BASE_COUNT 0x0a +#define AD1816A_CAPTURE_CURR_COUNT 0x0b +#define AD1816A_TIMER_BASE_COUNT 0x0c +#define AD1816A_TIMER_CURR_COUNT 0x0d +#define AD1816A_MASTER_ATT 0x0e +#define AD1816A_CD_GAIN_ATT 0x0f +#define AD1816A_SYNTH_GAIN_ATT 0x10 +#define AD1816A_VID_GAIN_ATT 0x11 +#define AD1816A_LINE_GAIN_ATT 0x12 +#define AD1816A_MIC_GAIN_ATT 0x13 +#define AD1816A_PHONE_IN_GAIN_ATT 0x13 +#define AD1816A_ADC_SOURCE_SEL 0x14 +#define AD1816A_ADC_PGA 0x14 +#define AD1816A_CHIP_CONFIG 0x20 +#define AD1816A_DSP_CONFIG 0x21 +#define AD1816A_FM_SAMPLE_RATE 0x22 +#define AD1816A_I2S_1_SAMPLE_RATE 0x23 +#define AD1816A_I2S_0_SAMPLE_RATE 0x24 +#define AD1816A_RESERVED_37 0x25 +#define AD1816A_PROGRAM_CLOCK_RATE 0x26 +#define AD1816A_3D_PHAT_CTRL 0x27 +#define AD1816A_PHONE_OUT_ATT 0x27 +#define AD1816A_RESERVED_40 0x28 +#define AD1816A_HW_VOL_BUT 0x29 +#define AD1816A_DSP_MAILBOX_0 0x2a +#define AD1816A_DSP_MAILBOX_1 0x2b +#define AD1816A_POWERDOWN_CTRL 0x2c +#define AD1816A_TIMER_CTRL 0x2c +#define AD1816A_VERSION_ID 0x2d +#define AD1816A_RESERVED_46 0x2e + +#define AD1816A_READY 0x80 + +#define AD1816A_PLAYBACK_IRQ_PENDING 0x80 +#define AD1816A_CAPTURE_IRQ_PENDING 0x40 +#define AD1816A_TIMER_IRQ_PENDING 0x20 + +#define AD1816A_PLAYBACK_ENABLE 0x01 +#define AD1816A_PLAYBACK_PIO 0x02 +#define AD1816A_CAPTURE_ENABLE 0x01 +#define AD1816A_CAPTURE_PIO 0x02 + +#define AD1816A_FMT_LINEAR_8 0x00 +#define AD1816A_FMT_ULAW_8 0x08 +#define AD1816A_FMT_LINEAR_16_LIT 0x10 +#define AD1816A_FMT_ALAW_8 0x18 +#define AD1816A_FMT_LINEAR_16_BIG 0x30 +#define AD1816A_FMT_ALL 0x38 +#define AD1816A_FMT_STEREO 0x04 + +#define AD1816A_PLAYBACK_IRQ_ENABLE 0x8000 +#define AD1816A_CAPTURE_IRQ_ENABLE 0x4000 +#define AD1816A_TIMER_IRQ_ENABLE 0x2000 +#define AD1816A_TIMER_ENABLE 0x0080 + +#define AD1816A_SRC_LINE 0x00 +#define AD1816A_SRC_OUT 0x10 +#define AD1816A_SRC_CD 0x20 +#define AD1816A_SRC_SYNTH 0x30 +#define AD1816A_SRC_VIDEO 0x40 +#define AD1816A_SRC_MIC 0x50 +#define AD1816A_SRC_MONO 0x50 +#define AD1816A_SRC_PHONE_IN 0x60 +#define AD1816A_SRC_MASK 0x70 + +#define AD1816A_CAPTURE_NOT_EQUAL 0x1000 +#define AD1816A_WSS_ENABLE 0x8000 + +struct snd_ad1816a { + unsigned long port; + struct resource *res_port; + int irq; + int dma1; + int dma2; + + unsigned short hardware; + unsigned short version; + + spinlock_t lock; + + unsigned short mode; + unsigned int clock_freq; + + struct snd_card *card; + struct snd_pcm *pcm; + + struct snd_pcm_substream *playback_substream; + struct snd_pcm_substream *capture_substream; + unsigned int p_dma_size; + unsigned int c_dma_size; + + struct snd_timer *timer; +#ifdef CONFIG_PM + unsigned short image[48]; +#endif +}; + + +#define AD1816A_HW_AUTO 0 +#define AD1816A_HW_AD1816A 1 +#define AD1816A_HW_AD1815 2 +#define AD1816A_HW_AD18MAX10 3 + +#define AD1816A_MODE_PLAYBACK 0x01 +#define AD1816A_MODE_CAPTURE 0x02 +#define AD1816A_MODE_TIMER 0x04 +#define AD1816A_MODE_OPEN (AD1816A_MODE_PLAYBACK | \ + AD1816A_MODE_CAPTURE | \ + AD1816A_MODE_TIMER) + + +extern int snd_ad1816a_create(struct snd_card *card, unsigned long port, + int irq, int dma1, int dma2, + struct snd_ad1816a *chip); + +extern int snd_ad1816a_pcm(struct snd_ad1816a *chip, int device); +extern int snd_ad1816a_mixer(struct snd_ad1816a *chip); +extern int snd_ad1816a_timer(struct snd_ad1816a *chip, int device); +#ifdef CONFIG_PM +extern void snd_ad1816a_suspend(struct snd_ad1816a *chip); +extern void snd_ad1816a_resume(struct snd_ad1816a *chip); +#endif + +#endif /* __SOUND_AD1816A_H */ diff --git a/include/sound/ad1843.h b/include/sound/ad1843.h new file mode 100644 index 000000000..b236a9d1d --- /dev/null +++ b/include/sound/ad1843.h @@ -0,0 +1,46 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright 2003 Vivien Chappelier <vivien.chappelier@linux-mips.org> + * Copyright 2008 Thomas Bogendoerfer <tsbogend@franken.de> + */ + +#ifndef __SOUND_AD1843_H +#define __SOUND_AD1843_H + +struct snd_ad1843 { + void *chip; + int (*read)(void *chip, int reg); + int (*write)(void *chip, int reg, int val); +}; + +#define AD1843_GAIN_RECLEV 0 +#define AD1843_GAIN_LINE 1 +#define AD1843_GAIN_LINE_2 2 +#define AD1843_GAIN_MIC 3 +#define AD1843_GAIN_PCM_0 4 +#define AD1843_GAIN_PCM_1 5 +#define AD1843_GAIN_SIZE (AD1843_GAIN_PCM_1+1) + +int ad1843_get_gain_max(struct snd_ad1843 *ad1843, int id); +int ad1843_get_gain(struct snd_ad1843 *ad1843, int id); +int ad1843_set_gain(struct snd_ad1843 *ad1843, int id, int newval); +int ad1843_get_recsrc(struct snd_ad1843 *ad1843); +int ad1843_set_recsrc(struct snd_ad1843 *ad1843, int newsrc); +void ad1843_setup_dac(struct snd_ad1843 *ad1843, + unsigned int id, + unsigned int framerate, + snd_pcm_format_t fmt, + unsigned int channels); +void ad1843_shutdown_dac(struct snd_ad1843 *ad1843, + unsigned int id); +void ad1843_setup_adc(struct snd_ad1843 *ad1843, + unsigned int framerate, + snd_pcm_format_t fmt, + unsigned int channels); +void ad1843_shutdown_adc(struct snd_ad1843 *ad1843); +int ad1843_init(struct snd_ad1843 *ad1843); + +#endif /* __SOUND_AD1843_H */ diff --git a/include/sound/adau1373.h b/include/sound/adau1373.h new file mode 100644 index 000000000..4c32ba132 --- /dev/null +++ b/include/sound/adau1373.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Analog Devices ADAU1373 Audio Codec drive + * + * Copyright 2011 Analog Devices Inc. + * Author: Lars-Peter Clausen <lars@metafoo.de> + */ + +#ifndef __SOUND_ADAU1373_H__ +#define __SOUND_ADAU1373_H__ + +enum adau1373_micbias_voltage { + ADAU1373_MICBIAS_2_9V = 0, + ADAU1373_MICBIAS_2_2V = 1, + ADAU1373_MICBIAS_2_6V = 2, + ADAU1373_MICBIAS_1_8V = 3, +}; + +#define ADAU1373_DRC_SIZE 13 + +struct adau1373_platform_data { + bool input_differential[4]; + bool lineout_differential; + bool lineout_ground_sense; + + unsigned int num_drc; + uint8_t drc_setting[3][ADAU1373_DRC_SIZE]; + + enum adau1373_micbias_voltage micbias1; + enum adau1373_micbias_voltage micbias2; +}; + +#endif diff --git a/include/sound/ak4113.h b/include/sound/ak4113.h new file mode 100644 index 000000000..9ac342ba8 --- /dev/null +++ b/include/sound/ak4113.h @@ -0,0 +1,320 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_AK4113_H +#define __SOUND_AK4113_H + +/* + * Routines for Asahi Kasei AK4113 + * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, + * Copyright (c) by Pavel Hofman <pavel.hofman@ivitera.com>, + */ + +/* AK4113 registers */ +/* power down */ +#define AK4113_REG_PWRDN 0x00 +/* format control */ +#define AK4113_REG_FORMAT 0x01 +/* input/output control */ +#define AK4113_REG_IO0 0x02 +/* input/output control */ +#define AK4113_REG_IO1 0x03 +/* interrupt0 mask */ +#define AK4113_REG_INT0_MASK 0x04 +/* interrupt1 mask */ +#define AK4113_REG_INT1_MASK 0x05 +/* DAT mask & DTS select */ +#define AK4113_REG_DATDTS 0x06 +/* receiver status 0 */ +#define AK4113_REG_RCS0 0x07 +/* receiver status 1 */ +#define AK4113_REG_RCS1 0x08 +/* receiver status 2 */ +#define AK4113_REG_RCS2 0x09 +/* RX channel status byte 0 */ +#define AK4113_REG_RXCSB0 0x0a +/* RX channel status byte 1 */ +#define AK4113_REG_RXCSB1 0x0b +/* RX channel status byte 2 */ +#define AK4113_REG_RXCSB2 0x0c +/* RX channel status byte 3 */ +#define AK4113_REG_RXCSB3 0x0d +/* RX channel status byte 4 */ +#define AK4113_REG_RXCSB4 0x0e +/* burst preamble Pc byte 0 */ +#define AK4113_REG_Pc0 0x0f +/* burst preamble Pc byte 1 */ +#define AK4113_REG_Pc1 0x10 +/* burst preamble Pd byte 0 */ +#define AK4113_REG_Pd0 0x11 +/* burst preamble Pd byte 1 */ +#define AK4113_REG_Pd1 0x12 +/* Q-subcode address + control */ +#define AK4113_REG_QSUB_ADDR 0x13 +/* Q-subcode track */ +#define AK4113_REG_QSUB_TRACK 0x14 +/* Q-subcode index */ +#define AK4113_REG_QSUB_INDEX 0x15 +/* Q-subcode minute */ +#define AK4113_REG_QSUB_MINUTE 0x16 +/* Q-subcode second */ +#define AK4113_REG_QSUB_SECOND 0x17 +/* Q-subcode frame */ +#define AK4113_REG_QSUB_FRAME 0x18 +/* Q-subcode zero */ +#define AK4113_REG_QSUB_ZERO 0x19 +/* Q-subcode absolute minute */ +#define AK4113_REG_QSUB_ABSMIN 0x1a +/* Q-subcode absolute second */ +#define AK4113_REG_QSUB_ABSSEC 0x1b +/* Q-subcode absolute frame */ +#define AK4113_REG_QSUB_ABSFRM 0x1c + +/* sizes */ +#define AK4113_REG_RXCSB_SIZE ((AK4113_REG_RXCSB4-AK4113_REG_RXCSB0)+1) +#define AK4113_REG_QSUB_SIZE ((AK4113_REG_QSUB_ABSFRM-AK4113_REG_QSUB_ADDR)\ + +1) + +#define AK4113_WRITABLE_REGS (AK4113_REG_DATDTS + 1) + +/* AK4113_REG_PWRDN bits */ +/* Channel Status Select */ +#define AK4113_CS12 (1<<7) +/* Block Start & C/U Output Mode */ +#define AK4113_BCU (1<<6) +/* Master Clock Operation Select */ +#define AK4113_CM1 (1<<5) +/* Master Clock Operation Select */ +#define AK4113_CM0 (1<<4) +/* Master Clock Frequency Select */ +#define AK4113_OCKS1 (1<<3) +/* Master Clock Frequency Select */ +#define AK4113_OCKS0 (1<<2) +/* 0 = power down, 1 = normal operation */ +#define AK4113_PWN (1<<1) +/* 0 = reset & initialize (except thisregister), 1 = normal operation */ +#define AK4113_RST (1<<0) + +/* AK4113_REQ_FORMAT bits */ +/* V/TX Output select: 0 = Validity Flag Output, 1 = TX */ +#define AK4113_VTX (1<<7) +/* Audio Data Control */ +#define AK4113_DIF2 (1<<6) +/* Audio Data Control */ +#define AK4113_DIF1 (1<<5) +/* Audio Data Control */ +#define AK4113_DIF0 (1<<4) +/* Deemphasis Autodetect Enable (1 = enable) */ +#define AK4113_DEAU (1<<3) +/* 32kHz-48kHz Deemphasis Control */ +#define AK4113_DEM1 (1<<2) +/* 32kHz-48kHz Deemphasis Control */ +#define AK4113_DEM0 (1<<1) +#define AK4113_DEM_OFF (AK4113_DEM0) +#define AK4113_DEM_44KHZ (0) +#define AK4113_DEM_48KHZ (AK4113_DEM1) +#define AK4113_DEM_32KHZ (AK4113_DEM0|AK4113_DEM1) +/* STDO: 16-bit, right justified */ +#define AK4113_DIF_16R (0) +/* STDO: 18-bit, right justified */ +#define AK4113_DIF_18R (AK4113_DIF0) +/* STDO: 20-bit, right justified */ +#define AK4113_DIF_20R (AK4113_DIF1) +/* STDO: 24-bit, right justified */ +#define AK4113_DIF_24R (AK4113_DIF1|AK4113_DIF0) +/* STDO: 24-bit, left justified */ +#define AK4113_DIF_24L (AK4113_DIF2) +/* STDO: I2S */ +#define AK4113_DIF_24I2S (AK4113_DIF2|AK4113_DIF0) +/* STDO: 24-bit, left justified; LRCLK, BICK = Input */ +#define AK4113_DIF_I24L (AK4113_DIF2|AK4113_DIF1) +/* STDO: I2S; LRCLK, BICK = Input */ +#define AK4113_DIF_I24I2S (AK4113_DIF2|AK4113_DIF1|AK4113_DIF0) + +/* AK4113_REG_IO0 */ +/* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */ +#define AK4113_XTL1 (1<<6) +/* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */ +#define AK4113_XTL0 (1<<5) +/* Block Start Signal Output: 0 = U-bit, 1 = C-bit (req. BCU = 1) */ +#define AK4113_UCE (1<<4) +/* TX Output Enable (1 = enable) */ +#define AK4113_TXE (1<<3) +/* Output Through Data Selector for TX pin */ +#define AK4113_OPS2 (1<<2) +/* Output Through Data Selector for TX pin */ +#define AK4113_OPS1 (1<<1) +/* Output Through Data Selector for TX pin */ +#define AK4113_OPS0 (1<<0) +/* 11.2896 MHz ref. Xtal freq. */ +#define AK4113_XTL_11_2896M (0) +/* 12.288 MHz ref. Xtal freq. */ +#define AK4113_XTL_12_288M (AK4113_XTL0) +/* 24.576 MHz ref. Xtal freq. */ +#define AK4113_XTL_24_576M (AK4113_XTL1) + +/* AK4113_REG_IO1 */ +/* Interrupt 0 pin Hold */ +#define AK4113_EFH1 (1<<7) +/* Interrupt 0 pin Hold */ +#define AK4113_EFH0 (1<<6) +#define AK4113_EFH_512LRCLK (0) +#define AK4113_EFH_1024LRCLK (AK4113_EFH0) +#define AK4113_EFH_2048LRCLK (AK4113_EFH1) +#define AK4113_EFH_4096LRCLK (AK4113_EFH1|AK4113_EFH0) +/* PLL Lock Time: 0 = 384/fs, 1 = 1/fs */ +#define AK4113_FAST (1<<5) +/* MCKO2 Output Select: 0 = CMx/OCKSx, 1 = Xtal */ +#define AK4113_XMCK (1<<4) +/* MCKO2 Output Freq. Select: 0 = x1, 1 = x0.5 (req. XMCK = 1) */ +#define AK4113_DIV (1<<3) +/* Input Recovery Data Select */ +#define AK4113_IPS2 (1<<2) +/* Input Recovery Data Select */ +#define AK4113_IPS1 (1<<1) +/* Input Recovery Data Select */ +#define AK4113_IPS0 (1<<0) +#define AK4113_IPS(x) ((x)&7) + +/* AK4113_REG_INT0_MASK && AK4113_REG_INT1_MASK*/ +/* mask enable for QINT bit */ +#define AK4113_MQI (1<<7) +/* mask enable for AUTO bit */ +#define AK4113_MAUT (1<<6) +/* mask enable for CINT bit */ +#define AK4113_MCIT (1<<5) +/* mask enable for UNLOCK bit */ +#define AK4113_MULK (1<<4) +/* mask enable for V bit */ +#define AK4113_V (1<<3) +/* mask enable for STC bit */ +#define AK4113_STC (1<<2) +/* mask enable for AUDN bit */ +#define AK4113_MAN (1<<1) +/* mask enable for PAR bit */ +#define AK4113_MPR (1<<0) + +/* AK4113_REG_DATDTS */ +/* DAT Start ID Counter */ +#define AK4113_DCNT (1<<4) +/* DTS-CD 16-bit Sync Word Detect */ +#define AK4113_DTS16 (1<<3) +/* DTS-CD 14-bit Sync Word Detect */ +#define AK4113_DTS14 (1<<2) +/* mask enable for DAT bit (if 1, no INT1 effect */ +#define AK4113_MDAT1 (1<<1) +/* mask enable for DAT bit (if 1, no INT0 effect */ +#define AK4113_MDAT0 (1<<0) + +/* AK4113_REG_RCS0 */ +/* Q-subcode buffer interrupt, 0 = no change, 1 = changed */ +#define AK4113_QINT (1<<7) +/* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */ +#define AK4113_AUTO (1<<6) +/* channel status buffer interrupt, 0 = no change, 1 = change */ +#define AK4113_CINT (1<<5) +/* PLL lock status, 0 = lock, 1 = unlock */ +#define AK4113_UNLCK (1<<4) +/* Validity bit, 0 = valid, 1 = invalid */ +#define AK4113_V (1<<3) +/* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */ +#define AK4113_STC (1<<2) +/* audio bit output, 0 = audio, 1 = non-audio */ +#define AK4113_AUDION (1<<1) +/* parity error or biphase error status, 0 = no error, 1 = error */ +#define AK4113_PAR (1<<0) + +/* AK4113_REG_RCS1 */ +/* sampling frequency detection */ +#define AK4113_FS3 (1<<7) +#define AK4113_FS2 (1<<6) +#define AK4113_FS1 (1<<5) +#define AK4113_FS0 (1<<4) +/* Pre-emphasis detect, 0 = OFF, 1 = ON */ +#define AK4113_PEM (1<<3) +/* DAT Start ID Detect, 0 = no detect, 1 = detect */ +#define AK4113_DAT (1<<2) +/* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */ +#define AK4113_DTSCD (1<<1) +/* Non-PCM bit stream detection, 0 = no detect, 1 = detect */ +#define AK4113_NPCM (1<<0) +#define AK4113_FS_8000HZ (AK4113_FS3|AK4113_FS0) +#define AK4113_FS_11025HZ (AK4113_FS2|AK4113_FS0) +#define AK4113_FS_16000HZ (AK4113_FS2|AK4113_FS1|AK4113_FS0) +#define AK4113_FS_22050HZ (AK4113_FS2) +#define AK4113_FS_24000HZ (AK4113_FS2|AK4113_FS1) +#define AK4113_FS_32000HZ (AK4113_FS1|AK4113_FS0) +#define AK4113_FS_44100HZ (0) +#define AK4113_FS_48000HZ (AK4113_FS1) +#define AK4113_FS_64000HZ (AK4113_FS3|AK4113_FS1|AK4113_FS0) +#define AK4113_FS_88200HZ (AK4113_FS3) +#define AK4113_FS_96000HZ (AK4113_FS3|AK4113_FS1) +#define AK4113_FS_176400HZ (AK4113_FS3|AK4113_FS2) +#define AK4113_FS_192000HZ (AK4113_FS3|AK4113_FS2|AK4113_FS1) + +/* AK4113_REG_RCS2 */ +/* CRC for Q-subcode, 0 = no error, 1 = error */ +#define AK4113_QCRC (1<<1) +/* CRC for channel status, 0 = no error, 1 = error */ +#define AK4113_CCRC (1<<0) + +/* flags for snd_ak4113_check_rate_and_errors() */ +#define AK4113_CHECK_NO_STAT (1<<0) /* no statistics */ +#define AK4113_CHECK_NO_RATE (1<<1) /* no rate check */ + +#define AK4113_CONTROLS 13 + +typedef void (ak4113_write_t)(void *private_data, unsigned char addr, + unsigned char data); +typedef unsigned char (ak4113_read_t)(void *private_data, unsigned char addr); + +enum { + AK4113_PARITY_ERRORS, + AK4113_V_BIT_ERRORS, + AK4113_QCRC_ERRORS, + AK4113_CCRC_ERRORS, + AK4113_NUM_ERRORS +}; + +struct ak4113 { + struct snd_card *card; + ak4113_write_t *write; + ak4113_read_t *read; + void *private_data; + atomic_t wq_processing; + struct mutex reinit_mutex; + spinlock_t lock; + unsigned char regmap[AK4113_WRITABLE_REGS]; + struct snd_kcontrol *kctls[AK4113_CONTROLS]; + struct snd_pcm_substream *substream; + unsigned long errors[AK4113_NUM_ERRORS]; + unsigned char rcs0; + unsigned char rcs1; + unsigned char rcs2; + struct delayed_work work; + unsigned int check_flags; + void *change_callback_private; + void (*change_callback)(struct ak4113 *ak4113, unsigned char c0, + unsigned char c1); +}; + +int snd_ak4113_create(struct snd_card *card, ak4113_read_t *read, + ak4113_write_t *write, + const unsigned char *pgm, + void *private_data, struct ak4113 **r_ak4113); +void snd_ak4113_reg_write(struct ak4113 *ak4113, unsigned char reg, + unsigned char mask, unsigned char val); +void snd_ak4113_reinit(struct ak4113 *ak4113); +int snd_ak4113_build(struct ak4113 *ak4113, + struct snd_pcm_substream *capture_substream); +int snd_ak4113_external_rate(struct ak4113 *ak4113); +int snd_ak4113_check_rate_and_errors(struct ak4113 *ak4113, unsigned int flags); + +#ifdef CONFIG_PM +void snd_ak4113_suspend(struct ak4113 *chip); +void snd_ak4113_resume(struct ak4113 *chip); +#else +static inline void snd_ak4113_suspend(struct ak4113 *chip) {} +static inline void snd_ak4113_resume(struct ak4113 *chip) {} +#endif + +#endif /* __SOUND_AK4113_H */ + diff --git a/include/sound/ak4114.h b/include/sound/ak4114.h new file mode 100644 index 000000000..c478a806f --- /dev/null +++ b/include/sound/ak4114.h @@ -0,0 +1,202 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_AK4114_H +#define __SOUND_AK4114_H + +/* + * Routines for Asahi Kasei AK4114 + * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, + */ + +/* AK4114 registers */ +#define AK4114_REG_PWRDN 0x00 /* power down */ +#define AK4114_REG_FORMAT 0x01 /* format control */ +#define AK4114_REG_IO0 0x02 /* input/output control */ +#define AK4114_REG_IO1 0x03 /* input/output control */ +#define AK4114_REG_INT0_MASK 0x04 /* interrupt0 mask */ +#define AK4114_REG_INT1_MASK 0x05 /* interrupt1 mask */ +#define AK4114_REG_RCS0 0x06 /* receiver status 0 */ +#define AK4114_REG_RCS1 0x07 /* receiver status 1 */ +#define AK4114_REG_RXCSB0 0x08 /* RX channel status byte 0 */ +#define AK4114_REG_RXCSB1 0x09 /* RX channel status byte 1 */ +#define AK4114_REG_RXCSB2 0x0a /* RX channel status byte 2 */ +#define AK4114_REG_RXCSB3 0x0b /* RX channel status byte 3 */ +#define AK4114_REG_RXCSB4 0x0c /* RX channel status byte 4 */ +#define AK4114_REG_TXCSB0 0x0d /* TX channel status byte 0 */ +#define AK4114_REG_TXCSB1 0x0e /* TX channel status byte 1 */ +#define AK4114_REG_TXCSB2 0x0f /* TX channel status byte 2 */ +#define AK4114_REG_TXCSB3 0x10 /* TX channel status byte 3 */ +#define AK4114_REG_TXCSB4 0x11 /* TX channel status byte 4 */ +#define AK4114_REG_Pc0 0x12 /* burst preamble Pc byte 0 */ +#define AK4114_REG_Pc1 0x13 /* burst preamble Pc byte 1 */ +#define AK4114_REG_Pd0 0x14 /* burst preamble Pd byte 0 */ +#define AK4114_REG_Pd1 0x15 /* burst preamble Pd byte 1 */ +#define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */ +#define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */ +#define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */ +#define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */ +#define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */ +#define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */ +#define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */ +#define AK4114_REG_QSUB_ABSMIN 0x1d /* Q-subcode absolute minute */ +#define AK4114_REG_QSUB_ABSSEC 0x1e /* Q-subcode absolute second */ +#define AK4114_REG_QSUB_ABSFRM 0x1f /* Q-subcode absolute frame */ + +/* sizes */ +#define AK4114_REG_RXCSB_SIZE ((AK4114_REG_RXCSB4-AK4114_REG_RXCSB0)+1) +#define AK4114_REG_TXCSB_SIZE ((AK4114_REG_TXCSB4-AK4114_REG_TXCSB0)+1) +#define AK4114_REG_QSUB_SIZE ((AK4114_REG_QSUB_ABSFRM-AK4114_REG_QSUB_ADDR)+1) + +/* AK4117_REG_PWRDN bits */ +#define AK4114_CS12 (1<<7) /* Channel Status Select */ +#define AK4114_BCU (1<<6) /* Block Start & C/U Output Mode */ +#define AK4114_CM1 (1<<5) /* Master Clock Operation Select */ +#define AK4114_CM0 (1<<4) /* Master Clock Operation Select */ +#define AK4114_OCKS1 (1<<3) /* Master Clock Frequency Select */ +#define AK4114_OCKS0 (1<<2) /* Master Clock Frequency Select */ +#define AK4114_PWN (1<<1) /* 0 = power down, 1 = normal operation */ +#define AK4114_RST (1<<0) /* 0 = reset & initialize (except this register), 1 = normal operation */ + +/* AK4114_REQ_FORMAT bits */ +#define AK4114_MONO (1<<7) /* Double Sampling Frequency Mode: 0 = stereo, 1 = mono */ +#define AK4114_DIF2 (1<<6) /* Audio Data Control */ +#define AK4114_DIF1 (1<<5) /* Audio Data Control */ +#define AK4114_DIF0 (1<<4) /* Audio Data Control */ +#define AK4114_DIF_16R (0) /* STDO: 16-bit, right justified */ +#define AK4114_DIF_18R (AK4114_DIF0) /* STDO: 18-bit, right justified */ +#define AK4114_DIF_20R (AK4114_DIF1) /* STDO: 20-bit, right justified */ +#define AK4114_DIF_24R (AK4114_DIF1|AK4114_DIF0) /* STDO: 24-bit, right justified */ +#define AK4114_DIF_24L (AK4114_DIF2) /* STDO: 24-bit, left justified */ +#define AK4114_DIF_24I2S (AK4114_DIF2|AK4114_DIF0) /* STDO: I2S */ +#define AK4114_DIF_I24L (AK4114_DIF2|AK4114_DIF1) /* STDO: 24-bit, left justified; LRCLK, BICK = Input */ +#define AK4114_DIF_I24I2S (AK4114_DIF2|AK4114_DIF1|AK4114_DIF0) /* STDO: I2S; LRCLK, BICK = Input */ +#define AK4114_DEAU (1<<3) /* Deemphasis Autodetect Enable (1 = enable) */ +#define AK4114_DEM1 (1<<2) /* 32kHz-48kHz Deemphasis Control */ +#define AK4114_DEM0 (1<<1) /* 32kHz-48kHz Deemphasis Control */ +#define AK4114_DEM_44KHZ (0) +#define AK4114_DEM_48KHZ (AK4114_DEM1) +#define AK4114_DEM_32KHZ (AK4114_DEM0|AK4114_DEM1) +#define AK4114_DEM_96KHZ (AK4114_DEM1) /* DFS must be set */ +#define AK4114_DFS (1<<0) /* 96kHz Deemphasis Control */ + +/* AK4114_REG_IO0 */ +#define AK4114_TX1E (1<<7) /* TX1 Output Enable (1 = enable) */ +#define AK4114_OPS12 (1<<6) /* Output Data Selector for TX1 pin */ +#define AK4114_OPS11 (1<<5) /* Output Data Selector for TX1 pin */ +#define AK4114_OPS10 (1<<4) /* Output Data Selector for TX1 pin */ +#define AK4114_TX0E (1<<3) /* TX0 Output Enable (1 = enable) */ +#define AK4114_OPS02 (1<<2) /* Output Data Selector for TX0 pin */ +#define AK4114_OPS01 (1<<1) /* Output Data Selector for TX0 pin */ +#define AK4114_OPS00 (1<<0) /* Output Data Selector for TX0 pin */ + +/* AK4114_REG_IO1 */ +#define AK4114_EFH1 (1<<7) /* Interrupt 0 pin Hold */ +#define AK4114_EFH0 (1<<6) /* Interrupt 0 pin Hold */ +#define AK4114_EFH_512 (0) +#define AK4114_EFH_1024 (AK4114_EFH0) +#define AK4114_EFH_2048 (AK4114_EFH1) +#define AK4114_EFH_4096 (AK4114_EFH1|AK4114_EFH0) +#define AK4114_UDIT (1<<5) /* U-bit Control for DIT (0 = fixed '0', 1 = recovered) */ +#define AK4114_TLR (1<<4) /* Double Sampling Frequency Select for DIT (0 = L channel, 1 = R channel) */ +#define AK4114_DIT (1<<3) /* TX1 out: 0 = Through Data (RX data), 1 = Transmit Data (DAUX data) */ +#define AK4114_IPS2 (1<<2) /* Input Recovery Data Select */ +#define AK4114_IPS1 (1<<1) /* Input Recovery Data Select */ +#define AK4114_IPS0 (1<<0) /* Input Recovery Data Select */ +#define AK4114_IPS(x) ((x)&7) + +/* AK4114_REG_INT0_MASK && AK4114_REG_INT1_MASK*/ +#define AK4117_MQI (1<<7) /* mask enable for QINT bit */ +#define AK4117_MAT (1<<6) /* mask enable for AUTO bit */ +#define AK4117_MCI (1<<5) /* mask enable for CINT bit */ +#define AK4117_MUL (1<<4) /* mask enable for UNLOCK bit */ +#define AK4117_MDTS (1<<3) /* mask enable for DTSCD bit */ +#define AK4117_MPE (1<<2) /* mask enable for PEM bit */ +#define AK4117_MAN (1<<1) /* mask enable for AUDN bit */ +#define AK4117_MPR (1<<0) /* mask enable for PAR bit */ + +/* AK4114_REG_RCS0 */ +#define AK4114_QINT (1<<7) /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */ +#define AK4114_AUTO (1<<6) /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */ +#define AK4114_CINT (1<<5) /* channel status buffer interrupt, 0 = no change, 1 = change */ +#define AK4114_UNLCK (1<<4) /* PLL lock status, 0 = lock, 1 = unlock */ +#define AK4114_DTSCD (1<<3) /* DTS-CD Detect, 0 = No detect, 1 = Detect */ +#define AK4114_PEM (1<<2) /* Pre-emphasis Detect, 0 = OFF, 1 = ON */ +#define AK4114_AUDION (1<<1) /* audio bit output, 0 = audio, 1 = non-audio */ +#define AK4114_PAR (1<<0) /* parity error or biphase error status, 0 = no error, 1 = error */ + +/* AK4114_REG_RCS1 */ +#define AK4114_FS3 (1<<7) /* sampling frequency detection */ +#define AK4114_FS2 (1<<6) +#define AK4114_FS1 (1<<5) +#define AK4114_FS0 (1<<4) +#define AK4114_FS_44100HZ (0) +#define AK4114_FS_48000HZ (AK4114_FS1) +#define AK4114_FS_32000HZ (AK4114_FS1|AK4114_FS0) +#define AK4114_FS_88200HZ (AK4114_FS3) +#define AK4114_FS_96000HZ (AK4114_FS3|AK4114_FS1) +#define AK4114_FS_176400HZ (AK4114_FS3|AK4114_FS2) +#define AK4114_FS_192000HZ (AK4114_FS3|AK4114_FS2|AK4114_FS1) +#define AK4114_V (1<<3) /* Validity of Channel Status, 0 = Valid, 1 = Invalid */ +#define AK4114_QCRC (1<<1) /* CRC for Q-subcode, 0 = no error, 1 = error */ +#define AK4114_CCRC (1<<0) /* CRC for channel status, 0 = no error, 1 = error */ + +/* flags for snd_ak4114_check_rate_and_errors() */ +#define AK4114_CHECK_NO_STAT (1<<0) /* no statistics */ +#define AK4114_CHECK_NO_RATE (1<<1) /* no rate check */ + +#define AK4114_CONTROLS 15 + +typedef void (ak4114_write_t)(void *private_data, unsigned char addr, unsigned char data); +typedef unsigned char (ak4114_read_t)(void *private_data, unsigned char addr); + +enum { + AK4114_PARITY_ERRORS, + AK4114_V_BIT_ERRORS, + AK4114_QCRC_ERRORS, + AK4114_CCRC_ERRORS, + AK4114_NUM_ERRORS +}; + +struct ak4114 { + struct snd_card *card; + ak4114_write_t * write; + ak4114_read_t * read; + void * private_data; + atomic_t wq_processing; + struct mutex reinit_mutex; + spinlock_t lock; + unsigned char regmap[6]; + unsigned char txcsb[5]; + struct snd_kcontrol *kctls[AK4114_CONTROLS]; + struct snd_pcm_substream *playback_substream; + struct snd_pcm_substream *capture_substream; + unsigned long errors[AK4114_NUM_ERRORS]; + unsigned char rcs0; + unsigned char rcs1; + struct delayed_work work; + unsigned int check_flags; + void *change_callback_private; + void (*change_callback)(struct ak4114 *ak4114, unsigned char c0, unsigned char c1); +}; + +int snd_ak4114_create(struct snd_card *card, + ak4114_read_t *read, ak4114_write_t *write, + const unsigned char pgm[6], const unsigned char txcsb[5], + void *private_data, struct ak4114 **r_ak4114); +void snd_ak4114_reg_write(struct ak4114 *ak4114, unsigned char reg, unsigned char mask, unsigned char val); +void snd_ak4114_reinit(struct ak4114 *ak4114); +int snd_ak4114_build(struct ak4114 *ak4114, + struct snd_pcm_substream *playback_substream, + struct snd_pcm_substream *capture_substream); +int snd_ak4114_external_rate(struct ak4114 *ak4114); +int snd_ak4114_check_rate_and_errors(struct ak4114 *ak4114, unsigned int flags); + +#ifdef CONFIG_PM +void snd_ak4114_suspend(struct ak4114 *chip); +void snd_ak4114_resume(struct ak4114 *chip); +#else +static inline void snd_ak4114_suspend(struct ak4114 *chip) {} +static inline void snd_ak4114_resume(struct ak4114 *chip) {} +#endif + +#endif /* __SOUND_AK4114_H */ + diff --git a/include/sound/ak4117.h b/include/sound/ak4117.h new file mode 100644 index 000000000..3f6bf74d9 --- /dev/null +++ b/include/sound/ak4117.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_AK4117_H +#define __SOUND_AK4117_H + +/* + * Routines for Asahi Kasei AK4117 + * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, + */ + +#define AK4117_REG_PWRDN 0x00 /* power down */ +#define AK4117_REG_CLOCK 0x01 /* clock control */ +#define AK4117_REG_IO 0x02 /* input/output control */ +#define AK4117_REG_INT0_MASK 0x03 /* interrupt0 mask */ +#define AK4117_REG_INT1_MASK 0x04 /* interrupt1 mask */ +#define AK4117_REG_RCS0 0x05 /* receiver status 0 */ +#define AK4117_REG_RCS1 0x06 /* receiver status 1 */ +#define AK4117_REG_RCS2 0x07 /* receiver status 2 */ +#define AK4117_REG_RXCSB0 0x08 /* RX channel status byte 0 */ +#define AK4117_REG_RXCSB1 0x09 /* RX channel status byte 1 */ +#define AK4117_REG_RXCSB2 0x0a /* RX channel status byte 2 */ +#define AK4117_REG_RXCSB3 0x0b /* RX channel status byte 3 */ +#define AK4117_REG_RXCSB4 0x0c /* RX channel status byte 4 */ +#define AK4117_REG_Pc0 0x0d /* burst preamble Pc byte 0 */ +#define AK4117_REG_Pc1 0x0e /* burst preamble Pc byte 1 */ +#define AK4117_REG_Pd0 0x0f /* burst preamble Pd byte 0 */ +#define AK4117_REG_Pd1 0x10 /* burst preamble Pd byte 1 */ +#define AK4117_REG_QSUB_ADDR 0x11 /* Q-subcode address + control */ +#define AK4117_REG_QSUB_TRACK 0x12 /* Q-subcode track */ +#define AK4117_REG_QSUB_INDEX 0x13 /* Q-subcode index */ +#define AK4117_REG_QSUB_MINUTE 0x14 /* Q-subcode minute */ +#define AK4117_REG_QSUB_SECOND 0x15 /* Q-subcode second */ +#define AK4117_REG_QSUB_FRAME 0x16 /* Q-subcode frame */ +#define AK4117_REG_QSUB_ZERO 0x17 /* Q-subcode zero */ +#define AK4117_REG_QSUB_ABSMIN 0x18 /* Q-subcode absolute minute */ +#define AK4117_REG_QSUB_ABSSEC 0x19 /* Q-subcode absolute second */ +#define AK4117_REG_QSUB_ABSFRM 0x1a /* Q-subcode absolute frame */ + +/* sizes */ +#define AK4117_REG_RXCSB_SIZE ((AK4117_REG_RXCSB4-AK4117_REG_RXCSB0)+1) +#define AK4117_REG_QSUB_SIZE ((AK4117_REG_QSUB_ABSFRM-AK4117_REG_QSUB_ADDR)+1) + +/* AK4117_REG_PWRDN bits */ +#define AK4117_EXCT (1<<4) /* 0 = X'tal mode, 1 = external clock mode */ +#define AK4117_XTL1 (1<<3) /* XTL1=0,XTL0=0 -> 11.2896Mhz; XTL1=0,XTL0=1 -> 12.288Mhz */ +#define AK4117_XTL0 (1<<2) /* XTL1=1,XTL0=0 -> 24.576Mhz; XTL1=1,XTL0=1 -> use channel status */ +#define AK4117_XTL_11_2896M (0) +#define AK4117_XTL_12_288M AK4117_XTL0 +#define AK4117_XTL_24_576M AK4117_XTL1 +#define AK4117_XTL_EXT (AK4117_XTL1|AK4117_XTL0) +#define AK4117_PWN (1<<1) /* 0 = power down, 1 = normal operation */ +#define AK4117_RST (1<<0) /* 0 = reset & initialize (except this register), 1 = normal operation */ + +/* AK4117_REQ_CLOCK bits */ +#define AK4117_LP (1<<7) /* 0 = normal mode, 1 = low power mode (Fs up to 48kHz only) */ +#define AK4117_PKCS1 (1<<6) /* master clock frequency at PLL mode (when LP == 0) */ +#define AK4117_PKCS0 (1<<5) +#define AK4117_PKCS_512fs (0) +#define AK4117_PKCS_256fs AK4117_PKCS0 +#define AK4117_PKCS_128fs AK4117_PKCS1 +#define AK4117_DIV (1<<4) /* 0 = MCKO == Fs, 1 = MCKO == Fs / 2; X'tal mode only */ +#define AK4117_XCKS1 (1<<3) /* master clock frequency at X'tal mode */ +#define AK4117_XCKS0 (1<<2) +#define AK4117_XCKS_128fs (0) +#define AK4117_XCKS_256fs AK4117_XCKS0 +#define AK4117_XCKS_512fs AK4117_XCKS1 +#define AK4117_XCKS_1024fs (AK4117_XCKS1|AK4117_XCKS0) +#define AK4117_CM1 (1<<1) /* MCKO operation mode select */ +#define AK4117_CM0 (1<<0) +#define AK4117_CM_PLL (0) /* use RX input as master clock */ +#define AK4117_CM_XTAL (AK4117_CM0) /* use X'tal as master clock */ +#define AK4117_CM_PLL_XTAL (AK4117_CM1) /* use Rx input but X'tal when PLL loses lock */ +#define AK4117_CM_MONITOR (AK4117_CM0|AK4117_CM1) /* use X'tal as master clock, but use PLL for monitoring */ + +/* AK4117_REG_IO */ +#define AK4117_IPS (1<<7) /* Input Recovery Data Select, 0 = RX0, 1 = RX1 */ +#define AK4117_UOUTE (1<<6) /* U-bit output enable to UOUT, 0 = disable, 1 = enable */ +#define AK4117_CS12 (1<<5) /* channel status select, 0 = channel1, 1 = channel2 */ +#define AK4117_EFH2 (1<<4) /* INT0 pin hold count select */ +#define AK4117_EFH1 (1<<3) +#define AK4117_EFH_512LRCLK (0) +#define AK4117_EFH_1024LRCLK (AK4117_EFH1) +#define AK4117_EFH_2048LRCLK (AK4117_EFH2) +#define AK4117_EFH_4096LRCLK (AK4117_EFH1|AK4117_EFH2) +#define AK4117_DIF2 (1<<2) /* audio data format control */ +#define AK4117_DIF1 (1<<1) +#define AK4117_DIF0 (1<<0) +#define AK4117_DIF_16R (0) /* STDO: 16-bit, right justified */ +#define AK4117_DIF_18R (AK4117_DIF0) /* STDO: 18-bit, right justified */ +#define AK4117_DIF_20R (AK4117_DIF1) /* STDO: 20-bit, right justified */ +#define AK4117_DIF_24R (AK4117_DIF1|AK4117_DIF0) /* STDO: 24-bit, right justified */ +#define AK4117_DIF_24L (AK4117_DIF2) /* STDO: 24-bit, left justified */ +#define AK4117_DIF_24I2S (AK4117_DIF2|AK4117_DIF0) /* STDO: I2S */ + +/* AK4117_REG_INT0_MASK & AK4117_REG_INT1_MASK */ +#define AK4117_MULK (1<<7) /* mask enable for UNLOCK bit */ +#define AK4117_MPAR (1<<6) /* mask enable for PAR bit */ +#define AK4117_MAUTO (1<<5) /* mask enable for AUTO bit */ +#define AK4117_MV (1<<4) /* mask enable for V bit */ +#define AK4117_MAUD (1<<3) /* mask enable for AUDION bit */ +#define AK4117_MSTC (1<<2) /* mask enable for STC bit */ +#define AK4117_MCIT (1<<1) /* mask enable for CINT bit */ +#define AK4117_MQIT (1<<0) /* mask enable for QINT bit */ + +/* AK4117_REG_RCS0 */ +#define AK4117_UNLCK (1<<7) /* PLL lock status, 0 = lock, 1 = unlock */ +#define AK4117_PAR (1<<6) /* parity error or biphase error status, 0 = no error, 1 = error */ +#define AK4117_AUTO (1<<5) /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */ +#define AK4117_V (1<<4) /* Validity bit, 0 = valid, 1 = invalid */ +#define AK4117_AUDION (1<<3) /* audio bit output, 0 = audio, 1 = non-audio */ +#define AK4117_STC (1<<2) /* sampling frequency or Pre-emphasis change, 0 = no detect, 1 = detect */ +#define AK4117_CINT (1<<1) /* channel status buffer interrupt, 0 = no change, 1 = change */ +#define AK4117_QINT (1<<0) /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */ + +/* AK4117_REG_RCS1 */ +#define AK4117_DTSCD (1<<6) /* DTS-CD bit audio stream detect, 0 = no detect, 1 = detect */ +#define AK4117_NPCM (1<<5) /* Non-PCM bit stream detection, 0 = no detect, 1 = detect */ +#define AK4117_PEM (1<<4) /* Pre-emphasis detect, 0 = OFF, 1 = ON */ +#define AK4117_FS3 (1<<3) /* sampling frequency detection */ +#define AK4117_FS2 (1<<2) +#define AK4117_FS1 (1<<1) +#define AK4117_FS0 (1<<0) +#define AK4117_FS_44100HZ (0) +#define AK4117_FS_48000HZ (AK4117_FS1) +#define AK4117_FS_32000HZ (AK4117_FS1|AK4117_FS0) +#define AK4117_FS_88200HZ (AK4117_FS3) +#define AK4117_FS_96000HZ (AK4117_FS3|AK4117_FS1) +#define AK4117_FS_176400HZ (AK4117_FS3|AK4117_FS2) +#define AK4117_FS_192000HZ (AK4117_FS3|AK4117_FS2|AK4117_FS1) + +/* AK4117_REG_RCS2 */ +#define AK4117_CCRC (1<<1) /* CRC for channel status, 0 = no error, 1 = error */ +#define AK4117_QCRC (1<<0) /* CRC for Q-subcode, 0 = no error, 1 = error */ + +/* flags for snd_ak4117_check_rate_and_errors() */ +#define AK4117_CHECK_NO_STAT (1<<0) /* no statistics */ +#define AK4117_CHECK_NO_RATE (1<<1) /* no rate check */ + +#define AK4117_CONTROLS 13 + +typedef void (ak4117_write_t)(void *private_data, unsigned char addr, unsigned char data); +typedef unsigned char (ak4117_read_t)(void *private_data, unsigned char addr); + +enum { + AK4117_PARITY_ERRORS, + AK4117_V_BIT_ERRORS, + AK4117_QCRC_ERRORS, + AK4117_CCRC_ERRORS, + AK4117_NUM_ERRORS +}; + +struct ak4117 { + struct snd_card *card; + ak4117_write_t * write; + ak4117_read_t * read; + void * private_data; + unsigned int init: 1; + spinlock_t lock; + unsigned char regmap[5]; + struct snd_kcontrol *kctls[AK4117_CONTROLS]; + struct snd_pcm_substream *substream; + unsigned long errors[AK4117_NUM_ERRORS]; + unsigned char rcs0; + unsigned char rcs1; + unsigned char rcs2; + struct timer_list timer; /* statistic timer */ + void *change_callback_private; + void (*change_callback)(struct ak4117 *ak4117, unsigned char c0, unsigned char c1); +}; + +int snd_ak4117_create(struct snd_card *card, ak4117_read_t *read, ak4117_write_t *write, + const unsigned char pgm[5], void *private_data, struct ak4117 **r_ak4117); +void snd_ak4117_reg_write(struct ak4117 *ak4117, unsigned char reg, unsigned char mask, unsigned char val); +void snd_ak4117_reinit(struct ak4117 *ak4117); +int snd_ak4117_build(struct ak4117 *ak4117, struct snd_pcm_substream *capture_substream); +int snd_ak4117_external_rate(struct ak4117 *ak4117); +int snd_ak4117_check_rate_and_errors(struct ak4117 *ak4117, unsigned int flags); + +#endif /* __SOUND_AK4117_H */ + diff --git a/include/sound/ak4531_codec.h b/include/sound/ak4531_codec.h new file mode 100644 index 000000000..9a4429970 --- /dev/null +++ b/include/sound/ak4531_codec.h @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_AK4531_CODEC_H +#define __SOUND_AK4531_CODEC_H + +/* + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + * Universal interface for Audio Codec '97 + * + * For more details look to AC '97 component specification revision 2.1 + * by Intel Corporation (http://developer.intel.com). + */ + +#include <sound/info.h> +#include <sound/control.h> + +/* + * ASAHI KASEI - AK4531 codec + * - not really AC'97 codec, but it uses very similar interface as AC'97 + */ + +/* + * AK4531 codec registers + */ + +#define AK4531_LMASTER 0x00 /* master volume left */ +#define AK4531_RMASTER 0x01 /* master volume right */ +#define AK4531_LVOICE 0x02 /* channel volume left */ +#define AK4531_RVOICE 0x03 /* channel volume right */ +#define AK4531_LFM 0x04 /* FM volume left */ +#define AK4531_RFM 0x05 /* FM volume right */ +#define AK4531_LCD 0x06 /* CD volume left */ +#define AK4531_RCD 0x07 /* CD volume right */ +#define AK4531_LLINE 0x08 /* LINE volume left */ +#define AK4531_RLINE 0x09 /* LINE volume right */ +#define AK4531_LAUXA 0x0a /* AUXA volume left */ +#define AK4531_RAUXA 0x0b /* AUXA volume right */ +#define AK4531_MONO1 0x0c /* MONO1 volume left */ +#define AK4531_MONO2 0x0d /* MONO1 volume right */ +#define AK4531_MIC 0x0e /* MIC volume */ +#define AK4531_MONO_OUT 0x0f /* Mono-out volume */ +#define AK4531_OUT_SW1 0x10 /* Output mixer switch 1 */ +#define AK4531_OUT_SW2 0x11 /* Output mixer switch 2 */ +#define AK4531_LIN_SW1 0x12 /* Input left mixer switch 1 */ +#define AK4531_RIN_SW1 0x13 /* Input right mixer switch 1 */ +#define AK4531_LIN_SW2 0x14 /* Input left mixer switch 2 */ +#define AK4531_RIN_SW2 0x15 /* Input right mixer switch 2 */ +#define AK4531_RESET 0x16 /* Reset & power down */ +#define AK4531_CLOCK 0x17 /* Clock select */ +#define AK4531_AD_IN 0x18 /* AD input select */ +#define AK4531_MIC_GAIN 0x19 /* MIC amplified gain */ + +struct snd_ak4531 { + void (*write) (struct snd_ak4531 *ak4531, unsigned short reg, + unsigned short val); + void *private_data; + void (*private_free) (struct snd_ak4531 *ak4531); + /* --- */ + unsigned char regs[0x20]; + struct mutex reg_mutex; +}; + +int snd_ak4531_mixer(struct snd_card *card, struct snd_ak4531 *_ak4531, + struct snd_ak4531 **rak4531); + +#ifdef CONFIG_PM +void snd_ak4531_suspend(struct snd_ak4531 *ak4531); +void snd_ak4531_resume(struct snd_ak4531 *ak4531); +#endif + +#endif /* __SOUND_AK4531_CODEC_H */ diff --git a/include/sound/ak4641.h b/include/sound/ak4641.h new file mode 100644 index 000000000..8b1941bbd --- /dev/null +++ b/include/sound/ak4641.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AK4641 ALSA SoC Codec driver + * + * Copyright 2009 Philipp Zabel + */ + +#ifndef __AK4641_H +#define __AK4641_H + +/** + * struct ak4641_platform_data - platform specific AK4641 configuration + * @gpio_power: GPIO to control external power to AK4641 + * @gpio_npdn: GPIO connected to AK4641 nPDN pin + * + * Both GPIO parameters are optional. + */ +struct ak4641_platform_data { + int gpio_power; + int gpio_npdn; +}; + +#endif /* __AK4641_H */ diff --git a/include/sound/ak4xxx-adda.h b/include/sound/ak4xxx-adda.h new file mode 100644 index 000000000..4f574cefe --- /dev/null +++ b/include/sound/ak4xxx-adda.h @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_AK4XXX_ADDA_H +#define __SOUND_AK4XXX_ADDA_H + +/* + * ALSA driver for AK4524 / AK4528 / AK4529 / AK4355 / AK4381 + * AD and DA converters + * + * Copyright (c) 2000 Jaroslav Kysela <perex@perex.cz> + */ + +#ifndef AK4XXX_MAX_CHIPS +#define AK4XXX_MAX_CHIPS 4 +#endif + +struct snd_akm4xxx; + +struct snd_ak4xxx_ops { + void (*lock)(struct snd_akm4xxx *ak, int chip); + void (*unlock)(struct snd_akm4xxx *ak, int chip); + void (*write)(struct snd_akm4xxx *ak, int chip, unsigned char reg, + unsigned char val); + void (*set_rate_val)(struct snd_akm4xxx *ak, unsigned int rate); +}; + +#define AK4XXX_IMAGE_SIZE (AK4XXX_MAX_CHIPS * 16) /* 64 bytes */ + +/* DAC label and channels */ +struct snd_akm4xxx_dac_channel { + char *name; /* mixer volume name */ + unsigned int num_channels; + char *switch_name; /* mixer switch*/ +}; + +/* ADC labels and channels */ +struct snd_akm4xxx_adc_channel { + char *name; /* capture gain volume label */ + char *switch_name; /* capture switch */ + unsigned int num_channels; + char *selector_name; /* capture source select label */ + const char **input_names; /* capture source names (NULL terminated) */ +}; + +struct snd_akm4xxx { + struct snd_card *card; + unsigned int num_adcs; /* AK4524 or AK4528 ADCs */ + unsigned int num_dacs; /* AK4524 or AK4528 DACs */ + unsigned char images[AK4XXX_IMAGE_SIZE]; /* saved register image */ + unsigned char volumes[AK4XXX_IMAGE_SIZE]; /* saved volume values */ + unsigned long private_value[AK4XXX_MAX_CHIPS]; /* helper for driver */ + void *private_data[AK4XXX_MAX_CHIPS]; /* helper for driver */ + /* template should fill the following fields */ + unsigned int idx_offset; /* control index offset */ + enum { + SND_AK4524, SND_AK4528, SND_AK4529, + SND_AK4355, SND_AK4358, SND_AK4381, + SND_AK5365, SND_AK4620, + } type; + + /* (array) information of combined codecs */ + const struct snd_akm4xxx_dac_channel *dac_info; + const struct snd_akm4xxx_adc_channel *adc_info; + + struct snd_ak4xxx_ops ops; + unsigned int num_chips; + unsigned int total_regs; + const char *name; +}; + +void snd_akm4xxx_write(struct snd_akm4xxx *ak, int chip, unsigned char reg, + unsigned char val); +void snd_akm4xxx_reset(struct snd_akm4xxx *ak, int state); +void snd_akm4xxx_init(struct snd_akm4xxx *ak); +int snd_akm4xxx_build_controls(struct snd_akm4xxx *ak); + +#define snd_akm4xxx_get(ak,chip,reg) \ + (ak)->images[(chip) * 16 + (reg)] +#define snd_akm4xxx_set(ak,chip,reg,val) \ + ((ak)->images[(chip) * 16 + (reg)] = (val)) +#define snd_akm4xxx_get_vol(ak,chip,reg) \ + (ak)->volumes[(chip) * 16 + (reg)] +#define snd_akm4xxx_set_vol(ak,chip,reg,val) \ + ((ak)->volumes[(chip) * 16 + (reg)] = (val)) + +#endif /* __SOUND_AK4XXX_ADDA_H */ diff --git a/include/sound/alc5623.h b/include/sound/alc5623.h new file mode 100644 index 000000000..0ebb0f6fc --- /dev/null +++ b/include/sound/alc5623.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _INCLUDE_SOUND_ALC5623_H +#define _INCLUDE_SOUND_ALC5623_H +struct alc5623_platform_data { + /* configure : */ + /* Lineout/Speaker Amps Vmid ratio control */ + /* enable/disable adc/dac high pass filters */ + unsigned int add_ctrl; + /* configure : */ + /* output to enable when jack is low */ + /* output to enable when jack is high */ + /* jack detect (gpio/nc/jack detect [12] */ + unsigned int jack_det_ctrl; +}; +#endif + diff --git a/include/sound/asequencer.h b/include/sound/asequencer.h new file mode 100644 index 000000000..18d4bc3ee --- /dev/null +++ b/include/sound/asequencer.h @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Main header file for the ALSA sequencer + * Copyright (c) 1998-1999 by Frank van de Pol <fvdpol@coil.demon.nl> + * (c) 1998-1999 by Jaroslav Kysela <perex@perex.cz> + */ +#ifndef __SOUND_ASEQUENCER_H +#define __SOUND_ASEQUENCER_H + +#include <linux/ioctl.h> +#include <sound/asound.h> +#include <uapi/sound/asequencer.h> + +/* helper macro */ +#define snd_seq_event_bounce_ext_data(ev) ((void*)((char *)(ev)->data.ext.ptr + sizeof(struct snd_seq_event_bounce))) + +/* + * type check macros + */ +/* result events: 0-4 */ +#define snd_seq_ev_is_result_type(ev) ((ev)->type < 5) +/* channel specific events: 5-19 */ +#define snd_seq_ev_is_channel_type(ev) ((ev)->type >= 5 && (ev)->type < 20) +/* note events: 5-9 */ +#define snd_seq_ev_is_note_type(ev) ((ev)->type >= 5 && (ev)->type < 10) +/* control events: 10-19 */ +#define snd_seq_ev_is_control_type(ev) ((ev)->type >= 10 && (ev)->type < 20) +/* queue control events: 30-39 */ +#define snd_seq_ev_is_queue_type(ev) ((ev)->type >= 30 && (ev)->type < 40) +/* system status messages */ +#define snd_seq_ev_is_message_type(ev) ((ev)->type >= 60 && (ev)->type < 69) +/* sample messages */ +#define snd_seq_ev_is_sample_type(ev) ((ev)->type >= 70 && (ev)->type < 79) +/* user-defined messages */ +#define snd_seq_ev_is_user_type(ev) ((ev)->type >= 90 && (ev)->type < 99) +/* fixed length events: 0-99 */ +#define snd_seq_ev_is_fixed_type(ev) ((ev)->type < 100) +/* variable length events: 130-139 */ +#define snd_seq_ev_is_variable_type(ev) ((ev)->type >= 130 && (ev)->type < 140) +/* reserved for kernel */ +#define snd_seq_ev_is_reserved(ev) ((ev)->type >= 150) + +/* direct dispatched events */ +#define snd_seq_ev_is_direct(ev) ((ev)->queue == SNDRV_SEQ_QUEUE_DIRECT) + +/* + * macros to check event flags + */ +/* prior events */ +#define snd_seq_ev_is_prior(ev) (((ev)->flags & SNDRV_SEQ_PRIORITY_MASK) == SNDRV_SEQ_PRIORITY_HIGH) + +/* event length type */ +#define snd_seq_ev_length_type(ev) ((ev)->flags & SNDRV_SEQ_EVENT_LENGTH_MASK) +#define snd_seq_ev_is_fixed(ev) (snd_seq_ev_length_type(ev) == SNDRV_SEQ_EVENT_LENGTH_FIXED) +#define snd_seq_ev_is_variable(ev) (snd_seq_ev_length_type(ev) == SNDRV_SEQ_EVENT_LENGTH_VARIABLE) +#define snd_seq_ev_is_varusr(ev) (snd_seq_ev_length_type(ev) == SNDRV_SEQ_EVENT_LENGTH_VARUSR) + +/* time-stamp type */ +#define snd_seq_ev_timestamp_type(ev) ((ev)->flags & SNDRV_SEQ_TIME_STAMP_MASK) +#define snd_seq_ev_is_tick(ev) (snd_seq_ev_timestamp_type(ev) == SNDRV_SEQ_TIME_STAMP_TICK) +#define snd_seq_ev_is_real(ev) (snd_seq_ev_timestamp_type(ev) == SNDRV_SEQ_TIME_STAMP_REAL) + +/* time-mode type */ +#define snd_seq_ev_timemode_type(ev) ((ev)->flags & SNDRV_SEQ_TIME_MODE_MASK) +#define snd_seq_ev_is_abstime(ev) (snd_seq_ev_timemode_type(ev) == SNDRV_SEQ_TIME_MODE_ABS) +#define snd_seq_ev_is_reltime(ev) (snd_seq_ev_timemode_type(ev) == SNDRV_SEQ_TIME_MODE_REL) + +/* queue sync port */ +#define snd_seq_queue_sync_port(q) ((q) + 16) + +#endif /* __SOUND_ASEQUENCER_H */ diff --git a/include/sound/asound.h b/include/sound/asound.h new file mode 100644 index 000000000..3fc5b216c --- /dev/null +++ b/include/sound/asound.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Advanced Linux Sound Architecture - ALSA - Driver + * Copyright (c) 1994-2003 by Jaroslav Kysela <perex@perex.cz>, + * Abramo Bagnara <abramo@alsa-project.org> + */ +#ifndef __SOUND_ASOUND_H +#define __SOUND_ASOUND_H + +#include <linux/ioctl.h> +#include <linux/time.h> +#include <asm/byteorder.h> + +#ifdef __LITTLE_ENDIAN +#define SNDRV_LITTLE_ENDIAN +#else +#ifdef __BIG_ENDIAN +#define SNDRV_BIG_ENDIAN +#else +#error "Unsupported endian..." +#endif +#endif + +#include <uapi/sound/asound.h> +#endif /* __SOUND_ASOUND_H */ diff --git a/include/sound/asoundef.h b/include/sound/asoundef.h new file mode 100644 index 000000000..9fdeac19d --- /dev/null +++ b/include/sound/asoundef.h @@ -0,0 +1,310 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_ASOUNDEF_H +#define __SOUND_ASOUNDEF_H + +/* + * Advanced Linux Sound Architecture - ALSA - Driver + * Copyright (c) 1994-2000 by Jaroslav Kysela <perex@perex.cz> + */ + +/**************************************************************************** + * * + * Digital audio interface * + * * + ****************************************************************************/ + +/* AES/IEC958 channel status bits */ +#define IEC958_AES0_PROFESSIONAL (1<<0) /* 0 = consumer, 1 = professional */ +#define IEC958_AES0_NONAUDIO (1<<1) /* 0 = audio, 1 = non-audio */ +#define IEC958_AES0_PRO_EMPHASIS (7<<2) /* mask - emphasis */ +#define IEC958_AES0_PRO_EMPHASIS_NOTID (0<<2) /* emphasis not indicated */ +#define IEC958_AES0_PRO_EMPHASIS_NONE (1<<2) /* none emphasis */ +#define IEC958_AES0_PRO_EMPHASIS_5015 (3<<2) /* 50/15us emphasis */ +#define IEC958_AES0_PRO_EMPHASIS_CCITT (7<<2) /* CCITT J.17 emphasis */ +#define IEC958_AES0_PRO_FREQ_UNLOCKED (1<<5) /* source sample frequency: 0 = locked, 1 = unlocked */ +#define IEC958_AES0_PRO_FS (3<<6) /* mask - sample frequency */ +#define IEC958_AES0_PRO_FS_NOTID (0<<6) /* fs not indicated */ +#define IEC958_AES0_PRO_FS_44100 (1<<6) /* 44.1kHz */ +#define IEC958_AES0_PRO_FS_48000 (2<<6) /* 48kHz */ +#define IEC958_AES0_PRO_FS_32000 (3<<6) /* 32kHz */ +#define IEC958_AES0_CON_NOT_COPYRIGHT (1<<2) /* 0 = copyright, 1 = not copyright */ +#define IEC958_AES0_CON_EMPHASIS (7<<3) /* mask - emphasis */ +#define IEC958_AES0_CON_EMPHASIS_NONE (0<<3) /* none emphasis */ +#define IEC958_AES0_CON_EMPHASIS_5015 (1<<3) /* 50/15us emphasis */ +#define IEC958_AES0_CON_MODE (3<<6) /* mask - mode */ +#define IEC958_AES1_PRO_MODE (15<<0) /* mask - channel mode */ +#define IEC958_AES1_PRO_MODE_NOTID (0<<0) /* not indicated */ +#define IEC958_AES1_PRO_MODE_STEREOPHONIC (2<<0) /* stereophonic - ch A is left */ +#define IEC958_AES1_PRO_MODE_SINGLE (4<<0) /* single channel */ +#define IEC958_AES1_PRO_MODE_TWO (8<<0) /* two channels */ +#define IEC958_AES1_PRO_MODE_PRIMARY (12<<0) /* primary/secondary */ +#define IEC958_AES1_PRO_MODE_BYTE3 (15<<0) /* vector to byte 3 */ +#define IEC958_AES1_PRO_USERBITS (15<<4) /* mask - user bits */ +#define IEC958_AES1_PRO_USERBITS_NOTID (0<<4) /* not indicated */ +#define IEC958_AES1_PRO_USERBITS_192 (8<<4) /* 192-bit structure */ +#define IEC958_AES1_PRO_USERBITS_UDEF (12<<4) /* user defined application */ +#define IEC958_AES1_CON_CATEGORY 0x7f +#define IEC958_AES1_CON_GENERAL 0x00 +#define IEC958_AES1_CON_LASEROPT_MASK 0x07 +#define IEC958_AES1_CON_LASEROPT_ID 0x01 +#define IEC958_AES1_CON_IEC908_CD (IEC958_AES1_CON_LASEROPT_ID|0x00) +#define IEC958_AES1_CON_NON_IEC908_CD (IEC958_AES1_CON_LASEROPT_ID|0x08) +#define IEC958_AES1_CON_MINI_DISC (IEC958_AES1_CON_LASEROPT_ID|0x48) +#define IEC958_AES1_CON_DVD (IEC958_AES1_CON_LASEROPT_ID|0x18) +#define IEC958_AES1_CON_LASTEROPT_OTHER (IEC958_AES1_CON_LASEROPT_ID|0x78) +#define IEC958_AES1_CON_DIGDIGCONV_MASK 0x07 +#define IEC958_AES1_CON_DIGDIGCONV_ID 0x02 +#define IEC958_AES1_CON_PCM_CODER (IEC958_AES1_CON_DIGDIGCONV_ID|0x00) +#define IEC958_AES1_CON_MIXER (IEC958_AES1_CON_DIGDIGCONV_ID|0x10) +#define IEC958_AES1_CON_RATE_CONVERTER (IEC958_AES1_CON_DIGDIGCONV_ID|0x18) +#define IEC958_AES1_CON_SAMPLER (IEC958_AES1_CON_DIGDIGCONV_ID|0x20) +#define IEC958_AES1_CON_DSP (IEC958_AES1_CON_DIGDIGCONV_ID|0x28) +#define IEC958_AES1_CON_DIGDIGCONV_OTHER (IEC958_AES1_CON_DIGDIGCONV_ID|0x78) +#define IEC958_AES1_CON_MAGNETIC_MASK 0x07 +#define IEC958_AES1_CON_MAGNETIC_ID 0x03 +#define IEC958_AES1_CON_DAT (IEC958_AES1_CON_MAGNETIC_ID|0x00) +#define IEC958_AES1_CON_VCR (IEC958_AES1_CON_MAGNETIC_ID|0x08) +#define IEC958_AES1_CON_DCC (IEC958_AES1_CON_MAGNETIC_ID|0x40) +#define IEC958_AES1_CON_MAGNETIC_DISC (IEC958_AES1_CON_MAGNETIC_ID|0x18) +#define IEC958_AES1_CON_MAGNETIC_OTHER (IEC958_AES1_CON_MAGNETIC_ID|0x78) +#define IEC958_AES1_CON_BROADCAST1_MASK 0x07 +#define IEC958_AES1_CON_BROADCAST1_ID 0x04 +#define IEC958_AES1_CON_DAB_JAPAN (IEC958_AES1_CON_BROADCAST1_ID|0x00) +#define IEC958_AES1_CON_DAB_EUROPE (IEC958_AES1_CON_BROADCAST1_ID|0x08) +#define IEC958_AES1_CON_DAB_USA (IEC958_AES1_CON_BROADCAST1_ID|0x60) +#define IEC958_AES1_CON_SOFTWARE (IEC958_AES1_CON_BROADCAST1_ID|0x40) +#define IEC958_AES1_CON_IEC62105 (IEC958_AES1_CON_BROADCAST1_ID|0x20) +#define IEC958_AES1_CON_BROADCAST1_OTHER (IEC958_AES1_CON_BROADCAST1_ID|0x78) +#define IEC958_AES1_CON_BROADCAST2_MASK 0x0f +#define IEC958_AES1_CON_BROADCAST2_ID 0x0e +#define IEC958_AES1_CON_MUSICAL_MASK 0x07 +#define IEC958_AES1_CON_MUSICAL_ID 0x05 +#define IEC958_AES1_CON_SYNTHESIZER (IEC958_AES1_CON_MUSICAL_ID|0x00) +#define IEC958_AES1_CON_MICROPHONE (IEC958_AES1_CON_MUSICAL_ID|0x08) +#define IEC958_AES1_CON_MUSICAL_OTHER (IEC958_AES1_CON_MUSICAL_ID|0x78) +#define IEC958_AES1_CON_ADC_MASK 0x1f +#define IEC958_AES1_CON_ADC_ID 0x06 +#define IEC958_AES1_CON_ADC (IEC958_AES1_CON_ADC_ID|0x00) +#define IEC958_AES1_CON_ADC_OTHER (IEC958_AES1_CON_ADC_ID|0x60) +#define IEC958_AES1_CON_ADC_COPYRIGHT_MASK 0x1f +#define IEC958_AES1_CON_ADC_COPYRIGHT_ID 0x16 +#define IEC958_AES1_CON_ADC_COPYRIGHT (IEC958_AES1_CON_ADC_COPYRIGHT_ID|0x00) +#define IEC958_AES1_CON_ADC_COPYRIGHT_OTHER (IEC958_AES1_CON_ADC_COPYRIGHT_ID|0x60) +#define IEC958_AES1_CON_SOLIDMEM_MASK 0x0f +#define IEC958_AES1_CON_SOLIDMEM_ID 0x08 +#define IEC958_AES1_CON_SOLIDMEM_DIGITAL_RECORDER_PLAYER (IEC958_AES1_CON_SOLIDMEM_ID|0x00) +#define IEC958_AES1_CON_SOLIDMEM_OTHER (IEC958_AES1_CON_SOLIDMEM_ID|0x70) +#define IEC958_AES1_CON_EXPERIMENTAL 0x40 +#define IEC958_AES1_CON_ORIGINAL (1<<7) /* this bits depends on the category code */ +#define IEC958_AES2_PRO_SBITS (7<<0) /* mask - sample bits */ +#define IEC958_AES2_PRO_SBITS_20 (2<<0) /* 20-bit - coordination */ +#define IEC958_AES2_PRO_SBITS_24 (4<<0) /* 24-bit - main audio */ +#define IEC958_AES2_PRO_SBITS_UDEF (6<<0) /* user defined application */ +#define IEC958_AES2_PRO_WORDLEN (7<<3) /* mask - source word length */ +#define IEC958_AES2_PRO_WORDLEN_NOTID (0<<3) /* not indicated */ +#define IEC958_AES2_PRO_WORDLEN_22_18 (2<<3) /* 22-bit or 18-bit */ +#define IEC958_AES2_PRO_WORDLEN_23_19 (4<<3) /* 23-bit or 19-bit */ +#define IEC958_AES2_PRO_WORDLEN_24_20 (5<<3) /* 24-bit or 20-bit */ +#define IEC958_AES2_PRO_WORDLEN_20_16 (6<<3) /* 20-bit or 16-bit */ +#define IEC958_AES2_CON_SOURCE (15<<0) /* mask - source number */ +#define IEC958_AES2_CON_SOURCE_UNSPEC (0<<0) /* unspecified */ +#define IEC958_AES2_CON_CHANNEL (15<<4) /* mask - channel number */ +#define IEC958_AES2_CON_CHANNEL_UNSPEC (0<<4) /* unspecified */ +#define IEC958_AES3_CON_FS (15<<0) /* mask - sample frequency */ +#define IEC958_AES3_CON_FS_44100 (0<<0) /* 44.1kHz */ +#define IEC958_AES3_CON_FS_NOTID (1<<0) /* non indicated */ +#define IEC958_AES3_CON_FS_48000 (2<<0) /* 48kHz */ +#define IEC958_AES3_CON_FS_32000 (3<<0) /* 32kHz */ +#define IEC958_AES3_CON_FS_22050 (4<<0) /* 22.05kHz */ +#define IEC958_AES3_CON_FS_24000 (6<<0) /* 24kHz */ +#define IEC958_AES3_CON_FS_88200 (8<<0) /* 88.2kHz */ +#define IEC958_AES3_CON_FS_768000 (9<<0) /* 768kHz */ +#define IEC958_AES3_CON_FS_96000 (10<<0) /* 96kHz */ +#define IEC958_AES3_CON_FS_176400 (12<<0) /* 176.4kHz */ +#define IEC958_AES3_CON_FS_192000 (14<<0) /* 192kHz */ +#define IEC958_AES3_CON_CLOCK (3<<4) /* mask - clock accuracy */ +#define IEC958_AES3_CON_CLOCK_1000PPM (0<<4) /* 1000 ppm */ +#define IEC958_AES3_CON_CLOCK_50PPM (1<<4) /* 50 ppm */ +#define IEC958_AES3_CON_CLOCK_VARIABLE (2<<4) /* variable pitch */ +#define IEC958_AES4_CON_MAX_WORDLEN_24 (1<<0) /* 0 = 20-bit, 1 = 24-bit */ +#define IEC958_AES4_CON_WORDLEN (7<<1) /* mask - sample word length */ +#define IEC958_AES4_CON_WORDLEN_NOTID (0<<1) /* not indicated */ +#define IEC958_AES4_CON_WORDLEN_20_16 (1<<1) /* 20-bit or 16-bit */ +#define IEC958_AES4_CON_WORDLEN_22_18 (2<<1) /* 22-bit or 18-bit */ +#define IEC958_AES4_CON_WORDLEN_23_19 (4<<1) /* 23-bit or 19-bit */ +#define IEC958_AES4_CON_WORDLEN_24_20 (5<<1) /* 24-bit or 20-bit */ +#define IEC958_AES4_CON_WORDLEN_21_17 (6<<1) /* 21-bit or 17-bit */ +#define IEC958_AES4_CON_ORIGFS (15<<4) /* mask - original sample frequency */ +#define IEC958_AES4_CON_ORIGFS_NOTID (0<<4) /* not indicated */ +#define IEC958_AES4_CON_ORIGFS_192000 (1<<4) /* 192kHz */ +#define IEC958_AES4_CON_ORIGFS_12000 (2<<4) /* 12kHz */ +#define IEC958_AES4_CON_ORIGFS_176400 (3<<4) /* 176.4kHz */ +#define IEC958_AES4_CON_ORIGFS_96000 (5<<4) /* 96kHz */ +#define IEC958_AES4_CON_ORIGFS_8000 (6<<4) /* 8kHz */ +#define IEC958_AES4_CON_ORIGFS_88200 (7<<4) /* 88.2kHz */ +#define IEC958_AES4_CON_ORIGFS_16000 (8<<4) /* 16kHz */ +#define IEC958_AES4_CON_ORIGFS_24000 (9<<4) /* 24kHz */ +#define IEC958_AES4_CON_ORIGFS_11025 (10<<4) /* 11.025kHz */ +#define IEC958_AES4_CON_ORIGFS_22050 (11<<4) /* 22.05kHz */ +#define IEC958_AES4_CON_ORIGFS_32000 (12<<4) /* 32kHz */ +#define IEC958_AES4_CON_ORIGFS_48000 (13<<4) /* 48kHz */ +#define IEC958_AES4_CON_ORIGFS_44100 (15<<4) /* 44.1kHz */ +#define IEC958_AES5_CON_CGMSA (3<<0) /* mask - CGMS-A */ +#define IEC958_AES5_CON_CGMSA_COPYFREELY (0<<0) /* copying is permitted without restriction */ +#define IEC958_AES5_CON_CGMSA_COPYONCE (1<<0) /* one generation of copies may be made */ +#define IEC958_AES5_CON_CGMSA_COPYNOMORE (2<<0) /* condition not be used */ +#define IEC958_AES5_CON_CGMSA_COPYNEVER (3<<0) /* no copying is permitted */ + +/**************************************************************************** + * * + * CEA-861 Audio InfoFrame. Used in HDMI and DisplayPort * + * * + ****************************************************************************/ +#define CEA861_AUDIO_INFOFRAME_DB1CC (7<<0) /* mask - channel count */ +#define CEA861_AUDIO_INFOFRAME_DB1CT (0xf<<4) /* mask - coding type */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_FROM_STREAM (0<<4) /* refer to stream */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_IEC60958 (1<<4) /* IEC-60958 L-PCM */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_AC3 (2<<4) /* AC-3 */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_MPEG1 (3<<4) /* MPEG1 Layers 1 & 2 */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_MP3 (4<<4) /* MPEG1 Layer 3 */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_MPEG2_MULTICH (5<<4) /* MPEG2 Multichannel */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_AAC (6<<4) /* AAC */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_DTS (7<<4) /* DTS */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_ATRAC (8<<4) /* ATRAC */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_ONEBIT (9<<4) /* One Bit Audio */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_DOLBY_DIG_PLUS (10<<4) /* Dolby Digital + */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_DTS_HD (11<<4) /* DTS-HD */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_MAT (12<<4) /* MAT (MLP) */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_DST (13<<4) /* DST */ +#define CEA861_AUDIO_INFOFRAME_DB1CT_WMA_PRO (14<<4) /* WMA Pro */ +#define CEA861_AUDIO_INFOFRAME_DB2SF (7<<2) /* mask - sample frequency */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_FROM_STREAM (0<<2) /* refer to stream */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_32000 (1<<2) /* 32kHz */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_44100 (2<<2) /* 44.1kHz */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_48000 (3<<2) /* 48kHz */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_88200 (4<<2) /* 88.2kHz */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_96000 (5<<2) /* 96kHz */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_176400 (6<<2) /* 176.4kHz */ +#define CEA861_AUDIO_INFOFRAME_DB2SF_192000 (7<<2) /* 192kHz */ +#define CEA861_AUDIO_INFOFRAME_DB2SS (3<<0) /* mask - sample size */ +#define CEA861_AUDIO_INFOFRAME_DB2SS_FROM_STREAM (0<<0) /* refer to stream */ +#define CEA861_AUDIO_INFOFRAME_DB2SS_16BIT (1<<0) /* 16 bits */ +#define CEA861_AUDIO_INFOFRAME_DB2SS_20BIT (2<<0) /* 20 bits */ +#define CEA861_AUDIO_INFOFRAME_DB2SS_24BIT (3<<0) /* 24 bits */ +#define CEA861_AUDIO_INFOFRAME_DB5_DM_INH (1<<7) /* mask - inhibit downmixing */ +#define CEA861_AUDIO_INFOFRAME_DB5_DM_INH_PERMITTED (0<<7) /* stereo downmix permitted */ +#define CEA861_AUDIO_INFOFRAME_DB5_DM_INH_PROHIBITED (1<<7) /* stereo downmis prohibited */ +#define CEA861_AUDIO_INFOFRAME_DB5_LSV (0xf<<3) /* mask - level-shift values */ + +/***************************************************************************** + * * + * MIDI v1.0 interface * + * * + *****************************************************************************/ + +#define MIDI_CHANNELS 16 +#define MIDI_GM_DRUM_CHANNEL (10-1) + +/* + * MIDI commands + */ + +#define MIDI_CMD_NOTE_OFF 0x80 +#define MIDI_CMD_NOTE_ON 0x90 +#define MIDI_CMD_NOTE_PRESSURE 0xa0 +#define MIDI_CMD_CONTROL 0xb0 +#define MIDI_CMD_PGM_CHANGE 0xc0 +#define MIDI_CMD_CHANNEL_PRESSURE 0xd0 +#define MIDI_CMD_BENDER 0xe0 + +#define MIDI_CMD_COMMON_SYSEX 0xf0 +#define MIDI_CMD_COMMON_MTC_QUARTER 0xf1 +#define MIDI_CMD_COMMON_SONG_POS 0xf2 +#define MIDI_CMD_COMMON_SONG_SELECT 0xf3 +#define MIDI_CMD_COMMON_TUNE_REQUEST 0xf6 +#define MIDI_CMD_COMMON_SYSEX_END 0xf7 +#define MIDI_CMD_COMMON_CLOCK 0xf8 +#define MIDI_CMD_COMMON_START 0xfa +#define MIDI_CMD_COMMON_CONTINUE 0xfb +#define MIDI_CMD_COMMON_STOP 0xfc +#define MIDI_CMD_COMMON_SENSING 0xfe +#define MIDI_CMD_COMMON_RESET 0xff + +/* + * MIDI controllers + */ + +#define MIDI_CTL_MSB_BANK 0x00 +#define MIDI_CTL_MSB_MODWHEEL 0x01 +#define MIDI_CTL_MSB_BREATH 0x02 +#define MIDI_CTL_MSB_FOOT 0x04 +#define MIDI_CTL_MSB_PORTAMENTO_TIME 0x05 +#define MIDI_CTL_MSB_DATA_ENTRY 0x06 +#define MIDI_CTL_MSB_MAIN_VOLUME 0x07 +#define MIDI_CTL_MSB_BALANCE 0x08 +#define MIDI_CTL_MSB_PAN 0x0a +#define MIDI_CTL_MSB_EXPRESSION 0x0b +#define MIDI_CTL_MSB_EFFECT1 0x0c +#define MIDI_CTL_MSB_EFFECT2 0x0d +#define MIDI_CTL_MSB_GENERAL_PURPOSE1 0x10 +#define MIDI_CTL_MSB_GENERAL_PURPOSE2 0x11 +#define MIDI_CTL_MSB_GENERAL_PURPOSE3 0x12 +#define MIDI_CTL_MSB_GENERAL_PURPOSE4 0x13 +#define MIDI_CTL_LSB_BANK 0x20 +#define MIDI_CTL_LSB_MODWHEEL 0x21 +#define MIDI_CTL_LSB_BREATH 0x22 +#define MIDI_CTL_LSB_FOOT 0x24 +#define MIDI_CTL_LSB_PORTAMENTO_TIME 0x25 +#define MIDI_CTL_LSB_DATA_ENTRY 0x26 +#define MIDI_CTL_LSB_MAIN_VOLUME 0x27 +#define MIDI_CTL_LSB_BALANCE 0x28 +#define MIDI_CTL_LSB_PAN 0x2a +#define MIDI_CTL_LSB_EXPRESSION 0x2b +#define MIDI_CTL_LSB_EFFECT1 0x2c +#define MIDI_CTL_LSB_EFFECT2 0x2d +#define MIDI_CTL_LSB_GENERAL_PURPOSE1 0x30 +#define MIDI_CTL_LSB_GENERAL_PURPOSE2 0x31 +#define MIDI_CTL_LSB_GENERAL_PURPOSE3 0x32 +#define MIDI_CTL_LSB_GENERAL_PURPOSE4 0x33 +#define MIDI_CTL_SUSTAIN 0x40 +#define MIDI_CTL_PORTAMENTO 0x41 +#define MIDI_CTL_SOSTENUTO 0x42 +#define MIDI_CTL_SOFT_PEDAL 0x43 +#define MIDI_CTL_LEGATO_FOOTSWITCH 0x44 +#define MIDI_CTL_HOLD2 0x45 +#define MIDI_CTL_SC1_SOUND_VARIATION 0x46 +#define MIDI_CTL_SC2_TIMBRE 0x47 +#define MIDI_CTL_SC3_RELEASE_TIME 0x48 +#define MIDI_CTL_SC4_ATTACK_TIME 0x49 +#define MIDI_CTL_SC5_BRIGHTNESS 0x4a +#define MIDI_CTL_SC6 0x4b +#define MIDI_CTL_SC7 0x4c +#define MIDI_CTL_SC8 0x4d +#define MIDI_CTL_SC9 0x4e +#define MIDI_CTL_SC10 0x4f +#define MIDI_CTL_GENERAL_PURPOSE5 0x50 +#define MIDI_CTL_GENERAL_PURPOSE6 0x51 +#define MIDI_CTL_GENERAL_PURPOSE7 0x52 +#define MIDI_CTL_GENERAL_PURPOSE8 0x53 +#define MIDI_CTL_PORTAMENTO_CONTROL 0x54 +#define MIDI_CTL_E1_REVERB_DEPTH 0x5b +#define MIDI_CTL_E2_TREMOLO_DEPTH 0x5c +#define MIDI_CTL_E3_CHORUS_DEPTH 0x5d +#define MIDI_CTL_E4_DETUNE_DEPTH 0x5e +#define MIDI_CTL_E5_PHASER_DEPTH 0x5f +#define MIDI_CTL_DATA_INCREMENT 0x60 +#define MIDI_CTL_DATA_DECREMENT 0x61 +#define MIDI_CTL_NONREG_PARM_NUM_LSB 0x62 +#define MIDI_CTL_NONREG_PARM_NUM_MSB 0x63 +#define MIDI_CTL_REGIST_PARM_NUM_LSB 0x64 +#define MIDI_CTL_REGIST_PARM_NUM_MSB 0x65 +#define MIDI_CTL_ALL_SOUNDS_OFF 0x78 +#define MIDI_CTL_RESET_CONTROLLERS 0x79 +#define MIDI_CTL_LOCAL_CONTROL_SWITCH 0x7a +#define MIDI_CTL_ALL_NOTES_OFF 0x7b +#define MIDI_CTL_OMNI_OFF 0x7c +#define MIDI_CTL_OMNI_ON 0x7d +#define MIDI_CTL_MONO1 0x7e +#define MIDI_CTL_MONO2 0x7f + +#endif /* __SOUND_ASOUNDEF_H */ diff --git a/include/sound/compress_driver.h b/include/sound/compress_driver.h new file mode 100644 index 000000000..d91289c6f --- /dev/null +++ b/include/sound/compress_driver.h @@ -0,0 +1,245 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * compress_driver.h - compress offload driver definations + * + * Copyright (C) 2011 Intel Corporation + * Authors: Vinod Koul <vinod.koul@linux.intel.com> + * Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> + */ + +#ifndef __COMPRESS_DRIVER_H +#define __COMPRESS_DRIVER_H + +#include <linux/types.h> +#include <linux/sched.h> +#include <sound/core.h> +#include <sound/compress_offload.h> +#include <sound/asound.h> +#include <sound/pcm.h> + +struct snd_compr_ops; + +/** + * struct snd_compr_runtime: runtime stream description + * @state: stream state + * @ops: pointer to DSP callbacks + * @buffer: pointer to kernel buffer, valid only when not in mmap mode or + * DSP doesn't implement copy + * @buffer_size: size of the above buffer + * @fragment_size: size of buffer fragment in bytes + * @fragments: number of such fragments + * @total_bytes_available: cumulative number of bytes made available in + * the ring buffer + * @total_bytes_transferred: cumulative bytes transferred by offload DSP + * @sleep: poll sleep + * @private_data: driver private data pointer + * @dma_area: virtual buffer address + * @dma_addr: physical buffer address (not accessible from main CPU) + * @dma_bytes: size of DMA area + * @dma_buffer_p: runtime dma buffer pointer + */ +struct snd_compr_runtime { + snd_pcm_state_t state; + struct snd_compr_ops *ops; + void *buffer; + u64 buffer_size; + u32 fragment_size; + u32 fragments; + u64 total_bytes_available; + u64 total_bytes_transferred; + wait_queue_head_t sleep; + void *private_data; + + unsigned char *dma_area; + dma_addr_t dma_addr; + size_t dma_bytes; + struct snd_dma_buffer *dma_buffer_p; +}; + +/** + * struct snd_compr_stream: compressed stream + * @name: device name + * @ops: pointer to DSP callbacks + * @runtime: pointer to runtime structure + * @device: device pointer + * @error_work: delayed work used when closing the stream due to an error + * @direction: stream direction, playback/recording + * @metadata_set: metadata set flag, true when set + * @next_track: has userspace signal next track transition, true when set + * @partial_drain: undergoing partial_drain for stream, true when set + * @pause_in_draining: paused during draining state, true when set + * @private_data: pointer to DSP private data + * @dma_buffer: allocated buffer if any + */ +struct snd_compr_stream { + const char *name; + struct snd_compr_ops *ops; + struct snd_compr_runtime *runtime; + struct snd_compr *device; + struct delayed_work error_work; + enum snd_compr_direction direction; + bool metadata_set; + bool next_track; + bool partial_drain; + bool pause_in_draining; + void *private_data; + struct snd_dma_buffer dma_buffer; +}; + +/** + * struct snd_compr_ops: compressed path DSP operations + * @open: Open the compressed stream + * This callback is mandatory and shall keep dsp ready to receive the stream + * parameter + * @free: Close the compressed stream, mandatory + * @set_params: Sets the compressed stream parameters, mandatory + * This can be called in during stream creation only to set codec params + * and the stream properties + * @get_params: retrieve the codec parameters, mandatory + * @set_metadata: Set the metadata values for a stream + * @get_metadata: retrieves the requested metadata values from stream + * @trigger: Trigger operations like start, pause, resume, drain, stop. + * This callback is mandatory + * @pointer: Retrieve current h/w pointer information. Mandatory + * @copy: Copy the compressed data to/from userspace, Optional + * Can't be implemented if DSP supports mmap + * @mmap: DSP mmap method to mmap DSP memory + * @ack: Ack for DSP when data is written to audio buffer, Optional + * Not valid if copy is implemented + * @get_caps: Retrieve DSP capabilities, mandatory + * @get_codec_caps: Retrieve capabilities for a specific codec, mandatory + */ +struct snd_compr_ops { + int (*open)(struct snd_compr_stream *stream); + int (*free)(struct snd_compr_stream *stream); + int (*set_params)(struct snd_compr_stream *stream, + struct snd_compr_params *params); + int (*get_params)(struct snd_compr_stream *stream, + struct snd_codec *params); + int (*set_metadata)(struct snd_compr_stream *stream, + struct snd_compr_metadata *metadata); + int (*get_metadata)(struct snd_compr_stream *stream, + struct snd_compr_metadata *metadata); + int (*trigger)(struct snd_compr_stream *stream, int cmd); + int (*pointer)(struct snd_compr_stream *stream, + struct snd_compr_tstamp *tstamp); + int (*copy)(struct snd_compr_stream *stream, char __user *buf, + size_t count); + int (*mmap)(struct snd_compr_stream *stream, + struct vm_area_struct *vma); + int (*ack)(struct snd_compr_stream *stream, size_t bytes); + int (*get_caps) (struct snd_compr_stream *stream, + struct snd_compr_caps *caps); + int (*get_codec_caps) (struct snd_compr_stream *stream, + struct snd_compr_codec_caps *codec); +}; + +/** + * struct snd_compr: Compressed device + * @name: DSP device name + * @dev: associated device instance + * @ops: pointer to DSP callbacks + * @private_data: pointer to DSP pvt data + * @card: sound card pointer + * @direction: Playback or capture direction + * @lock: device lock + * @device: device id + * @use_pause_in_draining: allow pause in draining, true when set + */ +struct snd_compr { + const char *name; + struct device dev; + struct snd_compr_ops *ops; + void *private_data; + struct snd_card *card; + unsigned int direction; + struct mutex lock; + int device; + bool use_pause_in_draining; +#ifdef CONFIG_SND_VERBOSE_PROCFS + /* private: */ + char id[64]; + struct snd_info_entry *proc_root; + struct snd_info_entry *proc_info_entry; +#endif +}; + +/* compress device register APIs */ +int snd_compress_new(struct snd_card *card, int device, + int type, const char *id, struct snd_compr *compr); + +/** + * snd_compr_use_pause_in_draining - Allow pause and resume in draining state + * @substream: compress substream to set + * + * Allow pause and resume in draining state. + * Only HW driver supports this transition can call this API. + */ +static inline void snd_compr_use_pause_in_draining(struct snd_compr_stream *substream) +{ + substream->device->use_pause_in_draining = true; +} + +/* dsp driver callback apis + * For playback: driver should call snd_compress_fragment_elapsed() to let the + * framework know that a fragment has been consumed from the ring buffer + * + * For recording: we want to know when a frame is available or when + * at least one frame is available so snd_compress_frame_elapsed() + * callback should be called when a encodeded frame is available + */ +static inline void snd_compr_fragment_elapsed(struct snd_compr_stream *stream) +{ + wake_up(&stream->runtime->sleep); +} + +static inline void snd_compr_drain_notify(struct snd_compr_stream *stream) +{ + if (snd_BUG_ON(!stream)) + return; + + /* for partial_drain case we are back to running state on success */ + if (stream->partial_drain) { + stream->runtime->state = SNDRV_PCM_STATE_RUNNING; + stream->partial_drain = false; /* clear this flag as well */ + } else { + stream->runtime->state = SNDRV_PCM_STATE_SETUP; + } + + wake_up(&stream->runtime->sleep); +} + +/** + * snd_compr_set_runtime_buffer - Set the Compress runtime buffer + * @stream: compress stream to set + * @bufp: the buffer information, NULL to clear + * + * Copy the buffer information to runtime buffer when @bufp is non-NULL. + * Otherwise it clears the current buffer information. + */ +static inline void +snd_compr_set_runtime_buffer(struct snd_compr_stream *stream, + struct snd_dma_buffer *bufp) +{ + struct snd_compr_runtime *runtime = stream->runtime; + + if (bufp) { + runtime->dma_buffer_p = bufp; + runtime->dma_area = bufp->area; + runtime->dma_addr = bufp->addr; + runtime->dma_bytes = bufp->bytes; + } else { + runtime->dma_buffer_p = NULL; + runtime->dma_area = NULL; + runtime->dma_addr = 0; + runtime->dma_bytes = 0; + } +} + +int snd_compr_malloc_pages(struct snd_compr_stream *stream, size_t size); +int snd_compr_free_pages(struct snd_compr_stream *stream); + +int snd_compr_stop_error(struct snd_compr_stream *stream, + snd_pcm_state_t state); + +#endif diff --git a/include/sound/control.h b/include/sound/control.h new file mode 100644 index 000000000..cc3dcc6cf --- /dev/null +++ b/include/sound/control.h @@ -0,0 +1,294 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_CONTROL_H +#define __SOUND_CONTROL_H + +/* + * Header file for control interface + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + */ + +#include <linux/wait.h> +#include <linux/nospec.h> +#include <sound/asound.h> + +#define snd_kcontrol_chip(kcontrol) ((kcontrol)->private_data) + +struct snd_kcontrol; +typedef int (snd_kcontrol_info_t) (struct snd_kcontrol * kcontrol, struct snd_ctl_elem_info * uinfo); +typedef int (snd_kcontrol_get_t) (struct snd_kcontrol * kcontrol, struct snd_ctl_elem_value * ucontrol); +typedef int (snd_kcontrol_put_t) (struct snd_kcontrol * kcontrol, struct snd_ctl_elem_value * ucontrol); +typedef int (snd_kcontrol_tlv_rw_t)(struct snd_kcontrol *kcontrol, + int op_flag, /* SNDRV_CTL_TLV_OP_XXX */ + unsigned int size, + unsigned int __user *tlv); + +/* internal flag for skipping validations */ +#ifdef CONFIG_SND_CTL_DEBUG +#define SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK (1 << 24) +#define snd_ctl_skip_validation(info) \ + ((info)->access & SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK) +#else +#define SNDRV_CTL_ELEM_ACCESS_SKIP_CHECK 0 +#define snd_ctl_skip_validation(info) true +#endif + +/* kernel only - LED bits */ +#define SNDRV_CTL_ELEM_ACCESS_LED_SHIFT 25 +#define SNDRV_CTL_ELEM_ACCESS_LED_MASK (7<<25) /* kernel three bits - LED group */ +#define SNDRV_CTL_ELEM_ACCESS_SPK_LED (1<<25) /* kernel speaker (output) LED flag */ +#define SNDRV_CTL_ELEM_ACCESS_MIC_LED (2<<25) /* kernel microphone (input) LED flag */ + +enum { + SNDRV_CTL_TLV_OP_READ = 0, + SNDRV_CTL_TLV_OP_WRITE = 1, + SNDRV_CTL_TLV_OP_CMD = -1, +}; + +struct snd_kcontrol_new { + snd_ctl_elem_iface_t iface; /* interface identifier */ + unsigned int device; /* device/client number */ + unsigned int subdevice; /* subdevice (substream) number */ + const char *name; /* ASCII name of item */ + unsigned int index; /* index of item */ + unsigned int access; /* access rights */ + unsigned int count; /* count of same elements */ + snd_kcontrol_info_t *info; + snd_kcontrol_get_t *get; + snd_kcontrol_put_t *put; + union { + snd_kcontrol_tlv_rw_t *c; + const unsigned int *p; + } tlv; + unsigned long private_value; +}; + +struct snd_kcontrol_volatile { + struct snd_ctl_file *owner; /* locked */ + unsigned int access; /* access rights */ +}; + +struct snd_kcontrol { + struct list_head list; /* list of controls */ + struct snd_ctl_elem_id id; + unsigned int count; /* count of same elements */ + snd_kcontrol_info_t *info; + snd_kcontrol_get_t *get; + snd_kcontrol_put_t *put; + union { + snd_kcontrol_tlv_rw_t *c; + const unsigned int *p; + } tlv; + unsigned long private_value; + void *private_data; + void (*private_free)(struct snd_kcontrol *kcontrol); + struct snd_kcontrol_volatile vd[]; /* volatile data */ +}; + +#define snd_kcontrol(n) list_entry(n, struct snd_kcontrol, list) + +struct snd_kctl_event { + struct list_head list; /* list of events */ + struct snd_ctl_elem_id id; + unsigned int mask; +}; + +#define snd_kctl_event(n) list_entry(n, struct snd_kctl_event, list) + +struct pid; + +enum { + SND_CTL_SUBDEV_PCM, + SND_CTL_SUBDEV_RAWMIDI, + SND_CTL_SUBDEV_ITEMS, +}; + +struct snd_ctl_file { + struct list_head list; /* list of all control files */ + struct snd_card *card; + struct pid *pid; + int preferred_subdevice[SND_CTL_SUBDEV_ITEMS]; + wait_queue_head_t change_sleep; + spinlock_t read_lock; + struct snd_fasync *fasync; + int subscribed; /* read interface is activated */ + struct list_head events; /* waiting events for read */ +}; + +struct snd_ctl_layer_ops { + struct snd_ctl_layer_ops *next; + const char *module_name; + void (*lregister)(struct snd_card *card); + void (*ldisconnect)(struct snd_card *card); + void (*lnotify)(struct snd_card *card, unsigned int mask, struct snd_kcontrol *kctl, unsigned int ioff); +}; + +#define snd_ctl_file(n) list_entry(n, struct snd_ctl_file, list) + +typedef int (*snd_kctl_ioctl_func_t) (struct snd_card * card, + struct snd_ctl_file * control, + unsigned int cmd, unsigned long arg); + +void snd_ctl_notify(struct snd_card * card, unsigned int mask, struct snd_ctl_elem_id * id); +void snd_ctl_notify_one(struct snd_card * card, unsigned int mask, struct snd_kcontrol * kctl, unsigned int ioff); + +struct snd_kcontrol *snd_ctl_new1(const struct snd_kcontrol_new * kcontrolnew, void * private_data); +void snd_ctl_free_one(struct snd_kcontrol * kcontrol); +int snd_ctl_add(struct snd_card * card, struct snd_kcontrol * kcontrol); +int snd_ctl_remove(struct snd_card * card, struct snd_kcontrol * kcontrol); +int snd_ctl_replace(struct snd_card *card, struct snd_kcontrol *kcontrol, bool add_on_replace); +int snd_ctl_remove_id(struct snd_card * card, struct snd_ctl_elem_id *id); +int snd_ctl_rename_id(struct snd_card * card, struct snd_ctl_elem_id *src_id, struct snd_ctl_elem_id *dst_id); +void snd_ctl_rename(struct snd_card *card, struct snd_kcontrol *kctl, const char *name); +int snd_ctl_activate_id(struct snd_card *card, struct snd_ctl_elem_id *id, int active); +struct snd_kcontrol *snd_ctl_find_numid(struct snd_card * card, unsigned int numid); +struct snd_kcontrol *snd_ctl_find_id(struct snd_card * card, struct snd_ctl_elem_id *id); + +int snd_ctl_create(struct snd_card *card); + +int snd_ctl_register_ioctl(snd_kctl_ioctl_func_t fcn); +int snd_ctl_unregister_ioctl(snd_kctl_ioctl_func_t fcn); +#ifdef CONFIG_COMPAT +int snd_ctl_register_ioctl_compat(snd_kctl_ioctl_func_t fcn); +int snd_ctl_unregister_ioctl_compat(snd_kctl_ioctl_func_t fcn); +#else +#define snd_ctl_register_ioctl_compat(fcn) +#define snd_ctl_unregister_ioctl_compat(fcn) +#endif + +int snd_ctl_request_layer(const char *module_name); +void snd_ctl_register_layer(struct snd_ctl_layer_ops *lops); +void snd_ctl_disconnect_layer(struct snd_ctl_layer_ops *lops); + +int snd_ctl_get_preferred_subdevice(struct snd_card *card, int type); + +static inline unsigned int snd_ctl_get_ioffnum(struct snd_kcontrol *kctl, struct snd_ctl_elem_id *id) +{ + unsigned int ioff = id->numid - kctl->id.numid; + return array_index_nospec(ioff, kctl->count); +} + +static inline unsigned int snd_ctl_get_ioffidx(struct snd_kcontrol *kctl, struct snd_ctl_elem_id *id) +{ + unsigned int ioff = id->index - kctl->id.index; + return array_index_nospec(ioff, kctl->count); +} + +static inline unsigned int snd_ctl_get_ioff(struct snd_kcontrol *kctl, struct snd_ctl_elem_id *id) +{ + if (id->numid) { + return snd_ctl_get_ioffnum(kctl, id); + } else { + return snd_ctl_get_ioffidx(kctl, id); + } +} + +static inline struct snd_ctl_elem_id *snd_ctl_build_ioff(struct snd_ctl_elem_id *dst_id, + struct snd_kcontrol *src_kctl, + unsigned int offset) +{ + *dst_id = src_kctl->id; + dst_id->index += offset; + dst_id->numid += offset; + return dst_id; +} + +/* + * Frequently used control callbacks/helpers + */ +int snd_ctl_boolean_mono_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_ctl_boolean_stereo_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_ctl_enum_info(struct snd_ctl_elem_info *info, unsigned int channels, + unsigned int items, const char *const names[]); + +/* + * virtual master control + */ +struct snd_kcontrol *snd_ctl_make_virtual_master(char *name, + const unsigned int *tlv); +int _snd_ctl_add_follower(struct snd_kcontrol *master, + struct snd_kcontrol *follower, + unsigned int flags); +/* optional flags for follower */ +#define SND_CTL_FOLLOWER_NEED_UPDATE (1 << 0) + +/** + * snd_ctl_add_follower - Add a virtual follower control + * @master: vmaster element + * @follower: follower element to add + * + * Add a virtual follower control to the given master element created via + * snd_ctl_create_virtual_master() beforehand. + * + * All followers must be the same type (returning the same information + * via info callback). The function doesn't check it, so it's your + * responsibility. + * + * Also, some additional limitations: + * at most two channels, + * logarithmic volume control (dB level) thus no linear volume, + * master can only attenuate the volume without gain + * + * Return: Zero if successful or a negative error code. + */ +static inline int +snd_ctl_add_follower(struct snd_kcontrol *master, struct snd_kcontrol *follower) +{ + return _snd_ctl_add_follower(master, follower, 0); +} + +/** + * snd_ctl_add_follower_uncached - Add a virtual follower control + * @master: vmaster element + * @follower: follower element to add + * + * Add a virtual follower control to the given master. + * Unlike snd_ctl_add_follower(), the element added via this function + * is supposed to have volatile values, and get callback is called + * at each time queried from the master. + * + * When the control peeks the hardware values directly and the value + * can be changed by other means than the put callback of the element, + * this function should be used to keep the value always up-to-date. + * + * Return: Zero if successful or a negative error code. + */ +static inline int +snd_ctl_add_follower_uncached(struct snd_kcontrol *master, + struct snd_kcontrol *follower) +{ + return _snd_ctl_add_follower(master, follower, SND_CTL_FOLLOWER_NEED_UPDATE); +} + +int snd_ctl_add_vmaster_hook(struct snd_kcontrol *kctl, + void (*hook)(void *private_data, int), + void *private_data); +void snd_ctl_sync_vmaster(struct snd_kcontrol *kctl, bool hook_only); +#define snd_ctl_sync_vmaster_hook(kctl) snd_ctl_sync_vmaster(kctl, true) +int snd_ctl_apply_vmaster_followers(struct snd_kcontrol *kctl, + int (*func)(struct snd_kcontrol *vfollower, + struct snd_kcontrol *follower, + void *arg), + void *arg); + +/* + * Control LED trigger layer + */ +#define SND_CTL_LAYER_MODULE_LED "snd-ctl-led" + +#if IS_MODULE(CONFIG_SND_CTL_LED) +static inline int snd_ctl_led_request(void) { return snd_ctl_request_layer(SND_CTL_LAYER_MODULE_LED); } +#else +static inline int snd_ctl_led_request(void) { return 0; } +#endif + +/* + * Helper functions for jack-detection controls + */ +struct snd_kcontrol * +snd_kctl_jack_new(const char *name, struct snd_card *card); +void snd_kctl_jack_report(struct snd_card *card, + struct snd_kcontrol *kctl, bool status); + +#endif /* __SOUND_CONTROL_H */ diff --git a/include/sound/core.h b/include/sound/core.h new file mode 100644 index 000000000..4365c35d0 --- /dev/null +++ b/include/sound/core.h @@ -0,0 +1,518 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_CORE_H +#define __SOUND_CORE_H + +/* + * Main header file for the ALSA driver + * Copyright (c) 1994-2001 by Jaroslav Kysela <perex@perex.cz> + */ + +#include <linux/device.h> +#include <linux/sched.h> /* wake_up() */ +#include <linux/mutex.h> /* struct mutex */ +#include <linux/rwsem.h> /* struct rw_semaphore */ +#include <linux/pm.h> /* pm_message_t */ +#include <linux/stringify.h> +#include <linux/printk.h> +#include <linux/xarray.h> + +/* number of supported soundcards */ +#ifdef CONFIG_SND_DYNAMIC_MINORS +#define SNDRV_CARDS CONFIG_SND_MAX_CARDS +#else +#define SNDRV_CARDS 8 /* don't change - minor numbers */ +#endif + +#define CONFIG_SND_MAJOR 116 /* standard configuration */ + +/* forward declarations */ +struct pci_dev; +struct module; +struct completion; + +/* device allocation stuff */ + +/* type of the object used in snd_device_*() + * this also defines the calling order + */ +enum snd_device_type { + SNDRV_DEV_LOWLEVEL, + SNDRV_DEV_INFO, + SNDRV_DEV_BUS, + SNDRV_DEV_CODEC, + SNDRV_DEV_PCM, + SNDRV_DEV_COMPRESS, + SNDRV_DEV_RAWMIDI, + SNDRV_DEV_TIMER, + SNDRV_DEV_SEQUENCER, + SNDRV_DEV_HWDEP, + SNDRV_DEV_JACK, + SNDRV_DEV_CONTROL, /* NOTE: this must be the last one */ +}; + +enum snd_device_state { + SNDRV_DEV_BUILD, + SNDRV_DEV_REGISTERED, + SNDRV_DEV_DISCONNECTED, +}; + +struct snd_device; + +struct snd_device_ops { + int (*dev_free)(struct snd_device *dev); + int (*dev_register)(struct snd_device *dev); + int (*dev_disconnect)(struct snd_device *dev); +}; + +struct snd_device { + struct list_head list; /* list of registered devices */ + struct snd_card *card; /* card which holds this device */ + enum snd_device_state state; /* state of the device */ + enum snd_device_type type; /* device type */ + void *device_data; /* device structure */ + const struct snd_device_ops *ops; /* operations */ +}; + +#define snd_device(n) list_entry(n, struct snd_device, list) + +/* main structure for soundcard */ + +struct snd_card { + int number; /* number of soundcard (index to + snd_cards) */ + + char id[16]; /* id string of this card */ + char driver[16]; /* driver name */ + char shortname[32]; /* short name of this soundcard */ + char longname[80]; /* name of this soundcard */ + char irq_descr[32]; /* Interrupt description */ + char mixername[80]; /* mixer name */ + char components[128]; /* card components delimited with + space */ + struct module *module; /* top-level module */ + + void *private_data; /* private data for soundcard */ + void (*private_free) (struct snd_card *card); /* callback for freeing of + private data */ + struct list_head devices; /* devices */ + + struct device ctl_dev; /* control device */ + unsigned int last_numid; /* last used numeric ID */ + struct rw_semaphore controls_rwsem; /* controls list lock */ + rwlock_t ctl_files_rwlock; /* ctl_files list lock */ + int controls_count; /* count of all controls */ + size_t user_ctl_alloc_size; // current memory allocation by user controls. + struct list_head controls; /* all controls for this card */ + struct list_head ctl_files; /* active control files */ +#ifdef CONFIG_SND_CTL_FAST_LOOKUP + struct xarray ctl_numids; /* hash table for numids */ + struct xarray ctl_hash; /* hash table for ctl id matching */ + bool ctl_hash_collision; /* ctl_hash collision seen? */ +#endif + + struct snd_info_entry *proc_root; /* root for soundcard specific files */ + struct proc_dir_entry *proc_root_link; /* number link to real id */ + + struct list_head files_list; /* all files associated to this card */ + struct snd_shutdown_f_ops *s_f_ops; /* file operations in the shutdown + state */ + spinlock_t files_lock; /* lock the files for this card */ + int shutdown; /* this card is going down */ + struct completion *release_completion; + struct device *dev; /* device assigned to this card */ + struct device card_dev; /* cardX object for sysfs */ + const struct attribute_group *dev_groups[4]; /* assigned sysfs attr */ + bool registered; /* card_dev is registered? */ + bool managed; /* managed via devres */ + bool releasing; /* during card free process */ + int sync_irq; /* assigned irq, used for PCM sync */ + wait_queue_head_t remove_sleep; + + size_t total_pcm_alloc_bytes; /* total amount of allocated buffers */ + struct mutex memory_mutex; /* protection for the above */ +#ifdef CONFIG_SND_DEBUG + struct dentry *debugfs_root; /* debugfs root for card */ +#endif + +#ifdef CONFIG_PM + unsigned int power_state; /* power state */ + atomic_t power_ref; + wait_queue_head_t power_sleep; + wait_queue_head_t power_ref_sleep; +#endif + +#if IS_ENABLED(CONFIG_SND_MIXER_OSS) + struct snd_mixer_oss *mixer_oss; + int mixer_oss_change_count; +#endif +}; + +#define dev_to_snd_card(p) container_of(p, struct snd_card, card_dev) + +#ifdef CONFIG_PM +static inline unsigned int snd_power_get_state(struct snd_card *card) +{ + return READ_ONCE(card->power_state); +} + +static inline void snd_power_change_state(struct snd_card *card, unsigned int state) +{ + WRITE_ONCE(card->power_state, state); + wake_up(&card->power_sleep); +} + +/** + * snd_power_ref - Take the reference count for power control + * @card: sound card object + * + * The power_ref reference of the card is used for managing to block + * the snd_power_sync_ref() operation. This function increments the reference. + * The counterpart snd_power_unref() has to be called appropriately later. + */ +static inline void snd_power_ref(struct snd_card *card) +{ + atomic_inc(&card->power_ref); +} + +/** + * snd_power_unref - Release the reference count for power control + * @card: sound card object + */ +static inline void snd_power_unref(struct snd_card *card) +{ + if (atomic_dec_and_test(&card->power_ref)) + wake_up(&card->power_ref_sleep); +} + +/** + * snd_power_sync_ref - wait until the card power_ref is freed + * @card: sound card object + * + * This function is used to synchronize with the pending power_ref being + * released. + */ +static inline void snd_power_sync_ref(struct snd_card *card) +{ + wait_event(card->power_ref_sleep, !atomic_read(&card->power_ref)); +} + +/* init.c */ +int snd_power_wait(struct snd_card *card); +int snd_power_ref_and_wait(struct snd_card *card); + +#else /* ! CONFIG_PM */ + +static inline int snd_power_wait(struct snd_card *card) { return 0; } +static inline void snd_power_ref(struct snd_card *card) {} +static inline void snd_power_unref(struct snd_card *card) {} +static inline int snd_power_ref_and_wait(struct snd_card *card) { return 0; } +static inline void snd_power_sync_ref(struct snd_card *card) {} +#define snd_power_get_state(card) ({ (void)(card); SNDRV_CTL_POWER_D0; }) +#define snd_power_change_state(card, state) do { (void)(card); } while (0) + +#endif /* CONFIG_PM */ + +struct snd_minor { + int type; /* SNDRV_DEVICE_TYPE_XXX */ + int card; /* card number */ + int device; /* device number */ + const struct file_operations *f_ops; /* file operations */ + void *private_data; /* private data for f_ops->open */ + struct device *dev; /* device for sysfs */ + struct snd_card *card_ptr; /* assigned card instance */ +}; + +/* return a device pointer linked to each sound device as a parent */ +static inline struct device *snd_card_get_device_link(struct snd_card *card) +{ + return card ? &card->card_dev : NULL; +} + +/* sound.c */ + +extern int snd_major; +extern int snd_ecards_limit; +extern struct class *sound_class; +#ifdef CONFIG_SND_DEBUG +extern struct dentry *sound_debugfs_root; +#endif + +void snd_request_card(int card); + +void snd_device_initialize(struct device *dev, struct snd_card *card); + +int snd_register_device(int type, struct snd_card *card, int dev, + const struct file_operations *f_ops, + void *private_data, struct device *device); +int snd_unregister_device(struct device *dev); +void *snd_lookup_minor_data(unsigned int minor, int type); + +#ifdef CONFIG_SND_OSSEMUL +int snd_register_oss_device(int type, struct snd_card *card, int dev, + const struct file_operations *f_ops, void *private_data); +int snd_unregister_oss_device(int type, struct snd_card *card, int dev); +void *snd_lookup_oss_minor_data(unsigned int minor, int type); +#endif + +int snd_minor_info_init(void); + +/* sound_oss.c */ + +#ifdef CONFIG_SND_OSSEMUL +int snd_minor_info_oss_init(void); +#else +static inline int snd_minor_info_oss_init(void) { return 0; } +#endif + +/* memory.c */ + +int copy_to_user_fromio(void __user *dst, const volatile void __iomem *src, size_t count); +int copy_from_user_toio(volatile void __iomem *dst, const void __user *src, size_t count); + +/* init.c */ + +int snd_card_locked(int card); +#if IS_ENABLED(CONFIG_SND_MIXER_OSS) +#define SND_MIXER_OSS_NOTIFY_REGISTER 0 +#define SND_MIXER_OSS_NOTIFY_DISCONNECT 1 +#define SND_MIXER_OSS_NOTIFY_FREE 2 +extern int (*snd_mixer_oss_notify_callback)(struct snd_card *card, int cmd); +#endif + +int snd_card_new(struct device *parent, int idx, const char *xid, + struct module *module, int extra_size, + struct snd_card **card_ret); +int snd_devm_card_new(struct device *parent, int idx, const char *xid, + struct module *module, size_t extra_size, + struct snd_card **card_ret); + +int snd_card_disconnect(struct snd_card *card); +void snd_card_disconnect_sync(struct snd_card *card); +int snd_card_free(struct snd_card *card); +int snd_card_free_when_closed(struct snd_card *card); +int snd_card_free_on_error(struct device *dev, int ret); +void snd_card_set_id(struct snd_card *card, const char *id); +int snd_card_register(struct snd_card *card); +int snd_card_info_init(void); +int snd_card_add_dev_attr(struct snd_card *card, + const struct attribute_group *group); +int snd_component_add(struct snd_card *card, const char *component); +int snd_card_file_add(struct snd_card *card, struct file *file); +int snd_card_file_remove(struct snd_card *card, struct file *file); + +struct snd_card *snd_card_ref(int card); + +/** + * snd_card_unref - Unreference the card object + * @card: the card object to unreference + * + * Call this function for the card object that was obtained via snd_card_ref() + * or snd_lookup_minor_data(). + */ +static inline void snd_card_unref(struct snd_card *card) +{ + put_device(&card->card_dev); +} + +#define snd_card_set_dev(card, devptr) ((card)->dev = (devptr)) + +/* device.c */ + +int snd_device_new(struct snd_card *card, enum snd_device_type type, + void *device_data, const struct snd_device_ops *ops); +int snd_device_register(struct snd_card *card, void *device_data); +int snd_device_register_all(struct snd_card *card); +void snd_device_disconnect(struct snd_card *card, void *device_data); +void snd_device_disconnect_all(struct snd_card *card); +void snd_device_free(struct snd_card *card, void *device_data); +void snd_device_free_all(struct snd_card *card); +int snd_device_get_state(struct snd_card *card, void *device_data); + +/* isadma.c */ + +#ifdef CONFIG_ISA_DMA_API +#define DMA_MODE_NO_ENABLE 0x0100 + +void snd_dma_program(unsigned long dma, unsigned long addr, unsigned int size, unsigned short mode); +void snd_dma_disable(unsigned long dma); +unsigned int snd_dma_pointer(unsigned long dma, unsigned int size); +int snd_devm_request_dma(struct device *dev, int dma, const char *name); +#endif + +/* misc.c */ +struct resource; +void release_and_free_resource(struct resource *res); + +/* --- */ + +/* sound printk debug levels */ +enum { + SND_PR_ALWAYS, + SND_PR_DEBUG, + SND_PR_VERBOSE, +}; + +#if defined(CONFIG_SND_DEBUG) || defined(CONFIG_SND_VERBOSE_PRINTK) +__printf(4, 5) +void __snd_printk(unsigned int level, const char *file, int line, + const char *format, ...); +#else +#define __snd_printk(level, file, line, format, ...) \ + printk(format, ##__VA_ARGS__) +#endif + +/** + * snd_printk - printk wrapper + * @fmt: format string + * + * Works like printk() but prints the file and the line of the caller + * when configured with CONFIG_SND_VERBOSE_PRINTK. + */ +#define snd_printk(fmt, ...) \ + __snd_printk(0, __FILE__, __LINE__, fmt, ##__VA_ARGS__) + +#ifdef CONFIG_SND_DEBUG +/** + * snd_printd - debug printk + * @fmt: format string + * + * Works like snd_printk() for debugging purposes. + * Ignored when CONFIG_SND_DEBUG is not set. + */ +#define snd_printd(fmt, ...) \ + __snd_printk(1, __FILE__, __LINE__, fmt, ##__VA_ARGS__) +#define _snd_printd(level, fmt, ...) \ + __snd_printk(level, __FILE__, __LINE__, fmt, ##__VA_ARGS__) + +/** + * snd_BUG - give a BUG warning message and stack trace + * + * Calls WARN() if CONFIG_SND_DEBUG is set. + * Ignored when CONFIG_SND_DEBUG is not set. + */ +#define snd_BUG() WARN(1, "BUG?\n") + +/** + * snd_printd_ratelimit - Suppress high rates of output when + * CONFIG_SND_DEBUG is enabled. + */ +#define snd_printd_ratelimit() printk_ratelimit() + +/** + * snd_BUG_ON - debugging check macro + * @cond: condition to evaluate + * + * Has the same behavior as WARN_ON when CONFIG_SND_DEBUG is set, + * otherwise just evaluates the conditional and returns the value. + */ +#define snd_BUG_ON(cond) WARN_ON((cond)) + +#else /* !CONFIG_SND_DEBUG */ + +__printf(1, 2) +static inline void snd_printd(const char *format, ...) {} +__printf(2, 3) +static inline void _snd_printd(int level, const char *format, ...) {} + +#define snd_BUG() do { } while (0) + +#define snd_BUG_ON(condition) ({ \ + int __ret_warn_on = !!(condition); \ + unlikely(__ret_warn_on); \ +}) + +static inline bool snd_printd_ratelimit(void) { return false; } + +#endif /* CONFIG_SND_DEBUG */ + +#ifdef CONFIG_SND_DEBUG_VERBOSE +/** + * snd_printdd - debug printk + * @format: format string + * + * Works like snd_printk() for debugging purposes. + * Ignored when CONFIG_SND_DEBUG_VERBOSE is not set. + */ +#define snd_printdd(format, ...) \ + __snd_printk(2, __FILE__, __LINE__, format, ##__VA_ARGS__) +#else +__printf(1, 2) +static inline void snd_printdd(const char *format, ...) {} +#endif + + +#define SNDRV_OSS_VERSION ((3<<16)|(8<<8)|(1<<4)|(0)) /* 3.8.1a */ + +/* for easier backward-porting */ +#if IS_ENABLED(CONFIG_GAMEPORT) +#define gameport_set_dev_parent(gp,xdev) ((gp)->dev.parent = (xdev)) +#define gameport_set_port_data(gp,r) ((gp)->port_data = (r)) +#define gameport_get_port_data(gp) (gp)->port_data +#endif + +/* PCI quirk list helper */ +struct snd_pci_quirk { + unsigned short subvendor; /* PCI subvendor ID */ + unsigned short subdevice; /* PCI subdevice ID */ + unsigned short subdevice_mask; /* bitmask to match */ + int value; /* value */ +#ifdef CONFIG_SND_DEBUG_VERBOSE + const char *name; /* name of the device (optional) */ +#endif +}; + +#define _SND_PCI_QUIRK_ID_MASK(vend, mask, dev) \ + .subvendor = (vend), .subdevice = (dev), .subdevice_mask = (mask) +#define _SND_PCI_QUIRK_ID(vend, dev) \ + _SND_PCI_QUIRK_ID_MASK(vend, 0xffff, dev) +#define SND_PCI_QUIRK_ID(vend,dev) {_SND_PCI_QUIRK_ID(vend, dev)} +#ifdef CONFIG_SND_DEBUG_VERBOSE +#define SND_PCI_QUIRK(vend,dev,xname,val) \ + {_SND_PCI_QUIRK_ID(vend, dev), .value = (val), .name = (xname)} +#define SND_PCI_QUIRK_VENDOR(vend, xname, val) \ + {_SND_PCI_QUIRK_ID_MASK(vend, 0, 0), .value = (val), .name = (xname)} +#define SND_PCI_QUIRK_MASK(vend, mask, dev, xname, val) \ + {_SND_PCI_QUIRK_ID_MASK(vend, mask, dev), \ + .value = (val), .name = (xname)} +#define snd_pci_quirk_name(q) ((q)->name) +#else +#define SND_PCI_QUIRK(vend,dev,xname,val) \ + {_SND_PCI_QUIRK_ID(vend, dev), .value = (val)} +#define SND_PCI_QUIRK_MASK(vend, mask, dev, xname, val) \ + {_SND_PCI_QUIRK_ID_MASK(vend, mask, dev), .value = (val)} +#define SND_PCI_QUIRK_VENDOR(vend, xname, val) \ + {_SND_PCI_QUIRK_ID_MASK(vend, 0, 0), .value = (val)} +#define snd_pci_quirk_name(q) "" +#endif + +#ifdef CONFIG_PCI +const struct snd_pci_quirk * +snd_pci_quirk_lookup(struct pci_dev *pci, const struct snd_pci_quirk *list); + +const struct snd_pci_quirk * +snd_pci_quirk_lookup_id(u16 vendor, u16 device, + const struct snd_pci_quirk *list); +#else +static inline const struct snd_pci_quirk * +snd_pci_quirk_lookup(struct pci_dev *pci, const struct snd_pci_quirk *list) +{ + return NULL; +} + +static inline const struct snd_pci_quirk * +snd_pci_quirk_lookup_id(u16 vendor, u16 device, + const struct snd_pci_quirk *list) +{ + return NULL; +} +#endif + +/* async signal helpers */ +struct snd_fasync; + +int snd_fasync_helper(int fd, struct file *file, int on, + struct snd_fasync **fasyncp); +void snd_kill_fasync(struct snd_fasync *fasync, int signal, int poll); +void snd_fasync_free(struct snd_fasync *fasync); + +#endif /* __SOUND_CORE_H */ diff --git a/include/sound/cs35l33.h b/include/sound/cs35l33.h new file mode 100644 index 000000000..a25084c4f --- /dev/null +++ b/include/sound/cs35l33.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/cs35l33.h -- Platform data for CS35l33 + * + * Copyright (c) 2016 Cirrus Logic Inc. + */ + +#ifndef __CS35L33_H +#define __CS35L33_H + +struct cs35l33_hg { + bool enable_hg_algo; + unsigned int mem_depth; + unsigned int release_rate; + unsigned int hd_rm; + unsigned int ldo_thld; + unsigned int ldo_path_disable; + unsigned int ldo_entry_delay; + bool vp_hg_auto; + unsigned int vp_hg; + unsigned int vp_hg_rate; + unsigned int vp_hg_va; +}; + +struct cs35l33_pdata { + /* Boost Controller Voltage Setting */ + unsigned int boost_ctl; + + /* Boost Controller Peak Current */ + unsigned int boost_ipk; + + /* Amplifier Drive Select */ + unsigned int amp_drv_sel; + + /* soft volume ramp */ + unsigned int ramp_rate; + + /* IMON adc scale */ + unsigned int imon_adc_scale; + + /* H/G algo configuration */ + struct cs35l33_hg hg_config; +}; + +#endif /* __CS35L33_H */ diff --git a/include/sound/cs35l34.h b/include/sound/cs35l34.h new file mode 100644 index 000000000..8b0c4d94d --- /dev/null +++ b/include/sound/cs35l34.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/cs35l34.h -- Platform data for CS35l34 + * + * Copyright (c) 2016 Cirrus Logic Inc. + */ + +#ifndef __CS35L34_H +#define __CS35L34_H + +struct cs35l34_platform_data { + /* Set AIF to half drive strength */ + bool aif_half_drv; + /* Digital Soft Ramp Disable */ + bool digsft_disable; + /* Amplifier Invert */ + bool amp_inv; + /* Peak current (mA) */ + unsigned int boost_peak; + /* Boost inductor value (nH) */ + unsigned int boost_ind; + /* Boost Controller Voltage Setting (mV) */ + unsigned int boost_vtge; + /* Gain Change Zero Cross */ + bool gain_zc_disable; + /* SDIN Left/Right Selection */ + unsigned int i2s_sdinloc; + /* TDM Rising Edge */ + bool tdm_rising_edge; +}; + +#endif /* __CS35L34_H */ diff --git a/include/sound/cs35l35.h b/include/sound/cs35l35.h new file mode 100644 index 000000000..3a770e40e --- /dev/null +++ b/include/sound/cs35l35.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/cs35l35.h -- Platform data for CS35l35 + * + * Copyright (c) 2016 Cirrus Logic Inc. + */ + +#ifndef __CS35L35_H +#define __CS35L35_H + +struct classh_cfg { + /* + * Class H Algorithm Control Variables + * You can either have it done + * automatically or you can adjust + * these variables for tuning + * + * if you do not enable the internal algorithm + * you will get a set of mixer controls for + * Class H tuning + * + * Section 4.3 of the datasheet + */ + bool classh_bst_override; + bool classh_algo_enable; + int classh_bst_max_limit; + int classh_mem_depth; + int classh_release_rate; + int classh_headroom; + int classh_wk_fet_disable; + int classh_wk_fet_delay; + int classh_wk_fet_thld; + int classh_vpch_auto; + int classh_vpch_rate; + int classh_vpch_man; +}; + +struct monitor_cfg { + /* + * Signal Monitor Data + * highly configurable signal monitoring + * data positioning and different types of + * monitoring data. + * + * Section 4.8.2 - 4.8.4 of the datasheet + */ + bool is_present; + bool imon_specs; + bool vmon_specs; + bool vpmon_specs; + bool vbstmon_specs; + bool vpbrstat_specs; + bool zerofill_specs; + u8 imon_dpth; + u8 imon_loc; + u8 imon_frm; + u8 imon_scale; + u8 vmon_dpth; + u8 vmon_loc; + u8 vmon_frm; + u8 vpmon_dpth; + u8 vpmon_loc; + u8 vpmon_frm; + u8 vbstmon_dpth; + u8 vbstmon_loc; + u8 vbstmon_frm; + u8 vpbrstat_dpth; + u8 vpbrstat_loc; + u8 vpbrstat_frm; + u8 zerofill_dpth; + u8 zerofill_loc; + u8 zerofill_frm; +}; + +struct cs35l35_platform_data { + + /* Stereo (2 Device) */ + bool stereo; + /* serial port drive strength */ + int sp_drv_str; + /* serial port drive in unused slots */ + int sp_drv_unused; + /* Boost Power Down with FET */ + bool bst_pdn_fet_on; + /* Boost Voltage : used if ClassH Algo Enabled */ + int bst_vctl; + /* Boost Converter Peak Current CTRL */ + int bst_ipk; + /* Amp Gain Zero Cross */ + bool gain_zc; + /* Audio Input Location */ + int aud_channel; + /* Advisory Input Location */ + int adv_channel; + /* Shared Boost for stereo */ + bool shared_bst; + /* Specifies this amp is using an external boost supply */ + bool ext_bst; + /* Inductor Value */ + int boost_ind; + /* ClassH Algorithm */ + struct classh_cfg classh_algo; + /* Monitor Config */ + struct monitor_cfg mon_cfg; +}; + +#endif /* __CS35L35_H */ diff --git a/include/sound/cs35l36.h b/include/sound/cs35l36.h new file mode 100644 index 000000000..8f8049d39 --- /dev/null +++ b/include/sound/cs35l36.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * linux/sound/cs35l36.h -- Platform data for CS35L36 + * + * Copyright 2018 Cirrus Logic, Inc. + * + * Author: James Schulman <james.schulman@cirrus.com> + * + */ + +#ifndef __CS35L36_H +#define __CS35L36_H + +struct cs35l36_vpbr_cfg { + bool is_present; + bool vpbr_en; + int vpbr_thld; + int vpbr_atk_rate; + int vpbr_atk_vol; + int vpbr_max_attn; + int vpbr_wait; + int vpbr_rel_rate; + int vpbr_mute_en; +}; + +struct cs35l36_platform_data { + bool multi_amp_mode; + bool dcm_mode; + bool amp_pcm_inv; + bool imon_pol_inv; + bool vmon_pol_inv; + int boost_ind; + int bst_vctl; + int bst_vctl_sel; + int bst_ipk; + bool extern_boost; + int temp_warn_thld; + int irq_drv_sel; + int irq_gpio_sel; + struct cs35l36_vpbr_cfg vpbr_config; +}; + +#endif /* __CS35L36_H */ diff --git a/include/sound/cs35l41.h b/include/sound/cs35l41.h new file mode 100644 index 000000000..9ac591826 --- /dev/null +++ b/include/sound/cs35l41.h @@ -0,0 +1,896 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * linux/sound/cs35l41.h -- Platform data for CS35L41 + * + * Copyright (c) 2017-2021 Cirrus Logic Inc. + * + * Author: David Rhodes <david.rhodes@cirrus.com> + */ + +#ifndef __CS35L41_H +#define __CS35L41_H + +#include <linux/regmap.h> +#include <linux/firmware/cirrus/cs_dsp.h> + +#define CS35L41_FIRSTREG 0x00000000 +#define CS35L41_LASTREG 0x03804FE8 +#define CS35L41_DEVID 0x00000000 +#define CS35L41_REVID 0x00000004 +#define CS35L41_FABID 0x00000008 +#define CS35L41_RELID 0x0000000C +#define CS35L41_OTPID 0x00000010 +#define CS35L41_SFT_RESET 0x00000020 +#define CS35L41_TEST_KEY_CTL 0x00000040 +#define CS35L41_USER_KEY_CTL 0x00000044 +#define CS35L41_OTP_MEM0 0x00000400 +#define CS35L41_OTP_MEM31 0x0000047C +#define CS35L41_OTP_CTRL0 0x00000500 +#define CS35L41_OTP_CTRL1 0x00000504 +#define CS35L41_OTP_CTRL3 0x00000508 +#define CS35L41_OTP_CTRL4 0x0000050C +#define CS35L41_OTP_CTRL5 0x00000510 +#define CS35L41_OTP_CTRL6 0x00000514 +#define CS35L41_OTP_CTRL7 0x00000518 +#define CS35L41_OTP_CTRL8 0x0000051C +#define CS35L41_PWR_CTRL1 0x00002014 +#define CS35L41_PWR_CTRL2 0x00002018 +#define CS35L41_PWR_CTRL3 0x0000201C +#define CS35L41_CTRL_OVRRIDE 0x00002020 +#define CS35L41_AMP_OUT_MUTE 0x00002024 +#define CS35L41_PROTECT_REL_ERR_IGN 0x00002034 +#define CS35L41_GPIO_PAD_CONTROL 0x0000242C +#define CS35L41_JTAG_CONTROL 0x00002438 +#define CS35L41_PWRMGT_CTL 0x00002900 +#define CS35L41_WAKESRC_CTL 0x00002904 +#define CS35L41_PWRMGT_STS 0x00002908 +#define CS35L41_PLL_CLK_CTRL 0x00002C04 +#define CS35L41_DSP_CLK_CTRL 0x00002C08 +#define CS35L41_GLOBAL_CLK_CTRL 0x00002C0C +#define CS35L41_DATA_FS_SEL 0x00002C10 +#define CS35L41_TST_FS_MON0 0x00002D10 +#define CS35L41_MDSYNC_EN 0x00003400 +#define CS35L41_MDSYNC_TX_ID 0x00003408 +#define CS35L41_MDSYNC_PWR_CTRL 0x0000340C +#define CS35L41_MDSYNC_DATA_TX 0x00003410 +#define CS35L41_MDSYNC_TX_STATUS 0x00003414 +#define CS35L41_MDSYNC_DATA_RX 0x0000341C +#define CS35L41_MDSYNC_RX_STATUS 0x00003420 +#define CS35L41_MDSYNC_ERR_STATUS 0x00003424 +#define CS35L41_MDSYNC_SYNC_PTE2 0x00003528 +#define CS35L41_MDSYNC_SYNC_PTE3 0x0000352C +#define CS35L41_MDSYNC_SYNC_MSM_STATUS 0x0000353C +#define CS35L41_BSTCVRT_VCTRL1 0x00003800 +#define CS35L41_BSTCVRT_VCTRL2 0x00003804 +#define CS35L41_BSTCVRT_PEAK_CUR 0x00003808 +#define CS35L41_BSTCVRT_SFT_RAMP 0x0000380C +#define CS35L41_BSTCVRT_COEFF 0x00003810 +#define CS35L41_BSTCVRT_SLOPE_LBST 0x00003814 +#define CS35L41_BSTCVRT_SW_FREQ 0x00003818 +#define CS35L41_BSTCVRT_DCM_CTRL 0x0000381C +#define CS35L41_BSTCVRT_DCM_MODE_FORCE 0x00003820 +#define CS35L41_BSTCVRT_OVERVOLT_CTRL 0x00003830 +#define CS35L41_VI_VOL_POL 0x00004000 +#define CS35L41_VIMON_SPKMON_RESYNC 0x00004100 +#define CS35L41_DTEMP_WARN_THLD 0x00004220 +#define CS35L41_DTEMP_CFG 0x00004224 +#define CS35L41_DTEMP_EN 0x00004308 +#define CS35L41_VPVBST_FS_SEL 0x00004400 +#define CS35L41_SP_ENABLES 0x00004800 +#define CS35L41_SP_RATE_CTRL 0x00004804 +#define CS35L41_SP_FORMAT 0x00004808 +#define CS35L41_SP_HIZ_CTRL 0x0000480C +#define CS35L41_SP_FRAME_TX_SLOT 0x00004810 +#define CS35L41_SP_FRAME_RX_SLOT 0x00004820 +#define CS35L41_SP_TX_WL 0x00004830 +#define CS35L41_SP_RX_WL 0x00004840 +#define CS35L41_ASP_CONTROL4 0x00004854 +#define CS35L41_DAC_PCM1_SRC 0x00004C00 +#define CS35L41_ASP_TX1_SRC 0x00004C20 +#define CS35L41_ASP_TX2_SRC 0x00004C24 +#define CS35L41_ASP_TX3_SRC 0x00004C28 +#define CS35L41_ASP_TX4_SRC 0x00004C2C +#define CS35L41_DSP1_RX1_SRC 0x00004C40 +#define CS35L41_DSP1_RX2_SRC 0x00004C44 +#define CS35L41_DSP1_RX3_SRC 0x00004C48 +#define CS35L41_DSP1_RX4_SRC 0x00004C4C +#define CS35L41_DSP1_RX5_SRC 0x00004C50 +#define CS35L41_DSP1_RX6_SRC 0x00004C54 +#define CS35L41_DSP1_RX7_SRC 0x00004C58 +#define CS35L41_DSP1_RX8_SRC 0x00004C5C +#define CS35L41_NGATE1_SRC 0x00004C60 +#define CS35L41_NGATE2_SRC 0x00004C64 +#define CS35L41_AMP_DIG_VOL_CTRL 0x00006000 +#define CS35L41_VPBR_CFG 0x00006404 +#define CS35L41_VBBR_CFG 0x00006408 +#define CS35L41_VPBR_STATUS 0x0000640C +#define CS35L41_VBBR_STATUS 0x00006410 +#define CS35L41_OVERTEMP_CFG 0x00006414 +#define CS35L41_AMP_ERR_VOL 0x00006418 +#define CS35L41_VOL_STATUS_TO_DSP 0x00006450 +#define CS35L41_CLASSH_CFG 0x00006800 +#define CS35L41_WKFET_CFG 0x00006804 +#define CS35L41_NG_CFG 0x00006808 +#define CS35L41_AMP_GAIN_CTRL 0x00006C04 +#define CS35L41_DAC_MSM_CFG 0x00007400 +#define CS35L41_IRQ1_CFG 0x00010000 +#define CS35L41_IRQ1_STATUS 0x00010004 +#define CS35L41_IRQ1_STATUS1 0x00010010 +#define CS35L41_IRQ1_STATUS2 0x00010014 +#define CS35L41_IRQ1_STATUS3 0x00010018 +#define CS35L41_IRQ1_STATUS4 0x0001001C +#define CS35L41_IRQ1_RAW_STATUS1 0x00010090 +#define CS35L41_IRQ1_RAW_STATUS2 0x00010094 +#define CS35L41_IRQ1_RAW_STATUS3 0x00010098 +#define CS35L41_IRQ1_RAW_STATUS4 0x0001009C +#define CS35L41_IRQ1_MASK1 0x00010110 +#define CS35L41_IRQ1_MASK2 0x00010114 +#define CS35L41_IRQ1_MASK3 0x00010118 +#define CS35L41_IRQ1_MASK4 0x0001011C +#define CS35L41_IRQ1_FRC1 0x00010190 +#define CS35L41_IRQ1_FRC2 0x00010194 +#define CS35L41_IRQ1_FRC3 0x00010198 +#define CS35L41_IRQ1_FRC4 0x0001019C +#define CS35L41_IRQ1_EDGE1 0x00010210 +#define CS35L41_IRQ1_EDGE4 0x0001021C +#define CS35L41_IRQ1_POL1 0x00010290 +#define CS35L41_IRQ1_POL2 0x00010294 +#define CS35L41_IRQ1_POL3 0x00010298 +#define CS35L41_IRQ1_POL4 0x0001029C +#define CS35L41_IRQ1_DB3 0x00010318 +#define CS35L41_IRQ2_CFG 0x00010800 +#define CS35L41_IRQ2_STATUS 0x00010804 +#define CS35L41_IRQ2_STATUS1 0x00010810 +#define CS35L41_IRQ2_STATUS2 0x00010814 +#define CS35L41_IRQ2_STATUS3 0x00010818 +#define CS35L41_IRQ2_STATUS4 0x0001081C +#define CS35L41_IRQ2_RAW_STATUS1 0x00010890 +#define CS35L41_IRQ2_RAW_STATUS2 0x00010894 +#define CS35L41_IRQ2_RAW_STATUS3 0x00010898 +#define CS35L41_IRQ2_RAW_STATUS4 0x0001089C +#define CS35L41_IRQ2_MASK1 0x00010910 +#define CS35L41_IRQ2_MASK2 0x00010914 +#define CS35L41_IRQ2_MASK3 0x00010918 +#define CS35L41_IRQ2_MASK4 0x0001091C +#define CS35L41_IRQ2_FRC1 0x00010990 +#define CS35L41_IRQ2_FRC2 0x00010994 +#define CS35L41_IRQ2_FRC3 0x00010998 +#define CS35L41_IRQ2_FRC4 0x0001099C +#define CS35L41_IRQ2_EDGE1 0x00010A10 +#define CS35L41_IRQ2_EDGE4 0x00010A1C +#define CS35L41_IRQ2_POL1 0x00010A90 +#define CS35L41_IRQ2_POL2 0x00010A94 +#define CS35L41_IRQ2_POL3 0x00010A98 +#define CS35L41_IRQ2_POL4 0x00010A9C +#define CS35L41_IRQ2_DB3 0x00010B18 +#define CS35L41_GPIO_STATUS1 0x00011000 +#define CS35L41_GPIO1_CTRL1 0x00011008 +#define CS35L41_GPIO2_CTRL1 0x0001100C +#define CS35L41_MIXER_NGATE_CFG 0x00012000 +#define CS35L41_MIXER_NGATE_CH1_CFG 0x00012004 +#define CS35L41_MIXER_NGATE_CH2_CFG 0x00012008 +#define CS35L41_DSP_MBOX_1 0x00013000 +#define CS35L41_DSP_MBOX_2 0x00013004 +#define CS35L41_DSP_MBOX_3 0x00013008 +#define CS35L41_DSP_MBOX_4 0x0001300C +#define CS35L41_DSP_MBOX_5 0x00013010 +#define CS35L41_DSP_MBOX_6 0x00013014 +#define CS35L41_DSP_MBOX_7 0x00013018 +#define CS35L41_DSP_MBOX_8 0x0001301C +#define CS35L41_DSP_VIRT1_MBOX_1 0x00013020 +#define CS35L41_DSP_VIRT1_MBOX_2 0x00013024 +#define CS35L41_DSP_VIRT1_MBOX_3 0x00013028 +#define CS35L41_DSP_VIRT1_MBOX_4 0x0001302C +#define CS35L41_DSP_VIRT1_MBOX_5 0x00013030 +#define CS35L41_DSP_VIRT1_MBOX_6 0x00013034 +#define CS35L41_DSP_VIRT1_MBOX_7 0x00013038 +#define CS35L41_DSP_VIRT1_MBOX_8 0x0001303C +#define CS35L41_DSP_VIRT2_MBOX_1 0x00013040 +#define CS35L41_DSP_VIRT2_MBOX_2 0x00013044 +#define CS35L41_DSP_VIRT2_MBOX_3 0x00013048 +#define CS35L41_DSP_VIRT2_MBOX_4 0x0001304C +#define CS35L41_DSP_VIRT2_MBOX_5 0x00013050 +#define CS35L41_DSP_VIRT2_MBOX_6 0x00013054 +#define CS35L41_DSP_VIRT2_MBOX_7 0x00013058 +#define CS35L41_DSP_VIRT2_MBOX_8 0x0001305C +#define CS35L41_CLOCK_DETECT_1 0x00014000 +#define CS35L41_TIMER1_CONTROL 0x00015000 +#define CS35L41_TIMER1_COUNT_PRESET 0x00015004 +#define CS35L41_TIMER1_START_STOP 0x0001500C +#define CS35L41_TIMER1_STATUS 0x00015010 +#define CS35L41_TIMER1_COUNT_READBACK 0x00015014 +#define CS35L41_TIMER1_DSP_CLK_CFG 0x00015018 +#define CS35L41_TIMER1_DSP_CLK_STATUS 0x0001501C +#define CS35L41_TIMER2_CONTROL 0x00015100 +#define CS35L41_TIMER2_COUNT_PRESET 0x00015104 +#define CS35L41_TIMER2_START_STOP 0x0001510C +#define CS35L41_TIMER2_STATUS 0x00015110 +#define CS35L41_TIMER2_COUNT_READBACK 0x00015114 +#define CS35L41_TIMER2_DSP_CLK_CFG 0x00015118 +#define CS35L41_TIMER2_DSP_CLK_STATUS 0x0001511C +#define CS35L41_DFT_JTAG_CONTROL 0x00016000 +#define CS35L41_DIE_STS1 0x00017040 +#define CS35L41_DIE_STS2 0x00017044 +#define CS35L41_TEMP_CAL1 0x00017048 +#define CS35L41_TEMP_CAL2 0x0001704C +#define CS35L41_DSP1_XMEM_PACK_0 0x02000000 +#define CS35L41_DSP1_XMEM_PACK_3068 0x02002FF0 +#define CS35L41_DSP1_XMEM_UNPACK32_0 0x02400000 +#define CS35L41_DSP1_XMEM_UNPACK32_2046 0x02401FF8 +#define CS35L41_DSP1_TIMESTAMP_COUNT 0x025C0800 +#define CS35L41_DSP1_SYS_ID 0x025E0000 +#define CS35L41_DSP1_SYS_VERSION 0x025E0004 +#define CS35L41_DSP1_SYS_CORE_ID 0x025E0008 +#define CS35L41_DSP1_SYS_AHB_ADDR 0x025E000C +#define CS35L41_DSP1_SYS_XSRAM_SIZE 0x025E0010 +#define CS35L41_DSP1_SYS_YSRAM_SIZE 0x025E0018 +#define CS35L41_DSP1_SYS_PSRAM_SIZE 0x025E0020 +#define CS35L41_DSP1_SYS_PM_BOOT_SIZE 0x025E0028 +#define CS35L41_DSP1_SYS_FEATURES 0x025E002C +#define CS35L41_DSP1_SYS_FIR_FILTERS 0x025E0030 +#define CS35L41_DSP1_SYS_LMS_FILTERS 0x025E0034 +#define CS35L41_DSP1_SYS_XM_BANK_SIZE 0x025E0038 +#define CS35L41_DSP1_SYS_YM_BANK_SIZE 0x025E003C +#define CS35L41_DSP1_SYS_PM_BANK_SIZE 0x025E0040 +#define CS35L41_DSP1_AHBM_WIN0_CTRL0 0x025E2000 +#define CS35L41_DSP1_AHBM_WIN0_CTRL1 0x025E2004 +#define CS35L41_DSP1_AHBM_WIN1_CTRL0 0x025E2008 +#define CS35L41_DSP1_AHBM_WIN1_CTRL1 0x025E200C +#define CS35L41_DSP1_AHBM_WIN2_CTRL0 0x025E2010 +#define CS35L41_DSP1_AHBM_WIN2_CTRL1 0x025E2014 +#define CS35L41_DSP1_AHBM_WIN3_CTRL0 0x025E2018 +#define CS35L41_DSP1_AHBM_WIN3_CTRL1 0x025E201C +#define CS35L41_DSP1_AHBM_WIN4_CTRL0 0x025E2020 +#define CS35L41_DSP1_AHBM_WIN4_CTRL1 0x025E2024 +#define CS35L41_DSP1_AHBM_WIN5_CTRL0 0x025E2028 +#define CS35L41_DSP1_AHBM_WIN5_CTRL1 0x025E202C +#define CS35L41_DSP1_AHBM_WIN6_CTRL0 0x025E2030 +#define CS35L41_DSP1_AHBM_WIN6_CTRL1 0x025E2034 +#define CS35L41_DSP1_AHBM_WIN7_CTRL0 0x025E2038 +#define CS35L41_DSP1_AHBM_WIN7_CTRL1 0x025E203C +#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL0 0x025E2040 +#define CS35L41_DSP1_AHBM_WIN_DBG_CTRL1 0x025E2044 +#define CS35L41_DSP1_XMEM_UNPACK24_0 0x02800000 +#define CS35L41_DSP1_XMEM_UNPACK24_4093 0x02803FF4 +#define CS35L41_DSP1_CTRL_BASE 0x02B80000 +#define CS35L41_DSP1_CORE_SOFT_RESET 0x02B80010 +#define CS35L41_DSP1_DEBUG 0x02B80040 +#define CS35L41_DSP1_TIMER_CTRL 0x02B80048 +#define CS35L41_DSP1_STREAM_ARB_CTRL 0x02B80050 +#define CS35L41_DSP1_RX1_RATE 0x02B80080 +#define CS35L41_DSP1_RX2_RATE 0x02B80088 +#define CS35L41_DSP1_RX3_RATE 0x02B80090 +#define CS35L41_DSP1_RX4_RATE 0x02B80098 +#define CS35L41_DSP1_RX5_RATE 0x02B800A0 +#define CS35L41_DSP1_RX6_RATE 0x02B800A8 +#define CS35L41_DSP1_RX7_RATE 0x02B800B0 +#define CS35L41_DSP1_RX8_RATE 0x02B800B8 +#define CS35L41_DSP1_TX1_RATE 0x02B80280 +#define CS35L41_DSP1_TX2_RATE 0x02B80288 +#define CS35L41_DSP1_TX3_RATE 0x02B80290 +#define CS35L41_DSP1_TX4_RATE 0x02B80298 +#define CS35L41_DSP1_TX5_RATE 0x02B802A0 +#define CS35L41_DSP1_TX6_RATE 0x02B802A8 +#define CS35L41_DSP1_TX7_RATE 0x02B802B0 +#define CS35L41_DSP1_TX8_RATE 0x02B802B8 +#define CS35L41_DSP1_NMI_CTRL1 0x02B80480 +#define CS35L41_DSP1_NMI_CTRL2 0x02B80488 +#define CS35L41_DSP1_NMI_CTRL3 0x02B80490 +#define CS35L41_DSP1_NMI_CTRL4 0x02B80498 +#define CS35L41_DSP1_NMI_CTRL5 0x02B804A0 +#define CS35L41_DSP1_NMI_CTRL6 0x02B804A8 +#define CS35L41_DSP1_NMI_CTRL7 0x02B804B0 +#define CS35L41_DSP1_NMI_CTRL8 0x02B804B8 +#define CS35L41_DSP1_RESUME_CTRL 0x02B80500 +#define CS35L41_DSP1_IRQ1_CTRL 0x02B80508 +#define CS35L41_DSP1_IRQ2_CTRL 0x02B80510 +#define CS35L41_DSP1_IRQ3_CTRL 0x02B80518 +#define CS35L41_DSP1_IRQ4_CTRL 0x02B80520 +#define CS35L41_DSP1_IRQ5_CTRL 0x02B80528 +#define CS35L41_DSP1_IRQ6_CTRL 0x02B80530 +#define CS35L41_DSP1_IRQ7_CTRL 0x02B80538 +#define CS35L41_DSP1_IRQ8_CTRL 0x02B80540 +#define CS35L41_DSP1_IRQ9_CTRL 0x02B80548 +#define CS35L41_DSP1_IRQ10_CTRL 0x02B80550 +#define CS35L41_DSP1_IRQ11_CTRL 0x02B80558 +#define CS35L41_DSP1_IRQ12_CTRL 0x02B80560 +#define CS35L41_DSP1_IRQ13_CTRL 0x02B80568 +#define CS35L41_DSP1_IRQ14_CTRL 0x02B80570 +#define CS35L41_DSP1_IRQ15_CTRL 0x02B80578 +#define CS35L41_DSP1_IRQ16_CTRL 0x02B80580 +#define CS35L41_DSP1_IRQ17_CTRL 0x02B80588 +#define CS35L41_DSP1_IRQ18_CTRL 0x02B80590 +#define CS35L41_DSP1_IRQ19_CTRL 0x02B80598 +#define CS35L41_DSP1_IRQ20_CTRL 0x02B805A0 +#define CS35L41_DSP1_IRQ21_CTRL 0x02B805A8 +#define CS35L41_DSP1_IRQ22_CTRL 0x02B805B0 +#define CS35L41_DSP1_IRQ23_CTRL 0x02B805B8 +#define CS35L41_DSP1_SCRATCH1 0x02B805C0 +#define CS35L41_DSP1_SCRATCH2 0x02B805C8 +#define CS35L41_DSP1_SCRATCH3 0x02B805D0 +#define CS35L41_DSP1_SCRATCH4 0x02B805D8 +#define CS35L41_DSP1_CCM_CORE_CTRL 0x02BC1000 +#define CS35L41_DSP1_CCM_CLK_OVERRIDE 0x02BC1008 +#define CS35L41_DSP1_XM_MSTR_EN 0x02BC2000 +#define CS35L41_DSP1_XM_CORE_PRI 0x02BC2008 +#define CS35L41_DSP1_XM_AHB_PACK_PL_PRI 0x02BC2010 +#define CS35L41_DSP1_XM_AHB_UP_PL_PRI 0x02BC2018 +#define CS35L41_DSP1_XM_ACCEL_PL0_PRI 0x02BC2020 +#define CS35L41_DSP1_XM_NPL0_PRI 0x02BC2078 +#define CS35L41_DSP1_YM_MSTR_EN 0x02BC20C0 +#define CS35L41_DSP1_YM_CORE_PRI 0x02BC20C8 +#define CS35L41_DSP1_YM_AHB_PACK_PL_PRI 0x02BC20D0 +#define CS35L41_DSP1_YM_AHB_UP_PL_PRI 0x02BC20D8 +#define CS35L41_DSP1_YM_ACCEL_PL0_PRI 0x02BC20E0 +#define CS35L41_DSP1_YM_NPL0_PRI 0x02BC2138 +#define CS35L41_DSP1_PM_MSTR_EN 0x02BC2180 +#define CS35L41_DSP1_PM_PATCH0_ADDR 0x02BC2188 +#define CS35L41_DSP1_PM_PATCH0_EN 0x02BC218C +#define CS35L41_DSP1_PM_PATCH0_DATA_LO 0x02BC2190 +#define CS35L41_DSP1_PM_PATCH0_DATA_HI 0x02BC2194 +#define CS35L41_DSP1_PM_PATCH1_ADDR 0x02BC2198 +#define CS35L41_DSP1_PM_PATCH1_EN 0x02BC219C +#define CS35L41_DSP1_PM_PATCH1_DATA_LO 0x02BC21A0 +#define CS35L41_DSP1_PM_PATCH1_DATA_HI 0x02BC21A4 +#define CS35L41_DSP1_PM_PATCH2_ADDR 0x02BC21A8 +#define CS35L41_DSP1_PM_PATCH2_EN 0x02BC21AC +#define CS35L41_DSP1_PM_PATCH2_DATA_LO 0x02BC21B0 +#define CS35L41_DSP1_PM_PATCH2_DATA_HI 0x02BC21B4 +#define CS35L41_DSP1_PM_PATCH3_ADDR 0x02BC21B8 +#define CS35L41_DSP1_PM_PATCH3_EN 0x02BC21BC +#define CS35L41_DSP1_PM_PATCH3_DATA_LO 0x02BC21C0 +#define CS35L41_DSP1_PM_PATCH3_DATA_HI 0x02BC21C4 +#define CS35L41_DSP1_PM_PATCH4_ADDR 0x02BC21C8 +#define CS35L41_DSP1_PM_PATCH4_EN 0x02BC21CC +#define CS35L41_DSP1_PM_PATCH4_DATA_LO 0x02BC21D0 +#define CS35L41_DSP1_PM_PATCH4_DATA_HI 0x02BC21D4 +#define CS35L41_DSP1_PM_PATCH5_ADDR 0x02BC21D8 +#define CS35L41_DSP1_PM_PATCH5_EN 0x02BC21DC +#define CS35L41_DSP1_PM_PATCH5_DATA_LO 0x02BC21E0 +#define CS35L41_DSP1_PM_PATCH5_DATA_HI 0x02BC21E4 +#define CS35L41_DSP1_PM_PATCH6_ADDR 0x02BC21E8 +#define CS35L41_DSP1_PM_PATCH6_EN 0x02BC21EC +#define CS35L41_DSP1_PM_PATCH6_DATA_LO 0x02BC21F0 +#define CS35L41_DSP1_PM_PATCH6_DATA_HI 0x02BC21F4 +#define CS35L41_DSP1_PM_PATCH7_ADDR 0x02BC21F8 +#define CS35L41_DSP1_PM_PATCH7_EN 0x02BC21FC +#define CS35L41_DSP1_PM_PATCH7_DATA_LO 0x02BC2200 +#define CS35L41_DSP1_PM_PATCH7_DATA_HI 0x02BC2204 +#define CS35L41_DSP1_MPU_XM_ACCESS0 0x02BC3000 +#define CS35L41_DSP1_MPU_YM_ACCESS0 0x02BC3004 +#define CS35L41_DSP1_MPU_WNDW_ACCESS0 0x02BC3008 +#define CS35L41_DSP1_MPU_XREG_ACCESS0 0x02BC300C +#define CS35L41_DSP1_MPU_YREG_ACCESS0 0x02BC3014 +#define CS35L41_DSP1_MPU_XM_ACCESS1 0x02BC3018 +#define CS35L41_DSP1_MPU_YM_ACCESS1 0x02BC301C +#define CS35L41_DSP1_MPU_WNDW_ACCESS1 0x02BC3020 +#define CS35L41_DSP1_MPU_XREG_ACCESS1 0x02BC3024 +#define CS35L41_DSP1_MPU_YREG_ACCESS1 0x02BC302C +#define CS35L41_DSP1_MPU_XM_ACCESS2 0x02BC3030 +#define CS35L41_DSP1_MPU_YM_ACCESS2 0x02BC3034 +#define CS35L41_DSP1_MPU_WNDW_ACCESS2 0x02BC3038 +#define CS35L41_DSP1_MPU_XREG_ACCESS2 0x02BC303C +#define CS35L41_DSP1_MPU_YREG_ACCESS2 0x02BC3044 +#define CS35L41_DSP1_MPU_XM_ACCESS3 0x02BC3048 +#define CS35L41_DSP1_MPU_YM_ACCESS3 0x02BC304C +#define CS35L41_DSP1_MPU_WNDW_ACCESS3 0x02BC3050 +#define CS35L41_DSP1_MPU_XREG_ACCESS3 0x02BC3054 +#define CS35L41_DSP1_MPU_YREG_ACCESS3 0x02BC305C +#define CS35L41_DSP1_MPU_XM_VIO_ADDR 0x02BC3100 +#define CS35L41_DSP1_MPU_XM_VIO_STATUS 0x02BC3104 +#define CS35L41_DSP1_MPU_YM_VIO_ADDR 0x02BC3108 +#define CS35L41_DSP1_MPU_YM_VIO_STATUS 0x02BC310C +#define CS35L41_DSP1_MPU_PM_VIO_ADDR 0x02BC3110 +#define CS35L41_DSP1_MPU_PM_VIO_STATUS 0x02BC3114 +#define CS35L41_DSP1_MPU_LOCK_CONFIG 0x02BC3140 +#define CS35L41_DSP1_MPU_WDT_RST_CTRL 0x02BC3180 +#define CS35L41_DSP1_STRMARB_MSTR0_CFG0 0x02BC5000 +#define CS35L41_DSP1_STRMARB_MSTR0_CFG1 0x02BC5004 +#define CS35L41_DSP1_STRMARB_MSTR0_CFG2 0x02BC5008 +#define CS35L41_DSP1_STRMARB_MSTR1_CFG0 0x02BC5010 +#define CS35L41_DSP1_STRMARB_MSTR1_CFG1 0x02BC5014 +#define CS35L41_DSP1_STRMARB_MSTR1_CFG2 0x02BC5018 +#define CS35L41_DSP1_STRMARB_MSTR2_CFG0 0x02BC5020 +#define CS35L41_DSP1_STRMARB_MSTR2_CFG1 0x02BC5024 +#define CS35L41_DSP1_STRMARB_MSTR2_CFG2 0x02BC5028 +#define CS35L41_DSP1_STRMARB_MSTR3_CFG0 0x02BC5030 +#define CS35L41_DSP1_STRMARB_MSTR3_CFG1 0x02BC5034 +#define CS35L41_DSP1_STRMARB_MSTR3_CFG2 0x02BC5038 +#define CS35L41_DSP1_STRMARB_MSTR4_CFG0 0x02BC5040 +#define CS35L41_DSP1_STRMARB_MSTR4_CFG1 0x02BC5044 +#define CS35L41_DSP1_STRMARB_MSTR4_CFG2 0x02BC5048 +#define CS35L41_DSP1_STRMARB_MSTR5_CFG0 0x02BC5050 +#define CS35L41_DSP1_STRMARB_MSTR5_CFG1 0x02BC5054 +#define CS35L41_DSP1_STRMARB_MSTR5_CFG2 0x02BC5058 +#define CS35L41_DSP1_STRMARB_MSTR6_CFG0 0x02BC5060 +#define CS35L41_DSP1_STRMARB_MSTR6_CFG1 0x02BC5064 +#define CS35L41_DSP1_STRMARB_MSTR6_CFG2 0x02BC5068 +#define CS35L41_DSP1_STRMARB_MSTR7_CFG0 0x02BC5070 +#define CS35L41_DSP1_STRMARB_MSTR7_CFG1 0x02BC5074 +#define CS35L41_DSP1_STRMARB_MSTR7_CFG2 0x02BC5078 +#define CS35L41_DSP1_STRMARB_TX0_CFG0 0x02BC5200 +#define CS35L41_DSP1_STRMARB_TX0_CFG1 0x02BC5204 +#define CS35L41_DSP1_STRMARB_TX1_CFG0 0x02BC5208 +#define CS35L41_DSP1_STRMARB_TX1_CFG1 0x02BC520C +#define CS35L41_DSP1_STRMARB_TX2_CFG0 0x02BC5210 +#define CS35L41_DSP1_STRMARB_TX2_CFG1 0x02BC5214 +#define CS35L41_DSP1_STRMARB_TX3_CFG0 0x02BC5218 +#define CS35L41_DSP1_STRMARB_TX3_CFG1 0x02BC521C +#define CS35L41_DSP1_STRMARB_TX4_CFG0 0x02BC5220 +#define CS35L41_DSP1_STRMARB_TX4_CFG1 0x02BC5224 +#define CS35L41_DSP1_STRMARB_TX5_CFG0 0x02BC5228 +#define CS35L41_DSP1_STRMARB_TX5_CFG1 0x02BC522C +#define CS35L41_DSP1_STRMARB_TX6_CFG0 0x02BC5230 +#define CS35L41_DSP1_STRMARB_TX6_CFG1 0x02BC5234 +#define CS35L41_DSP1_STRMARB_TX7_CFG0 0x02BC5238 +#define CS35L41_DSP1_STRMARB_TX7_CFG1 0x02BC523C +#define CS35L41_DSP1_STRMARB_RX0_CFG0 0x02BC5400 +#define CS35L41_DSP1_STRMARB_RX0_CFG1 0x02BC5404 +#define CS35L41_DSP1_STRMARB_RX1_CFG0 0x02BC5408 +#define CS35L41_DSP1_STRMARB_RX1_CFG1 0x02BC540C +#define CS35L41_DSP1_STRMARB_RX2_CFG0 0x02BC5410 +#define CS35L41_DSP1_STRMARB_RX2_CFG1 0x02BC5414 +#define CS35L41_DSP1_STRMARB_RX3_CFG0 0x02BC5418 +#define CS35L41_DSP1_STRMARB_RX3_CFG1 0x02BC541C +#define CS35L41_DSP1_STRMARB_RX4_CFG0 0x02BC5420 +#define CS35L41_DSP1_STRMARB_RX4_CFG1 0x02BC5424 +#define CS35L41_DSP1_STRMARB_RX5_CFG0 0x02BC5428 +#define CS35L41_DSP1_STRMARB_RX5_CFG1 0x02BC542C +#define CS35L41_DSP1_STRMARB_RX6_CFG0 0x02BC5430 +#define CS35L41_DSP1_STRMARB_RX6_CFG1 0x02BC5434 +#define CS35L41_DSP1_STRMARB_RX7_CFG0 0x02BC5438 +#define CS35L41_DSP1_STRMARB_RX7_CFG1 0x02BC543C +#define CS35L41_DSP1_STRMARB_IRQ0_CFG0 0x02BC5600 +#define CS35L41_DSP1_STRMARB_IRQ0_CFG1 0x02BC5604 +#define CS35L41_DSP1_STRMARB_IRQ0_CFG2 0x02BC5608 +#define CS35L41_DSP1_STRMARB_IRQ1_CFG0 0x02BC5610 +#define CS35L41_DSP1_STRMARB_IRQ1_CFG1 0x02BC5614 +#define CS35L41_DSP1_STRMARB_IRQ1_CFG2 0x02BC5618 +#define CS35L41_DSP1_STRMARB_IRQ2_CFG0 0x02BC5620 +#define CS35L41_DSP1_STRMARB_IRQ2_CFG1 0x02BC5624 +#define CS35L41_DSP1_STRMARB_IRQ2_CFG2 0x02BC5628 +#define CS35L41_DSP1_STRMARB_IRQ3_CFG0 0x02BC5630 +#define CS35L41_DSP1_STRMARB_IRQ3_CFG1 0x02BC5634 +#define CS35L41_DSP1_STRMARB_IRQ3_CFG2 0x02BC5638 +#define CS35L41_DSP1_STRMARB_IRQ4_CFG0 0x02BC5640 +#define CS35L41_DSP1_STRMARB_IRQ4_CFG1 0x02BC5644 +#define CS35L41_DSP1_STRMARB_IRQ4_CFG2 0x02BC5648 +#define CS35L41_DSP1_STRMARB_IRQ5_CFG0 0x02BC5650 +#define CS35L41_DSP1_STRMARB_IRQ5_CFG1 0x02BC5654 +#define CS35L41_DSP1_STRMARB_IRQ5_CFG2 0x02BC5658 +#define CS35L41_DSP1_STRMARB_IRQ6_CFG0 0x02BC5660 +#define CS35L41_DSP1_STRMARB_IRQ6_CFG1 0x02BC5664 +#define CS35L41_DSP1_STRMARB_IRQ6_CFG2 0x02BC5668 +#define CS35L41_DSP1_STRMARB_IRQ7_CFG0 0x02BC5670 +#define CS35L41_DSP1_STRMARB_IRQ7_CFG1 0x02BC5674 +#define CS35L41_DSP1_STRMARB_IRQ7_CFG2 0x02BC5678 +#define CS35L41_DSP1_STRMARB_RESYNC_MSK 0x02BC5A00 +#define CS35L41_DSP1_STRMARB_ERR_STATUS 0x02BC5A08 +#define CS35L41_DSP1_INTPCTL_RES_STATIC 0x02BC6000 +#define CS35L41_DSP1_INTPCTL_RES_DYN 0x02BC6004 +#define CS35L41_DSP1_INTPCTL_NMI_CTRL 0x02BC6008 +#define CS35L41_DSP1_INTPCTL_IRQ_INV 0x02BC6010 +#define CS35L41_DSP1_INTPCTL_IRQ_MODE 0x02BC6014 +#define CS35L41_DSP1_INTPCTL_IRQ_EN 0x02BC6018 +#define CS35L41_DSP1_INTPCTL_IRQ_MSK 0x02BC601C +#define CS35L41_DSP1_INTPCTL_IRQ_FLUSH 0x02BC6020 +#define CS35L41_DSP1_INTPCTL_IRQ_MSKCLR 0x02BC6024 +#define CS35L41_DSP1_INTPCTL_IRQ_FRC 0x02BC6028 +#define CS35L41_DSP1_INTPCTL_IRQ_MSKSET 0x02BC602C +#define CS35L41_DSP1_INTPCTL_IRQ_ERR 0x02BC6030 +#define CS35L41_DSP1_INTPCTL_IRQ_PEND 0x02BC6034 +#define CS35L41_DSP1_INTPCTL_IRQ_GEN 0x02BC6038 +#define CS35L41_DSP1_INTPCTL_TESTBITS 0x02BC6040 +#define CS35L41_DSP1_WDT_CONTROL 0x02BC7000 +#define CS35L41_DSP1_WDT_STATUS 0x02BC7008 +#define CS35L41_DSP1_YMEM_PACK_0 0x02C00000 +#define CS35L41_DSP1_YMEM_PACK_1532 0x02C017F0 +#define CS35L41_DSP1_YMEM_UNPACK32_0 0x03000000 +#define CS35L41_DSP1_YMEM_UNPACK32_1022 0x03000FF8 +#define CS35L41_DSP1_YMEM_UNPACK24_0 0x03400000 +#define CS35L41_DSP1_YMEM_UNPACK24_2045 0x03401FF4 +#define CS35L41_DSP1_PMEM_0 0x03800000 +#define CS35L41_DSP1_PMEM_5114 0x03804FE8 + +/*test regs for emulation bringup*/ +#define CS35L41_PLL_OVR 0x00003018 +#define CS35L41_BST_TEST_DUTY 0x00003900 +#define CS35L41_DIGPWM_IOCTRL 0x0000706C + +/*registers populated by OTP*/ +#define CS35L41_OTP_TRIM_1 0x0000208c +#define CS35L41_OTP_TRIM_2 0x00002090 +#define CS35L41_OTP_TRIM_3 0x00003010 +#define CS35L41_OTP_TRIM_4 0x0000300C +#define CS35L41_OTP_TRIM_5 0x0000394C +#define CS35L41_OTP_TRIM_6 0x00003950 +#define CS35L41_OTP_TRIM_7 0x00003954 +#define CS35L41_OTP_TRIM_8 0x00003958 +#define CS35L41_OTP_TRIM_9 0x0000395C +#define CS35L41_OTP_TRIM_10 0x0000416C +#define CS35L41_OTP_TRIM_11 0x00004160 +#define CS35L41_OTP_TRIM_12 0x00004170 +#define CS35L41_OTP_TRIM_13 0x00004360 +#define CS35L41_OTP_TRIM_14 0x00004448 +#define CS35L41_OTP_TRIM_15 0x0000444C +#define CS35L41_OTP_TRIM_16 0x00006E30 +#define CS35L41_OTP_TRIM_17 0x00006E34 +#define CS35L41_OTP_TRIM_18 0x00006E38 +#define CS35L41_OTP_TRIM_19 0x00006E3C +#define CS35L41_OTP_TRIM_20 0x00006E40 +#define CS35L41_OTP_TRIM_21 0x00006E44 +#define CS35L41_OTP_TRIM_22 0x00006E48 +#define CS35L41_OTP_TRIM_23 0x00006E4C +#define CS35L41_OTP_TRIM_24 0x00006E50 +#define CS35L41_OTP_TRIM_25 0x00006E54 +#define CS35L41_OTP_TRIM_26 0x00006E58 +#define CS35L41_OTP_TRIM_27 0x00006E5C +#define CS35L41_OTP_TRIM_28 0x00006E60 +#define CS35L41_OTP_TRIM_29 0x00006E64 +#define CS35L41_OTP_TRIM_30 0x00007418 +#define CS35L41_OTP_TRIM_31 0x0000741C +#define CS35L41_OTP_TRIM_32 0x00007434 +#define CS35L41_OTP_TRIM_33 0x00007068 +#define CS35L41_OTP_TRIM_34 0x0000410C +#define CS35L41_OTP_TRIM_35 0x0000400C +#define CS35L41_OTP_TRIM_36 0x00002030 + +#define CS35L41_MAX_CACHE_REG 36 +#define CS35L41_OTP_SIZE_WORDS 32 + +#define CS35L41_NUM_SUPPLIES 2 + +#define CS35L41_SCLK_MSTR_MASK 0x10 +#define CS35L41_SCLK_MSTR_SHIFT 4 +#define CS35L41_LRCLK_MSTR_MASK 0x01 +#define CS35L41_LRCLK_MSTR_SHIFT 0 +#define CS35L41_SCLK_INV_MASK 0x40 +#define CS35L41_SCLK_INV_SHIFT 6 +#define CS35L41_LRCLK_INV_MASK 0x04 +#define CS35L41_LRCLK_INV_SHIFT 2 +#define CS35L41_SCLK_FRC_MASK 0x20 +#define CS35L41_SCLK_FRC_SHIFT 5 +#define CS35L41_LRCLK_FRC_MASK 0x02 +#define CS35L41_LRCLK_FRC_SHIFT 1 + +#define CS35L41_AMP_GAIN_PCM_MASK 0x3E0 +#define CS35L41_AMP_GAIN_ZC_MASK 0x0400 +#define CS35L41_AMP_GAIN_ZC_SHIFT 10 + +#define CS35L41_BST_CTL_MASK 0xFF +#define CS35L41_BST_CTL_SEL_MASK 0x03 +#define CS35L41_BST_CTL_SEL_REG 0x00 +#define CS35L41_BST_CTL_SEL_CLASSH 0x01 +#define CS35L41_BST_IPK_MASK 0x7F +#define CS35L41_BST_IPK_SHIFT 0 +#define CS35L41_BST_LIM_MASK 0x4 +#define CS35L41_BST_LIM_SHIFT 2 +#define CS35L41_BST_K1_MASK 0x000000FF +#define CS35L41_BST_K1_SHIFT 0 +#define CS35L41_BST_K2_MASK 0x0000FF00 +#define CS35L41_BST_K2_SHIFT 8 +#define CS35L41_BST_SLOPE_MASK 0x0000FF00 +#define CS35L41_BST_SLOPE_SHIFT 8 +#define CS35L41_BST_LBST_VAL_MASK 0x00000003 +#define CS35L41_BST_LBST_VAL_SHIFT 0 + +#define CS35L41_TEMP_THLD_MASK 0x03 +#define CS35L41_VMON_IMON_VOL_MASK 0x07FF07FF +#define CS35L41_PDM_MODE_MASK 0x01 +#define CS35L41_PDM_MODE_SHIFT 0 + +#define CS35L41_CH_MEM_DEPTH_MASK 0x07 +#define CS35L41_CH_MEM_DEPTH_SHIFT 0 +#define CS35L41_CH_HDRM_CTL_MASK 0x007F0000 +#define CS35L41_CH_HDRM_CTL_SHIFT 16 +#define CS35L41_CH_REL_RATE_MASK 0xFF00 +#define CS35L41_CH_REL_RATE_SHIFT 8 +#define CS35L41_CH_WKFET_DLY_MASK 0x001C +#define CS35L41_CH_WKFET_DLY_SHIFT 2 +#define CS35L41_CH_WKFET_THLD_MASK 0x0F00 +#define CS35L41_CH_WKFET_THLD_SHIFT 8 + +#define CS35L41_HW_NG_SEL_MASK 0x3F00 +#define CS35L41_HW_NG_SEL_SHIFT 8 +#define CS35L41_HW_NG_DLY_MASK 0x0070 +#define CS35L41_HW_NG_DLY_SHIFT 4 +#define CS35L41_HW_NG_THLD_MASK 0x0007 +#define CS35L41_HW_NG_THLD_SHIFT 0 + +#define CS35L41_DSP_NG_ENABLE_MASK 0x00010000 +#define CS35L41_DSP_NG_ENABLE_SHIFT 16 +#define CS35L41_DSP_NG_THLD_MASK 0x7 +#define CS35L41_DSP_NG_THLD_SHIFT 0 +#define CS35L41_DSP_NG_DELAY_MASK 0x0F00 +#define CS35L41_DSP_NG_DELAY_SHIFT 8 + +#define CS35L41_ASP_FMT_MASK 0x0700 +#define CS35L41_ASP_FMT_SHIFT 8 +#define CS35L41_ASP_DOUT_HIZ_MASK 0x03 +#define CS35L41_ASP_DOUT_HIZ_SHIFT 0 +#define CS35L41_ASP_WIDTH_16 0x10 +#define CS35L41_ASP_WIDTH_24 0x18 +#define CS35L41_ASP_WIDTH_32 0x20 +#define CS35L41_ASP_WIDTH_TX_MASK 0xFF0000 +#define CS35L41_ASP_WIDTH_TX_SHIFT 16 +#define CS35L41_ASP_WIDTH_RX_MASK 0xFF000000 +#define CS35L41_ASP_WIDTH_RX_SHIFT 24 +#define CS35L41_ASP_RX1_SLOT_MASK 0x3F +#define CS35L41_ASP_RX1_SLOT_SHIFT 0 +#define CS35L41_ASP_RX2_SLOT_MASK 0x3F00 +#define CS35L41_ASP_RX2_SLOT_SHIFT 8 +#define CS35L41_ASP_RX_WL_MASK 0x3F +#define CS35L41_ASP_TX_WL_MASK 0x3F +#define CS35L41_ASP_RX_WL_SHIFT 0 +#define CS35L41_ASP_TX_WL_SHIFT 0 +#define CS35L41_ASP_SOURCE_MASK 0x7F + +#define CS35L41_INPUT_SRC_ASPRX1 0x08 +#define CS35L41_INPUT_SRC_ASPRX2 0x09 +#define CS35L41_INPUT_SRC_VMON 0x18 +#define CS35L41_INPUT_SRC_IMON 0x19 +#define CS35L41_INPUT_SRC_CLASSH 0x21 +#define CS35L41_INPUT_SRC_VPMON 0x28 +#define CS35L41_INPUT_SRC_VBSTMON 0x29 +#define CS35L41_INPUT_SRC_TEMPMON 0x3A +#define CS35L41_INPUT_SRC_RSVD 0x3B +#define CS35L41_INPUT_DSP_TX1 0x32 +#define CS35L41_INPUT_DSP_TX2 0x33 + +#define CS35L41_WR_PEND_STS_MASK 0x2 + +#define CS35L41_PLL_CLK_SEL_MASK 0x07 +#define CS35L41_PLL_CLK_SEL_SHIFT 0 +#define CS35L41_PLL_CLK_EN_MASK 0x10 +#define CS35L41_PLL_CLK_EN_SHIFT 4 +#define CS35L41_PLL_OPENLOOP_MASK 0x0800 +#define CS35L41_PLL_OPENLOOP_SHIFT 11 +#define CS35L41_PLLSRC_SCLK 0 +#define CS35L41_PLLSRC_LRCLK 1 +#define CS35L41_PLLSRC_SELF 3 +#define CS35L41_PLLSRC_PDMCLK 4 +#define CS35L41_PLLSRC_MCLK 5 +#define CS35L41_PLLSRC_SWIRE 7 +#define CS35L41_REFCLK_FREQ_MASK 0x7E0 +#define CS35L41_REFCLK_FREQ_SHIFT 5 + +#define CS35L41_GLOBAL_FS_MASK 0x1F +#define CS35L41_GLOBAL_FS_SHIFT 0 + +#define CS35L41_GLOBAL_EN_MASK 0x01 +#define CS35L41_GLOBAL_EN_SHIFT 0 +#define CS35L41_BST_EN_MASK 0x0030 +#define CS35L41_BST_EN_SHIFT 4 +#define CS35L41_BST_DIS_FET_OFF 0x00 +#define CS35L41_BST_EN_DEFAULT 0x2 +#define CS35L41_AMP_EN_SHIFT 0 +#define CS35L41_AMP_EN_MASK 1 +#define CS35L41_VMON_EN_MASK 0x1000 +#define CS35L41_VMON_EN_SHIFT 12 +#define CS35L41_IMON_EN_MASK 0x2000 +#define CS35L41_IMON_EN_SHIFT 13 + +#define CS35L41_PDN_DONE_MASK 0x00800000 +#define CS35L41_PDN_DONE_SHIFT 23 +#define CS35L41_PUP_DONE_MASK 0x01000000 +#define CS35L41_PUP_DONE_SHIFT 24 + +#define CS35L36_PUP_DONE_IRQ_UNMASK 0x5F +#define CS35L36_PUP_DONE_IRQ_MASK 0xBF + +#define CS35L41_AMP_SHORT_ERR 0x80000000 +#define CS35L41_BST_SHORT_ERR 0x0100 +#define CS35L41_TEMP_WARN 0x8000 +#define CS35L41_TEMP_ERR 0x00020000 +#define CS35L41_BST_OVP_ERR 0x40 +#define CS35L41_BST_DCM_UVP_ERR 0x80 +#define CS35L41_OTP_BOOT_DONE 0x02 +#define CS35L41_PLL_UNLOCK 0x10 +#define CS35L41_OTP_BOOT_ERR 0x80000000 + +#define CS35L41_AMP_SHORT_ERR_RLS 0x02 +#define CS35L41_BST_SHORT_ERR_RLS 0x04 +#define CS35L41_BST_OVP_ERR_RLS 0x08 +#define CS35L41_BST_UVP_ERR_RLS 0x10 +#define CS35L41_TEMP_WARN_ERR_RLS 0x20 +#define CS35L41_TEMP_ERR_RLS 0x40 + +#define CS35L41_AMP_SHORT_ERR_RLS_SHIFT 1 +#define CS35L41_BST_SHORT_ERR_RLS_SHIFT 2 +#define CS35L41_BST_OVP_ERR_RLS_SHIFT 3 +#define CS35L41_BST_UVP_ERR_RLS_SHIFT 4 +#define CS35L41_TEMP_WARN_ERR_RLS_SHIFT 5 +#define CS35L41_TEMP_ERR_RLS_SHIFT 6 + +#define CS35L41_INT1_MASK_DEFAULT 0x7FFCFE3F +#define CS35L41_INT1_UNMASK_PUP 0xFEFFFFFF +#define CS35L41_INT1_UNMASK_PDN 0xFF7FFFFF + +#define CS35L41_GPIO_DIR_MASK 0x80000000 +#define CS35L41_GPIO_DIR_SHIFT 31 +#define CS35L41_GPIO1_CTRL_MASK 0x00030000 +#define CS35L41_GPIO1_CTRL_SHIFT 16 +#define CS35L41_GPIO2_CTRL_MASK 0x07000000 +#define CS35L41_GPIO2_CTRL_SHIFT 24 +#define CS35L41_GPIO_LVL_SHIFT 15 +#define CS35L41_GPIO_LVL_MASK BIT(CS35L41_GPIO_LVL_SHIFT) +#define CS35L41_GPIO_POL_MASK 0x1000 +#define CS35L41_GPIO_POL_SHIFT 12 + +#define CS35L41_AMP_INV_PCM_SHIFT 14 +#define CS35L41_AMP_INV_PCM_MASK BIT(CS35L41_AMP_INV_PCM_SHIFT) +#define CS35L41_AMP_PCM_VOL_SHIFT 3 +#define CS35L41_AMP_PCM_VOL_MASK (0x7FF << 3) +#define CS35L41_AMP_PCM_VOL_MUTE 0x4CF + +#define CS35L41_CHIP_ID 0x35a40 +#define CS35L41R_CHIP_ID 0x35b40 +#define CS35L41_MTLREVID_MASK 0x0F +#define CS35L41_REVID_A0 0xA0 +#define CS35L41_REVID_B0 0xB0 +#define CS35L41_REVID_B2 0xB2 + +#define CS35L41_HALO_CORE_RESET 0x00000200 + +#define CS35L41_FS1_WINDOW_MASK 0x000007FF +#define CS35L41_FS2_WINDOW_MASK 0x00FFF800 +#define CS35L41_FS2_WINDOW_SHIFT 12 + +#define CS35L41_SPI_MAX_FREQ 4000000 +#define CS35L41_REGSTRIDE 4 + +enum cs35l41_boost_type { + CS35L41_INT_BOOST, + CS35L41_EXT_BOOST, + CS35L41_EXT_BOOST_NO_VSPK_SWITCH, +}; + +enum cs35l41_clk_ids { + CS35L41_CLKID_SCLK = 0, + CS35L41_CLKID_LRCLK = 1, + CS35L41_CLKID_MCLK = 4, +}; + +enum cs35l41_gpio1_func { + CS35L41_GPIO1_HIZ, + CS35L41_GPIO1_GPIO, + CS35L41_GPIO1_MDSYNC, + CS35L41_GPIO1_MCLK, + CS35L41_GPIO1_PDM_CLK, + CS35L41_GPIO1_PDM_DATA, +}; + +enum cs35l41_gpio2_func { + CS35L41_GPIO2_HIZ, + CS35L41_GPIO2_GPIO, + CS35L41_GPIO2_INT_OPEN_DRAIN, + CS35L41_GPIO2_MCLK, + CS35L41_GPIO2_INT_PUSH_PULL_LOW, + CS35L41_GPIO2_INT_PUSH_PULL_HIGH, + CS35L41_GPIO2_PDM_CLK, + CS35L41_GPIO2_PDM_DATA, +}; + +struct cs35l41_gpio_cfg { + bool valid; + bool pol_inv; + bool out_en; + unsigned int func; +}; + +struct cs35l41_hw_cfg { + bool valid; + int bst_ind; + int bst_ipk; + int bst_cap; + int dout_hiz; + struct cs35l41_gpio_cfg gpio1; + struct cs35l41_gpio_cfg gpio2; + unsigned int spk_pos; + + enum cs35l41_boost_type bst_type; +}; + +struct cs35l41_otp_packed_element_t { + u32 reg; + u8 shift; + u8 size; +}; + +struct cs35l41_otp_map_element_t { + u32 id; + u32 num_elements; + const struct cs35l41_otp_packed_element_t *map; + u32 bit_offset; + u32 word_offset; +}; + +enum cs35l41_cspl_mbox_status { + CSPL_MBOX_STS_RUNNING = 0, + CSPL_MBOX_STS_PAUSED = 1, + CSPL_MBOX_STS_RDY_FOR_REINIT = 2, +}; + +enum cs35l41_cspl_mbox_cmd { + CSPL_MBOX_CMD_NONE = 0, + CSPL_MBOX_CMD_PAUSE = 1, + CSPL_MBOX_CMD_RESUME = 2, + CSPL_MBOX_CMD_REINIT = 3, + CSPL_MBOX_CMD_STOP_PRE_REINIT = 4, + CSPL_MBOX_CMD_HIBERNATE = 5, + CSPL_MBOX_CMD_OUT_OF_HIBERNATE = 6, + CSPL_MBOX_CMD_UNKNOWN_CMD = -1, + CSPL_MBOX_CMD_INVALID_SEQUENCE = -2, +}; + +/* + * IRQs + */ +#define CS35L41_IRQ(_irq, _name, _hand) \ + { \ + .irq = CS35L41_ ## _irq ## _IRQ,\ + .name = _name, \ + .handler = _hand, \ + } + +struct cs35l41_irq { + int irq; + const char *name; + irqreturn_t (*handler)(int irq, void *data); +}; + +#define CS35L41_REG_IRQ(_reg, _irq) \ + [CS35L41_ ## _irq ## _IRQ] = { \ + .reg_offset = (CS35L41_ ## _reg) - CS35L41_IRQ1_STATUS1,\ + .mask = CS35L41_ ## _irq ## _MASK \ + } + +/* (0x0000E010) CS35L41_IRQ1_STATUS1 */ +#define CS35L41_BST_OVP_ERR_SHIFT 6 +#define CS35L41_BST_OVP_ERR_MASK BIT(CS35L41_BST_OVP_ERR_SHIFT) +#define CS35L41_BST_DCM_UVP_ERR_SHIFT 7 +#define CS35L41_BST_DCM_UVP_ERR_MASK BIT(CS35L41_BST_DCM_UVP_ERR_SHIFT) +#define CS35L41_BST_SHORT_ERR_SHIFT 8 +#define CS35L41_BST_SHORT_ERR_MASK BIT(CS35L41_BST_SHORT_ERR_SHIFT) +#define CS35L41_TEMP_WARN_SHIFT 15 +#define CS35L41_TEMP_WARN_MASK BIT(CS35L41_TEMP_WARN_SHIFT) +#define CS35L41_TEMP_ERR_SHIFT 17 +#define CS35L41_TEMP_ERR_MASK BIT(CS35L41_TEMP_ERR_SHIFT) +#define CS35L41_AMP_SHORT_ERR_SHIFT 31 +#define CS35L41_AMP_SHORT_ERR_MASK BIT(CS35L41_AMP_SHORT_ERR_SHIFT) + +enum cs35l41_irq_list { + CS35L41_BST_OVP_ERR_IRQ, + CS35L41_BST_DCM_UVP_ERR_IRQ, + CS35L41_BST_SHORT_ERR_IRQ, + CS35L41_TEMP_WARN_IRQ, + CS35L41_TEMP_ERR_IRQ, + CS35L41_AMP_SHORT_ERR_IRQ, + + CS35L41_NUM_IRQ +}; + +extern struct regmap_config cs35l41_regmap_i2c; +extern struct regmap_config cs35l41_regmap_spi; + +int cs35l41_test_key_unlock(struct device *dev, struct regmap *regmap); +int cs35l41_test_key_lock(struct device *dev, struct regmap *regmap); +int cs35l41_otp_unpack(struct device *dev, struct regmap *regmap); +int cs35l41_register_errata_patch(struct device *dev, struct regmap *reg, unsigned int reg_revid); +int cs35l41_set_channels(struct device *dev, struct regmap *reg, + unsigned int tx_num, unsigned int *tx_slot, + unsigned int rx_num, unsigned int *rx_slot); +int cs35l41_gpio_config(struct regmap *regmap, struct cs35l41_hw_cfg *hw_cfg); +void cs35l41_configure_cs_dsp(struct device *dev, struct regmap *reg, struct cs_dsp *dsp); +int cs35l41_set_cspl_mbox_cmd(struct device *dev, struct regmap *regmap, + enum cs35l41_cspl_mbox_cmd cmd); +int cs35l41_write_fs_errata(struct device *dev, struct regmap *regmap); +int cs35l41_enter_hibernate(struct device *dev, struct regmap *regmap, + enum cs35l41_boost_type b_type); +int cs35l41_exit_hibernate(struct device *dev, struct regmap *regmap); +int cs35l41_init_boost(struct device *dev, struct regmap *regmap, + struct cs35l41_hw_cfg *hw_cfg); +bool cs35l41_safe_reset(struct regmap *regmap, enum cs35l41_boost_type b_type); +int cs35l41_global_enable(struct regmap *regmap, enum cs35l41_boost_type b_type, int enable); + +#endif /* __CS35L41_H */ diff --git a/include/sound/cs4231-regs.h b/include/sound/cs4231-regs.h new file mode 100644 index 000000000..806a55104 --- /dev/null +++ b/include/sound/cs4231-regs.h @@ -0,0 +1,172 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_CS4231_REGS_H +#define __SOUND_CS4231_REGS_H + +/* + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + * Definitions for CS4231 & InterWave chips & compatible chips registers + */ + +/* IO ports */ + +#define CS4231P(x) (c_d_c_CS4231##x) + +#define c_d_c_CS4231REGSEL 0 +#define c_d_c_CS4231REG 1 +#define c_d_c_CS4231STATUS 2 +#define c_d_c_CS4231PIO 3 + +/* codec registers */ + +#define CS4231_LEFT_INPUT 0x00 /* left input control */ +#define CS4231_RIGHT_INPUT 0x01 /* right input control */ +#define CS4231_AUX1_LEFT_INPUT 0x02 /* left AUX1 input control */ +#define CS4231_AUX1_RIGHT_INPUT 0x03 /* right AUX1 input control */ +#define CS4231_AUX2_LEFT_INPUT 0x04 /* left AUX2 input control */ +#define CS4231_AUX2_RIGHT_INPUT 0x05 /* right AUX2 input control */ +#define CS4231_LEFT_OUTPUT 0x06 /* left output control register */ +#define CS4231_RIGHT_OUTPUT 0x07 /* right output control register */ +#define CS4231_PLAYBK_FORMAT 0x08 /* clock and data format - playback - bits 7-0 MCE */ +#define CS4231_IFACE_CTRL 0x09 /* interface control - bits 7-2 MCE */ +#define CS4231_PIN_CTRL 0x0a /* pin control */ +#define CS4231_TEST_INIT 0x0b /* test and initialization */ +#define CS4231_MISC_INFO 0x0c /* miscellaneous information */ +#define CS4231_LOOPBACK 0x0d /* loopback control */ +#define CS4231_PLY_UPR_CNT 0x0e /* playback upper base count */ +#define CS4231_PLY_LWR_CNT 0x0f /* playback lower base count */ +#define CS4231_ALT_FEATURE_1 0x10 /* alternate #1 feature enable */ +#define AD1845_AF1_MIC_LEFT 0x10 /* alternate #1 feature + MIC left */ +#define CS4231_ALT_FEATURE_2 0x11 /* alternate #2 feature enable */ +#define AD1845_AF2_MIC_RIGHT 0x11 /* alternate #2 feature + MIC right */ +#define CS4231_LEFT_LINE_IN 0x12 /* left line input control */ +#define CS4231_RIGHT_LINE_IN 0x13 /* right line input control */ +#define CS4231_TIMER_LOW 0x14 /* timer low byte */ +#define CS4231_TIMER_HIGH 0x15 /* timer high byte */ +#define CS4231_LEFT_MIC_INPUT 0x16 /* left MIC input control register (InterWave only) */ +#define AD1845_UPR_FREQ_SEL 0x16 /* upper byte of frequency select */ +#define CS4231_RIGHT_MIC_INPUT 0x17 /* right MIC input control register (InterWave only) */ +#define AD1845_LWR_FREQ_SEL 0x17 /* lower byte of frequency select */ +#define CS4236_EXT_REG 0x17 /* extended register access */ +#define CS4231_IRQ_STATUS 0x18 /* irq status register */ +#define CS4231_LINE_LEFT_OUTPUT 0x19 /* left line output control register (InterWave only) */ +#define CS4231_VERSION 0x19 /* CS4231(A) - version values */ +#define CS4231_MONO_CTRL 0x1a /* mono input/output control */ +#define CS4231_LINE_RIGHT_OUTPUT 0x1b /* right line output control register (InterWave only) */ +#define AD1845_PWR_DOWN 0x1b /* power down control */ +#define CS4235_LEFT_MASTER 0x1b /* left master output control */ +#define CS4231_REC_FORMAT 0x1c /* clock and data format - record - bits 7-0 MCE */ +#define AD1845_CLOCK 0x1d /* crystal clock select and total power down */ +#define CS4235_RIGHT_MASTER 0x1d /* right master output control */ +#define CS4231_REC_UPR_CNT 0x1e /* record upper count */ +#define CS4231_REC_LWR_CNT 0x1f /* record lower count */ + +/* definitions for codec register select port - CODECP( REGSEL ) */ + +#define CS4231_INIT 0x80 /* CODEC is initializing */ +#define CS4231_MCE 0x40 /* mode change enable */ +#define CS4231_TRD 0x20 /* transfer request disable */ + +/* definitions for codec status register - CODECP( STATUS ) */ + +#define CS4231_GLOBALIRQ 0x01 /* IRQ is active */ + +/* definitions for codec irq status */ + +#define CS4231_PLAYBACK_IRQ 0x10 +#define CS4231_RECORD_IRQ 0x20 +#define CS4231_TIMER_IRQ 0x40 +#define CS4231_ALL_IRQS 0x70 +#define CS4231_REC_UNDERRUN 0x08 +#define CS4231_REC_OVERRUN 0x04 +#define CS4231_PLY_OVERRUN 0x02 +#define CS4231_PLY_UNDERRUN 0x01 + +/* definitions for CS4231_LEFT_INPUT and CS4231_RIGHT_INPUT registers */ + +#define CS4231_ENABLE_MIC_GAIN 0x20 + +#define CS4231_MIXS_LINE 0x00 +#define CS4231_MIXS_AUX1 0x40 +#define CS4231_MIXS_MIC 0x80 +#define CS4231_MIXS_ALL 0xc0 + +/* definitions for clock and data format register - CS4231_PLAYBK_FORMAT */ + +#define CS4231_LINEAR_8 0x00 /* 8-bit unsigned data */ +#define CS4231_ALAW_8 0x60 /* 8-bit A-law companded */ +#define CS4231_ULAW_8 0x20 /* 8-bit U-law companded */ +#define CS4231_LINEAR_16 0x40 /* 16-bit twos complement data - little endian */ +#define CS4231_LINEAR_16_BIG 0xc0 /* 16-bit twos complement data - big endian */ +#define CS4231_ADPCM_16 0xa0 /* 16-bit ADPCM */ +#define CS4231_STEREO 0x10 /* stereo mode */ +/* bits 3-1 define frequency divisor */ +#define CS4231_XTAL1 0x00 /* 24.576 crystal */ +#define CS4231_XTAL2 0x01 /* 16.9344 crystal */ + +/* definitions for interface control register - CS4231_IFACE_CTRL */ + +#define CS4231_RECORD_PIO 0x80 /* record PIO enable */ +#define CS4231_PLAYBACK_PIO 0x40 /* playback PIO enable */ +#define CS4231_CALIB_MODE 0x18 /* calibration mode bits */ +#define CS4231_AUTOCALIB 0x08 /* auto calibrate */ +#define CS4231_SINGLE_DMA 0x04 /* use single DMA channel */ +#define CS4231_RECORD_ENABLE 0x02 /* record enable */ +#define CS4231_PLAYBACK_ENABLE 0x01 /* playback enable */ + +/* definitions for pin control register - CS4231_PIN_CTRL */ + +#define CS4231_IRQ_ENABLE 0x02 /* enable IRQ */ +#define CS4231_XCTL1 0x40 /* external control #1 */ +#define CS4231_XCTL0 0x80 /* external control #0 */ + +/* definitions for test and init register - CS4231_TEST_INIT */ + +#define CS4231_CALIB_IN_PROGRESS 0x20 /* auto calibrate in progress */ +#define CS4231_DMA_REQUEST 0x10 /* DMA request in progress */ + +/* definitions for misc control register - CS4231_MISC_INFO */ + +#define CS4231_MODE2 0x40 /* MODE 2 */ +#define CS4231_IW_MODE3 0x6c /* MODE 3 - InterWave enhanced mode */ +#define CS4231_4236_MODE3 0xe0 /* MODE 3 - CS4236+ enhanced mode */ + +/* definitions for alternate feature 1 register - CS4231_ALT_FEATURE_1 */ + +#define CS4231_DACZ 0x01 /* zero DAC when underrun */ +#define CS4231_TIMER_ENABLE 0x40 /* codec timer enable */ +#define CS4231_OLB 0x80 /* output level bit */ + +/* definitions for Extended Registers - CS4236+ */ + +#define CS4236_REG(i23val) (((i23val << 2) & 0x10) | ((i23val >> 4) & 0x0f)) +#define CS4236_I23VAL(reg) ((((reg)&0xf) << 4) | (((reg)&0x10) >> 2) | 0x8) + +#define CS4236_LEFT_LINE 0x08 /* left LINE alternate volume */ +#define CS4236_RIGHT_LINE 0x18 /* right LINE alternate volume */ +#define CS4236_LEFT_MIC 0x28 /* left MIC volume */ +#define CS4236_RIGHT_MIC 0x38 /* right MIC volume */ +#define CS4236_LEFT_MIX_CTRL 0x48 /* synthesis and left input mixer control */ +#define CS4236_RIGHT_MIX_CTRL 0x58 /* right input mixer control */ +#define CS4236_LEFT_FM 0x68 /* left FM volume */ +#define CS4236_RIGHT_FM 0x78 /* right FM volume */ +#define CS4236_LEFT_DSP 0x88 /* left DSP serial port volume */ +#define CS4236_RIGHT_DSP 0x98 /* right DSP serial port volume */ +#define CS4236_RIGHT_LOOPBACK 0xa8 /* right loopback monitor volume */ +#define CS4236_DAC_MUTE 0xb8 /* DAC mute and IFSE enable */ +#define CS4236_ADC_RATE 0xc8 /* indenpendent ADC sample frequency */ +#define CS4236_DAC_RATE 0xd8 /* indenpendent DAC sample frequency */ +#define CS4236_LEFT_MASTER 0xe8 /* left master digital audio volume */ +#define CS4236_RIGHT_MASTER 0xf8 /* right master digital audio volume */ +#define CS4236_LEFT_WAVE 0x0c /* left wavetable serial port volume */ +#define CS4236_RIGHT_WAVE 0x1c /* right wavetable serial port volume */ +#define CS4236_VERSION 0x9c /* chip version and ID */ + +/* definitions for extended registers - OPTI93X */ +#define OPTi931_AUX_LEFT_INPUT 0x10 +#define OPTi931_AUX_RIGHT_INPUT 0x11 +#define OPTi93X_MIC_LEFT_INPUT 0x14 +#define OPTi93X_MIC_RIGHT_INPUT 0x15 +#define OPTi93X_OUT_LEFT 0x16 +#define OPTi93X_OUT_RIGHT 0x17 + +#endif /* __SOUND_CS4231_REGS_H */ diff --git a/include/sound/cs4271.h b/include/sound/cs4271.h new file mode 100644 index 000000000..6ff23ab48 --- /dev/null +++ b/include/sound/cs4271.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Definitions for CS4271 ASoC codec driver + * + * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru> + */ + +#ifndef __CS4271_H +#define __CS4271_H + +struct cs4271_platform_data { + int gpio_nreset; /* GPIO driving Reset pin, if any */ + bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */ + + /* + * The CS4271 requires its LRCLK and MCLK to be stable before its RESET + * line is de-asserted. That also means that clocks cannot be changed + * without putting the chip back into hardware reset, which also requires + * a complete re-initialization of all registers. + * + * One (undocumented) workaround is to assert and de-assert the PDN bit + * in the MODE2 register. This workaround can be enabled with the + * following flag. + * + * Note that this is not needed in case the clocks are stable + * throughout the entire runtime of the codec. + */ + bool enable_soft_reset; +}; + +#endif /* __CS4271_H */ diff --git a/include/sound/cs42l42.h b/include/sound/cs42l42.h new file mode 100644 index 000000000..1d1c24fdd --- /dev/null +++ b/include/sound/cs42l42.h @@ -0,0 +1,811 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/cs42l42.h -- Platform data for CS42L42 ALSA SoC audio driver header + * + * Copyright 2016-2022 Cirrus Logic, Inc. + * + * Author: James Schulman <james.schulman@cirrus.com> + * Author: Brian Austin <brian.austin@cirrus.com> + * Author: Michael White <michael.white@cirrus.com> + */ + +#ifndef __CS42L42_H +#define __CS42L42_H + +#define CS42L42_PAGE_REGISTER 0x00 /* Page Select Register */ +#define CS42L42_WIN_START 0x00 +#define CS42L42_WIN_LEN 0x100 +#define CS42L42_RANGE_MIN 0x00 +#define CS42L42_RANGE_MAX 0x7F + +#define CS42L42_PAGE_10 0x1000 +#define CS42L42_PAGE_11 0x1100 +#define CS42L42_PAGE_12 0x1200 +#define CS42L42_PAGE_13 0x1300 +#define CS42L42_PAGE_15 0x1500 +#define CS42L42_PAGE_19 0x1900 +#define CS42L42_PAGE_1B 0x1B00 +#define CS42L42_PAGE_1C 0x1C00 +#define CS42L42_PAGE_1D 0x1D00 +#define CS42L42_PAGE_1F 0x1F00 +#define CS42L42_PAGE_20 0x2000 +#define CS42L42_PAGE_21 0x2100 +#define CS42L42_PAGE_23 0x2300 +#define CS42L42_PAGE_24 0x2400 +#define CS42L42_PAGE_25 0x2500 +#define CS42L42_PAGE_26 0x2600 +#define CS42L42_PAGE_28 0x2800 +#define CS42L42_PAGE_29 0x2900 +#define CS42L42_PAGE_2A 0x2A00 +#define CS42L42_PAGE_30 0x3000 + +#define CS42L42_CHIP_ID 0x42A42 +#define CS42L83_CHIP_ID 0x42A83 + +/* Page 0x10 Global Registers */ +#define CS42L42_DEVID_AB (CS42L42_PAGE_10 + 0x01) +#define CS42L42_DEVID_CD (CS42L42_PAGE_10 + 0x02) +#define CS42L42_DEVID_E (CS42L42_PAGE_10 + 0x03) +#define CS42L42_FABID (CS42L42_PAGE_10 + 0x04) +#define CS42L42_REVID (CS42L42_PAGE_10 + 0x05) +#define CS42L42_FRZ_CTL (CS42L42_PAGE_10 + 0x06) + +#define CS42L42_SRC_CTL (CS42L42_PAGE_10 + 0x07) +#define CS42L42_SRC_BYPASS_DAC_SHIFT 1 +#define CS42L42_SRC_BYPASS_DAC_MASK (1 << CS42L42_SRC_BYPASS_DAC_SHIFT) + +#define CS42L42_MCLK_STATUS (CS42L42_PAGE_10 + 0x08) + +#define CS42L42_MCLK_CTL (CS42L42_PAGE_10 + 0x09) +#define CS42L42_INTERNAL_FS_SHIFT 1 +#define CS42L42_INTERNAL_FS_MASK (1 << CS42L42_INTERNAL_FS_SHIFT) + +#define CS42L42_SFTRAMP_RATE (CS42L42_PAGE_10 + 0x0A) +#define CS42L42_SLOW_START_ENABLE (CS42L42_PAGE_10 + 0x0B) +#define CS42L42_SLOW_START_EN_MASK GENMASK(6, 4) +#define CS42L42_SLOW_START_EN_SHIFT 4 +#define CS42L42_I2C_DEBOUNCE (CS42L42_PAGE_10 + 0x0E) +#define CS42L42_I2C_STRETCH (CS42L42_PAGE_10 + 0x0F) +#define CS42L42_I2C_TIMEOUT (CS42L42_PAGE_10 + 0x10) + +/* Page 0x11 Power and Headset Detect Registers */ +#define CS42L42_PWR_CTL1 (CS42L42_PAGE_11 + 0x01) +#define CS42L42_ASP_DAO_PDN_SHIFT 7 +#define CS42L42_ASP_DAO_PDN_MASK (1 << CS42L42_ASP_DAO_PDN_SHIFT) +#define CS42L42_ASP_DAI_PDN_SHIFT 6 +#define CS42L42_ASP_DAI_PDN_MASK (1 << CS42L42_ASP_DAI_PDN_SHIFT) +#define CS42L42_MIXER_PDN_SHIFT 5 +#define CS42L42_MIXER_PDN_MASK (1 << CS42L42_MIXER_PDN_SHIFT) +#define CS42L42_EQ_PDN_SHIFT 4 +#define CS42L42_EQ_PDN_MASK (1 << CS42L42_EQ_PDN_SHIFT) +#define CS42L42_HP_PDN_SHIFT 3 +#define CS42L42_HP_PDN_MASK (1 << CS42L42_HP_PDN_SHIFT) +#define CS42L42_ADC_PDN_SHIFT 2 +#define CS42L42_ADC_PDN_MASK (1 << CS42L42_ADC_PDN_SHIFT) +#define CS42L42_PDN_ALL_SHIFT 0 +#define CS42L42_PDN_ALL_MASK (1 << CS42L42_PDN_ALL_SHIFT) + +#define CS42L42_PWR_CTL2 (CS42L42_PAGE_11 + 0x02) +#define CS42L42_ADC_SRC_PDNB_SHIFT 0 +#define CS42L42_ADC_SRC_PDNB_MASK (1 << CS42L42_ADC_SRC_PDNB_SHIFT) +#define CS42L42_DAC_SRC_PDNB_SHIFT 1 +#define CS42L42_DAC_SRC_PDNB_MASK (1 << CS42L42_DAC_SRC_PDNB_SHIFT) +#define CS42L42_ASP_DAI1_PDN_SHIFT 2 +#define CS42L42_ASP_DAI1_PDN_MASK (1 << CS42L42_ASP_DAI1_PDN_SHIFT) +#define CS42L42_SRC_PDN_OVERRIDE_SHIFT 3 +#define CS42L42_SRC_PDN_OVERRIDE_MASK (1 << CS42L42_SRC_PDN_OVERRIDE_SHIFT) +#define CS42L42_DISCHARGE_FILT_SHIFT 4 +#define CS42L42_DISCHARGE_FILT_MASK (1 << CS42L42_DISCHARGE_FILT_SHIFT) + +#define CS42L42_PWR_CTL3 (CS42L42_PAGE_11 + 0x03) +#define CS42L42_RING_SENSE_PDNB_SHIFT 1 +#define CS42L42_RING_SENSE_PDNB_MASK (1 << CS42L42_RING_SENSE_PDNB_SHIFT) +#define CS42L42_VPMON_PDNB_SHIFT 2 +#define CS42L42_VPMON_PDNB_MASK (1 << CS42L42_VPMON_PDNB_SHIFT) +#define CS42L42_SW_CLK_STP_STAT_SEL_SHIFT 5 +#define CS42L42_SW_CLK_STP_STAT_SEL_MASK (3 << CS42L42_SW_CLK_STP_STAT_SEL_SHIFT) + +#define CS42L42_RSENSE_CTL1 (CS42L42_PAGE_11 + 0x04) +#define CS42L42_RS_TRIM_R_SHIFT 0 +#define CS42L42_RS_TRIM_R_MASK (1 << CS42L42_RS_TRIM_R_SHIFT) +#define CS42L42_RS_TRIM_T_SHIFT 1 +#define CS42L42_RS_TRIM_T_MASK (1 << CS42L42_RS_TRIM_T_SHIFT) +#define CS42L42_HPREF_RS_SHIFT 2 +#define CS42L42_HPREF_RS_MASK (1 << CS42L42_HPREF_RS_SHIFT) +#define CS42L42_HSBIAS_FILT_REF_RS_SHIFT 3 +#define CS42L42_HSBIAS_FILT_REF_RS_MASK (1 << CS42L42_HSBIAS_FILT_REF_RS_SHIFT) +#define CS42L42_RING_SENSE_PU_HIZ_SHIFT 6 +#define CS42L42_RING_SENSE_PU_HIZ_MASK (1 << CS42L42_RING_SENSE_PU_HIZ_SHIFT) + +#define CS42L42_RSENSE_CTL2 (CS42L42_PAGE_11 + 0x05) +#define CS42L42_TS_RS_GATE_SHIFT 7 +#define CS42L42_TS_RS_GATE_MAS (1 << CS42L42_TS_RS_GATE_SHIFT) + +#define CS42L42_OSC_SWITCH (CS42L42_PAGE_11 + 0x07) +#define CS42L42_SCLK_PRESENT_SHIFT 0 +#define CS42L42_SCLK_PRESENT_MASK (1 << CS42L42_SCLK_PRESENT_SHIFT) + +#define CS42L42_OSC_SWITCH_STATUS (CS42L42_PAGE_11 + 0x09) +#define CS42L42_OSC_SW_SEL_STAT_SHIFT 0 +#define CS42L42_OSC_SW_SEL_STAT_MASK (3 << CS42L42_OSC_SW_SEL_STAT_SHIFT) +#define CS42L42_OSC_PDNB_STAT_SHIFT 2 +#define CS42L42_OSC_PDNB_STAT_MASK (1 << CS42L42_OSC_SW_SEL_STAT_SHIFT) + +#define CS42L42_RSENSE_CTL3 (CS42L42_PAGE_11 + 0x12) +#define CS42L42_RS_RISE_DBNCE_TIME_SHIFT 0 +#define CS42L42_RS_RISE_DBNCE_TIME_MASK (7 << CS42L42_RS_RISE_DBNCE_TIME_SHIFT) +#define CS42L42_RS_FALL_DBNCE_TIME_SHIFT 3 +#define CS42L42_RS_FALL_DBNCE_TIME_MASK (7 << CS42L42_RS_FALL_DBNCE_TIME_SHIFT) +#define CS42L42_RS_PU_EN_SHIFT 6 +#define CS42L42_RS_PU_EN_MASK (1 << CS42L42_RS_PU_EN_SHIFT) +#define CS42L42_RS_INV_SHIFT 7 +#define CS42L42_RS_INV_MASK (1 << CS42L42_RS_INV_SHIFT) + +#define CS42L42_TSENSE_CTL (CS42L42_PAGE_11 + 0x13) +#define CS42L42_TS_RISE_DBNCE_TIME_SHIFT 0 +#define CS42L42_TS_RISE_DBNCE_TIME_MASK (7 << CS42L42_TS_RISE_DBNCE_TIME_SHIFT) +#define CS42L42_TS_FALL_DBNCE_TIME_SHIFT 3 +#define CS42L42_TS_FALL_DBNCE_TIME_MASK (7 << CS42L42_TS_FALL_DBNCE_TIME_SHIFT) +#define CS42L42_TS_INV_SHIFT 7 +#define CS42L42_TS_INV_MASK (1 << CS42L42_TS_INV_SHIFT) + +#define CS42L42_TSRS_INT_DISABLE (CS42L42_PAGE_11 + 0x14) +#define CS42L42_D_RS_PLUG_DBNC_SHIFT 0 +#define CS42L42_D_RS_PLUG_DBNC_MASK (1 << CS42L42_D_RS_PLUG_DBNC_SHIFT) +#define CS42L42_D_RS_UNPLUG_DBNC_SHIFT 1 +#define CS42L42_D_RS_UNPLUG_DBNC_MASK (1 << CS42L42_D_RS_UNPLUG_DBNC_SHIFT) +#define CS42L42_D_TS_PLUG_DBNC_SHIFT 2 +#define CS42L42_D_TS_PLUG_DBNC_MASK (1 << CS42L42_D_TS_PLUG_DBNC_SHIFT) +#define CS42L42_D_TS_UNPLUG_DBNC_SHIFT 3 +#define CS42L42_D_TS_UNPLUG_DBNC_MASK (1 << CS42L42_D_TS_UNPLUG_DBNC_SHIFT) + +#define CS42L42_TRSENSE_STATUS (CS42L42_PAGE_11 + 0x15) +#define CS42L42_RS_PLUG_DBNC_SHIFT 0 +#define CS42L42_RS_PLUG_DBNC_MASK (1 << CS42L42_RS_PLUG_DBNC_SHIFT) +#define CS42L42_RS_UNPLUG_DBNC_SHIFT 1 +#define CS42L42_RS_UNPLUG_DBNC_MASK (1 << CS42L42_RS_UNPLUG_DBNC_SHIFT) +#define CS42L42_TS_PLUG_DBNC_SHIFT 2 +#define CS42L42_TS_PLUG_DBNC_MASK (1 << CS42L42_TS_PLUG_DBNC_SHIFT) +#define CS42L42_TS_UNPLUG_DBNC_SHIFT 3 +#define CS42L42_TS_UNPLUG_DBNC_MASK (1 << CS42L42_TS_UNPLUG_DBNC_SHIFT) + +#define CS42L42_HSDET_CTL1 (CS42L42_PAGE_11 + 0x1F) +#define CS42L42_HSDET_COMP1_LVL_SHIFT 0 +#define CS42L42_HSDET_COMP1_LVL_MASK (15 << CS42L42_HSDET_COMP1_LVL_SHIFT) +#define CS42L42_HSDET_COMP2_LVL_SHIFT 4 +#define CS42L42_HSDET_COMP2_LVL_MASK (15 << CS42L42_HSDET_COMP2_LVL_SHIFT) + +#define CS42L42_HSDET_COMP1_LVL_VAL 12 /* 1.25V Comparator */ +#define CS42L42_HSDET_COMP2_LVL_VAL 2 /* 1.75V Comparator */ +#define CS42L42_HSDET_COMP1_LVL_DEFAULT 7 /* 1V Comparator */ +#define CS42L42_HSDET_COMP2_LVL_DEFAULT 7 /* 2V Comparator */ + +#define CS42L42_HSDET_CTL2 (CS42L42_PAGE_11 + 0x20) +#define CS42L42_HSDET_AUTO_TIME_SHIFT 0 +#define CS42L42_HSDET_AUTO_TIME_MASK (3 << CS42L42_HSDET_AUTO_TIME_SHIFT) +#define CS42L42_HSBIAS_REF_SHIFT 3 +#define CS42L42_HSBIAS_REF_MASK (1 << CS42L42_HSBIAS_REF_SHIFT) +#define CS42L42_HSDET_SET_SHIFT 4 +#define CS42L42_HSDET_SET_MASK (3 << CS42L42_HSDET_SET_SHIFT) +#define CS42L42_HSDET_CTRL_SHIFT 6 +#define CS42L42_HSDET_CTRL_MASK (3 << CS42L42_HSDET_CTRL_SHIFT) + +#define CS42L42_HS_SWITCH_CTL (CS42L42_PAGE_11 + 0x21) +#define CS42L42_SW_GNDHS_HS4_SHIFT 0 +#define CS42L42_SW_GNDHS_HS4_MASK (1 << CS42L42_SW_GNDHS_HS4_SHIFT) +#define CS42L42_SW_GNDHS_HS3_SHIFT 1 +#define CS42L42_SW_GNDHS_HS3_MASK (1 << CS42L42_SW_GNDHS_HS3_SHIFT) +#define CS42L42_SW_HSB_HS4_SHIFT 2 +#define CS42L42_SW_HSB_HS4_MASK (1 << CS42L42_SW_HSB_HS4_SHIFT) +#define CS42L42_SW_HSB_HS3_SHIFT 3 +#define CS42L42_SW_HSB_HS3_MASK (1 << CS42L42_SW_HSB_HS3_SHIFT) +#define CS42L42_SW_HSB_FILT_HS4_SHIFT 4 +#define CS42L42_SW_HSB_FILT_HS4_MASK (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) +#define CS42L42_SW_HSB_FILT_HS3_SHIFT 5 +#define CS42L42_SW_HSB_FILT_HS3_MASK (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) +#define CS42L42_SW_REF_HS4_SHIFT 6 +#define CS42L42_SW_REF_HS4_MASK (1 << CS42L42_SW_REF_HS4_SHIFT) +#define CS42L42_SW_REF_HS3_SHIFT 7 +#define CS42L42_SW_REF_HS3_MASK (1 << CS42L42_SW_REF_HS3_SHIFT) + +#define CS42L42_HS_DET_STATUS (CS42L42_PAGE_11 + 0x24) +#define CS42L42_HSDET_TYPE_SHIFT 0 +#define CS42L42_HSDET_TYPE_MASK (3 << CS42L42_HSDET_TYPE_SHIFT) +#define CS42L42_HSDET_COMP1_OUT_SHIFT 6 +#define CS42L42_HSDET_COMP1_OUT_MASK (1 << CS42L42_HSDET_COMP1_OUT_SHIFT) +#define CS42L42_HSDET_COMP2_OUT_SHIFT 7 +#define CS42L42_HSDET_COMP2_OUT_MASK (1 << CS42L42_HSDET_COMP2_OUT_SHIFT) +#define CS42L42_PLUG_CTIA 0 +#define CS42L42_PLUG_OMTP 1 +#define CS42L42_PLUG_HEADPHONE 2 +#define CS42L42_PLUG_INVALID 3 + +#define CS42L42_HSDET_SW_COMP1 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ + (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ + (1 << CS42L42_SW_HSB_HS4_SHIFT) | \ + (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ + (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ + (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ + (0 << CS42L42_SW_REF_HS4_SHIFT) | \ + (1 << CS42L42_SW_REF_HS3_SHIFT)) +#define CS42L42_HSDET_SW_COMP2 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ + (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ + (0 << CS42L42_SW_HSB_HS4_SHIFT) | \ + (1 << CS42L42_SW_HSB_HS3_SHIFT) | \ + (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ + (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ + (1 << CS42L42_SW_REF_HS4_SHIFT) | \ + (0 << CS42L42_SW_REF_HS3_SHIFT)) +#define CS42L42_HSDET_SW_TYPE1 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ + (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ + (1 << CS42L42_SW_HSB_HS4_SHIFT) | \ + (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ + (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ + (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ + (0 << CS42L42_SW_REF_HS4_SHIFT) | \ + (1 << CS42L42_SW_REF_HS3_SHIFT)) +#define CS42L42_HSDET_SW_TYPE2 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ + (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ + (0 << CS42L42_SW_HSB_HS4_SHIFT) | \ + (1 << CS42L42_SW_HSB_HS3_SHIFT) | \ + (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ + (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ + (1 << CS42L42_SW_REF_HS4_SHIFT) | \ + (0 << CS42L42_SW_REF_HS3_SHIFT)) +#define CS42L42_HSDET_SW_TYPE3 ((1 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ + (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ + (0 << CS42L42_SW_HSB_HS4_SHIFT) | \ + (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ + (1 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ + (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ + (1 << CS42L42_SW_REF_HS4_SHIFT) | \ + (1 << CS42L42_SW_REF_HS3_SHIFT)) +#define CS42L42_HSDET_SW_TYPE4 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \ + (1 << CS42L42_SW_GNDHS_HS3_SHIFT) | \ + (1 << CS42L42_SW_HSB_HS4_SHIFT) | \ + (0 << CS42L42_SW_HSB_HS3_SHIFT) | \ + (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \ + (1 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \ + (0 << CS42L42_SW_REF_HS4_SHIFT) | \ + (1 << CS42L42_SW_REF_HS3_SHIFT)) + +#define CS42L42_HSDET_COMP_TYPE1 1 +#define CS42L42_HSDET_COMP_TYPE2 2 +#define CS42L42_HSDET_COMP_TYPE3 0 +#define CS42L42_HSDET_COMP_TYPE4 3 + +#define CS42L42_HS_CLAMP_DISABLE (CS42L42_PAGE_11 + 0x29) +#define CS42L42_HS_CLAMP_DISABLE_SHIFT 0 +#define CS42L42_HS_CLAMP_DISABLE_MASK (1 << CS42L42_HS_CLAMP_DISABLE_SHIFT) + +/* Page 0x12 Clocking Registers */ +#define CS42L42_MCLK_SRC_SEL (CS42L42_PAGE_12 + 0x01) +#define CS42L42_MCLKDIV_SHIFT 1 +#define CS42L42_MCLKDIV_MASK (1 << CS42L42_MCLKDIV_SHIFT) +#define CS42L42_MCLK_SRC_SEL_SHIFT 0 +#define CS42L42_MCLK_SRC_SEL_MASK (1 << CS42L42_MCLK_SRC_SEL_SHIFT) + +#define CS42L42_SPDIF_CLK_CFG (CS42L42_PAGE_12 + 0x02) +#define CS42L42_FSYNC_PW_LOWER (CS42L42_PAGE_12 + 0x03) + +#define CS42L42_FSYNC_PW_UPPER (CS42L42_PAGE_12 + 0x04) +#define CS42L42_FSYNC_PULSE_WIDTH_SHIFT 0 +#define CS42L42_FSYNC_PULSE_WIDTH_MASK (0xff << \ + CS42L42_FSYNC_PULSE_WIDTH_SHIFT) + +#define CS42L42_FSYNC_P_LOWER (CS42L42_PAGE_12 + 0x05) + +#define CS42L42_FSYNC_P_UPPER (CS42L42_PAGE_12 + 0x06) +#define CS42L42_FSYNC_PERIOD_SHIFT 0 +#define CS42L42_FSYNC_PERIOD_MASK (0xff << CS42L42_FSYNC_PERIOD_SHIFT) + +#define CS42L42_ASP_CLK_CFG (CS42L42_PAGE_12 + 0x07) +#define CS42L42_ASP_SCLK_EN_SHIFT 5 +#define CS42L42_ASP_SCLK_EN_MASK (1 << CS42L42_ASP_SCLK_EN_SHIFT) +#define CS42L42_ASP_MASTER_MODE 0x01 +#define CS42L42_ASP_SLAVE_MODE 0x00 +#define CS42L42_ASP_MODE_SHIFT 4 +#define CS42L42_ASP_MODE_MASK (1 << CS42L42_ASP_MODE_SHIFT) +#define CS42L42_ASP_SCPOL_SHIFT 2 +#define CS42L42_ASP_SCPOL_MASK (3 << CS42L42_ASP_SCPOL_SHIFT) +#define CS42L42_ASP_SCPOL_NOR 3 +#define CS42L42_ASP_LCPOL_SHIFT 0 +#define CS42L42_ASP_LCPOL_MASK (3 << CS42L42_ASP_LCPOL_SHIFT) +#define CS42L42_ASP_LCPOL_INV 3 + +#define CS42L42_ASP_FRM_CFG (CS42L42_PAGE_12 + 0x08) +#define CS42L42_ASP_STP_SHIFT 4 +#define CS42L42_ASP_STP_MASK (1 << CS42L42_ASP_STP_SHIFT) +#define CS42L42_ASP_5050_SHIFT 3 +#define CS42L42_ASP_5050_MASK (1 << CS42L42_ASP_5050_SHIFT) +#define CS42L42_ASP_FSD_SHIFT 0 +#define CS42L42_ASP_FSD_MASK (7 << CS42L42_ASP_FSD_SHIFT) +#define CS42L42_ASP_FSD_0_5 1 +#define CS42L42_ASP_FSD_1_0 2 +#define CS42L42_ASP_FSD_1_5 3 +#define CS42L42_ASP_FSD_2_0 4 + +#define CS42L42_FS_RATE_EN (CS42L42_PAGE_12 + 0x09) +#define CS42L42_FS_EN_SHIFT 0 +#define CS42L42_FS_EN_MASK (0xf << CS42L42_FS_EN_SHIFT) +#define CS42L42_FS_EN_IASRC_96K 0x1 +#define CS42L42_FS_EN_OASRC_96K 0x2 + +#define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A) +#define CS42L42_CLK_IASRC_SEL_SHIFT 0 +#define CS42L42_CLK_IASRC_SEL_MASK (1 << CS42L42_CLK_IASRC_SEL_SHIFT) +#define CS42L42_CLK_IASRC_SEL_6 0 +#define CS42L42_CLK_IASRC_SEL_12 1 + +#define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B) +#define CS42L42_CLK_OASRC_SEL_SHIFT 0 +#define CS42L42_CLK_OASRC_SEL_MASK (1 << CS42L42_CLK_OASRC_SEL_SHIFT) +#define CS42L42_CLK_OASRC_SEL_12 1 + +#define CS42L42_PLL_DIV_CFG1 (CS42L42_PAGE_12 + 0x0C) +#define CS42L42_SCLK_PREDIV_SHIFT 0 +#define CS42L42_SCLK_PREDIV_MASK (3 << CS42L42_SCLK_PREDIV_SHIFT) + +/* Page 0x13 Interrupt Registers */ +/* Interrupts */ +#define CS42L42_ADC_OVFL_STATUS (CS42L42_PAGE_13 + 0x01) +#define CS42L42_MIXER_STATUS (CS42L42_PAGE_13 + 0x02) +#define CS42L42_SRC_STATUS (CS42L42_PAGE_13 + 0x03) +#define CS42L42_ASP_RX_STATUS (CS42L42_PAGE_13 + 0x04) +#define CS42L42_ASP_TX_STATUS (CS42L42_PAGE_13 + 0x05) +#define CS42L42_CODEC_STATUS (CS42L42_PAGE_13 + 0x08) +#define CS42L42_DET_INT_STATUS1 (CS42L42_PAGE_13 + 0x09) +#define CS42L42_DET_INT_STATUS2 (CS42L42_PAGE_13 + 0x0A) +#define CS42L42_SRCPL_INT_STATUS (CS42L42_PAGE_13 + 0x0B) +#define CS42L42_VPMON_STATUS (CS42L42_PAGE_13 + 0x0D) +#define CS42L42_PLL_LOCK_STATUS (CS42L42_PAGE_13 + 0x0E) +#define CS42L42_TSRS_PLUG_STATUS (CS42L42_PAGE_13 + 0x0F) +/* Masks */ +#define CS42L42_ADC_OVFL_INT_MASK (CS42L42_PAGE_13 + 0x16) +#define CS42L42_ADC_OVFL_SHIFT 0 +#define CS42L42_ADC_OVFL_MASK (1 << CS42L42_ADC_OVFL_SHIFT) +#define CS42L42_ADC_OVFL_VAL_MASK CS42L42_ADC_OVFL_MASK + +#define CS42L42_MIXER_INT_MASK (CS42L42_PAGE_13 + 0x17) +#define CS42L42_MIX_CHB_OVFL_SHIFT 0 +#define CS42L42_MIX_CHB_OVFL_MASK (1 << CS42L42_MIX_CHB_OVFL_SHIFT) +#define CS42L42_MIX_CHA_OVFL_SHIFT 1 +#define CS42L42_MIX_CHA_OVFL_MASK (1 << CS42L42_MIX_CHA_OVFL_SHIFT) +#define CS42L42_EQ_OVFL_SHIFT 2 +#define CS42L42_EQ_OVFL_MASK (1 << CS42L42_EQ_OVFL_SHIFT) +#define CS42L42_EQ_BIQUAD_OVFL_SHIFT 3 +#define CS42L42_EQ_BIQUAD_OVFL_MASK (1 << CS42L42_EQ_BIQUAD_OVFL_SHIFT) +#define CS42L42_MIXER_VAL_MASK (CS42L42_MIX_CHB_OVFL_MASK | \ + CS42L42_MIX_CHA_OVFL_MASK | \ + CS42L42_EQ_OVFL_MASK | \ + CS42L42_EQ_BIQUAD_OVFL_MASK) + +#define CS42L42_SRC_INT_MASK (CS42L42_PAGE_13 + 0x18) +#define CS42L42_SRC_ILK_SHIFT 0 +#define CS42L42_SRC_ILK_MASK (1 << CS42L42_SRC_ILK_SHIFT) +#define CS42L42_SRC_OLK_SHIFT 1 +#define CS42L42_SRC_OLK_MASK (1 << CS42L42_SRC_OLK_SHIFT) +#define CS42L42_SRC_IUNLK_SHIFT 2 +#define CS42L42_SRC_IUNLK_MASK (1 << CS42L42_SRC_IUNLK_SHIFT) +#define CS42L42_SRC_OUNLK_SHIFT 3 +#define CS42L42_SRC_OUNLK_MASK (1 << CS42L42_SRC_OUNLK_SHIFT) +#define CS42L42_SRC_VAL_MASK (CS42L42_SRC_ILK_MASK | \ + CS42L42_SRC_OLK_MASK | \ + CS42L42_SRC_IUNLK_MASK | \ + CS42L42_SRC_OUNLK_MASK) + +#define CS42L42_ASP_RX_INT_MASK (CS42L42_PAGE_13 + 0x19) +#define CS42L42_ASPRX_NOLRCK_SHIFT 0 +#define CS42L42_ASPRX_NOLRCK_MASK (1 << CS42L42_ASPRX_NOLRCK_SHIFT) +#define CS42L42_ASPRX_EARLY_SHIFT 1 +#define CS42L42_ASPRX_EARLY_MASK (1 << CS42L42_ASPRX_EARLY_SHIFT) +#define CS42L42_ASPRX_LATE_SHIFT 2 +#define CS42L42_ASPRX_LATE_MASK (1 << CS42L42_ASPRX_LATE_SHIFT) +#define CS42L42_ASPRX_ERROR_SHIFT 3 +#define CS42L42_ASPRX_ERROR_MASK (1 << CS42L42_ASPRX_ERROR_SHIFT) +#define CS42L42_ASPRX_OVLD_SHIFT 4 +#define CS42L42_ASPRX_OVLD_MASK (1 << CS42L42_ASPRX_OVLD_SHIFT) +#define CS42L42_ASP_RX_VAL_MASK (CS42L42_ASPRX_NOLRCK_MASK | \ + CS42L42_ASPRX_EARLY_MASK | \ + CS42L42_ASPRX_LATE_MASK | \ + CS42L42_ASPRX_ERROR_MASK | \ + CS42L42_ASPRX_OVLD_MASK) + +#define CS42L42_ASP_TX_INT_MASK (CS42L42_PAGE_13 + 0x1A) +#define CS42L42_ASPTX_NOLRCK_SHIFT 0 +#define CS42L42_ASPTX_NOLRCK_MASK (1 << CS42L42_ASPTX_NOLRCK_SHIFT) +#define CS42L42_ASPTX_EARLY_SHIFT 1 +#define CS42L42_ASPTX_EARLY_MASK (1 << CS42L42_ASPTX_EARLY_SHIFT) +#define CS42L42_ASPTX_LATE_SHIFT 2 +#define CS42L42_ASPTX_LATE_MASK (1 << CS42L42_ASPTX_LATE_SHIFT) +#define CS42L42_ASPTX_SMERROR_SHIFT 3 +#define CS42L42_ASPTX_SMERROR_MASK (1 << CS42L42_ASPTX_SMERROR_SHIFT) +#define CS42L42_ASP_TX_VAL_MASK (CS42L42_ASPTX_NOLRCK_MASK | \ + CS42L42_ASPTX_EARLY_MASK | \ + CS42L42_ASPTX_LATE_MASK | \ + CS42L42_ASPTX_SMERROR_MASK) + +#define CS42L42_CODEC_INT_MASK (CS42L42_PAGE_13 + 0x1B) +#define CS42L42_PDN_DONE_SHIFT 0 +#define CS42L42_PDN_DONE_MASK (1 << CS42L42_PDN_DONE_SHIFT) +#define CS42L42_HSDET_AUTO_DONE_SHIFT 1 +#define CS42L42_HSDET_AUTO_DONE_MASK (1 << CS42L42_HSDET_AUTO_DONE_SHIFT) +#define CS42L42_CODEC_VAL_MASK (CS42L42_PDN_DONE_MASK | \ + CS42L42_HSDET_AUTO_DONE_MASK) + +#define CS42L42_SRCPL_INT_MASK (CS42L42_PAGE_13 + 0x1C) +#define CS42L42_SRCPL_ADC_LK_SHIFT 0 +#define CS42L42_SRCPL_ADC_LK_MASK (1 << CS42L42_SRCPL_ADC_LK_SHIFT) +#define CS42L42_SRCPL_DAC_LK_SHIFT 2 +#define CS42L42_SRCPL_DAC_LK_MASK (1 << CS42L42_SRCPL_DAC_LK_SHIFT) +#define CS42L42_SRCPL_ADC_UNLK_SHIFT 5 +#define CS42L42_SRCPL_ADC_UNLK_MASK (1 << CS42L42_SRCPL_ADC_UNLK_SHIFT) +#define CS42L42_SRCPL_DAC_UNLK_SHIFT 6 +#define CS42L42_SRCPL_DAC_UNLK_MASK (1 << CS42L42_SRCPL_DAC_UNLK_SHIFT) +#define CS42L42_SRCPL_VAL_MASK (CS42L42_SRCPL_ADC_LK_MASK | \ + CS42L42_SRCPL_DAC_LK_MASK | \ + CS42L42_SRCPL_ADC_UNLK_MASK | \ + CS42L42_SRCPL_DAC_UNLK_MASK) + +#define CS42L42_VPMON_INT_MASK (CS42L42_PAGE_13 + 0x1E) +#define CS42L42_VPMON_SHIFT 0 +#define CS42L42_VPMON_MASK (1 << CS42L42_VPMON_SHIFT) +#define CS42L42_VPMON_VAL_MASK CS42L42_VPMON_MASK + +#define CS42L42_PLL_LOCK_INT_MASK (CS42L42_PAGE_13 + 0x1F) +#define CS42L42_PLL_LOCK_SHIFT 0 +#define CS42L42_PLL_LOCK_MASK (1 << CS42L42_PLL_LOCK_SHIFT) +#define CS42L42_PLL_LOCK_VAL_MASK CS42L42_PLL_LOCK_MASK + +#define CS42L42_TSRS_PLUG_INT_MASK (CS42L42_PAGE_13 + 0x20) +#define CS42L42_RS_PLUG_SHIFT 0 +#define CS42L42_RS_PLUG_MASK (1 << CS42L42_RS_PLUG_SHIFT) +#define CS42L42_RS_UNPLUG_SHIFT 1 +#define CS42L42_RS_UNPLUG_MASK (1 << CS42L42_RS_UNPLUG_SHIFT) +#define CS42L42_TS_PLUG_SHIFT 2 +#define CS42L42_TS_PLUG_MASK (1 << CS42L42_TS_PLUG_SHIFT) +#define CS42L42_TS_UNPLUG_SHIFT 3 +#define CS42L42_TS_UNPLUG_MASK (1 << CS42L42_TS_UNPLUG_SHIFT) +#define CS42L42_TSRS_PLUG_VAL_MASK (CS42L42_RS_PLUG_MASK | \ + CS42L42_RS_UNPLUG_MASK | \ + CS42L42_TS_PLUG_MASK | \ + CS42L42_TS_UNPLUG_MASK) +#define CS42L42_TS_PLUG 3 +#define CS42L42_TS_UNPLUG 0 +#define CS42L42_TS_TRANS 1 + +/* + * NOTE: PLL_START must be 0 while both ADC_PDN=1 and HP_PDN=1. + * Otherwise it will prevent FILT+ from charging properly. + */ +#define CS42L42_PLL_CTL1 (CS42L42_PAGE_15 + 0x01) +#define CS42L42_PLL_START_SHIFT 0 +#define CS42L42_PLL_START_MASK (1 << CS42L42_PLL_START_SHIFT) + +#define CS42L42_PLL_DIV_FRAC0 (CS42L42_PAGE_15 + 0x02) +#define CS42L42_PLL_DIV_FRAC_SHIFT 0 +#define CS42L42_PLL_DIV_FRAC_MASK (0xff << CS42L42_PLL_DIV_FRAC_SHIFT) + +#define CS42L42_PLL_DIV_FRAC1 (CS42L42_PAGE_15 + 0x03) +#define CS42L42_PLL_DIV_FRAC2 (CS42L42_PAGE_15 + 0x04) + +#define CS42L42_PLL_DIV_INT (CS42L42_PAGE_15 + 0x05) +#define CS42L42_PLL_DIV_INT_SHIFT 0 +#define CS42L42_PLL_DIV_INT_MASK (0xff << CS42L42_PLL_DIV_INT_SHIFT) + +#define CS42L42_PLL_CTL3 (CS42L42_PAGE_15 + 0x08) +#define CS42L42_PLL_DIVOUT_SHIFT 0 +#define CS42L42_PLL_DIVOUT_MASK (0xff << CS42L42_PLL_DIVOUT_SHIFT) + +#define CS42L42_PLL_CAL_RATIO (CS42L42_PAGE_15 + 0x0A) +#define CS42L42_PLL_CAL_RATIO_SHIFT 0 +#define CS42L42_PLL_CAL_RATIO_MASK (0xff << CS42L42_PLL_CAL_RATIO_SHIFT) + +#define CS42L42_PLL_CTL4 (CS42L42_PAGE_15 + 0x1B) +#define CS42L42_PLL_MODE_SHIFT 0 +#define CS42L42_PLL_MODE_MASK (3 << CS42L42_PLL_MODE_SHIFT) + +/* Page 0x19 HP Load Detect Registers */ +#define CS42L42_LOAD_DET_RCSTAT (CS42L42_PAGE_19 + 0x25) +#define CS42L42_RLA_STAT_SHIFT 0 +#define CS42L42_RLA_STAT_MASK (3 << CS42L42_RLA_STAT_SHIFT) +#define CS42L42_RLA_STAT_15_OHM 0 + +#define CS42L42_LOAD_DET_DONE (CS42L42_PAGE_19 + 0x26) +#define CS42L42_HPLOAD_DET_DONE_SHIFT 0 +#define CS42L42_HPLOAD_DET_DONE_MASK (1 << CS42L42_HPLOAD_DET_DONE_SHIFT) + +#define CS42L42_LOAD_DET_EN (CS42L42_PAGE_19 + 0x27) +#define CS42L42_HP_LD_EN_SHIFT 0 +#define CS42L42_HP_LD_EN_MASK (1 << CS42L42_HP_LD_EN_SHIFT) + +/* Page 0x1B Headset Interface Registers */ +#define CS42L42_HSBIAS_SC_AUTOCTL (CS42L42_PAGE_1B + 0x70) +#define CS42L42_HSBIAS_SENSE_TRIP_SHIFT 0 +#define CS42L42_HSBIAS_SENSE_TRIP_MASK (7 << CS42L42_HSBIAS_SENSE_TRIP_SHIFT) +#define CS42L42_TIP_SENSE_EN_SHIFT 5 +#define CS42L42_TIP_SENSE_EN_MASK (1 << CS42L42_TIP_SENSE_EN_SHIFT) +#define CS42L42_AUTO_HSBIAS_HIZ_SHIFT 6 +#define CS42L42_AUTO_HSBIAS_HIZ_MASK (1 << CS42L42_AUTO_HSBIAS_HIZ_SHIFT) +#define CS42L42_HSBIAS_SENSE_EN_SHIFT 7 +#define CS42L42_HSBIAS_SENSE_EN_MASK (1 << CS42L42_HSBIAS_SENSE_EN_SHIFT) + +#define CS42L42_WAKE_CTL (CS42L42_PAGE_1B + 0x71) +#define CS42L42_WAKEB_CLEAR_SHIFT 0 +#define CS42L42_WAKEB_CLEAR_MASK (1 << CS42L42_WAKEB_CLEAR_SHIFT) +#define CS42L42_WAKEB_MODE_SHIFT 5 +#define CS42L42_WAKEB_MODE_MASK (1 << CS42L42_WAKEB_MODE_SHIFT) +#define CS42L42_M_HP_WAKE_SHIFT 6 +#define CS42L42_M_HP_WAKE_MASK (1 << CS42L42_M_HP_WAKE_SHIFT) +#define CS42L42_M_MIC_WAKE_SHIFT 7 +#define CS42L42_M_MIC_WAKE_MASK (1 << CS42L42_M_MIC_WAKE_SHIFT) + +#define CS42L42_ADC_DISABLE_MUTE (CS42L42_PAGE_1B + 0x72) +#define CS42L42_ADC_DISABLE_S0_MUTE_SHIFT 7 +#define CS42L42_ADC_DISABLE_S0_MUTE_MASK (1 << CS42L42_ADC_DISABLE_S0_MUTE_SHIFT) + +#define CS42L42_TIPSENSE_CTL (CS42L42_PAGE_1B + 0x73) +#define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT 0 +#define CS42L42_TIP_SENSE_DEBOUNCE_MASK (3 << CS42L42_TIP_SENSE_DEBOUNCE_SHIFT) +#define CS42L42_TIP_SENSE_INV_SHIFT 5 +#define CS42L42_TIP_SENSE_INV_MASK (1 << CS42L42_TIP_SENSE_INV_SHIFT) +#define CS42L42_TIP_SENSE_CTRL_SHIFT 6 +#define CS42L42_TIP_SENSE_CTRL_MASK (3 << CS42L42_TIP_SENSE_CTRL_SHIFT) + +/* + * NOTE: DETECT_MODE must be 0 while both ADC_PDN=1 and HP_PDN=1. + * Otherwise it will prevent FILT+ from charging properly. + */ +#define CS42L42_MISC_DET_CTL (CS42L42_PAGE_1B + 0x74) +#define CS42L42_PDN_MIC_LVL_DET_SHIFT 0 +#define CS42L42_PDN_MIC_LVL_DET_MASK (1 << CS42L42_PDN_MIC_LVL_DET_SHIFT) +#define CS42L42_HSBIAS_CTL_SHIFT 1 +#define CS42L42_HSBIAS_CTL_MASK (3 << CS42L42_HSBIAS_CTL_SHIFT) +#define CS42L42_DETECT_MODE_SHIFT 3 +#define CS42L42_DETECT_MODE_MASK (3 << CS42L42_DETECT_MODE_SHIFT) + +#define CS42L42_MIC_DET_CTL1 (CS42L42_PAGE_1B + 0x75) +#define CS42L42_HS_DET_LEVEL_SHIFT 0 +#define CS42L42_HS_DET_LEVEL_MASK (0x3F << CS42L42_HS_DET_LEVEL_SHIFT) +#define CS42L42_EVENT_STAT_SEL_SHIFT 6 +#define CS42L42_EVENT_STAT_SEL_MASK (1 << CS42L42_EVENT_STAT_SEL_SHIFT) +#define CS42L42_LATCH_TO_VP_SHIFT 7 +#define CS42L42_LATCH_TO_VP_MASK (1 << CS42L42_LATCH_TO_VP_SHIFT) + +#define CS42L42_MIC_DET_CTL2 (CS42L42_PAGE_1B + 0x76) +#define CS42L42_DEBOUNCE_TIME_SHIFT 5 +#define CS42L42_DEBOUNCE_TIME_MASK (0x07 << CS42L42_DEBOUNCE_TIME_SHIFT) + +#define CS42L42_DET_STATUS1 (CS42L42_PAGE_1B + 0x77) +#define CS42L42_HSBIAS_HIZ_MODE_SHIFT 6 +#define CS42L42_HSBIAS_HIZ_MODE_MASK (1 << CS42L42_HSBIAS_HIZ_MODE_SHIFT) +#define CS42L42_TIP_SENSE_SHIFT 7 +#define CS42L42_TIP_SENSE_MASK (1 << CS42L42_TIP_SENSE_SHIFT) + +#define CS42L42_DET_STATUS2 (CS42L42_PAGE_1B + 0x78) +#define CS42L42_SHORT_TRUE_SHIFT 0 +#define CS42L42_SHORT_TRUE_MASK (1 << CS42L42_SHORT_TRUE_SHIFT) +#define CS42L42_HS_TRUE_SHIFT 1 +#define CS42L42_HS_TRUE_MASK (1 << CS42L42_HS_TRUE_SHIFT) + +#define CS42L42_DET_INT1_MASK (CS42L42_PAGE_1B + 0x79) +#define CS42L42_TIP_SENSE_UNPLUG_SHIFT 5 +#define CS42L42_TIP_SENSE_UNPLUG_MASK (1 << CS42L42_TIP_SENSE_UNPLUG_SHIFT) +#define CS42L42_TIP_SENSE_PLUG_SHIFT 6 +#define CS42L42_TIP_SENSE_PLUG_MASK (1 << CS42L42_TIP_SENSE_PLUG_SHIFT) +#define CS42L42_HSBIAS_SENSE_SHIFT 7 +#define CS42L42_HSBIAS_SENSE_MASK (1 << CS42L42_HSBIAS_SENSE_SHIFT) +#define CS42L42_DET_INT_VAL1_MASK (CS42L42_TIP_SENSE_UNPLUG_MASK | \ + CS42L42_TIP_SENSE_PLUG_MASK | \ + CS42L42_HSBIAS_SENSE_MASK) + +#define CS42L42_DET_INT2_MASK (CS42L42_PAGE_1B + 0x7A) +#define CS42L42_M_SHORT_DET_SHIFT 0 +#define CS42L42_M_SHORT_DET_MASK (1 << CS42L42_M_SHORT_DET_SHIFT) +#define CS42L42_M_SHORT_RLS_SHIFT 1 +#define CS42L42_M_SHORT_RLS_MASK (1 << CS42L42_M_SHORT_RLS_SHIFT) +#define CS42L42_M_HSBIAS_HIZ_SHIFT 2 +#define CS42L42_M_HSBIAS_HIZ_MASK (1 << CS42L42_M_HSBIAS_HIZ_SHIFT) +#define CS42L42_M_DETECT_FT_SHIFT 6 +#define CS42L42_M_DETECT_FT_MASK (1 << CS42L42_M_DETECT_FT_SHIFT) +#define CS42L42_M_DETECT_TF_SHIFT 7 +#define CS42L42_M_DETECT_TF_MASK (1 << CS42L42_M_DETECT_TF_SHIFT) +#define CS42L42_DET_INT_VAL2_MASK (CS42L42_M_SHORT_DET_MASK | \ + CS42L42_M_SHORT_RLS_MASK | \ + CS42L42_M_HSBIAS_HIZ_MASK | \ + CS42L42_M_DETECT_FT_MASK | \ + CS42L42_M_DETECT_TF_MASK) + +/* Page 0x1C Headset Bias Registers */ +#define CS42L42_HS_BIAS_CTL (CS42L42_PAGE_1C + 0x03) +#define CS42L42_HSBIAS_RAMP_SHIFT 0 +#define CS42L42_HSBIAS_RAMP_MASK (3 << CS42L42_HSBIAS_RAMP_SHIFT) +#define CS42L42_HSBIAS_PD_SHIFT 4 +#define CS42L42_HSBIAS_PD_MASK (1 << CS42L42_HSBIAS_PD_SHIFT) +#define CS42L42_HSBIAS_CAPLESS_SHIFT 7 +#define CS42L42_HSBIAS_CAPLESS_MASK (1 << CS42L42_HSBIAS_CAPLESS_SHIFT) + +/* Page 0x1D ADC Registers */ +#define CS42L42_ADC_CTL (CS42L42_PAGE_1D + 0x01) +#define CS42L42_ADC_NOTCH_DIS_SHIFT 5 +#define CS42L42_ADC_FORCE_WEAK_VCM_SHIFT 4 +#define CS42L42_ADC_INV_SHIFT 2 +#define CS42L42_ADC_DIG_BOOST_SHIFT 0 + +#define CS42L42_ADC_VOLUME (CS42L42_PAGE_1D + 0x03) +#define CS42L42_ADC_VOL_SHIFT 0 + +#define CS42L42_ADC_WNF_HPF_CTL (CS42L42_PAGE_1D + 0x04) +#define CS42L42_ADC_WNF_CF_SHIFT 4 +#define CS42L42_ADC_WNF_EN_SHIFT 3 +#define CS42L42_ADC_HPF_CF_SHIFT 1 +#define CS42L42_ADC_HPF_EN_SHIFT 0 + +/* Page 0x1F DAC Registers */ +#define CS42L42_DAC_CTL1 (CS42L42_PAGE_1F + 0x01) +#define CS42L42_DACB_INV_SHIFT 1 +#define CS42L42_DACA_INV_SHIFT 0 + +#define CS42L42_DAC_CTL2 (CS42L42_PAGE_1F + 0x06) +#define CS42L42_HPOUT_PULLDOWN_SHIFT 4 +#define CS42L42_HPOUT_PULLDOWN_MASK (15 << CS42L42_HPOUT_PULLDOWN_SHIFT) +#define CS42L42_HPOUT_LOAD_SHIFT 3 +#define CS42L42_HPOUT_LOAD_MASK (1 << CS42L42_HPOUT_LOAD_SHIFT) +#define CS42L42_HPOUT_CLAMP_SHIFT 2 +#define CS42L42_HPOUT_CLAMP_MASK (1 << CS42L42_HPOUT_CLAMP_SHIFT) +#define CS42L42_DAC_HPF_EN_SHIFT 1 +#define CS42L42_DAC_HPF_EN_MASK (1 << CS42L42_DAC_HPF_EN_SHIFT) +#define CS42L42_DAC_MON_EN_SHIFT 0 +#define CS42L42_DAC_MON_EN_MASK (1 << CS42L42_DAC_MON_EN_SHIFT) + +/* Page 0x20 HP CTL Registers */ +#define CS42L42_HP_CTL (CS42L42_PAGE_20 + 0x01) +#define CS42L42_HP_ANA_BMUTE_SHIFT 3 +#define CS42L42_HP_ANA_BMUTE_MASK (1 << CS42L42_HP_ANA_BMUTE_SHIFT) +#define CS42L42_HP_ANA_AMUTE_SHIFT 2 +#define CS42L42_HP_ANA_AMUTE_MASK (1 << CS42L42_HP_ANA_AMUTE_SHIFT) +#define CS42L42_HP_FULL_SCALE_VOL_SHIFT 1 +#define CS42L42_HP_FULL_SCALE_VOL_MASK (1 << CS42L42_HP_FULL_SCALE_VOL_SHIFT) + +/* Page 0x21 Class H Registers */ +#define CS42L42_CLASSH_CTL (CS42L42_PAGE_21 + 0x01) + +/* Page 0x23 Mixer Volume Registers */ +#define CS42L42_MIXER_CHA_VOL (CS42L42_PAGE_23 + 0x01) +#define CS42L42_MIXER_ADC_VOL (CS42L42_PAGE_23 + 0x02) + +#define CS42L42_MIXER_CHB_VOL (CS42L42_PAGE_23 + 0x03) +#define CS42L42_MIXER_CH_VOL_SHIFT 0 +#define CS42L42_MIXER_CH_VOL_MASK (0x3f << CS42L42_MIXER_CH_VOL_SHIFT) + +/* Page 0x24 EQ Registers */ +#define CS42L42_EQ_COEF_IN0 (CS42L42_PAGE_24 + 0x01) +#define CS42L42_EQ_COEF_IN1 (CS42L42_PAGE_24 + 0x02) +#define CS42L42_EQ_COEF_IN2 (CS42L42_PAGE_24 + 0x03) +#define CS42L42_EQ_COEF_IN3 (CS42L42_PAGE_24 + 0x04) +#define CS42L42_EQ_COEF_RW (CS42L42_PAGE_24 + 0x06) +#define CS42L42_EQ_COEF_OUT0 (CS42L42_PAGE_24 + 0x07) +#define CS42L42_EQ_COEF_OUT1 (CS42L42_PAGE_24 + 0x08) +#define CS42L42_EQ_COEF_OUT2 (CS42L42_PAGE_24 + 0x09) +#define CS42L42_EQ_COEF_OUT3 (CS42L42_PAGE_24 + 0x0A) +#define CS42L42_EQ_INIT_STAT (CS42L42_PAGE_24 + 0x0B) +#define CS42L42_EQ_START_FILT (CS42L42_PAGE_24 + 0x0C) +#define CS42L42_EQ_MUTE_CTL (CS42L42_PAGE_24 + 0x0E) + +/* Page 0x25 Audio Port Registers */ +#define CS42L42_SP_RX_CH_SEL (CS42L42_PAGE_25 + 0x01) +#define CS42L42_SP_RX_CHB_SEL_SHIFT 2 +#define CS42L42_SP_RX_CHB_SEL_MASK (3 << CS42L42_SP_RX_CHB_SEL_SHIFT) + +#define CS42L42_SP_RX_ISOC_CTL (CS42L42_PAGE_25 + 0x02) +#define CS42L42_SP_RX_RSYNC_SHIFT 6 +#define CS42L42_SP_RX_RSYNC_MASK (1 << CS42L42_SP_RX_RSYNC_SHIFT) +#define CS42L42_SP_RX_NSB_POS_SHIFT 3 +#define CS42L42_SP_RX_NSB_POS_MASK (7 << CS42L42_SP_RX_NSB_POS_SHIFT) +#define CS42L42_SP_RX_NFS_NSBB_SHIFT 2 +#define CS42L42_SP_RX_NFS_NSBB_MASK (1 << CS42L42_SP_RX_NFS_NSBB_SHIFT) +#define CS42L42_SP_RX_ISOC_MODE_SHIFT 0 +#define CS42L42_SP_RX_ISOC_MODE_MASK (3 << CS42L42_SP_RX_ISOC_MODE_SHIFT) + +#define CS42L42_SP_RX_FS (CS42L42_PAGE_25 + 0x03) +#define CS42l42_SPDIF_CH_SEL (CS42L42_PAGE_25 + 0x04) +#define CS42L42_SP_TX_ISOC_CTL (CS42L42_PAGE_25 + 0x05) +#define CS42L42_SP_TX_FS (CS42L42_PAGE_25 + 0x06) +#define CS42L42_SPDIF_SW_CTL1 (CS42L42_PAGE_25 + 0x07) + +/* Page 0x26 SRC Registers */ +#define CS42L42_SRC_SDIN_FS (CS42L42_PAGE_26 + 0x01) +#define CS42L42_SRC_SDIN_FS_SHIFT 0 +#define CS42L42_SRC_SDIN_FS_MASK (0x1f << CS42L42_SRC_SDIN_FS_SHIFT) + +#define CS42L42_SRC_SDOUT_FS (CS42L42_PAGE_26 + 0x09) + +/* Page 0x28 S/PDIF Registers */ +#define CS42L42_SPDIF_CTL1 (CS42L42_PAGE_28 + 0x01) +#define CS42L42_SPDIF_CTL2 (CS42L42_PAGE_28 + 0x02) +#define CS42L42_SPDIF_CTL3 (CS42L42_PAGE_28 + 0x03) +#define CS42L42_SPDIF_CTL4 (CS42L42_PAGE_28 + 0x04) + +/* Page 0x29 Serial Port TX Registers */ +#define CS42L42_ASP_TX_SZ_EN (CS42L42_PAGE_29 + 0x01) +#define CS42L42_ASP_TX_EN_SHIFT 0 +#define CS42L42_ASP_TX_CH_EN (CS42L42_PAGE_29 + 0x02) +#define CS42L42_ASP_TX0_CH2_SHIFT 1 +#define CS42L42_ASP_TX0_CH1_SHIFT 0 + +#define CS42L42_ASP_TX_CH_AP_RES (CS42L42_PAGE_29 + 0x03) +#define CS42L42_ASP_TX_CH1_AP_SHIFT 7 +#define CS42L42_ASP_TX_CH1_AP_MASK (1 << CS42L42_ASP_TX_CH1_AP_SHIFT) +#define CS42L42_ASP_TX_CH2_AP_SHIFT 6 +#define CS42L42_ASP_TX_CH2_AP_MASK (1 << CS42L42_ASP_TX_CH2_AP_SHIFT) +#define CS42L42_ASP_TX_CH2_RES_SHIFT 2 +#define CS42L42_ASP_TX_CH2_RES_MASK (3 << CS42L42_ASP_TX_CH2_RES_SHIFT) +#define CS42L42_ASP_TX_CH1_RES_SHIFT 0 +#define CS42L42_ASP_TX_CH1_RES_MASK (3 << CS42L42_ASP_TX_CH1_RES_SHIFT) +#define CS42L42_ASP_TX_CH1_BIT_MSB (CS42L42_PAGE_29 + 0x04) +#define CS42L42_ASP_TX_CH1_BIT_LSB (CS42L42_PAGE_29 + 0x05) +#define CS42L42_ASP_TX_HIZ_DLY_CFG (CS42L42_PAGE_29 + 0x06) +#define CS42L42_ASP_TX_CH2_BIT_MSB (CS42L42_PAGE_29 + 0x0A) +#define CS42L42_ASP_TX_CH2_BIT_LSB (CS42L42_PAGE_29 + 0x0B) + +/* Page 0x2A Serial Port RX Registers */ +#define CS42L42_ASP_RX_DAI0_EN (CS42L42_PAGE_2A + 0x01) +#define CS42L42_ASP_RX0_CH_EN_SHIFT 2 +#define CS42L42_ASP_RX0_CH_EN_MASK (0xf << CS42L42_ASP_RX0_CH_EN_SHIFT) +#define CS42L42_ASP_RX0_CH1_SHIFT 2 +#define CS42L42_ASP_RX0_CH2_SHIFT 3 +#define CS42L42_ASP_RX0_CH3_SHIFT 4 +#define CS42L42_ASP_RX0_CH4_SHIFT 5 + +#define CS42L42_ASP_RX_DAI0_CH1_AP_RES (CS42L42_PAGE_2A + 0x02) +#define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x03) +#define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x04) +#define CS42L42_ASP_RX_DAI0_CH2_AP_RES (CS42L42_PAGE_2A + 0x05) +#define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x06) +#define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x07) +#define CS42L42_ASP_RX_DAI0_CH3_AP_RES (CS42L42_PAGE_2A + 0x08) +#define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB (CS42L42_PAGE_2A + 0x09) +#define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB (CS42L42_PAGE_2A + 0x0A) +#define CS42L42_ASP_RX_DAI0_CH4_AP_RES (CS42L42_PAGE_2A + 0x0B) +#define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB (CS42L42_PAGE_2A + 0x0C) +#define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB (CS42L42_PAGE_2A + 0x0D) +#define CS42L42_ASP_RX_DAI1_CH1_AP_RES (CS42L42_PAGE_2A + 0x0E) +#define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x0F) +#define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x10) +#define CS42L42_ASP_RX_DAI1_CH2_AP_RES (CS42L42_PAGE_2A + 0x11) +#define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x12) +#define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x13) + +#define CS42L42_ASP_RX_CH_AP_SHIFT 6 +#define CS42L42_ASP_RX_CH_AP_MASK (1 << CS42L42_ASP_RX_CH_AP_SHIFT) +#define CS42L42_ASP_RX_CH_AP_LOW 0 +#define CS42L42_ASP_RX_CH_AP_HI 1 +#define CS42L42_ASP_RX_CH_RES_SHIFT 0 +#define CS42L42_ASP_RX_CH_RES_MASK (3 << CS42L42_ASP_RX_CH_RES_SHIFT) +#define CS42L42_ASP_RX_CH_RES_32 3 +#define CS42L42_ASP_RX_CH_RES_16 1 +#define CS42L42_ASP_RX_CH_BIT_ST_SHIFT 0 +#define CS42L42_ASP_RX_CH_BIT_ST_MASK (0xff << CS42L42_ASP_RX_CH_BIT_ST_SHIFT) + +/* Page 0x30 ID Registers */ +#define CS42L42_SUB_REVID (CS42L42_PAGE_30 + 0x14) +#define CS42L42_MAX_REGISTER (CS42L42_PAGE_30 + 0x14) + +/* Defines for fracturing values spread across multiple registers */ +#define CS42L42_FRAC0_VAL(val) ((val) & 0x0000ff) +#define CS42L42_FRAC1_VAL(val) (((val) & 0x00ff00) >> 8) +#define CS42L42_FRAC2_VAL(val) (((val) & 0xff0000) >> 16) + +#define CS42L42_NUM_SUPPLIES 5 +#define CS42L42_BOOT_TIME_US 3000 +#define CS42L42_PLL_DIVOUT_TIME_US 800 +#define CS42L42_CLOCK_SWITCH_DELAY_US 150 +#define CS42L42_PLL_LOCK_POLL_US 250 +#define CS42L42_PLL_LOCK_TIMEOUT_US 1250 +#define CS42L42_HP_ADC_EN_TIME_US 20000 +#define CS42L42_PDN_DONE_POLL_US 1000 +#define CS42L42_PDN_DONE_TIMEOUT_US 200000 +#define CS42L42_PDN_DONE_TIME_MS 100 +#define CS42L42_FILT_DISCHARGE_TIME_MS 46 + +#endif /* __CS42L42_H */ diff --git a/include/sound/cs42l52.h b/include/sound/cs42l52.h new file mode 100644 index 000000000..c20649666 --- /dev/null +++ b/include/sound/cs42l52.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/cs42l52.h -- Platform data for CS42L52 + * + * Copyright (c) 2012 Cirrus Logic Inc. + */ + +#ifndef __CS42L52_H +#define __CS42L52_H + +struct cs42l52_platform_data { + + /* MICBIAS Level. Check datasheet Pg48 */ + unsigned int micbias_lvl; + + /* MICA mode selection Differential or Single-ended */ + bool mica_diff_cfg; + + /* MICB mode selection Differential or Single-ended */ + bool micb_diff_cfg; + + /* Charge Pump Freq. Check datasheet Pg73 */ + unsigned int chgfreq; + + /* Reset GPIO */ + unsigned int reset_gpio; +}; + +#endif /* __CS42L52_H */ diff --git a/include/sound/cs42l56.h b/include/sound/cs42l56.h new file mode 100644 index 000000000..62e9f7a3b --- /dev/null +++ b/include/sound/cs42l56.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/cs42l56.h -- Platform data for CS42L56 + * + * Copyright (c) 2014 Cirrus Logic Inc. + */ + +#ifndef __CS42L56_H +#define __CS42L56_H + +struct cs42l56_platform_data { + + /* GPIO for Reset */ + unsigned int gpio_nreset; + + /* MICBIAS Level. Check datasheet Pg48 */ + unsigned int micbias_lvl; + + /* Analog Input 1A Reference 0=Single 1=Pseudo-Differential */ + unsigned int ain1a_ref_cfg; + + /* Analog Input 2A Reference 0=Single 1=Pseudo-Differential */ + unsigned int ain2a_ref_cfg; + + /* Analog Input 1B Reference 0=Single 1=Pseudo-Differential */ + unsigned int ain1b_ref_cfg; + + /* Analog Input 2B Reference 0=Single 1=Pseudo-Differential */ + unsigned int ain2b_ref_cfg; + + /* Charge Pump Freq. Check datasheet Pg62 */ + unsigned int chgfreq; + + /* HighPass Filter Right Channel Corner Frequency */ + unsigned int hpfb_freq; + + /* HighPass Filter Left Channel Corner Frequency */ + unsigned int hpfa_freq; + + /* Adaptive Power Control for LO/HP */ + unsigned int adaptive_pwr; + +}; + +#endif /* __CS42L56_H */ diff --git a/include/sound/cs42l73.h b/include/sound/cs42l73.h new file mode 100644 index 000000000..5a93393b6 --- /dev/null +++ b/include/sound/cs42l73.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/cs42l73.h -- Platform data for CS42L73 + * + * Copyright (c) 2012 Cirrus Logic Inc. + */ + +#ifndef __CS42L73_H +#define __CS42L73_H + +struct cs42l73_platform_data { + /* RST GPIO */ + unsigned int reset_gpio; + unsigned int chgfreq; + int jack_detection; + unsigned int mclk_freq; +}; + +#endif /* __CS42L73_H */ diff --git a/include/sound/cs8403.h b/include/sound/cs8403.h new file mode 100644 index 000000000..c27f77639 --- /dev/null +++ b/include/sound/cs8403.h @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_CS8403_H +#define __SOUND_CS8403_H + +/* + * Routines for Cirrus Logic CS8403/CS8404A IEC958 (S/PDIF) Transmitter + * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, + * Takashi Iwai <tiwai@suse.de> + */ + +#ifdef SND_CS8403 + +#ifndef SND_CS8403_DECL +#define SND_CS8403_DECL static +#endif +#ifndef SND_CS8403_DECODE +#define SND_CS8403_DECODE snd_cs8403_decode_spdif_bits +#endif +#ifndef SND_CS8403_ENCODE +#define SND_CS8403_ENCODE snd_cs8403_encode_spdif_bits +#endif + + +SND_CS8403_DECL void SND_CS8403_DECODE(struct snd_aes_iec958 *diga, unsigned char bits) +{ + if (bits & 0x01) { /* consumer */ + if (!(bits & 0x02)) + diga->status[0] |= IEC958_AES0_NONAUDIO; + if (!(bits & 0x08)) + diga->status[0] |= IEC958_AES0_CON_NOT_COPYRIGHT; + switch (bits & 0x10) { + case 0x10: diga->status[0] |= IEC958_AES0_CON_EMPHASIS_NONE; break; + case 0x00: diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015; break; + } + if (!(bits & 0x80)) + diga->status[1] |= IEC958_AES1_CON_ORIGINAL; + switch (bits & 0x60) { + case 0x00: diga->status[1] |= IEC958_AES1_CON_MAGNETIC_ID; break; + case 0x20: diga->status[1] |= IEC958_AES1_CON_DIGDIGCONV_ID; break; + case 0x40: diga->status[1] |= IEC958_AES1_CON_LASEROPT_ID; break; + case 0x60: diga->status[1] |= IEC958_AES1_CON_GENERAL; break; + } + switch (bits & 0x06) { + case 0x00: diga->status[3] |= IEC958_AES3_CON_FS_44100; break; + case 0x02: diga->status[3] |= IEC958_AES3_CON_FS_48000; break; + case 0x04: diga->status[3] |= IEC958_AES3_CON_FS_32000; break; + } + } else { + diga->status[0] = IEC958_AES0_PROFESSIONAL; + switch (bits & 0x18) { + case 0x00: diga->status[0] |= IEC958_AES0_PRO_FS_32000; break; + case 0x10: diga->status[0] |= IEC958_AES0_PRO_FS_44100; break; + case 0x08: diga->status[0] |= IEC958_AES0_PRO_FS_48000; break; + case 0x18: diga->status[0] |= IEC958_AES0_PRO_FS_NOTID; break; + } + switch (bits & 0x60) { + case 0x20: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NONE; break; + case 0x40: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015; break; + case 0x00: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_CCITT; break; + case 0x60: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NOTID; break; + } + if (bits & 0x80) + diga->status[1] |= IEC958_AES1_PRO_MODE_STEREOPHONIC; + } +} + +SND_CS8403_DECL unsigned char SND_CS8403_ENCODE(struct snd_aes_iec958 *diga) +{ + unsigned char bits; + + if (!(diga->status[0] & IEC958_AES0_PROFESSIONAL)) { + bits = 0x01; /* consumer mode */ + if (diga->status[0] & IEC958_AES0_NONAUDIO) + bits &= ~0x02; + else + bits |= 0x02; + if (diga->status[0] & IEC958_AES0_CON_NOT_COPYRIGHT) + bits &= ~0x08; + else + bits |= 0x08; + switch (diga->status[0] & IEC958_AES0_CON_EMPHASIS) { + default: + case IEC958_AES0_CON_EMPHASIS_NONE: bits |= 0x10; break; + case IEC958_AES0_CON_EMPHASIS_5015: bits |= 0x00; break; + } + if (diga->status[1] & IEC958_AES1_CON_ORIGINAL) + bits &= ~0x80; + else + bits |= 0x80; + if ((diga->status[1] & IEC958_AES1_CON_CATEGORY) == IEC958_AES1_CON_GENERAL) + bits |= 0x60; + else { + switch(diga->status[1] & IEC958_AES1_CON_MAGNETIC_MASK) { + case IEC958_AES1_CON_MAGNETIC_ID: + bits |= 0x00; break; + case IEC958_AES1_CON_DIGDIGCONV_ID: + bits |= 0x20; break; + default: + case IEC958_AES1_CON_LASEROPT_ID: + bits |= 0x40; break; + } + } + switch (diga->status[3] & IEC958_AES3_CON_FS) { + default: + case IEC958_AES3_CON_FS_44100: bits |= 0x00; break; + case IEC958_AES3_CON_FS_48000: bits |= 0x02; break; + case IEC958_AES3_CON_FS_32000: bits |= 0x04; break; + } + } else { + bits = 0x00; /* professional mode */ + if (diga->status[0] & IEC958_AES0_NONAUDIO) + bits &= ~0x02; + else + bits |= 0x02; + /* CHECKME: I'm not sure about the bit order in val here */ + switch (diga->status[0] & IEC958_AES0_PRO_FS) { + case IEC958_AES0_PRO_FS_32000: bits |= 0x00; break; + case IEC958_AES0_PRO_FS_44100: bits |= 0x10; break; /* 44.1kHz */ + case IEC958_AES0_PRO_FS_48000: bits |= 0x08; break; /* 48kHz */ + default: + case IEC958_AES0_PRO_FS_NOTID: bits |= 0x18; break; + } + switch (diga->status[0] & IEC958_AES0_PRO_EMPHASIS) { + case IEC958_AES0_PRO_EMPHASIS_NONE: bits |= 0x20; break; + case IEC958_AES0_PRO_EMPHASIS_5015: bits |= 0x40; break; + case IEC958_AES0_PRO_EMPHASIS_CCITT: bits |= 0x00; break; + default: + case IEC958_AES0_PRO_EMPHASIS_NOTID: bits |= 0x60; break; + } + switch (diga->status[1] & IEC958_AES1_PRO_MODE) { + case IEC958_AES1_PRO_MODE_TWO: + case IEC958_AES1_PRO_MODE_STEREOPHONIC: bits |= 0x00; break; + default: bits |= 0x80; break; + } + } + return bits; +} + +#endif /* SND_CS8403 */ + +#ifdef SND_CS8404 + +#ifndef SND_CS8404_DECL +#define SND_CS8404_DECL static +#endif +#ifndef SND_CS8404_DECODE +#define SND_CS8404_DECODE snd_cs8404_decode_spdif_bits +#endif +#ifndef SND_CS8404_ENCODE +#define SND_CS8404_ENCODE snd_cs8404_encode_spdif_bits +#endif + + +SND_CS8404_DECL void SND_CS8404_DECODE(struct snd_aes_iec958 *diga, unsigned char bits) +{ + if (bits & 0x10) { /* consumer */ + if (!(bits & 0x20)) + diga->status[0] |= IEC958_AES0_CON_NOT_COPYRIGHT; + if (!(bits & 0x40)) + diga->status[0] |= IEC958_AES0_CON_EMPHASIS_5015; + if (!(bits & 0x80)) + diga->status[1] |= IEC958_AES1_CON_ORIGINAL; + switch (bits & 0x03) { + case 0x00: diga->status[1] |= IEC958_AES1_CON_DAT; break; + case 0x03: diga->status[1] |= IEC958_AES1_CON_GENERAL; break; + } + switch (bits & 0x06) { + case 0x02: diga->status[3] |= IEC958_AES3_CON_FS_32000; break; + case 0x04: diga->status[3] |= IEC958_AES3_CON_FS_48000; break; + case 0x06: diga->status[3] |= IEC958_AES3_CON_FS_44100; break; + } + } else { + diga->status[0] = IEC958_AES0_PROFESSIONAL; + if (!(bits & 0x04)) + diga->status[0] |= IEC958_AES0_NONAUDIO; + switch (bits & 0x60) { + case 0x00: diga->status[0] |= IEC958_AES0_PRO_FS_32000; break; + case 0x40: diga->status[0] |= IEC958_AES0_PRO_FS_44100; break; + case 0x20: diga->status[0] |= IEC958_AES0_PRO_FS_48000; break; + case 0x60: diga->status[0] |= IEC958_AES0_PRO_FS_NOTID; break; + } + switch (bits & 0x03) { + case 0x02: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NONE; break; + case 0x01: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_5015; break; + case 0x00: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_CCITT; break; + case 0x03: diga->status[0] |= IEC958_AES0_PRO_EMPHASIS_NOTID; break; + } + if (!(bits & 0x80)) + diga->status[1] |= IEC958_AES1_PRO_MODE_STEREOPHONIC; + } +} + +SND_CS8404_DECL unsigned char SND_CS8404_ENCODE(struct snd_aes_iec958 *diga) +{ + unsigned char bits; + + if (!(diga->status[0] & IEC958_AES0_PROFESSIONAL)) { + bits = 0x10; /* consumer mode */ + if (!(diga->status[0] & IEC958_AES0_CON_NOT_COPYRIGHT)) + bits |= 0x20; + if ((diga->status[0] & IEC958_AES0_CON_EMPHASIS) == IEC958_AES0_CON_EMPHASIS_NONE) + bits |= 0x40; + if (!(diga->status[1] & IEC958_AES1_CON_ORIGINAL)) + bits |= 0x80; + if ((diga->status[1] & IEC958_AES1_CON_CATEGORY) == IEC958_AES1_CON_GENERAL) + bits |= 0x03; + switch (diga->status[3] & IEC958_AES3_CON_FS) { + default: + case IEC958_AES3_CON_FS_44100: bits |= 0x06; break; + case IEC958_AES3_CON_FS_48000: bits |= 0x04; break; + case IEC958_AES3_CON_FS_32000: bits |= 0x02; break; + } + } else { + bits = 0x00; /* professional mode */ + if (!(diga->status[0] & IEC958_AES0_NONAUDIO)) + bits |= 0x04; + switch (diga->status[0] & IEC958_AES0_PRO_FS) { + case IEC958_AES0_PRO_FS_32000: bits |= 0x00; break; + case IEC958_AES0_PRO_FS_44100: bits |= 0x40; break; /* 44.1kHz */ + case IEC958_AES0_PRO_FS_48000: bits |= 0x20; break; /* 48kHz */ + default: + case IEC958_AES0_PRO_FS_NOTID: bits |= 0x00; break; + } + switch (diga->status[0] & IEC958_AES0_PRO_EMPHASIS) { + case IEC958_AES0_PRO_EMPHASIS_NONE: bits |= 0x02; break; + case IEC958_AES0_PRO_EMPHASIS_5015: bits |= 0x01; break; + case IEC958_AES0_PRO_EMPHASIS_CCITT: bits |= 0x00; break; + default: + case IEC958_AES0_PRO_EMPHASIS_NOTID: bits |= 0x03; break; + } + switch (diga->status[1] & IEC958_AES1_PRO_MODE) { + case IEC958_AES1_PRO_MODE_TWO: + case IEC958_AES1_PRO_MODE_STEREOPHONIC: bits |= 0x00; break; + default: bits |= 0x80; break; + } + } + return bits; +} + +#endif /* SND_CS8404 */ + +#endif /* __SOUND_CS8403_H */ diff --git a/include/sound/cs8427.h b/include/sound/cs8427.h new file mode 100644 index 000000000..38b730bd5 --- /dev/null +++ b/include/sound/cs8427.h @@ -0,0 +1,187 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_CS8427_H +#define __SOUND_CS8427_H + +/* + * Routines for Cirrus Logic CS8427 + * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, + */ + +#include <sound/i2c.h> + +#define CS8427_BASE_ADDR 0x10 /* base I2C address */ + +#define CS8427_REG_AUTOINC 0x80 /* flag - autoincrement */ +#define CS8427_REG_CONTROL1 0x01 +#define CS8427_REG_CONTROL2 0x02 +#define CS8427_REG_DATAFLOW 0x03 +#define CS8427_REG_CLOCKSOURCE 0x04 +#define CS8427_REG_SERIALINPUT 0x05 +#define CS8427_REG_SERIALOUTPUT 0x06 +#define CS8427_REG_INT1STATUS 0x07 +#define CS8427_REG_INT2STATUS 0x08 +#define CS8427_REG_INT1MASK 0x09 +#define CS8427_REG_INT1MODEMSB 0x0a +#define CS8427_REG_INT1MODELSB 0x0b +#define CS8427_REG_INT2MASK 0x0c +#define CS8427_REG_INT2MODEMSB 0x0d +#define CS8427_REG_INT2MODELSB 0x0e +#define CS8427_REG_RECVCSDATA 0x0f +#define CS8427_REG_RECVERRORS 0x10 +#define CS8427_REG_RECVERRMASK 0x11 +#define CS8427_REG_CSDATABUF 0x12 +#define CS8427_REG_UDATABUF 0x13 +#define CS8427_REG_QSUBCODE 0x14 /* 0x14-0x1d (10 bytes) */ +#define CS8427_REG_OMCKRMCKRATIO 0x1e +#define CS8427_REG_CORU_DATABUF 0x20 /* 24 byte buffer area */ +#define CS8427_REG_ID_AND_VER 0x7f + +/* CS8427_REG_CONTROL1 bits */ +#define CS8427_SWCLK (1<<7) /* 0 = RMCK default, 1 = OMCK output on RMCK pin */ +#define CS8427_VSET (1<<6) /* 0 = valid PCM data, 1 = invalid PCM data */ +#define CS8427_MUTESAO (1<<5) /* mute control for the serial audio output port, 0 = disabled, 1 = enabled */ +#define CS8427_MUTEAES (1<<4) /* mute control for the AES transmitter output, 0 = disabled, 1 = enabled */ +#define CS8427_INTMASK (3<<1) /* interrupt output pin setup mask */ +#define CS8427_INTACTHIGH (0<<1) /* active high */ +#define CS8427_INTACTLOW (1<<1) /* active low */ +#define CS8427_INTOPENDRAIN (2<<1) /* open drain, active low */ +#define CS8427_TCBLDIR (1<<0) /* 0 = TCBL is an input, 1 = TCBL is an output */ + +/* CS8427_REQ_CONTROL2 bits */ +#define CS8427_HOLDMASK (3<<5) /* action when a receiver error occurs */ +#define CS8427_HOLDLASTSAMPLE (0<<5) /* hold the last valid sample */ +#define CS8427_HOLDZERO (1<<5) /* replace the current audio sample with zero (mute) */ +#define CS8427_HOLDNOCHANGE (2<<5) /* do not change the received audio sample */ +#define CS8427_RMCKF (1<<4) /* 0 = 256*Fsi, 1 = 128*Fsi */ +#define CS8427_MMR (1<<3) /* AES3 receiver operation, 0 = stereo, 1 = mono */ +#define CS8427_MMT (1<<2) /* AES3 transmitter operation, 0 = stereo, 1 = mono */ +#define CS8427_MMTCS (1<<1) /* 0 = use A + B CS data, 1 = use MMTLR CS data */ +#define CS8427_MMTLR (1<<0) /* 0 = use A CS data, 1 = use B CS data */ + +/* CS8427_REG_DATAFLOW */ +#define CS8427_TXOFF (1<<6) /* AES3 transmitter Output, 0 = normal operation, 1 = off (0V) */ +#define CS8427_AESBP (1<<5) /* AES3 hardware bypass mode, 0 = normal, 1 = bypass (RX->TX) */ +#define CS8427_TXDMASK (3<<3) /* AES3 Transmitter Data Source Mask */ +#define CS8427_TXDSERIAL (1<<3) /* TXD - serial audio input port */ +#define CS8427_TXAES3DRECEIVER (2<<3) /* TXD - AES3 receiver */ +#define CS8427_SPDMASK (3<<1) /* Serial Audio Output Port Data Source Mask */ +#define CS8427_SPDSERIAL (1<<1) /* SPD - serial audio input port */ +#define CS8427_SPDAES3RECEIVER (2<<1) /* SPD - AES3 receiver */ + +/* CS8427_REG_CLOCKSOURCE */ +#define CS8427_RUN (1<<6) /* 0 = clock off, 1 = clock on */ +#define CS8427_CLKMASK (3<<4) /* OMCK frequency mask */ +#define CS8427_CLK256 (0<<4) /* 256*Fso */ +#define CS8427_CLK384 (1<<4) /* 384*Fso */ +#define CS8427_CLK512 (2<<4) /* 512*Fso */ +#define CS8427_OUTC (1<<3) /* Output Time Base, 0 = OMCK, 1 = recovered input clock */ +#define CS8427_INC (1<<2) /* Input Time Base Clock Source, 0 = recoverd input clock, 1 = OMCK input pin */ +#define CS8427_RXDMASK (3<<0) /* Recovered Input Clock Source Mask */ +#define CS8427_RXDILRCK (0<<0) /* 256*Fsi from ILRCK pin */ +#define CS8427_RXDAES3INPUT (1<<0) /* 256*Fsi from AES3 input */ +#define CS8427_EXTCLOCKRESET (2<<0) /* bypass PLL, 256*Fsi clock, synchronous reset */ +#define CS8427_EXTCLOCK (3<<0) /* bypass PLL, 256*Fsi clock */ + +/* CS8427_REG_SERIALINPUT */ +#define CS8427_SIMS (1<<7) /* 0 = slave, 1 = master mode */ +#define CS8427_SISF (1<<6) /* ISCLK freq, 0 = 64*Fsi, 1 = 128*Fsi */ +#define CS8427_SIRESMASK (3<<4) /* Resolution of the input data for right justified formats */ +#define CS8427_SIRES24 (0<<4) /* SIRES 24-bit */ +#define CS8427_SIRES20 (1<<4) /* SIRES 20-bit */ +#define CS8427_SIRES16 (2<<4) /* SIRES 16-bit */ +#define CS8427_SIJUST (1<<3) /* Justification of SDIN data relative to ILRCK, 0 = left-justified, 1 = right-justified */ +#define CS8427_SIDEL (1<<2) /* Delay of SDIN data relative to ILRCK for left-justified data formats, 0 = first ISCLK period, 1 = second ISCLK period */ +#define CS8427_SISPOL (1<<1) /* ICLK clock polarity, 0 = rising edge of ISCLK, 1 = falling edge of ISCLK */ +#define CS8427_SILRPOL (1<<0) /* ILRCK clock polarity, 0 = SDIN data left channel when ILRCK is high, 1 = SDIN right when ILRCK is high */ + +/* CS8427_REG_SERIALOUTPUT */ +#define CS8427_SOMS (1<<7) /* 0 = slave, 1 = master mode */ +#define CS8427_SOSF (1<<6) /* OSCLK freq, 0 = 64*Fso, 1 = 128*Fso */ +#define CS8427_SORESMASK (3<<4) /* Resolution of the output data on SDOUT and AES3 output */ +#define CS8427_SORES24 (0<<4) /* SIRES 24-bit */ +#define CS8427_SORES20 (1<<4) /* SIRES 20-bit */ +#define CS8427_SORES16 (2<<4) /* SIRES 16-bit */ +#define CS8427_SORESDIRECT (2<<4) /* SIRES direct copy from AES3 receiver */ +#define CS8427_SOJUST (1<<3) /* Justification of SDOUT data relative to OLRCK, 0 = left-justified, 1 = right-justified */ +#define CS8427_SODEL (1<<2) /* Delay of SDOUT data relative to OLRCK for left-justified data formats, 0 = first OSCLK period, 1 = second OSCLK period */ +#define CS8427_SOSPOL (1<<1) /* OSCLK clock polarity, 0 = rising edge of ISCLK, 1 = falling edge of ISCLK */ +#define CS8427_SOLRPOL (1<<0) /* OLRCK clock polarity, 0 = SDOUT data left channel when OLRCK is high, 1 = SDOUT right when OLRCK is high */ + +/* CS8427_REG_INT1STATUS */ +#define CS8427_TSLIP (1<<7) /* AES3 transmitter source data slip interrupt */ +#define CS8427_OSLIP (1<<6) /* Serial audio output port data slip interrupt */ +#define CS8427_DETC (1<<2) /* D to E C-buffer transfer interrupt */ +#define CS8427_EFTC (1<<1) /* E to F C-buffer transfer interrupt */ +#define CS8427_RERR (1<<0) /* A receiver error has occurred */ + +/* CS8427_REG_INT2STATUS */ +#define CS8427_DETU (1<<3) /* D to E U-buffer transfer interrupt */ +#define CS8427_EFTU (1<<2) /* E to F U-buffer transfer interrupt */ +#define CS8427_QCH (1<<1) /* A new block of Q-subcode data is available for reading */ + +/* CS8427_REG_INT1MODEMSB && CS8427_REG_INT1MODELSB */ +/* bits are defined in CS8427_REG_INT1STATUS */ +/* CS8427_REG_INT2MODEMSB && CS8427_REG_INT2MODELSB */ +/* bits are defined in CS8427_REG_INT2STATUS */ +#define CS8427_INTMODERISINGMSB 0 +#define CS8427_INTMODERESINGLSB 0 +#define CS8427_INTMODEFALLINGMSB 0 +#define CS8427_INTMODEFALLINGLSB 1 +#define CS8427_INTMODELEVELMSB 1 +#define CS8427_INTMODELEVELLSB 0 + +/* CS8427_REG_RECVCSDATA */ +#define CS8427_AUXMASK (15<<4) /* auxiliary data field width */ +#define CS8427_AUXSHIFT 4 +#define CS8427_PRO (1<<3) /* Channel status block format indicator */ +#define CS8427_AUDIO (1<<2) /* Audio indicator (0 = audio, 1 = nonaudio */ +#define CS8427_COPY (1<<1) /* 0 = copyright asserted, 1 = copyright not asserted */ +#define CS8427_ORIG (1<<0) /* SCMS generation indicator, 0 = 1st generation or highter, 1 = original */ + +/* CS8427_REG_RECVERRORS */ +/* CS8427_REG_RECVERRMASK for CS8427_RERR */ +#define CS8427_QCRC (1<<6) /* Q-subcode data CRC error indicator */ +#define CS8427_CCRC (1<<5) /* Chancnel Status Block Cyclick Redundancy Check Bit */ +#define CS8427_UNLOCK (1<<4) /* PLL lock status bit */ +#define CS8427_V (1<<3) /* 0 = valid data */ +#define CS8427_CONF (1<<2) /* Confidence bit */ +#define CS8427_BIP (1<<1) /* Bi-phase error bit */ +#define CS8427_PAR (1<<0) /* Parity error */ + +/* CS8427_REG_CSDATABUF */ +#define CS8427_BSEL (1<<5) /* 0 = CS data, 1 = U data */ +#define CS8427_CBMR (1<<4) /* 0 = overwrite first 5 bytes for CS D to E buffer, 1 = prevent */ +#define CS8427_DETCI (1<<3) /* D to E CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */ +#define CS8427_EFTCI (1<<2) /* E to F CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */ +#define CS8427_CAM (1<<1) /* CS data buffer control port access mode bit, 0 = one byte, 1 = two byte */ +#define CS8427_CHS (1<<0) /* Channel select bit, 0 = Channel A, 1 = Channel B */ + +/* CS8427_REG_UDATABUF */ +#define CS8427_UD (1<<4) /* User data pin (U) direction, 0 = input, 1 = output */ +#define CS8427_UBMMASK (3<<2) /* Operating mode of the AES3 U bit manager */ +#define CS8427_UBMZEROS (0<<2) /* transmit all zeros mode */ +#define CS8427_UBMBLOCK (1<<2) /* block mode */ +#define CS8427_DETUI (1<<1) /* D to E U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */ +#define CS8427_EFTUI (1<<1) /* E to F U-data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */ + +/* CS8427_REG_ID_AND_VER */ +#define CS8427_IDMASK (15<<4) +#define CS8427_IDSHIFT 4 +#define CS8427_VERMASK (15<<0) +#define CS8427_VERSHIFT 0 +#define CS8427_VER8427A 0x71 + +struct snd_pcm_substream; + +int snd_cs8427_init(struct snd_i2c_bus *bus, struct snd_i2c_device *device); +int snd_cs8427_create(struct snd_i2c_bus *bus, unsigned char addr, + unsigned int reset_timeout, struct snd_i2c_device **r_cs8427); +int snd_cs8427_reg_write(struct snd_i2c_device *device, unsigned char reg, + unsigned char val); +int snd_cs8427_iec958_build(struct snd_i2c_device *cs8427, + struct snd_pcm_substream *playback_substream, + struct snd_pcm_substream *capture_substream); +int snd_cs8427_iec958_active(struct snd_i2c_device *cs8427, int active); +int snd_cs8427_iec958_pcm(struct snd_i2c_device *cs8427, unsigned int rate); + +#endif /* __SOUND_CS8427_H */ diff --git a/include/sound/da7213.h b/include/sound/da7213.h new file mode 100644 index 000000000..6216a0a7b --- /dev/null +++ b/include/sound/da7213.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * da7213.h - DA7213 ASoC Codec Driver Platform Data + * + * Copyright (c) 2013 Dialog Semiconductor + * + * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com> + */ + +#ifndef _DA7213_PDATA_H +#define _DA7213_PDATA_H + +enum da7213_micbias_voltage { + DA7213_MICBIAS_1_6V = 0, + DA7213_MICBIAS_2_2V = 1, + DA7213_MICBIAS_2_5V = 2, + DA7213_MICBIAS_3_0V = 3, +}; + +enum da7213_dmic_data_sel { + DA7213_DMIC_DATA_LRISE_RFALL = 0, + DA7213_DMIC_DATA_LFALL_RRISE = 1, +}; + +enum da7213_dmic_samplephase { + DA7213_DMIC_SAMPLE_ON_CLKEDGE = 0, + DA7213_DMIC_SAMPLE_BETWEEN_CLKEDGE = 1, +}; + +enum da7213_dmic_clk_rate { + DA7213_DMIC_CLK_3_0MHZ = 0, + DA7213_DMIC_CLK_1_5MHZ = 1, +}; + +struct da7213_platform_data { + /* Mic Bias voltage */ + enum da7213_micbias_voltage micbias1_lvl; + enum da7213_micbias_voltage micbias2_lvl; + + /* DMIC config */ + enum da7213_dmic_data_sel dmic_data_sel; + enum da7213_dmic_samplephase dmic_samplephase; + enum da7213_dmic_clk_rate dmic_clk_rate; +}; + +#endif /* _DA7213_PDATA_H */ diff --git a/include/sound/da7218.h b/include/sound/da7218.h new file mode 100644 index 000000000..9d0a82fbe --- /dev/null +++ b/include/sound/da7218.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * da7218.h - DA7218 ASoC Codec Driver Platform Data + * + * Copyright (c) 2015 Dialog Semiconductor + * + * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com> + */ + +#ifndef _DA7218_PDATA_H +#define _DA7218_PDATA_H + +/* Mic Bias */ +enum da7218_micbias_voltage { + DA7218_MICBIAS_1_2V = -1, + DA7218_MICBIAS_1_6V, + DA7218_MICBIAS_1_8V, + DA7218_MICBIAS_2_0V, + DA7218_MICBIAS_2_2V, + DA7218_MICBIAS_2_4V, + DA7218_MICBIAS_2_6V, + DA7218_MICBIAS_2_8V, + DA7218_MICBIAS_3_0V, +}; + +enum da7218_mic_amp_in_sel { + DA7218_MIC_AMP_IN_SEL_DIFF = 0, + DA7218_MIC_AMP_IN_SEL_SE_P, + DA7218_MIC_AMP_IN_SEL_SE_N, +}; + +/* DMIC */ +enum da7218_dmic_data_sel { + DA7218_DMIC_DATA_LRISE_RFALL = 0, + DA7218_DMIC_DATA_LFALL_RRISE, +}; + +enum da7218_dmic_samplephase { + DA7218_DMIC_SAMPLE_ON_CLKEDGE = 0, + DA7218_DMIC_SAMPLE_BETWEEN_CLKEDGE, +}; + +enum da7218_dmic_clk_rate { + DA7218_DMIC_CLK_3_0MHZ = 0, + DA7218_DMIC_CLK_1_5MHZ, +}; + +/* Headphone Detect */ +enum da7218_hpldet_jack_rate { + DA7218_HPLDET_JACK_RATE_5US = 0, + DA7218_HPLDET_JACK_RATE_10US, + DA7218_HPLDET_JACK_RATE_20US, + DA7218_HPLDET_JACK_RATE_40US, + DA7218_HPLDET_JACK_RATE_80US, + DA7218_HPLDET_JACK_RATE_160US, + DA7218_HPLDET_JACK_RATE_320US, + DA7218_HPLDET_JACK_RATE_640US, +}; + +enum da7218_hpldet_jack_debounce { + DA7218_HPLDET_JACK_DEBOUNCE_OFF = 0, + DA7218_HPLDET_JACK_DEBOUNCE_2, + DA7218_HPLDET_JACK_DEBOUNCE_3, + DA7218_HPLDET_JACK_DEBOUNCE_4, +}; + +enum da7218_hpldet_jack_thr { + DA7218_HPLDET_JACK_THR_84PCT = 0, + DA7218_HPLDET_JACK_THR_88PCT, + DA7218_HPLDET_JACK_THR_92PCT, + DA7218_HPLDET_JACK_THR_96PCT, +}; + +struct da7218_hpldet_pdata { + enum da7218_hpldet_jack_rate jack_rate; + enum da7218_hpldet_jack_debounce jack_debounce; + enum da7218_hpldet_jack_thr jack_thr; + bool comp_inv; + bool hyst; + bool discharge; +}; + +struct da7218_pdata { + /* Mic */ + enum da7218_micbias_voltage micbias1_lvl; + enum da7218_micbias_voltage micbias2_lvl; + enum da7218_mic_amp_in_sel mic1_amp_in_sel; + enum da7218_mic_amp_in_sel mic2_amp_in_sel; + + /* DMIC */ + enum da7218_dmic_data_sel dmic1_data_sel; + enum da7218_dmic_data_sel dmic2_data_sel; + enum da7218_dmic_samplephase dmic1_samplephase; + enum da7218_dmic_samplephase dmic2_samplephase; + enum da7218_dmic_clk_rate dmic1_clk_rate; + enum da7218_dmic_clk_rate dmic2_clk_rate; + + /* HP Diff Supply - DA7217 only */ + bool hp_diff_single_supply; + + /* HP Detect - DA7218 only */ + struct da7218_hpldet_pdata *hpldet_pdata; +}; + +#endif /* _DA7218_PDATA_H */ diff --git a/include/sound/da7219-aad.h b/include/sound/da7219-aad.h new file mode 100644 index 000000000..24ee7baa2 --- /dev/null +++ b/include/sound/da7219-aad.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * da7219-aad.h - DA7322 ASoC Codec AAD Driver Platform Data + * + * Copyright (c) 2015 Dialog Semiconductor Ltd. + * + * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com> + */ + +#ifndef __DA7219_AAD_PDATA_H +#define __DA7219_AAD_PDATA_H + +enum da7219_aad_micbias_pulse_lvl { + DA7219_AAD_MICBIAS_PULSE_LVL_OFF = 0, + DA7219_AAD_MICBIAS_PULSE_LVL_2_8V = 6, + DA7219_AAD_MICBIAS_PULSE_LVL_2_9V, +}; + +enum da7219_aad_btn_cfg { + DA7219_AAD_BTN_CFG_2MS = 1, + DA7219_AAD_BTN_CFG_5MS, + DA7219_AAD_BTN_CFG_10MS, + DA7219_AAD_BTN_CFG_50MS, + DA7219_AAD_BTN_CFG_100MS, + DA7219_AAD_BTN_CFG_200MS, + DA7219_AAD_BTN_CFG_500MS, +}; + +enum da7219_aad_mic_det_thr { + DA7219_AAD_MIC_DET_THR_200_OHMS = 0, + DA7219_AAD_MIC_DET_THR_500_OHMS, + DA7219_AAD_MIC_DET_THR_750_OHMS, + DA7219_AAD_MIC_DET_THR_1000_OHMS, +}; + +enum da7219_aad_jack_ins_deb { + DA7219_AAD_JACK_INS_DEB_5MS = 0, + DA7219_AAD_JACK_INS_DEB_10MS, + DA7219_AAD_JACK_INS_DEB_20MS, + DA7219_AAD_JACK_INS_DEB_50MS, + DA7219_AAD_JACK_INS_DEB_100MS, + DA7219_AAD_JACK_INS_DEB_200MS, + DA7219_AAD_JACK_INS_DEB_500MS, + DA7219_AAD_JACK_INS_DEB_1S, +}; + +enum da7219_aad_jack_det_rate { + DA7219_AAD_JACK_DET_RATE_32_64MS = 0, + DA7219_AAD_JACK_DET_RATE_64_128MS, + DA7219_AAD_JACK_DET_RATE_128_256MS, + DA7219_AAD_JACK_DET_RATE_256_512MS, +}; + +enum da7219_aad_jack_rem_deb { + DA7219_AAD_JACK_REM_DEB_1MS = 0, + DA7219_AAD_JACK_REM_DEB_5MS, + DA7219_AAD_JACK_REM_DEB_10MS, + DA7219_AAD_JACK_REM_DEB_20MS, +}; + +enum da7219_aad_btn_avg { + DA7219_AAD_BTN_AVG_1 = 0, + DA7219_AAD_BTN_AVG_2, + DA7219_AAD_BTN_AVG_4, + DA7219_AAD_BTN_AVG_8, +}; + +enum da7219_aad_adc_1bit_rpt { + DA7219_AAD_ADC_1BIT_RPT_1 = 0, + DA7219_AAD_ADC_1BIT_RPT_2, + DA7219_AAD_ADC_1BIT_RPT_4, + DA7219_AAD_ADC_1BIT_RPT_8, +}; + +struct da7219_aad_pdata { + int irq; + + enum da7219_aad_micbias_pulse_lvl micbias_pulse_lvl; + u32 micbias_pulse_time; + enum da7219_aad_btn_cfg btn_cfg; + enum da7219_aad_mic_det_thr mic_det_thr; + enum da7219_aad_jack_ins_deb jack_ins_deb; + enum da7219_aad_jack_det_rate jack_det_rate; + enum da7219_aad_jack_rem_deb jack_rem_deb; + + u8 a_d_btn_thr; + u8 d_b_btn_thr; + u8 b_c_btn_thr; + u8 c_mic_btn_thr; + + enum da7219_aad_btn_avg btn_avg; + enum da7219_aad_adc_1bit_rpt adc_1bit_rpt; +}; + +#endif /* __DA7219_AAD_PDATA_H */ diff --git a/include/sound/da7219.h b/include/sound/da7219.h new file mode 100644 index 000000000..dde4542b0 --- /dev/null +++ b/include/sound/da7219.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * da7219.h - DA7219 ASoC Codec Driver Platform Data + * + * Copyright (c) 2015 Dialog Semiconductor + * + * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com> + */ + +#ifndef __DA7219_PDATA_H +#define __DA7219_PDATA_H + +/* Mic Bias */ +enum da7219_micbias_voltage { + DA7219_MICBIAS_1_6V = 0, + DA7219_MICBIAS_1_8V, + DA7219_MICBIAS_2_0V, + DA7219_MICBIAS_2_2V, + DA7219_MICBIAS_2_4V, + DA7219_MICBIAS_2_6V, +}; + +/* Mic input type */ +enum da7219_mic_amp_in_sel { + DA7219_MIC_AMP_IN_SEL_DIFF = 0, + DA7219_MIC_AMP_IN_SEL_SE_P, + DA7219_MIC_AMP_IN_SEL_SE_N, +}; + +struct da7219_aad_pdata; + +enum da7219_dai_clks { + DA7219_DAI_WCLK_IDX = 0, + DA7219_DAI_BCLK_IDX, + DA7219_DAI_NUM_CLKS, +}; + +struct da7219_pdata { + bool wakeup_source; + + const char *dai_clk_names[DA7219_DAI_NUM_CLKS]; + + /* Mic */ + enum da7219_micbias_voltage micbias_lvl; + enum da7219_mic_amp_in_sel mic_amp_in_sel; + + /* AAD */ + struct da7219_aad_pdata *aad_pdata; +}; + +#endif /* __DA7219_PDATA_H */ diff --git a/include/sound/da9055.h b/include/sound/da9055.h new file mode 100644 index 000000000..5c9a3c23e --- /dev/null +++ b/include/sound/da9055.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * DA9055 ALSA Soc codec driver + * + * Copyright (c) 2012 Dialog Semiconductor + * + * Tested on (Samsung SMDK6410 board + DA9055 EVB) using I2S and I2C + * Written by David Chen <david.chen@diasemi.com> and + * Ashish Chavan <ashish.chavan@kpitcummins.com> + */ + +#ifndef __SOUND_DA9055_H__ +#define __SOUND_DA9055_H__ + +enum da9055_micbias_voltage { + DA9055_MICBIAS_1_6V = 0, + DA9055_MICBIAS_1_8V = 1, + DA9055_MICBIAS_2_1V = 2, + DA9055_MICBIAS_2_2V = 3, +}; + +struct da9055_platform_data { + /* Selects which of the two MicBias pins acts as the bias source */ + bool micbias_source; + /* Selects the micbias voltage */ + enum da9055_micbias_voltage micbias; +}; + +#endif diff --git a/include/sound/designware_i2s.h b/include/sound/designware_i2s.h new file mode 100644 index 000000000..80d275b9a --- /dev/null +++ b/include/sound/designware_i2s.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com) + */ + +#ifndef __SOUND_DESIGNWARE_I2S_H +#define __SOUND_DESIGNWARE_I2S_H + +#include <linux/dmaengine.h> +#include <linux/types.h> + +/* + * struct i2s_clk_config_data - represent i2s clk configuration data + * @chan_nr: number of channel + * @data_width: number of bits per sample (8/16/24/32 bit) + * @sample_rate: sampling frequency (8Khz, 16Khz, 32Khz, 44Khz, 48Khz) + */ +struct i2s_clk_config_data { + int chan_nr; + u32 data_width; + u32 sample_rate; +}; + +struct i2s_platform_data { + #define DWC_I2S_PLAY (1 << 0) + #define DWC_I2S_RECORD (1 << 1) + #define DW_I2S_SLAVE (1 << 2) + #define DW_I2S_MASTER (1 << 3) + unsigned int cap; + int channel; + u32 snd_fmts; + u32 snd_rates; + + #define DW_I2S_QUIRK_COMP_REG_OFFSET (1 << 0) + #define DW_I2S_QUIRK_COMP_PARAM1 (1 << 1) + #define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2) + unsigned int quirks; + unsigned int i2s_reg_comp1; + unsigned int i2s_reg_comp2; + + void *play_dma_data; + void *capture_dma_data; + bool (*filter)(struct dma_chan *chan, void *slave); + int (*i2s_clk_cfg)(struct i2s_clk_config_data *config); +}; + +struct i2s_dma_data { + void *data; + dma_addr_t addr; + u32 max_burst; + enum dma_slave_buswidth addr_width; + bool (*filter)(struct dma_chan *chan, void *slave); +}; + +/* I2S DMA registers */ +#define I2S_RXDMA 0x01C0 +#define I2S_TXDMA 0x01C8 + +#define TWO_CHANNEL_SUPPORT 2 /* up to 2.0 */ +#define FOUR_CHANNEL_SUPPORT 4 /* up to 3.1 */ +#define SIX_CHANNEL_SUPPORT 6 /* up to 5.1 */ +#define EIGHT_CHANNEL_SUPPORT 8 /* up to 7.1 */ + +#endif /* __SOUND_DESIGNWARE_I2S_H */ diff --git a/include/sound/dmaengine_pcm.h b/include/sound/dmaengine_pcm.h new file mode 100644 index 000000000..2df54cf02 --- /dev/null +++ b/include/sound/dmaengine_pcm.h @@ -0,0 +1,180 @@ +/* SPDX-License-Identifier: GPL-2.0+ + * + * Copyright (C) 2012, Analog Devices Inc. + * Author: Lars-Peter Clausen <lars@metafoo.de> + */ + +#ifndef __SOUND_DMAENGINE_PCM_H__ +#define __SOUND_DMAENGINE_PCM_H__ + +#include <sound/pcm.h> +#include <sound/soc.h> +#include <linux/dmaengine.h> + +/** + * snd_pcm_substream_to_dma_direction - Get dma_transfer_direction for a PCM + * substream + * @substream: PCM substream + * + * Return: DMA transfer direction + */ +static inline enum dma_transfer_direction +snd_pcm_substream_to_dma_direction(const struct snd_pcm_substream *substream) +{ + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) + return DMA_MEM_TO_DEV; + else + return DMA_DEV_TO_MEM; +} + +int snd_hwparams_to_dma_slave_config(const struct snd_pcm_substream *substream, + const struct snd_pcm_hw_params *params, struct dma_slave_config *slave_config); +int snd_dmaengine_pcm_trigger(struct snd_pcm_substream *substream, int cmd); +snd_pcm_uframes_t snd_dmaengine_pcm_pointer(struct snd_pcm_substream *substream); +snd_pcm_uframes_t snd_dmaengine_pcm_pointer_no_residue(struct snd_pcm_substream *substream); + +int snd_dmaengine_pcm_open(struct snd_pcm_substream *substream, + struct dma_chan *chan); +int snd_dmaengine_pcm_close(struct snd_pcm_substream *substream); + +int snd_dmaengine_pcm_open_request_chan(struct snd_pcm_substream *substream, + dma_filter_fn filter_fn, void *filter_data); +int snd_dmaengine_pcm_close_release_chan(struct snd_pcm_substream *substream); + +struct dma_chan *snd_dmaengine_pcm_request_channel(dma_filter_fn filter_fn, + void *filter_data); +struct dma_chan *snd_dmaengine_pcm_get_chan(struct snd_pcm_substream *substream); + +/* + * The DAI supports packed transfers, eg 2 16-bit samples in a 32-bit word. + * If this flag is set the dmaengine driver won't put any restriction on + * the supported sample formats and set the DMA transfer size to undefined. + * The DAI driver is responsible to disable any unsupported formats in it's + * configuration and catch corner cases that are not already handled in + * the ALSA core. + */ +#define SND_DMAENGINE_PCM_DAI_FLAG_PACK BIT(0) + +/** + * struct snd_dmaengine_dai_dma_data - DAI DMA configuration data + * @addr: Address of the DAI data source or destination register. + * @addr_width: Width of the DAI data source or destination register. + * @maxburst: Maximum number of words(note: words, as in units of the + * src_addr_width member, not bytes) that can be send to or received from the + * DAI in one burst. + * @filter_data: Custom DMA channel filter data, this will usually be used when + * requesting the DMA channel. + * @chan_name: Custom channel name to use when requesting DMA channel. + * @fifo_size: FIFO size of the DAI controller in bytes + * @flags: PCM_DAI flags, only SND_DMAENGINE_PCM_DAI_FLAG_PACK for now + * @peripheral_config: peripheral configuration for programming peripheral + * for dmaengine transfer + * @peripheral_size: peripheral configuration buffer size + */ +struct snd_dmaengine_dai_dma_data { + dma_addr_t addr; + enum dma_slave_buswidth addr_width; + u32 maxburst; + void *filter_data; + const char *chan_name; + unsigned int fifo_size; + unsigned int flags; + void *peripheral_config; + size_t peripheral_size; +}; + +void snd_dmaengine_pcm_set_config_from_dai_data( + const struct snd_pcm_substream *substream, + const struct snd_dmaengine_dai_dma_data *dma_data, + struct dma_slave_config *config); + +int snd_dmaengine_pcm_refine_runtime_hwparams( + struct snd_pcm_substream *substream, + struct snd_dmaengine_dai_dma_data *dma_data, + struct snd_pcm_hardware *hw, + struct dma_chan *chan); + +/* + * Try to request the DMA channel using compat_request_channel or + * compat_filter_fn if it couldn't be requested through devicetree. + */ +#define SND_DMAENGINE_PCM_FLAG_COMPAT BIT(0) +/* + * Don't try to request the DMA channels through devicetree. This flag only + * makes sense if SND_DMAENGINE_PCM_FLAG_COMPAT is set as well. + */ +#define SND_DMAENGINE_PCM_FLAG_NO_DT BIT(1) +/* + * The PCM is half duplex and the DMA channel is shared between capture and + * playback. + */ +#define SND_DMAENGINE_PCM_FLAG_HALF_DUPLEX BIT(3) + +/** + * struct snd_dmaengine_pcm_config - Configuration data for dmaengine based PCM + * @prepare_slave_config: Callback used to fill in the DMA slave_config for a + * PCM substream. Will be called from the PCM drivers hwparams callback. + * @compat_request_channel: Callback to request a DMA channel for platforms + * which do not use devicetree. + * @process: Callback used to apply processing on samples transferred from/to + * user space. + * @compat_filter_fn: Will be used as the filter function when requesting a + * channel for platforms which do not use devicetree. The filter parameter + * will be the DAI's DMA data. + * @dma_dev: If set, request DMA channel on this device rather than the DAI + * device. + * @chan_names: If set, these custom DMA channel names will be requested at + * registration time. + * @pcm_hardware: snd_pcm_hardware struct to be used for the PCM. + * @prealloc_buffer_size: Size of the preallocated audio buffer. + * + * Note: If both compat_request_channel and compat_filter_fn are set + * compat_request_channel will be used to request the channel and + * compat_filter_fn will be ignored. Otherwise the channel will be requested + * using dma_request_channel with compat_filter_fn as the filter function. + */ +struct snd_dmaengine_pcm_config { + int (*prepare_slave_config)(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct dma_slave_config *slave_config); + struct dma_chan *(*compat_request_channel)( + struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_substream *substream); + int (*process)(struct snd_pcm_substream *substream, + int channel, unsigned long hwoff, + void *buf, unsigned long bytes); + dma_filter_fn compat_filter_fn; + struct device *dma_dev; + const char *chan_names[SNDRV_PCM_STREAM_LAST + 1]; + + const struct snd_pcm_hardware *pcm_hardware; + unsigned int prealloc_buffer_size; +}; + +int snd_dmaengine_pcm_register(struct device *dev, + const struct snd_dmaengine_pcm_config *config, + unsigned int flags); +void snd_dmaengine_pcm_unregister(struct device *dev); + +int devm_snd_dmaengine_pcm_register(struct device *dev, + const struct snd_dmaengine_pcm_config *config, + unsigned int flags); + +int snd_dmaengine_pcm_prepare_slave_config(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct dma_slave_config *slave_config); + +#define SND_DMAENGINE_PCM_DRV_NAME "snd_dmaengine_pcm" + +struct dmaengine_pcm { + struct dma_chan *chan[SNDRV_PCM_STREAM_LAST + 1]; + const struct snd_dmaengine_pcm_config *config; + struct snd_soc_component component; + unsigned int flags; +}; + +static inline struct dmaengine_pcm *soc_component_to_pcm(struct snd_soc_component *p) +{ + return container_of(p, struct dmaengine_pcm, component); +} +#endif diff --git a/include/sound/emu10k1.h b/include/sound/emu10k1.h new file mode 100644 index 000000000..39787fecc --- /dev/null +++ b/include/sound/emu10k1.h @@ -0,0 +1,1892 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, + * Creative Labs, Inc. + * Definitions for EMU10K1 (SB Live!) chips + */ +#ifndef __SOUND_EMU10K1_H +#define __SOUND_EMU10K1_H + + +#include <sound/pcm.h> +#include <sound/rawmidi.h> +#include <sound/hwdep.h> +#include <sound/ac97_codec.h> +#include <sound/util_mem.h> +#include <sound/pcm-indirect.h> +#include <sound/timer.h> +#include <linux/interrupt.h> +#include <linux/mutex.h> +#include <linux/firmware.h> +#include <linux/io.h> + +#include <uapi/sound/emu10k1.h> + +/* ------------------- DEFINES -------------------- */ + +#define EMUPAGESIZE 4096 +#define MAXREQVOICES 8 +#define MAXPAGES0 4096 /* 32 bit mode */ +#define MAXPAGES1 8192 /* 31 bit mode */ +#define RESERVED 0 +#define NUM_MIDI 16 +#define NUM_G 64 /* use all channels */ +#define NUM_FXSENDS 4 +#define NUM_EFX_PLAYBACK 16 + +/* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */ +#define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */ +#define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */ + +#define TMEMSIZE 256*1024 +#define TMEMSIZEREG 4 + +#define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL)) + +// Audigy specify registers are prefixed with 'A_' + +/************************************************************************************************/ +/* PCI function 0 registers, address = <val> + PCIBASE0 */ +/************************************************************************************************/ + +#define PTR 0x00 /* Indexed register set pointer register */ + /* NOTE: The CHANNELNUM and ADDRESS words can */ + /* be modified independently of each other. */ +#define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */ + /* channel number of the register to be */ + /* accessed. For non per-channel registers the */ + /* value should be set to zero. */ +#define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */ +#define A_PTR_ADDRESS_MASK 0x0fff0000 + +#define DATA 0x04 /* Indexed register set data register */ + +#define IPR 0x08 /* Global interrupt pending register */ + /* Clear pending interrupts by writing a 1 to */ + /* the relevant bits and zero to the other bits */ +#define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes + to interrupt */ +#define IPR_GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure + which INTE bits enable it) */ + +/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */ +#define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */ +#define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */ + +#define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */ +#define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */ + +#define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */ +#define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */ +#define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */ +#define IPR_PCIERROR 0x00200000 /* PCI bus error */ +#define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */ +#define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */ +#define IPR_MUTE 0x00040000 /* Mute button pressed */ +#define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */ +#define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */ +#define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */ +#define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */ +#define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */ +#define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */ +#define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */ +#define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */ +#define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */ +#define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */ +#define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */ +#define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */ +#define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */ + /* highest set channel in CLIPL, CLIPH, HLIPL, */ + /* or HLIPH. When IP is written with CL set, */ + /* the bit in H/CLIPL or H/CLIPH corresponding */ + /* to the CIN value written will be cleared. */ + +#define INTE 0x0c /* Interrupt enable register */ +#define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */ +#define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */ +#define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */ +#define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */ +#define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */ +#define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */ +#define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */ +#define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */ +#define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */ +#define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */ +#define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */ +#define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */ +#define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */ +#define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */ +#define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */ +#define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */ +#define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */ +#define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */ + +#define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */ + /* NOTE: There is no reason to use this under */ + /* Linux, and it will cause odd hardware */ + /* behavior and possibly random segfaults and */ + /* lockups if enabled. */ + +/* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */ +#define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */ +#define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */ + + +#define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */ + /* NOTE: This bit must always be enabled */ +#define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */ +#define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */ +#define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */ +#define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */ +#define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */ +#define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */ +#define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */ +#define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */ +#define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */ +#define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */ +#define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */ +#define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */ +#define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */ + +#define WC 0x10 /* Wall Clock register */ +#define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */ +#define WC_SAMPLECOUNTER 0x14060010 +#define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */ + /* NOTE: Each channel takes 1/64th of a sample */ + /* period to be serviced. */ + +#define HCFG 0x14 /* Hardware config register */ + /* NOTE: There is no reason to use the legacy */ + /* SoundBlaster emulation stuff described below */ + /* under Linux, and all kinds of weird hardware */ + /* behavior can result if you try. Don't. */ +#define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */ +#define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */ +#define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */ +#define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */ +#define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */ +#define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */ +#define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */ +#define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */ +#define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */ +#define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */ +#define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */ +#define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */ + /* NOTE: The rest of the bits in this register */ + /* _are_ relevant under Linux. */ +#define HCFG_PUSH_BUTTON_ENABLE 0x00100000 /* Enables Volume Inc/Dec and Mute functions */ +#define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */ +#define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */ +#define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */ + +/* Specific to Alice2, CA0102 */ +#define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */ +#define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */ +#define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */ + /* will automatically mute their output when */ + /* they are not rate-locked to the external */ + /* async audio source */ +#define HCFG_AUTOMUTE_SPDIF 0x00004000 /* When set, the async sample rate convertors */ + /* will automatically mute their output when */ + /* the SPDIF V-bit indicates invalid audio */ +#define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */ +#define HCFG_SLOW_RAMP 0x00001000 /* Increases Send Smoothing time constant */ +/* 0x00000800 not used on Alice2 */ +#define HCFG_PHASE_TRACK_MASK 0x00000700 /* When set, forces corresponding input to */ + /* phase track the previous input. */ + /* I2S0 can phase track the last S/PDIF input */ +#define HCFG_I2S_ASRC_ENABLE 0x00000070 /* When set, enables asynchronous sample rate */ + /* conversion for the corresponding */ + /* I2S format input */ +/* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */ + + + +/* Older chips */ +#define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */ +#define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */ +#define HCFG_GPINPUT0 0x00004000 /* External pin112 */ +#define HCFG_GPINPUT1 0x00002000 /* External pin110 */ +#define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */ +#define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */ +#define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */ +#define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */ +#define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */ +#define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */ + /* 1 = Force all 3 async digital inputs to use */ + /* the same async sample rate tracker (ZVIDEO) */ +#define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */ +#define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */ +#define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */ +#define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */ +#define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */ + /* will automatically mute their output when */ + /* they are not rate-locked to the external */ + /* async audio source */ +#define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */ + /* NOTE: This should generally never be used. */ +#define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */ + /* NOTE: This should generally never be used. */ +#define HCFG_LOCKTANKCACHE 0x01020014 +#define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */ + /* NOTE: This is a 'cheap' way to implement a */ + /* master mute function on the mute button, and */ + /* in general should not be used unless a more */ + /* sophisticated master mute function has not */ + /* been written. */ +#define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */ + /* Should be set to 1 when the EMU10K1 is */ + /* completely initialized. */ + +//For Audigy, MPU port move to 0x70-0x74 ptr register + +#define MUDATA 0x18 /* MPU401 data register (8 bits) */ + +#define MUCMD 0x19 /* MPU401 command register (8 bits) */ +#define MUCMD_RESET 0xff /* RESET command */ +#define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */ + /* NOTE: All other commands are ignored */ + +#define MUSTAT MUCMD /* MPU401 status register (8 bits) */ +#define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */ +#define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */ + +#define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */ +#define A_GPINPUT_MASK 0xff00 +#define A_GPOUTPUT_MASK 0x00ff + +// Audigy output/GPIO stuff taken from the kX drivers +#define A_IOCFG_GPOUT0 0x0044 /* analog/digital */ +#define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */ +#define A_IOCFG_ENABLE_DIGITAL 0x0004 +#define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080 +#define A_IOCFG_UNKNOWN_20 0x0020 +#define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */ +#define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */ +#define A_IOCFG_GPOUT2 0x0001 /* IR */ +#define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */ + /* + digital for generic 10k2 */ +#define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */ +#define A_IOCFG_FRONT_JACK 0x4000 +#define A_IOCFG_REAR_JACK 0x8000 +#define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */ + +/* outputs: + * for audigy2 platinum: 0xa00 + * for a2 platinum ex: 0x1c00 + * for a1 platinum: 0x0 + */ + +#define TIMER 0x1a /* Timer terminal count register */ + /* NOTE: After the rate is changed, a maximum */ + /* of 1024 sample periods should be allowed */ + /* before the new rate is guaranteed accurate. */ +#define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */ + /* 0 == 1024 periods, [1..4] are not useful */ +#define TIMER_RATE 0x0a00001a + +#define AC97DATA 0x1c /* AC97 register set data register (16 bit) */ + +#define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */ +#define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */ +#define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */ + +/* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */ +#define PTR2 0x20 /* Indexed register set pointer register */ +#define DATA2 0x24 /* Indexed register set data register */ +#define IPR2 0x28 /* P16V interrupt pending register */ +#define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */ +#define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */ +#define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */ +#define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */ + /* 0x00000100 Playback. Only in once per period. + * 0x00110000 Capture. Int on half buffer. + */ +#define INTE2 0x2c /* P16V Interrupt enable register. */ +#define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */ +#define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */ +#define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */ +#define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */ +#define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */ +#define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */ +#define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */ +#define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */ +#define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */ +#define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */ +#define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */ + /* 0x00000000 2-channel output. */ + /* 0x00000200 8-channel output. */ + /* 0x00000004 pauses stream/irq fail. */ + /* Rest of bits no nothing to sound output */ + /* bit 0: Enable P16V audio. + * bit 1: Lock P16V record memory cache. + * bit 2: Lock P16V playback memory cache. + * bit 3: Dummy record insert zero samples. + * bit 8: Record 8-channel in phase. + * bit 9: Playback 8-channel in phase. + * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute. + * bit 13: Playback mixer enable. + * bit 14: Route SRC48 mixer output to fx engine. + * bit 15: Enable IEEE 1394 chip. + */ +#define IPR3 0x38 /* Cdif interrupt pending register */ +#define INTE3 0x3c /* Cdif interrupt enable register. */ +/************************************************************************************************/ +/* PCI function 1 registers, address = <val> + PCIBASE1 */ +/************************************************************************************************/ + +#define JOYSTICK1 0x00 /* Analog joystick port register */ +#define JOYSTICK2 0x01 /* Analog joystick port register */ +#define JOYSTICK3 0x02 /* Analog joystick port register */ +#define JOYSTICK4 0x03 /* Analog joystick port register */ +#define JOYSTICK5 0x04 /* Analog joystick port register */ +#define JOYSTICK6 0x05 /* Analog joystick port register */ +#define JOYSTICK7 0x06 /* Analog joystick port register */ +#define JOYSTICK8 0x07 /* Analog joystick port register */ + +/* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */ +/* When reading, use these bitfields: */ +#define JOYSTICK_BUTTONS 0x0f /* Joystick button data */ +#define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */ + + +/********************************************************************************************************/ +/* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */ +/********************************************************************************************************/ + +#define CPF 0x00 /* Current pitch and fraction register */ +#define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */ +#define CPF_CURRENTPITCH 0x10100000 +#define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */ +#define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */ +#define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */ + +#define PTRX 0x01 /* Pitch target and send A/B amounts register */ +#define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */ +#define PTRX_PITCHTARGET 0x10100001 +#define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */ +#define PTRX_FXSENDAMOUNT_A 0x08080001 +#define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */ +#define PTRX_FXSENDAMOUNT_B 0x08000001 + +#define CVCF 0x02 /* Current volume and filter cutoff register */ +#define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */ +#define CVCF_CURRENTVOL 0x10100002 +#define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */ +#define CVCF_CURRENTFILTER 0x10000002 + +#define VTFT 0x03 /* Volume target and filter cutoff target register */ +#define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */ +#define VTFT_VOLUMETARGET 0x10100003 +#define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */ +#define VTFT_FILTERTARGET 0x10000003 + +#define Z1 0x05 /* Filter delay memory 1 register */ + +#define Z2 0x04 /* Filter delay memory 2 register */ + +#define PSST 0x06 /* Send C amount and loop start address register */ +#define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */ + +#define PSST_FXSENDAMOUNT_C 0x08180006 + +#define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */ +#define PSST_LOOPSTARTADDR 0x18000006 + +#define DSL 0x07 /* Send D amount and loop start address register */ +#define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */ + +#define DSL_FXSENDAMOUNT_D 0x08180007 + +#define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */ +#define DSL_LOOPENDADDR 0x18000007 + +#define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */ +#define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */ +#define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */ + /* 1 == full band, 7 == lowpass */ + /* ROM 0 is used when pitch shifting downward or less */ + /* then 3 semitones upward. Increasingly higher ROM */ + /* numbers are used, typically in steps of 3 semitones, */ + /* as upward pitch shifting is performed. */ +#define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */ +#define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */ +#define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */ +#define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */ +#define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */ +#define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */ +#define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */ +#define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */ +#define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */ +#define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */ +#define CCCA_CURRADDR 0x18000008 + +#define CCR 0x09 /* Cache control register */ +#define CCR_CACHEINVALIDSIZE 0x07190009 +#define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */ +#define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */ +#define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */ +#define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */ +#define CCR_READADDRESS 0x06100009 +#define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */ +#define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */ + /* NOTE: This is valid only if CACHELOOPFLAG is set */ +#define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */ +#define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */ + +#define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */ + /* NOTE: This register is normally not used */ +#define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */ + +#define FXRT 0x0b /* Effects send routing register */ + /* NOTE: It is illegal to assign the same routing to */ + /* two effects sends. */ +#define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */ +#define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */ +#define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */ +#define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */ + +#define A_HR 0x0b /* High Resolution. 24bit playback from host to DSP. */ +#define MAPA 0x0c /* Cache map A */ + +#define MAPB 0x0d /* Cache map B */ + +#define MAP_PTE_MASK0 0xfffff000 /* The 20 MSBs of the PTE indexed by the PTI */ +#define MAP_PTI_MASK0 0x00000fff /* The 12 bit index to one of the 4096 PTE dwords */ + +#define MAP_PTE_MASK1 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */ +#define MAP_PTI_MASK1 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */ + +/* 0x0e, 0x0f: Not used */ + +#define ENVVOL 0x10 /* Volume envelope register */ +#define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */ + /* 0x8000-n == 666*n usec delay */ + +#define ATKHLDV 0x11 /* Volume envelope hold and attack register */ +#define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */ +#define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */ +#define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */ + /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */ + +#define DCYSUSV 0x12 /* Volume envelope sustain and decay register */ +#define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */ +#define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ +#define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */ + /* this channel and from writing to pitch, filter and */ + /* volume targets. */ +#define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */ + /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */ + +#define LFOVAL1 0x13 /* Modulation LFO value */ +#define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */ + /* 0x8000-n == 666*n usec delay */ + +#define ENVVAL 0x14 /* Modulation envelope register */ +#define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */ + /* 0x8000-n == 666*n usec delay */ + +#define ATKHLDM 0x15 /* Modulation envelope hold and attack register */ +#define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */ +#define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */ +#define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */ + /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */ + +#define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */ +#define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */ +#define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */ +#define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */ + /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */ + +#define LFOVAL2 0x17 /* Vibrato LFO register */ +#define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */ + /* 0x8000-n == 666*n usec delay */ + +#define IP 0x18 /* Initial pitch register */ +#define IP_MASK 0x0000ffff /* Exponential initial pitch shift */ + /* 4 bits of octave, 12 bits of fractional octave */ +#define IP_UNITY 0x0000e000 /* Unity pitch shift */ + +#define IFATN 0x19 /* Initial filter cutoff and attenuation register */ +#define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */ + /* 6 most significant bits are semitones */ + /* 2 least significant bits are fractions */ +#define IFATN_FILTERCUTOFF 0x08080019 +#define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */ +#define IFATN_ATTENUATION 0x08000019 + + +#define PEFE 0x1a /* Pitch envelope and filter envelope amount register */ +#define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */ + /* Signed 2's complement, +/- one octave peak extremes */ +#define PEFE_PITCHAMOUNT 0x0808001a +#define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */ + /* Signed 2's complement, +/- six octaves peak extremes */ +#define PEFE_FILTERAMOUNT 0x0800001a +#define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */ +#define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */ + /* Signed 2's complement, +/- one octave extremes */ +#define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */ + /* Signed 2's complement, +/- three octave extremes */ + + +#define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */ +#define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */ + /* Signed 2's complement, with +/- 12dB extremes */ + +#define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */ + /* ??Hz steps, maximum of ?? Hz. */ +#define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */ +#define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */ + /* Signed 2's complement, +/- one octave extremes */ +#define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */ + /* 0.039Hz steps, maximum of 9.85 Hz. */ + +#define TEMPENV 0x1e /* Tempory envelope register */ +#define TEMPENV_MASK 0x0000ffff /* 16-bit value */ + /* NOTE: All channels contain internal variables; do */ + /* not write to these locations. */ + +/* 0x1f: not used */ + +#define CD0 0x20 /* Cache data 0 register */ +#define CD1 0x21 /* Cache data 1 register */ +#define CD2 0x22 /* Cache data 2 register */ +#define CD3 0x23 /* Cache data 3 register */ +#define CD4 0x24 /* Cache data 4 register */ +#define CD5 0x25 /* Cache data 5 register */ +#define CD6 0x26 /* Cache data 6 register */ +#define CD7 0x27 /* Cache data 7 register */ +#define CD8 0x28 /* Cache data 8 register */ +#define CD9 0x29 /* Cache data 9 register */ +#define CDA 0x2a /* Cache data A register */ +#define CDB 0x2b /* Cache data B register */ +#define CDC 0x2c /* Cache data C register */ +#define CDD 0x2d /* Cache data D register */ +#define CDE 0x2e /* Cache data E register */ +#define CDF 0x2f /* Cache data F register */ + +/* 0x30-3f seem to be the same as 0x20-2f */ + +#define PTB 0x40 /* Page table base register */ +#define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */ + +#define TCB 0x41 /* Tank cache base register */ +#define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */ + +#define ADCCR 0x42 /* ADC sample rate/stereo control register */ +#define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */ +#define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */ + /* NOTE: To guarantee phase coherency, both channels */ + /* must be disabled prior to enabling both channels. */ +#define A_ADCCR_RCHANENABLE 0x00000020 +#define A_ADCCR_LCHANENABLE 0x00000010 + +#define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */ +#define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */ +#define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */ +#define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */ +#define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */ +#define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */ +#define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */ +#define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */ +#define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */ +#define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */ +#define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */ +#define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */ +#define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */ + +#define FXWC 0x43 /* FX output write channels register */ + /* When set, each bit enables the writing of the */ + /* corresponding FX output channel (internal registers */ + /* 0x20-0x3f) to host memory. This mode of recording */ + /* is 16bit, 48KHz only. All 32 channels can be enabled */ + /* simultaneously. */ + +#define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */ +#define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */ +#define FXWC_DEFAULTROUTE_A (1<<12) +#define FXWC_DEFAULTROUTE_D (1<<13) +#define FXWC_ADCLEFT (1<<18) +#define FXWC_CDROMSPDIFLEFT (1<<18) +#define FXWC_ADCRIGHT (1<<19) +#define FXWC_CDROMSPDIFRIGHT (1<<19) +#define FXWC_MIC (1<<20) +#define FXWC_ZOOMLEFT (1<<20) +#define FXWC_ZOOMRIGHT (1<<21) +#define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */ +#define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */ + +#define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */ + +#define TCBS 0x44 /* Tank cache buffer size register */ +#define TCBS_MASK 0x00000007 /* Tank cache buffer size field */ +#define TCBS_BUFFSIZE_16K 0x00000000 +#define TCBS_BUFFSIZE_32K 0x00000001 +#define TCBS_BUFFSIZE_64K 0x00000002 +#define TCBS_BUFFSIZE_128K 0x00000003 +#define TCBS_BUFFSIZE_256K 0x00000004 +#define TCBS_BUFFSIZE_512K 0x00000005 +#define TCBS_BUFFSIZE_1024K 0x00000006 +#define TCBS_BUFFSIZE_2048K 0x00000007 + +#define MICBA 0x45 /* AC97 microphone buffer address register */ +#define MICBA_MASK 0xfffff000 /* 20 bit base address */ + +#define ADCBA 0x46 /* ADC buffer address register */ +#define ADCBA_MASK 0xfffff000 /* 20 bit base address */ + +#define FXBA 0x47 /* FX Buffer Address */ +#define FXBA_MASK 0xfffff000 /* 20 bit base address */ + +#define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */ + +#define MICBS 0x49 /* Microphone buffer size register */ + +#define ADCBS 0x4a /* ADC buffer size register */ + +#define FXBS 0x4b /* FX buffer size register */ + +/* register: 0x4c..4f: ffff-ffff current amounts, per-channel */ + +/* The following mask values define the size of the ADC, MIX and FX buffers in bytes */ +#define ADCBS_BUFSIZE_NONE 0x00000000 +#define ADCBS_BUFSIZE_384 0x00000001 +#define ADCBS_BUFSIZE_448 0x00000002 +#define ADCBS_BUFSIZE_512 0x00000003 +#define ADCBS_BUFSIZE_640 0x00000004 +#define ADCBS_BUFSIZE_768 0x00000005 +#define ADCBS_BUFSIZE_896 0x00000006 +#define ADCBS_BUFSIZE_1024 0x00000007 +#define ADCBS_BUFSIZE_1280 0x00000008 +#define ADCBS_BUFSIZE_1536 0x00000009 +#define ADCBS_BUFSIZE_1792 0x0000000a +#define ADCBS_BUFSIZE_2048 0x0000000b +#define ADCBS_BUFSIZE_2560 0x0000000c +#define ADCBS_BUFSIZE_3072 0x0000000d +#define ADCBS_BUFSIZE_3584 0x0000000e +#define ADCBS_BUFSIZE_4096 0x0000000f +#define ADCBS_BUFSIZE_5120 0x00000010 +#define ADCBS_BUFSIZE_6144 0x00000011 +#define ADCBS_BUFSIZE_7168 0x00000012 +#define ADCBS_BUFSIZE_8192 0x00000013 +#define ADCBS_BUFSIZE_10240 0x00000014 +#define ADCBS_BUFSIZE_12288 0x00000015 +#define ADCBS_BUFSIZE_14366 0x00000016 +#define ADCBS_BUFSIZE_16384 0x00000017 +#define ADCBS_BUFSIZE_20480 0x00000018 +#define ADCBS_BUFSIZE_24576 0x00000019 +#define ADCBS_BUFSIZE_28672 0x0000001a +#define ADCBS_BUFSIZE_32768 0x0000001b +#define ADCBS_BUFSIZE_40960 0x0000001c +#define ADCBS_BUFSIZE_49152 0x0000001d +#define ADCBS_BUFSIZE_57344 0x0000001e +#define ADCBS_BUFSIZE_65536 0x0000001f + +/* Current Send B, A Amounts */ +#define A_CSBA 0x4c + +/* Current Send D, C Amounts */ +#define A_CSDC 0x4d + +/* Current Send F, E Amounts */ +#define A_CSFE 0x4e + +/* Current Send H, G Amounts */ +#define A_CSHG 0x4f + + +#define CDCS 0x50 /* CD-ROM digital channel status register */ + +#define GPSCS 0x51 /* General Purpose SPDIF channel status register*/ + +#define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ + +/* S/PDIF Input C Channel Status */ +#define A_SPSC 0x52 + +#define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */ + +#define A_DBG 0x53 +#define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */ +#define A_DBG_ZC 0x40000000 /* zero tram counter */ +#define A_DBG_STEP_ADDR 0x000003ff +#define A_DBG_SATURATION_OCCURED 0x20000000 +#define A_DBG_SATURATION_ADDR 0x0ffc0000 + +// NOTE: 0x54,55,56: 64-bit +#define SPCS0 0x54 /* SPDIF output Channel Status 0 register */ + +#define SPCS1 0x55 /* SPDIF output Channel Status 1 register */ + +#define SPCS2 0x56 /* SPDIF output Channel Status 2 register */ + +#define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */ +#define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */ +#define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */ +#define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */ +#define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */ +#define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */ +#define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */ +#define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */ +#define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */ +#define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */ +#define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */ +#define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */ +#define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */ +#define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */ +#define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */ +#define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */ +#define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */ +#define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */ +#define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */ +#define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */ +#define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */ +#define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */ +#define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */ + +/* 0x57: Not used */ + +/* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */ +#define CLIEL 0x58 /* Channel loop interrupt enable low register */ + +#define CLIEH 0x59 /* Channel loop interrupt enable high register */ + +#define CLIPL 0x5a /* Channel loop interrupt pending low register */ + +#define CLIPH 0x5b /* Channel loop interrupt pending high register */ + +#define SOLEL 0x5c /* Stop on loop enable low register */ + +#define SOLEH 0x5d /* Stop on loop enable high register */ + +#define SPBYPASS 0x5e /* SPDIF BYPASS mode register */ +#define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */ +#define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */ +/* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */ +#define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */ + +#define AC97SLOT 0x5f /* additional AC97 slots enable bits */ +#define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */ +#define AC97SLOT_REAR_LEFT 0x02 /* Rear right */ +#define AC97SLOT_CNTR 0x10 /* Center enable */ +#define AC97SLOT_LFE 0x20 /* LFE enable */ + +/* PCB Revision */ +#define A_PCB 0x5f + +// NOTE: 0x60,61,62: 64-bit +#define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */ + +#define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */ + +#define ZVSRCS 0x62 /* ZVideo sample rate converter status */ + /* NOTE: This one has no SPDIFLOCKED field */ + /* Assumes sample lock */ + +/* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */ +#define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */ +#define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */ +#define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */ +#define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */ + +/* Note that these values can vary +/- by a small amount */ +#define SRCS_SPDIFRATE_44 0x0003acd9 +#define SRCS_SPDIFRATE_48 0x00040000 +#define SRCS_SPDIFRATE_96 0x00080000 + +#define MICIDX 0x63 /* Microphone recording buffer index register */ +#define MICIDX_MASK 0x0000ffff /* 16-bit value */ +#define MICIDX_IDX 0x10000063 + +#define ADCIDX 0x64 /* ADC recording buffer index register */ +#define ADCIDX_MASK 0x0000ffff /* 16 bit index field */ +#define ADCIDX_IDX 0x10000064 + +#define A_ADCIDX 0x63 +#define A_ADCIDX_IDX 0x10000063 + +#define A_MICIDX 0x64 +#define A_MICIDX_IDX 0x10000064 + +#define FXIDX 0x65 /* FX recording buffer index register */ +#define FXIDX_MASK 0x0000ffff /* 16-bit value */ +#define FXIDX_IDX 0x10000065 + +/* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */ +#define HLIEL 0x66 /* Channel half loop interrupt enable low register */ + +#define HLIEH 0x67 /* Channel half loop interrupt enable high register */ + +#define HLIPL 0x68 /* Channel half loop interrupt pending low register */ + +#define HLIPH 0x69 /* Channel half loop interrupt pending high register */ + +/* S/PDIF Host Record Index (bypasses SRC) */ +#define A_SPRI 0x6a +/* S/PDIF Host Record Address */ +#define A_SPRA 0x6b +/* S/PDIF Host Record Control */ +#define A_SPRC 0x6c +/* Delayed Interrupt Counter & Enable */ +#define A_DICE 0x6d +/* Tank Table Base */ +#define A_TTB 0x6e +/* Tank Delay Offset */ +#define A_TDOF 0x6f + +/* This is the MPU port on the card (via the game port) */ +#define A_MUDATA1 0x70 +#define A_MUCMD1 0x71 +#define A_MUSTAT1 A_MUCMD1 + +/* This is the MPU port on the Audigy Drive */ +#define A_MUDATA2 0x72 +#define A_MUCMD2 0x73 +#define A_MUSTAT2 A_MUCMD2 + +/* The next two are the Audigy equivalent of FXWC */ +/* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */ +/* Each bit selects a channel for recording */ +#define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */ +#define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */ + +/* Extended Hardware Control */ +#define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */ +#define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */ +#define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */ +#define A_SAMPLE_RATE_UNKNOWN 0xf0030001 /* Bits that can be set, but have unknown use. */ +#define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */ +#define A_SPDIF_48000 0x00000000 +#define A_SPDIF_192000 0x00000020 +#define A_SPDIF_96000 0x00000040 +#define A_SPDIF_44100 0x00000080 + +#define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */ +#define A_I2S_CAPTURE_48000 0x00000000 /* unclear if this sets the ADC rate as well. */ +#define A_I2S_CAPTURE_192000 0x00000200 +#define A_I2S_CAPTURE_96000 0x00000400 +#define A_I2S_CAPTURE_44100 0x00000800 + +#define A_PCM_RATE_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */ +#define A_PCM_48000 0x00000000 +#define A_PCM_192000 0x00002000 +#define A_PCM_96000 0x00004000 +#define A_PCM_44100 0x00008000 + +/* I2S0 Sample Rate Tracker Status */ +#define A_SRT3 0x77 + +/* I2S1 Sample Rate Tracker Status */ +#define A_SRT4 0x78 + +/* I2S2 Sample Rate Tracker Status */ +#define A_SRT5 0x79 +/* - default to 0x01080000 on my audigy 2 ZS --rlrevell */ + +/* Tank Table DMA Address */ +#define A_TTDA 0x7a +/* Tank Table DMA Data */ +#define A_TTDD 0x7b + +#define A_FXRT2 0x7c +#define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */ +#define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */ +#define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */ +#define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */ + +#define A_SENDAMOUNTS 0x7d +#define A_FXSENDAMOUNT_E_MASK 0xFF000000 +#define A_FXSENDAMOUNT_F_MASK 0x00FF0000 +#define A_FXSENDAMOUNT_G_MASK 0x0000FF00 +#define A_FXSENDAMOUNT_H_MASK 0x000000FF +/* 0x7c, 0x7e "high bit is used for filtering" */ + +/* The send amounts for this one are the same as used with the emu10k1 */ +#define A_FXRT1 0x7e +#define A_FXRT_CHANNELA 0x0000003f +#define A_FXRT_CHANNELB 0x00003f00 +#define A_FXRT_CHANNELC 0x003f0000 +#define A_FXRT_CHANNELD 0x3f000000 + +/* 0x7f: Not used */ +/* Each FX general purpose register is 32 bits in length, all bits are used */ +#define FXGPREGBASE 0x100 /* FX general purpose registers base */ +#define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */ + +#define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */ +#define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */ + +/* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */ +/* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */ +/* locations are for external TRAM. */ +#define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */ +#define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */ + +/* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */ +#define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */ +#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */ +#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */ +#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */ +#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */ +#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */ + +#define MICROCODEBASE 0x400 /* Microcode data base address */ + +/* Each DSP microcode instruction is mapped into 2 doublewords */ +/* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */ +#define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */ +#define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */ +#define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */ +#define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */ +#define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */ + + +/* Audigy Soundcard have a different instruction format */ +#define A_MICROCODEBASE 0x600 +#define A_LOWORD_OPY_MASK 0x000007ff +#define A_LOWORD_OPX_MASK 0x007ff000 +#define A_HIWORD_OPCODE_MASK 0x0f000000 +#define A_HIWORD_RESULT_MASK 0x007ff000 +#define A_HIWORD_OPA_MASK 0x000007ff + +/************************************************************************************************/ +/* EMU1010m HANA FPGA registers */ +/************************************************************************************************/ +#define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */ +#define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */ +#define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */ +#define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */ +#define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */ +#define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */ +#define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */ + /* Must be written after power on to reset DLL */ + /* One is unable to detect the Audio dock without this */ +#define EMU_HANA_WCLOCK_SRC_MASK 0x07 +#define EMU_HANA_WCLOCK_INT_48K 0x00 +#define EMU_HANA_WCLOCK_INT_44_1K 0x01 +#define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02 +#define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03 +#define EMU_HANA_WCLOCK_SYNC_BNCN 0x04 +#define EMU_HANA_WCLOCK_2ND_HANA 0x05 +#define EMU_HANA_WCLOCK_SRC_RESERVED 0x06 +#define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */ +#define EMU_HANA_WCLOCK_MULT_MASK 0x18 +#define EMU_HANA_WCLOCK_1X 0x00 +#define EMU_HANA_WCLOCK_2X 0x08 +#define EMU_HANA_WCLOCK_4X 0x10 +#define EMU_HANA_WCLOCK_MULT_RESERVED 0x18 + +#define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */ +#define EMU_HANA_DEFCLOCK_48K 0x00 +#define EMU_HANA_DEFCLOCK_44_1K 0x01 + +#define EMU_HANA_UNMUTE 0x07 /* 000000x 1 bits Mute all audio outputs */ +#define EMU_MUTE 0x00 +#define EMU_UNMUTE 0x01 + +#define EMU_HANA_FPGA_CONFIG 0x08 /* 00000xx 2 bits Config control of FPGAs */ +#define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 /* Set in order to program FPGA on Audio Dock */ +#define EMU_HANA_FPGA_CONFIG_HANA 0x02 /* Set in order to program FPGA on Hana */ + +#define EMU_HANA_IRQ_ENABLE 0x09 /* 000xxxx 4 bits IRQ Enable */ +#define EMU_HANA_IRQ_WCLK_CHANGED 0x01 +#define EMU_HANA_IRQ_ADAT 0x02 +#define EMU_HANA_IRQ_DOCK 0x04 +#define EMU_HANA_IRQ_DOCK_LOST 0x08 + +#define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */ +#define EMU_HANA_SPDIF_MODE_TX_COMSUMER 0x00 +#define EMU_HANA_SPDIF_MODE_TX_PRO 0x01 +#define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02 +#define EMU_HANA_SPDIF_MODE_RX_COMSUMER 0x00 +#define EMU_HANA_SPDIF_MODE_RX_PRO 0x04 +#define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08 +#define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10 + +#define EMU_HANA_OPTICAL_TYPE 0x0b /* 00000xx 2 bits ADAT or SPDIF in/out */ +#define EMU_HANA_OPTICAL_IN_SPDIF 0x00 +#define EMU_HANA_OPTICAL_IN_ADAT 0x01 +#define EMU_HANA_OPTICAL_OUT_SPDIF 0x00 +#define EMU_HANA_OPTICAL_OUT_ADAT 0x02 + +#define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */ +#define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00 /* HAMOA MIDI in to Alice 2 MIDI B */ +#define EMU_HANA_MIDI_IN_FROM_DOCK 0x01 /* Audio Dock MIDI in to Alice 2 MIDI B */ + +#define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */ +#define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */ +#define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02 /* MIDI 2 LED on */ +#define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04 /* SMPTE IN LED on */ +#define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08 /* SMPTE OUT LED on */ + +#define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */ +#define EMU_HANA_DOCK_LEDS_2_44K 0x01 /* 44.1 kHz LED on */ +#define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */ +#define EMU_HANA_DOCK_LEDS_2_96K 0x04 /* 96 kHz LED on */ +#define EMU_HANA_DOCK_LEDS_2_192K 0x08 /* 192 kHz LED on */ +#define EMU_HANA_DOCK_LEDS_2_LOCK 0x10 /* LOCK LED on */ +#define EMU_HANA_DOCK_LEDS_2_EXT 0x20 /* EXT LED on */ + +#define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */ +#define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01 /* Mic A Clip LED on */ +#define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02 /* Mic B Clip LED on */ +#define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04 /* Signal A Clip LED on */ +#define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08 /* Signal B Clip LED on */ +#define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10 /* Manual Clip detection */ +#define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */ + +#define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */ +#define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */ +#define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */ +#define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */ +#define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */ + +#define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */ +#define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */ +#define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */ +#define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */ +#define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */ +#define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */ +#define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */ +#define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */ +#define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */ + +#define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */ +#define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */ +#define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */ + +#define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */ +#define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */ +#define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */ +#define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */ +#define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */ +#define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */ + +/* 0x14 - 0x1f Unused R/W registers */ +#define EMU_HANA_IRQ_STATUS 0x20 /* 000xxxx 4 bits IRQ Status */ +#if 0 /* Already defined for reg 0x09 IRQ_ENABLE */ +#define EMU_HANA_IRQ_WCLK_CHANGED 0x01 +#define EMU_HANA_IRQ_ADAT 0x02 +#define EMU_HANA_IRQ_DOCK 0x04 +#define EMU_HANA_IRQ_DOCK_LOST 0x08 +#endif + +#define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */ +#define EMU_HANA_OPTION_HAMOA 0x01 /* HAMOA card present */ +#define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */ +#define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio Dock online and FPGA configured */ +#define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio Dock online and FPGA not configured */ + +#define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 */ + +#define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */ +#define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */ + +#define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */ +#define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */ + +#define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */ +#define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */ +#define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */ + +#define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */ +#define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */ + +#define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */ +#define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */ + +#define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */ +#define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */ + +#define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */ +#define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */ +/* 0x30 - 0x3f Unused Read only registers */ + +/************************************************************************************************/ +/* EMU1010m HANA Destinations */ +/************************************************************************************************/ +/* Hana, original 1010,1212,1820 using Alice2 + * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2 + * 0x01, 0x10-0x1f: 32 Elink channels to Audio Dock + * 0x01, 0x00: Dock DAC 1 Left + * 0x01, 0x04: Dock DAC 1 Right + * 0x01, 0x08: Dock DAC 2 Left + * 0x01, 0x0c: Dock DAC 2 Right + * 0x01, 0x10: Dock DAC 3 Left + * 0x01, 0x12: PHONES Left + * 0x01, 0x14: Dock DAC 3 Right + * 0x01, 0x16: PHONES Right + * 0x01, 0x18: Dock DAC 4 Left + * 0x01, 0x1a: S/PDIF Left + * 0x01, 0x1c: Dock DAC 4 Right + * 0x01, 0x1e: S/PDIF Right + * 0x02, 0x00: Hana S/PDIF Left + * 0x02, 0x01: Hana S/PDIF Right + * 0x03, 0x00: Hanoa DAC Left + * 0x03, 0x01: Hanoa DAC Right + * 0x04, 0x00-0x07: Hana ADAT + * 0x05, 0x00: I2S0 Left to Alice2 + * 0x05, 0x01: I2S0 Right to Alice2 + * 0x06, 0x00: I2S0 Left to Alice2 + * 0x06, 0x01: I2S0 Right to Alice2 + * 0x07, 0x00: I2S0 Left to Alice2 + * 0x07, 0x01: I2S0 Right to Alice2 + * + * Hana2 never released, but used Tina + * Not needed. + * + * Hana3, rev2 1010,1212,1616 using Tina + * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina + * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock + * 0x01, 0x00: Dock DAC 1 Left + * 0x01, 0x04: Dock DAC 1 Right + * 0x01, 0x08: Dock DAC 2 Left + * 0x01, 0x0c: Dock DAC 2 Right + * 0x01, 0x10: Dock DAC 3 Left + * 0x01, 0x12: Dock S/PDIF Left + * 0x01, 0x14: Dock DAC 3 Right + * 0x01, 0x16: Dock S/PDIF Right + * 0x01, 0x18-0x1f: Dock ADAT 0-7 + * 0x02, 0x00: Hana3 S/PDIF Left + * 0x02, 0x01: Hana3 S/PDIF Right + * 0x03, 0x00: Hanoa DAC Left + * 0x03, 0x01: Hanoa DAC Right + * 0x04, 0x00-0x07: Hana3 ADAT 0-7 + * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina + * 0x06-0x07: Not used + * + * HanaLite, rev1 0404 using Alice2 + * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2 + * 0x01: Not used + * 0x02, 0x00: S/PDIF Left + * 0x02, 0x01: S/PDIF Right + * 0x03, 0x00: DAC Left + * 0x03, 0x01: DAC Right + * 0x04-0x07: Not used + * + * HanaLiteLite, rev2 0404 using Alice2 + * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2 + * 0x01: Not used + * 0x02, 0x00: S/PDIF Left + * 0x02, 0x01: S/PDIF Right + * 0x03, 0x00: DAC Left + * 0x03, 0x01: DAC Right + * 0x04-0x07: Not used + * + * Mana, Cardbus 1616 using Tina2 + * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2 + * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock + * 0x01, 0x00: Dock DAC 1 Left + * 0x01, 0x04: Dock DAC 1 Right + * 0x01, 0x08: Dock DAC 2 Left + * 0x01, 0x0c: Dock DAC 2 Right + * 0x01, 0x10: Dock DAC 3 Left + * 0x01, 0x12: Dock S/PDIF Left + * 0x01, 0x14: Dock DAC 3 Right + * 0x01, 0x16: Dock S/PDIF Right + * 0x01, 0x18-0x1f: Dock ADAT 0-7 + * 0x02: Not used + * 0x03, 0x00: Mana DAC Left + * 0x03, 0x01: Mana DAC Right + * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2 + * 0x05-0x07: Not used + * + * + */ +/* 32-bit destinations of signal in the Hana FPGA. Destinations are either + * physical outputs of Hana, or outputs going to Alice2 (audigy) for capture + * - 16 x EMU_DST_ALICE2_EMU32_X. + */ +/* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */ +/* EMU_DST_ALICE2_EMU32_X - data channels from Hana to Alice2 used for capture. + * Which data is fed into a EMU_DST_ALICE2_EMU32_X channel in Hana depends on + * setup of mixer control for each destination - see emumixer.c - + * snd_emu1010_output_enum_ctls[], snd_emu1010_input_enum_ctls[] + */ +#define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_4 0x0003 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_5 0x0004 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_6 0x0005 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_7 0x0006 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_8 0x0007 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_9 0x0008 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_A 0x0009 /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_B 0x000a /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_C 0x000b /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_D 0x000c /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_E 0x000d /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_ALICE2_EMU32_F 0x000e /* 16 EMU32 channels to Alice2 +0 to +0xf */ +#define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Audio Dock DAC1 Left, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Audio Dock DAC1 Left, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Audio Dock DAC1 Left, 4th or 192kHz */ +#define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC1_RIGHT2 0x0105 /* Audio Dock DAC1 Right, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC1_RIGHT3 0x0106 /* Audio Dock DAC1 Right, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC1_RIGHT4 0x0107 /* Audio Dock DAC1 Right, 4th or 192kHz */ +#define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Audio Dock DAC2 Left, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Audio Dock DAC2 Left, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Audio Dock DAC2 Left, 4th or 192kHz */ +#define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC2_RIGHT2 0x010d /* Audio Dock DAC2 Right, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC2_RIGHT3 0x010e /* Audio Dock DAC2 Right, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC2_RIGHT4 0x010f /* Audio Dock DAC2 Right, 4th or 192kHz */ +#define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Audio Dock DAC1 Left, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Audio Dock DAC1 Left, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Audio Dock DAC1 Left, 4th or 192kHz */ +#define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */ +#define EMU_DST_DOCK_PHONES_LEFT2 0x0113 /* Audio Dock PHONES Left, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC3_RIGHT2 0x0115 /* Audio Dock DAC1 Right, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC3_RIGHT3 0x0116 /* Audio Dock DAC1 Right, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC3_RIGHT4 0x0117 /* Audio Dock DAC1 Right, 4th or 192kHz */ +#define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */ +#define EMU_DST_DOCK_PHONES_RIGHT2 0x0117 /* Audio Dock PHONES Right, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Audio Dock DAC2 Left, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Audio Dock DAC2 Left, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Audio Dock DAC2 Left, 4th or 192kHz */ +#define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */ +#define EMU_DST_DOCK_SPDIF_LEFT2 0x011b /* Audio Dock SPDIF Left, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */ +#define EMU_DST_DOCK_DAC4_RIGHT2 0x011d /* Audio Dock DAC2 Right, 2nd or 96kHz */ +#define EMU_DST_DOCK_DAC4_RIGHT3 0x011e /* Audio Dock DAC2 Right, 3rd or 192kHz */ +#define EMU_DST_DOCK_DAC4_RIGHT4 0x011f /* Audio Dock DAC2 Right, 4th or 192kHz */ +#define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */ +#define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */ +#define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */ +#define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */ +#define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */ +#define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */ +#define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */ +#define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */ +#define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */ +#define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Hamoa DAC Left, 4th or 192kHz */ +#define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */ +#define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */ +#define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */ +#define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */ +#define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */ +#define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */ +#define EMU_DST_ALICE_I2S0_RIGHT 0x0501 /* Alice2 I2S0 Right */ +#define EMU_DST_ALICE_I2S1_LEFT 0x0600 /* Alice2 I2S1 Left */ +#define EMU_DST_ALICE_I2S1_RIGHT 0x0601 /* Alice2 I2S1 Right */ +#define EMU_DST_ALICE_I2S2_LEFT 0x0700 /* Alice2 I2S2 Left */ +#define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */ + +/* Additional destinations for 1616(M)/Microdock */ +/* Microdock S/PDIF OUT Left, 1st or 48kHz only */ +#define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112 +/* Microdock S/PDIF OUT Left, 2nd or 96kHz */ +#define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113 +/* Microdock S/PDIF OUT Right, 1st or 48kHz only */ +#define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116 +/* Microdock S/PDIF OUT Right, 2nd or 96kHz */ +#define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117 +/* Microdock S/PDIF ADAT 8 channel out +8 to +f */ +#define EMU_DST_MDOCK_ADAT 0x0118 + +/* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ +#define EMU_DST_MANA_DAC_LEFT 0x0300 +/* Headphone jack on 1010 cardbus? 44.1/48kHz only? */ +#define EMU_DST_MANA_DAC_RIGHT 0x0301 + +/************************************************************************************************/ +/* EMU1010m HANA Sources */ +/************************************************************************************************/ +/* Hana, original 1010,1212,1820 using Alice2 + * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00,0x00-0x1f: Silence + * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock + * 0x01, 0x00: Dock Mic A + * 0x01, 0x04: Dock Mic B + * 0x01, 0x08: Dock ADC 1 Left + * 0x01, 0x0c: Dock ADC 1 Right + * 0x01, 0x10: Dock ADC 2 Left + * 0x01, 0x14: Dock ADC 2 Right + * 0x01, 0x18: Dock ADC 3 Left + * 0x01, 0x1c: Dock ADC 3 Right + * 0x02, 0x00: Hana ADC Left + * 0x02, 0x01: Hana ADC Right + * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output + * 0x04, 0x00-0x07: Hana ADAT + * 0x05, 0x00: Hana S/PDIF Left + * 0x05, 0x01: Hana S/PDIF Right + * 0x06-0x07: Not used + * + * Hana2 never released, but used Tina + * Not needed. + * + * Hana3, rev2 1010,1212,1616 using Tina + * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00,0x00-0x1f: Silence + * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock + * 0x01, 0x00: Dock Mic A + * 0x01, 0x04: Dock Mic B + * 0x01, 0x08: Dock ADC 1 Left + * 0x01, 0x0c: Dock ADC 1 Right + * 0x01, 0x10: Dock ADC 2 Left + * 0x01, 0x12: Dock S/PDIF Left + * 0x01, 0x14: Dock ADC 2 Right + * 0x01, 0x16: Dock S/PDIF Right + * 0x01, 0x18-0x1f: Dock ADAT 0-7 + * 0x01, 0x18: Dock ADC 3 Left + * 0x01, 0x1c: Dock ADC 3 Right + * 0x02, 0x00: Hanoa ADC Left + * 0x02, 0x01: Hanoa ADC Right + * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output + * 0x04, 0x00-0x07: Hana3 ADAT + * 0x05, 0x00: Hana3 S/PDIF Left + * 0x05, 0x01: Hana3 S/PDIF Right + * 0x06-0x07: Not used + * + * HanaLite, rev1 0404 using Alice2 + * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00,0x00-0x1f: Silence + * 0x01: Not used + * 0x02, 0x00: ADC Left + * 0x02, 0x01: ADC Right + * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output + * 0x04: Not used + * 0x05, 0x00: S/PDIF Left + * 0x05, 0x01: S/PDIF Right + * 0x06-0x07: Not used + * + * HanaLiteLite, rev2 0404 using Alice2 + * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00,0x00-0x1f: Silence + * 0x01: Not used + * 0x02, 0x00: ADC Left + * 0x02, 0x01: ADC Right + * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output + * 0x04: Not used + * 0x05, 0x00: S/PDIF Left + * 0x05, 0x01: S/PDIF Right + * 0x06-0x07: Not used + * + * Mana, Cardbus 1616 using Tina2 + * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz + * 0x00,0x00-0x1f: Silence + * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock + * 0x01, 0x00: Dock Mic A + * 0x01, 0x04: Dock Mic B + * 0x01, 0x08: Dock ADC 1 Left + * 0x01, 0x0c: Dock ADC 1 Right + * 0x01, 0x10: Dock ADC 2 Left + * 0x01, 0x12: Dock S/PDIF Left + * 0x01, 0x14: Dock ADC 2 Right + * 0x01, 0x16: Dock S/PDIF Right + * 0x01, 0x18-0x1f: Dock ADAT 0-7 + * 0x01, 0x18: Dock ADC 3 Left + * 0x01, 0x1c: Dock ADC 3 Right + * 0x02: Not used + * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output + * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output + * 0x04-0x07: Not used + * + */ + +/* 32-bit sources of signal in the Hana FPGA. The sources are routed to + * destinations using mixer control for each destination - see emumixer.c + * Sources are either physical inputs of FPGA, + * or outputs from Alice (audigy) - 16 x EMU_SRC_ALICE_EMU32A + + * 16 x EMU_SRC_ALICE_EMU32B + */ +#define EMU_SRC_SILENCE 0x0000 /* Silence */ +#define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */ +#define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */ +#define EMU_SRC_DOCK_MIC_A3 0x0102 /* Audio Dock Mic A, 3rd or 192kHz */ +#define EMU_SRC_DOCK_MIC_A4 0x0103 /* Audio Dock Mic A, 4th or 192kHz */ +#define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */ +#define EMU_SRC_DOCK_MIC_B2 0x0105 /* Audio Dock Mic B, 2nd or 96kHz */ +#define EMU_SRC_DOCK_MIC_B3 0x0106 /* Audio Dock Mic B, 3rd or 192kHz */ +#define EMU_SRC_DOCK_MIC_B4 0x0107 /* Audio Dock Mic B, 4th or 192kHz */ +#define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */ +#define EMU_SRC_DOCK_ADC1_LEFT2 0x0109 /* Audio Dock ADC1 Left, 2nd or 96kHz */ +#define EMU_SRC_DOCK_ADC1_LEFT3 0x010a /* Audio Dock ADC1 Left, 3rd or 192kHz */ +#define EMU_SRC_DOCK_ADC1_LEFT4 0x010b /* Audio Dock ADC1 Left, 4th or 192kHz */ +#define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */ +#define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d /* Audio Dock ADC1 Right, 2nd or 96kHz */ +#define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e /* Audio Dock ADC1 Right, 3rd or 192kHz */ +#define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f /* Audio Dock ADC1 Right, 4th or 192kHz */ +#define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */ +#define EMU_SRC_DOCK_ADC2_LEFT2 0x0111 /* Audio Dock ADC2 Left, 2nd or 96kHz */ +#define EMU_SRC_DOCK_ADC2_LEFT3 0x0112 /* Audio Dock ADC2 Left, 3rd or 192kHz */ +#define EMU_SRC_DOCK_ADC2_LEFT4 0x0113 /* Audio Dock ADC2 Left, 4th or 192kHz */ +#define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */ +#define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115 /* Audio Dock ADC2 Right, 2nd or 96kHz */ +#define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116 /* Audio Dock ADC2 Right, 3rd or 192kHz */ +#define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117 /* Audio Dock ADC2 Right, 4th or 192kHz */ +#define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */ +#define EMU_SRC_DOCK_ADC3_LEFT2 0x0119 /* Audio Dock ADC3 Left, 2nd or 96kHz */ +#define EMU_SRC_DOCK_ADC3_LEFT3 0x011a /* Audio Dock ADC3 Left, 3rd or 192kHz */ +#define EMU_SRC_DOCK_ADC3_LEFT4 0x011b /* Audio Dock ADC3 Left, 4th or 192kHz */ +#define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */ +#define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d /* Audio Dock ADC3 Right, 2nd or 96kHz */ +#define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e /* Audio Dock ADC3 Right, 3rd or 192kHz */ +#define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f /* Audio Dock ADC3 Right, 4th or 192kHz */ +#define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */ +#define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */ +#define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */ +#define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */ +#define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */ +#define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */ +#define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */ +#define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */ +#define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */ +#define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */ +#define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */ +#define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */ +#define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */ +#define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */ +#define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */ + +/* Additional inputs for 1616(M)/Microdock */ +/* Microdock S/PDIF Left, 1st or 48kHz only */ +#define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112 +/* Microdock S/PDIF Left, 2nd or 96kHz */ +#define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113 +/* Microdock S/PDIF Right, 1st or 48kHz only */ +#define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116 +/* Microdock S/PDIF Right, 2nd or 96kHz */ +#define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117 +/* Microdock ADAT 8 channel in +8 to +f */ +#define EMU_SRC_MDOCK_ADAT 0x0118 + +/* 0x600 and 0x700 no used */ + +/* ------------------- STRUCTURES -------------------- */ + +enum { + EMU10K1_EFX, + EMU10K1_PCM, + EMU10K1_SYNTH, + EMU10K1_MIDI +}; + +struct snd_emu10k1; + +struct snd_emu10k1_voice { + struct snd_emu10k1 *emu; + int number; + unsigned int use: 1, + pcm: 1, + efx: 1, + synth: 1, + midi: 1; + void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); + + struct snd_emu10k1_pcm *epcm; +}; + +enum { + PLAYBACK_EMUVOICE, + PLAYBACK_EFX, + CAPTURE_AC97ADC, + CAPTURE_AC97MIC, + CAPTURE_EFX +}; + +struct snd_emu10k1_pcm { + struct snd_emu10k1 *emu; + int type; + struct snd_pcm_substream *substream; + struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK]; + struct snd_emu10k1_voice *extra; + unsigned short running; + unsigned short first_ptr; + struct snd_util_memblk *memblk; + unsigned int start_addr; + unsigned int ccca_start_addr; + unsigned int capture_ipr; /* interrupt acknowledge mask */ + unsigned int capture_inte; /* interrupt enable mask */ + unsigned int capture_ba_reg; /* buffer address register */ + unsigned int capture_bs_reg; /* buffer size register */ + unsigned int capture_idx_reg; /* buffer index register */ + unsigned int capture_cr_val; /* control value */ + unsigned int capture_cr_val2; /* control value2 (for audigy) */ + unsigned int capture_bs_val; /* buffer size value */ + unsigned int capture_bufsize; /* buffer size in bytes */ +}; + +struct snd_emu10k1_pcm_mixer { + /* mono, left, right x 8 sends (4 on emu10k1) */ + unsigned char send_routing[3][8]; + unsigned char send_volume[3][8]; + unsigned short attn[3]; + struct snd_emu10k1_pcm *epcm; +}; + +#define snd_emu10k1_compose_send_routing(route) \ +((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16) + +#define snd_emu10k1_compose_audigy_fxrt1(route) \ +((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24)) + +#define snd_emu10k1_compose_audigy_fxrt2(route) \ +((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24)) + +struct snd_emu10k1_memblk { + struct snd_util_memblk mem; + /* private part */ + int first_page, last_page, pages, mapped_page; + unsigned int map_locked; + struct list_head mapped_link; + struct list_head mapped_order_link; +}; + +#define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1))) + +#define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16 + +struct snd_emu10k1_fx8010_ctl { + struct list_head list; /* list link container */ + unsigned int vcount; + unsigned int count; /* count of GPR (1..16) */ + unsigned short gpr[32]; /* GPR number(s) */ + unsigned int value[32]; + unsigned int min; /* minimum range */ + unsigned int max; /* maximum range */ + unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ + struct snd_kcontrol *kcontrol; +}; + +typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data); + +struct snd_emu10k1_fx8010_irq { + struct snd_emu10k1_fx8010_irq *next; + snd_fx8010_irq_handler_t *handler; + unsigned short gpr_running; + void *private_data; +}; + +struct snd_emu10k1_fx8010_pcm { + unsigned int valid: 1, + opened: 1, + active: 1; + unsigned int channels; /* 16-bit channels count */ + unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */ + unsigned int buffer_size; /* count of buffered samples */ + unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */ + unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */ + unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */ + unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */ + unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */ + unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */ + unsigned char etram[32]; /* external TRAM address & data */ + struct snd_pcm_indirect pcm_rec; + unsigned int tram_pos; + unsigned int tram_shift; + struct snd_emu10k1_fx8010_irq irq; +}; + +struct snd_emu10k1_fx8010 { + unsigned short fxbus_mask; /* used FX buses (bitmask) */ + unsigned short extin_mask; /* used external inputs (bitmask) */ + unsigned short extout_mask; /* used external outputs (bitmask) */ + unsigned short pad1; + unsigned int itram_size; /* internal TRAM size in samples */ + struct snd_dma_buffer etram_pages; /* external TRAM pages and size */ + unsigned int dbg; /* FX debugger register */ + unsigned char name[128]; + int gpr_size; /* size of allocated GPR controls */ + int gpr_count; /* count of used kcontrols */ + struct list_head gpr_ctl; /* GPR controls */ + struct mutex lock; + struct snd_emu10k1_fx8010_pcm pcm[8]; + spinlock_t irq_lock; + struct snd_emu10k1_fx8010_irq *irq_handlers; +}; + +struct snd_emu10k1_midi { + struct snd_emu10k1 *emu; + struct snd_rawmidi *rmidi; + struct snd_rawmidi_substream *substream_input; + struct snd_rawmidi_substream *substream_output; + unsigned int midi_mode; + spinlock_t input_lock; + spinlock_t output_lock; + spinlock_t open_lock; + int tx_enable, rx_enable; + int port; + int ipr_tx, ipr_rx; + void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status); +}; + +enum { + EMU_MODEL_SB, + EMU_MODEL_EMU1010, + EMU_MODEL_EMU1010B, + EMU_MODEL_EMU1616, + EMU_MODEL_EMU0404, +}; + +struct snd_emu_chip_details { + u32 vendor; + u32 device; + u32 subsystem; + unsigned char revision; + unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */ + unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */ + unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */ + unsigned char ca0108_chip; /* Audigy 2 Value */ + unsigned char ca_cardbus_chip; /* Audigy 2 ZS Notebook */ + unsigned char ca0151_chip; /* P16V */ + unsigned char spk71; /* Has 7.1 speakers */ + unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */ + unsigned char spdif_bug; /* Has Spdif phasing bug */ + unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */ + unsigned char ecard; /* APS EEPROM */ + unsigned char emu_model; /* EMU model type */ + unsigned char spi_dac; /* SPI interface for DAC */ + unsigned char i2c_adc; /* I2C interface for ADC */ + unsigned char adc_1361t; /* Use Philips 1361T ADC */ + unsigned char invert_shared_spdif; /* analog/digital switch inverted */ + const char *driver; + const char *name; + const char *id; /* for backward compatibility - can be NULL if not needed */ +}; + +struct snd_emu1010 { + unsigned int output_source[64]; + unsigned int input_source[64]; + unsigned int adc_pads; /* bit mask */ + unsigned int dac_pads; /* bit mask */ + unsigned int internal_clock; /* 44100 or 48000 */ + unsigned int optical_in; /* 0:SPDIF, 1:ADAT */ + unsigned int optical_out; /* 0:SPDIF, 1:ADAT */ + struct delayed_work firmware_work; + u32 last_reg; +}; + +struct snd_emu10k1 { + int irq; + + unsigned long port; /* I/O port number */ + unsigned int tos_link: 1, /* tos link detected */ + rear_ac97: 1, /* rear channels are on AC'97 */ + enable_ir: 1; + unsigned int support_tlv :1; + /* Contains profile of card capabilities */ + const struct snd_emu_chip_details *card_capabilities; + unsigned int audigy; /* is Audigy? */ + unsigned int revision; /* chip revision */ + unsigned int serial; /* serial number */ + unsigned short model; /* subsystem id */ + unsigned int card_type; /* EMU10K1_CARD_* */ + unsigned int ecard_ctrl; /* ecard control bits */ + unsigned int address_mode; /* address mode */ + unsigned long dma_mask; /* PCI DMA mask */ + bool iommu_workaround; /* IOMMU workaround needed */ + unsigned int delay_pcm_irq; /* in samples */ + int max_cache_pages; /* max memory size / PAGE_SIZE */ + struct snd_dma_buffer silent_page; /* silent page */ + struct snd_dma_buffer ptb_pages; /* page table pages */ + struct snd_dma_device p16v_dma_dev; + struct snd_dma_buffer *p16v_buffer; + + struct snd_util_memhdr *memhdr; /* page allocation list */ + + struct list_head mapped_link_head; + struct list_head mapped_order_link_head; + void **page_ptr_table; + unsigned long *page_addr_table; + spinlock_t memblk_lock; + + unsigned int spdif_bits[3]; /* s/pdif out setup */ + unsigned int i2c_capture_source; + u8 i2c_capture_volume[4][2]; + + struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */ + int gpr_base; + + struct snd_ac97 *ac97; + + struct pci_dev *pci; + struct snd_card *card; + struct snd_pcm *pcm; + struct snd_pcm *pcm_mic; + struct snd_pcm *pcm_efx; + struct snd_pcm *pcm_multi; + struct snd_pcm *pcm_p16v; + + spinlock_t synth_lock; + void *synth; + int (*get_synth_voice)(struct snd_emu10k1 *emu); + + spinlock_t reg_lock; + spinlock_t emu_lock; + spinlock_t voice_lock; + spinlock_t spi_lock; /* serialises access to spi port */ + spinlock_t i2c_lock; /* serialises access to i2c port */ + + struct snd_emu10k1_voice voices[NUM_G]; + struct snd_emu10k1_voice p16v_voices[4]; + struct snd_emu10k1_voice p16v_capture_voice; + int p16v_device_offset; + u32 p16v_capture_source; + u32 p16v_capture_channel; + struct snd_emu1010 emu1010; + struct snd_emu10k1_pcm_mixer pcm_mixer[32]; + struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK]; + struct snd_kcontrol *ctl_send_routing; + struct snd_kcontrol *ctl_send_volume; + struct snd_kcontrol *ctl_attn; + struct snd_kcontrol *ctl_efx_send_routing; + struct snd_kcontrol *ctl_efx_send_volume; + struct snd_kcontrol *ctl_efx_attn; + + void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status); + void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status); + void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status); + void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status); + void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status); + void (*dsp_interrupt)(struct snd_emu10k1 *emu); + + struct snd_pcm_substream *pcm_capture_substream; + struct snd_pcm_substream *pcm_capture_mic_substream; + struct snd_pcm_substream *pcm_capture_efx_substream; + struct snd_pcm_substream *pcm_playback_efx_substream; + + struct snd_timer *timer; + + struct snd_emu10k1_midi midi; + struct snd_emu10k1_midi midi2; /* for audigy */ + + unsigned int efx_voices_mask[2]; + unsigned int next_free_voice; + + const struct firmware *firmware; + const struct firmware *dock_fw; + +#ifdef CONFIG_PM_SLEEP + unsigned int *saved_ptr; + unsigned int *saved_gpr; + unsigned int *tram_val_saved; + unsigned int *tram_addr_saved; + unsigned int *saved_icode; + unsigned int *p16v_saved; + unsigned int saved_a_iocfg, saved_hcfg; + bool suspend; +#endif + +}; + +int snd_emu10k1_create(struct snd_card *card, + struct pci_dev *pci, + unsigned short extin_mask, + unsigned short extout_mask, + long max_cache_bytes, + int enable_ir, + uint subsystem); + +int snd_emu10k1_pcm(struct snd_emu10k1 *emu, int device); +int snd_emu10k1_pcm_mic(struct snd_emu10k1 *emu, int device); +int snd_emu10k1_pcm_efx(struct snd_emu10k1 *emu, int device); +int snd_p16v_pcm(struct snd_emu10k1 *emu, int device); +int snd_p16v_mixer(struct snd_emu10k1 * emu); +int snd_emu10k1_pcm_multi(struct snd_emu10k1 *emu, int device); +int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 *emu, int device); +int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device); +int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device); +int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device); + +irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id); + +void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice); +int snd_emu10k1_init_efx(struct snd_emu10k1 *emu); +void snd_emu10k1_free_efx(struct snd_emu10k1 *emu); +int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size); +int snd_emu10k1_done(struct snd_emu10k1 * emu); + +/* I/O functions */ +unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); +void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); +unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn); +void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data); +int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data); +int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value); +int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, u32 reg, u32 value); +int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, u32 reg, u32 *value); +int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, u32 dst, u32 src); +unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc); +void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb); +void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb); +void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum); +void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum); +void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum); +void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum); +void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum); +void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum); +void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); +void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum); +void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait); +static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; } +unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg); +void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data); +unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate); + +#ifdef CONFIG_PM_SLEEP +void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu); +void snd_emu10k1_resume_init(struct snd_emu10k1 *emu); +void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu); +int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu); +void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu); +void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu); +void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu); +int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu); +void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu); +void snd_p16v_suspend(struct snd_emu10k1 *emu); +void snd_p16v_resume(struct snd_emu10k1 *emu); +#endif + +/* memory allocation */ +struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream); +int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk); +int snd_emu10k1_alloc_pages_maybe_wider(struct snd_emu10k1 *emu, size_t size, + struct snd_dma_buffer *dmab); +struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size); +int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk); +int snd_emu10k1_synth_bzero(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size); +int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size); +int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk); + +/* voice allocation */ +int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice); +int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice); + +/* MIDI uart */ +int snd_emu10k1_midi(struct snd_emu10k1 * emu); +int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu); + +/* proc interface */ +int snd_emu10k1_proc_init(struct snd_emu10k1 * emu); + +/* fx8010 irq handler */ +int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu, + snd_fx8010_irq_handler_t *handler, + unsigned char gpr_running, + void *private_data, + struct snd_emu10k1_fx8010_irq *irq); +int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu, + struct snd_emu10k1_fx8010_irq *irq); + +#endif /* __SOUND_EMU10K1_H */ diff --git a/include/sound/emu10k1_synth.h b/include/sound/emu10k1_synth.h new file mode 100644 index 000000000..05af4f921 --- /dev/null +++ b/include/sound/emu10k1_synth.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __EMU10K1_SYNTH_H +#define __EMU10K1_SYNTH_H +/* + * Defines for the Emu10k1 WaveTable synth + * + * Copyright (C) 2000 Takashi Iwai <tiwai@suse.de> + */ + +#include <sound/emu10k1.h> +#include <sound/emux_synth.h> + +/* sequencer device id */ +#define SNDRV_SEQ_DEV_ID_EMU10K1_SYNTH "emu10k1-synth" + +/* argument for snd_seq_device_new */ +struct snd_emu10k1_synth_arg { + struct snd_emu10k1 *hwptr; /* chip */ + int index; /* sequencer client index */ + int seq_ports; /* number of sequencer ports to be created */ + int max_voices; /* maximum number of voices for wavetable */ +}; + +#define EMU10K1_MAX_MEMSIZE (32 * 1024 * 1024) /* 32MB */ + +#endif diff --git a/include/sound/emu8000.h b/include/sound/emu8000.h new file mode 100644 index 000000000..072791bbc --- /dev/null +++ b/include/sound/emu8000.h @@ -0,0 +1,105 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_EMU8000_H +#define __SOUND_EMU8000_H +/* + * Defines for the emu8000 (AWE32/64) + * + * Copyright (C) 1999 Steve Ratcliffe + * Copyright (C) 1999-2000 Takashi Iwai <tiwai@suse.de> + */ + +#include <sound/emux_synth.h> +#include <sound/seq_kernel.h> + +/* + * Hardware parameters. + */ +#define EMU8000_MAX_DRAM (28 * 1024 * 1024) /* Max on-board mem is 28Mb ???*/ +#define EMU8000_DRAM_OFFSET 0x200000 /* Beginning of on board ram */ +#define EMU8000_CHANNELS 32 /* Number of hardware channels */ +#define EMU8000_DRAM_VOICES 30 /* number of normal voices */ + +/* Flags to set a dma channel to read or write */ +#define EMU8000_RAM_READ 0 +#define EMU8000_RAM_WRITE 1 +#define EMU8000_RAM_CLOSE 2 +#define EMU8000_RAM_MODE_MASK 0x03 +#define EMU8000_RAM_RIGHT 0x10 /* use 'right' DMA channel */ + +enum { + EMU8000_CONTROL_BASS = 0, + EMU8000_CONTROL_TREBLE, + EMU8000_CONTROL_CHORUS_MODE, + EMU8000_CONTROL_REVERB_MODE, + EMU8000_CONTROL_FM_CHORUS_DEPTH, + EMU8000_CONTROL_FM_REVERB_DEPTH, + EMU8000_NUM_CONTROLS, +}; + +/* + * Structure to hold all state information for the emu8000 driver. + * + * Note 1: The chip supports 32 channels in hardware this is max_channels + * some of the channels may be used for other things so max_channels is + * the number in use for wave voices. + */ +struct snd_emu8000 { + + struct snd_emux *emu; + + int index; /* sequencer client index */ + int seq_ports; /* number of sequencer ports */ + int fm_chorus_depth; /* FM OPL3 chorus depth */ + int fm_reverb_depth; /* FM OPL3 reverb depth */ + + int mem_size; /* memory size */ + unsigned long port1; /* Port usually base+0 */ + unsigned long port2; /* Port usually at base+0x400 */ + unsigned long port3; /* Port usually at base+0x800 */ + unsigned short last_reg;/* Last register command */ + spinlock_t reg_lock; + + int dram_checked; + + struct snd_card *card; /* The card that this belongs to */ + + int chorus_mode; + int reverb_mode; + int bass_level; + int treble_level; + + struct snd_util_memhdr *memhdr; + + spinlock_t control_lock; + struct snd_kcontrol *controls[EMU8000_NUM_CONTROLS]; + + struct snd_pcm *pcm; /* pcm on emu8000 wavetable */ + +}; + +/* sequencer device id */ +#define SNDRV_SEQ_DEV_ID_EMU8000 "emu8000-synth" + + +/* exported functions */ +int snd_emu8000_new(struct snd_card *card, int device, long port, int seq_ports, + struct snd_seq_device **ret); +void snd_emu8000_poke(struct snd_emu8000 *emu, unsigned int port, unsigned int reg, + unsigned int val); +unsigned short snd_emu8000_peek(struct snd_emu8000 *emu, unsigned int port, + unsigned int reg); +void snd_emu8000_poke_dw(struct snd_emu8000 *emu, unsigned int port, unsigned int reg, + unsigned int val); +unsigned int snd_emu8000_peek_dw(struct snd_emu8000 *emu, unsigned int port, + unsigned int reg); +void snd_emu8000_dma_chan(struct snd_emu8000 *emu, int ch, int mode); + +void snd_emu8000_init_fm(struct snd_emu8000 *emu); + +void snd_emu8000_update_chorus_mode(struct snd_emu8000 *emu); +void snd_emu8000_update_reverb_mode(struct snd_emu8000 *emu); +void snd_emu8000_update_equalizer(struct snd_emu8000 *emu); +int snd_emu8000_load_chorus_fx(struct snd_emu8000 *emu, int mode, const void __user *buf, long len); +int snd_emu8000_load_reverb_fx(struct snd_emu8000 *emu, int mode, const void __user *buf, long len); + +#endif /* __SOUND_EMU8000_H */ diff --git a/include/sound/emu8000_reg.h b/include/sound/emu8000_reg.h new file mode 100644 index 000000000..04cedff25 --- /dev/null +++ b/include/sound/emu8000_reg.h @@ -0,0 +1,193 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_EMU8000_REG_H +#define __SOUND_EMU8000_REG_H +/* + * Register operations for the EMU8000 + * + * Copyright (C) 1999 Steve Ratcliffe + * + * Based on awe_wave.c by Takashi Iwai + */ + +/* + * Data port addresses relative to the EMU base. + */ +#define EMU8000_DATA0(e) ((e)->port1) +#define EMU8000_DATA1(e) ((e)->port2) +#define EMU8000_DATA2(e) ((e)->port2+2) +#define EMU8000_DATA3(e) ((e)->port3) +#define EMU8000_PTR(e) ((e)->port3+2) + +/* + * Make a command from a register and channel. + */ +#define EMU8000_CMD(reg, chan) ((reg)<<5 | (chan)) + +/* + * Commands to read and write the EMU8000 registers. + * These macros should be used for all register accesses. + */ +#define EMU8000_CPF_READ(emu, chan) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan))) +#define EMU8000_PTRX_READ(emu, chan) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan))) +#define EMU8000_CVCF_READ(emu, chan) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan))) +#define EMU8000_VTFT_READ(emu, chan) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan))) +#define EMU8000_PSST_READ(emu, chan) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(6, (chan))) +#define EMU8000_CSL_READ(emu, chan) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(7, (chan))) +#define EMU8000_CCCA_READ(emu, chan) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(0, (chan))) +#define EMU8000_HWCF4_READ(emu) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 9)) +#define EMU8000_HWCF5_READ(emu) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 10)) +#define EMU8000_HWCF6_READ(emu) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 13)) +#define EMU8000_SMALR_READ(emu) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 20)) +#define EMU8000_SMARR_READ(emu) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 21)) +#define EMU8000_SMALW_READ(emu) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 22)) +#define EMU8000_SMARW_READ(emu) \ + snd_emu8000_peek_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 23)) +#define EMU8000_SMLD_READ(emu) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 26)) +#define EMU8000_SMRD_READ(emu) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 26)) +#define EMU8000_WC_READ(emu) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 27)) +#define EMU8000_HWCF1_READ(emu) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 29)) +#define EMU8000_HWCF2_READ(emu) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 30)) +#define EMU8000_HWCF3_READ(emu) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 31)) +#define EMU8000_INIT1_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(2, (chan))) +#define EMU8000_INIT2_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(2, (chan))) +#define EMU8000_INIT3_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(3, (chan))) +#define EMU8000_INIT4_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(3, (chan))) +#define EMU8000_ENVVOL_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(4, (chan))) +#define EMU8000_DCYSUSV_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(5, (chan))) +#define EMU8000_ENVVAL_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(6, (chan))) +#define EMU8000_DCYSUS_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA1(emu), EMU8000_CMD(7, (chan))) +#define EMU8000_ATKHLDV_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(4, (chan))) +#define EMU8000_LFO1VAL_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(5, (chan))) +#define EMU8000_ATKHLD_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(6, (chan))) +#define EMU8000_LFO2VAL_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA2(emu), EMU8000_CMD(7, (chan))) +#define EMU8000_IP_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(0, (chan))) +#define EMU8000_IFATN_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(1, (chan))) +#define EMU8000_PEFE_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(2, (chan))) +#define EMU8000_FMMOD_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(3, (chan))) +#define EMU8000_TREMFRQ_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(4, (chan))) +#define EMU8000_FM2FRQ2_READ(emu, chan) \ + snd_emu8000_peek((emu), EMU8000_DATA3(emu), EMU8000_CMD(5, (chan))) + + +#define EMU8000_CPF_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(0, (chan)), (val)) +#define EMU8000_PTRX_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (chan)), (val)) +#define EMU8000_CVCF_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(2, (chan)), (val)) +#define EMU8000_VTFT_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(3, (chan)), (val)) +#define EMU8000_PSST_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(6, (chan)), (val)) +#define EMU8000_CSL_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(7, (chan)), (val)) +#define EMU8000_CCCA_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(0, (chan)), (val)) +#define EMU8000_HWCF4_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 9), (val)) +#define EMU8000_HWCF5_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 10), (val)) +#define EMU8000_HWCF6_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 13), (val)) +/* this register is not documented */ +#define EMU8000_HWCF7_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 14), (val)) +#define EMU8000_SMALR_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 20), (val)) +#define EMU8000_SMARR_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 21), (val)) +#define EMU8000_SMALW_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 22), (val)) +#define EMU8000_SMARW_WRITE(emu, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 23), (val)) +#define EMU8000_SMLD_WRITE(emu, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 26), (val)) +#define EMU8000_SMRD_WRITE(emu, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 26), (val)) +#define EMU8000_WC_WRITE(emu, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(1, 27), (val)) +#define EMU8000_HWCF1_WRITE(emu, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 29), (val)) +#define EMU8000_HWCF2_WRITE(emu, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 30), (val)) +#define EMU8000_HWCF3_WRITE(emu, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(1, 31), (val)) +#define EMU8000_INIT1_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(2, (chan)), (val)) +#define EMU8000_INIT2_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(2, (chan)), (val)) +#define EMU8000_INIT3_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(3, (chan)), (val)) +#define EMU8000_INIT4_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(3, (chan)), (val)) +#define EMU8000_ENVVOL_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(4, (chan)), (val)) +#define EMU8000_DCYSUSV_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(5, (chan)), (val)) +#define EMU8000_ENVVAL_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(6, (chan)), (val)) +#define EMU8000_DCYSUS_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA1(emu), EMU8000_CMD(7, (chan)), (val)) +#define EMU8000_ATKHLDV_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(4, (chan)), (val)) +#define EMU8000_LFO1VAL_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(5, (chan)), (val)) +#define EMU8000_ATKHLD_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(6, (chan)), (val)) +#define EMU8000_LFO2VAL_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA2(emu), EMU8000_CMD(7, (chan)), (val)) +#define EMU8000_IP_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(0, (chan)), (val)) +#define EMU8000_IFATN_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(1, (chan)), (val)) +#define EMU8000_PEFE_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(2, (chan)), (val)) +#define EMU8000_FMMOD_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(3, (chan)), (val)) +#define EMU8000_TREMFRQ_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(4, (chan)), (val)) +#define EMU8000_FM2FRQ2_WRITE(emu, chan, val) \ + snd_emu8000_poke((emu), EMU8000_DATA3(emu), EMU8000_CMD(5, (chan)), (val)) + +#define EMU8000_0080_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(4, (chan)), (val)) +#define EMU8000_00A0_WRITE(emu, chan, val) \ + snd_emu8000_poke_dw((emu), EMU8000_DATA0(emu), EMU8000_CMD(5, (chan)), (val)) + +#endif /* __SOUND_EMU8000_REG_H */ diff --git a/include/sound/emux_legacy.h b/include/sound/emux_legacy.h new file mode 100644 index 000000000..1127e30d3 --- /dev/null +++ b/include/sound/emux_legacy.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_EMUX_LEGACY_H +#define __SOUND_EMUX_LEGACY_H + +/* + * Copyright (c) 1999-2000 Takashi Iwai <tiwai@suse.de> + * + * Definitions of OSS compatible headers for Emu8000 device informations + */ + +#include <sound/seq_oss_legacy.h> + +/* + * awe hardware controls + */ + +#define _EMUX_OSS_DEBUG_MODE 0x00 +#define _EMUX_OSS_REVERB_MODE 0x01 +#define _EMUX_OSS_CHORUS_MODE 0x02 +#define _EMUX_OSS_REMOVE_LAST_SAMPLES 0x03 +#define _EMUX_OSS_INITIALIZE_CHIP 0x04 +#define _EMUX_OSS_SEND_EFFECT 0x05 +#define _EMUX_OSS_TERMINATE_CHANNEL 0x06 +#define _EMUX_OSS_TERMINATE_ALL 0x07 +#define _EMUX_OSS_INITIAL_VOLUME 0x08 +#define _EMUX_OSS_INITIAL_ATTEN _EMUX_OSS_INITIAL_VOLUME +#define _EMUX_OSS_RESET_CHANNEL 0x09 +#define _EMUX_OSS_CHANNEL_MODE 0x0a +#define _EMUX_OSS_DRUM_CHANNELS 0x0b +#define _EMUX_OSS_MISC_MODE 0x0c +#define _EMUX_OSS_RELEASE_ALL 0x0d +#define _EMUX_OSS_NOTEOFF_ALL 0x0e +#define _EMUX_OSS_CHN_PRESSURE 0x0f +#define _EMUX_OSS_EQUALIZER 0x11 + +#define _EMUX_OSS_MODE_FLAG 0x80 +#define _EMUX_OSS_COOKED_FLAG 0x40 /* not supported */ +#define _EMUX_OSS_MODE_VALUE_MASK 0x3F + + +/* + * mode type definitions + */ +enum { +/* 0*/ EMUX_MD_EXCLUSIVE_OFF, /* obsolete */ +/* 1*/ EMUX_MD_EXCLUSIVE_ON, /* obsolete */ +/* 2*/ EMUX_MD_VERSION, /* read only */ +/* 3*/ EMUX_MD_EXCLUSIVE_SOUND, /* 0/1: exclusive note on (default=1) */ +/* 4*/ EMUX_MD_REALTIME_PAN, /* 0/1: do realtime pan change (default=1) */ +/* 5*/ EMUX_MD_GUS_BANK, /* bank number for GUS patches (default=0) */ +/* 6*/ EMUX_MD_KEEP_EFFECT, /* 0/1: keep effect values, (default=0) */ +/* 7*/ EMUX_MD_ZERO_ATTEN, /* attenuation of max volume (default=32) */ +/* 8*/ EMUX_MD_CHN_PRIOR, /* 0/1: set MIDI channel priority mode (default=1) */ +/* 9*/ EMUX_MD_MOD_SENSE, /* integer: modwheel sensitivity (def=18) */ +/*10*/ EMUX_MD_DEF_PRESET, /* integer: default preset number (def=0) */ +/*11*/ EMUX_MD_DEF_BANK, /* integer: default bank number (def=0) */ +/*12*/ EMUX_MD_DEF_DRUM, /* integer: default drumset number (def=0) */ +/*13*/ EMUX_MD_TOGGLE_DRUM_BANK, /* 0/1: toggle drum flag with bank# (def=0) */ +/*14*/ EMUX_MD_NEW_VOLUME_CALC, /* 0/1: volume calculation mode (def=1) */ +/*15*/ EMUX_MD_CHORUS_MODE, /* integer: chorus mode (def=2) */ +/*16*/ EMUX_MD_REVERB_MODE, /* integer: chorus mode (def=4) */ +/*17*/ EMUX_MD_BASS_LEVEL, /* integer: bass level (def=5) */ +/*18*/ EMUX_MD_TREBLE_LEVEL, /* integer: treble level (def=9) */ +/*19*/ EMUX_MD_DEBUG_MODE, /* integer: debug level (def=0) */ +/*20*/ EMUX_MD_PAN_EXCHANGE, /* 0/1: exchange panning direction (def=0) */ + EMUX_MD_END, +}; + + +/* + * effect parameters + */ +enum { + +/* modulation envelope parameters */ +/* 0*/ EMUX_FX_ENV1_DELAY, /* WORD: ENVVAL */ +/* 1*/ EMUX_FX_ENV1_ATTACK, /* BYTE: up ATKHLD */ +/* 2*/ EMUX_FX_ENV1_HOLD, /* BYTE: lw ATKHLD */ +/* 3*/ EMUX_FX_ENV1_DECAY, /* BYTE: lw DCYSUS */ +/* 4*/ EMUX_FX_ENV1_RELEASE, /* BYTE: lw DCYSUS */ +/* 5*/ EMUX_FX_ENV1_SUSTAIN, /* BYTE: up DCYSUS */ +/* 6*/ EMUX_FX_ENV1_PITCH, /* BYTE: up PEFE */ +/* 7*/ EMUX_FX_ENV1_CUTOFF, /* BYTE: lw PEFE */ + +/* volume envelope parameters */ +/* 8*/ EMUX_FX_ENV2_DELAY, /* WORD: ENVVOL */ +/* 9*/ EMUX_FX_ENV2_ATTACK, /* BYTE: up ATKHLDV */ +/*10*/ EMUX_FX_ENV2_HOLD, /* BYTE: lw ATKHLDV */ +/*11*/ EMUX_FX_ENV2_DECAY, /* BYTE: lw DCYSUSV */ +/*12*/ EMUX_FX_ENV2_RELEASE, /* BYTE: lw DCYSUSV */ +/*13*/ EMUX_FX_ENV2_SUSTAIN, /* BYTE: up DCYSUSV */ + +/* LFO1 (tremolo & vibrato) parameters */ +/*14*/ EMUX_FX_LFO1_DELAY, /* WORD: LFO1VAL */ +/*15*/ EMUX_FX_LFO1_FREQ, /* BYTE: lo TREMFRQ */ +/*16*/ EMUX_FX_LFO1_VOLUME, /* BYTE: up TREMFRQ */ +/*17*/ EMUX_FX_LFO1_PITCH, /* BYTE: up FMMOD */ +/*18*/ EMUX_FX_LFO1_CUTOFF, /* BYTE: lo FMMOD */ + +/* LFO2 (vibrato) parameters */ +/*19*/ EMUX_FX_LFO2_DELAY, /* WORD: LFO2VAL */ +/*20*/ EMUX_FX_LFO2_FREQ, /* BYTE: lo FM2FRQ2 */ +/*21*/ EMUX_FX_LFO2_PITCH, /* BYTE: up FM2FRQ2 */ + +/* Other overall effect parameters */ +/*22*/ EMUX_FX_INIT_PITCH, /* SHORT: pitch offset */ +/*23*/ EMUX_FX_CHORUS, /* BYTE: chorus effects send (0-255) */ +/*24*/ EMUX_FX_REVERB, /* BYTE: reverb effects send (0-255) */ +/*25*/ EMUX_FX_CUTOFF, /* BYTE: up IFATN */ +/*26*/ EMUX_FX_FILTERQ, /* BYTE: up CCCA */ + +/* Sample / loop offset changes */ +/*27*/ EMUX_FX_SAMPLE_START, /* SHORT: offset */ +/*28*/ EMUX_FX_LOOP_START, /* SHORT: offset */ +/*29*/ EMUX_FX_LOOP_END, /* SHORT: offset */ +/*30*/ EMUX_FX_COARSE_SAMPLE_START, /* SHORT: upper word offset */ +/*31*/ EMUX_FX_COARSE_LOOP_START, /* SHORT: upper word offset */ +/*32*/ EMUX_FX_COARSE_LOOP_END, /* SHORT: upper word offset */ +/*33*/ EMUX_FX_ATTEN, /* BYTE: lo IFATN */ + + EMUX_FX_END, +}; +/* number of effects */ +#define EMUX_NUM_EFFECTS EMUX_FX_END + +/* effect flag values */ +#define EMUX_FX_FLAG_OFF 0 +#define EMUX_FX_FLAG_SET 1 +#define EMUX_FX_FLAG_ADD 2 + + +#endif /* __SOUND_EMUX_LEGACY_H */ diff --git a/include/sound/emux_synth.h b/include/sound/emux_synth.h new file mode 100644 index 000000000..d499b6812 --- /dev/null +++ b/include/sound/emux_synth.h @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_EMUX_SYNTH_H +#define __SOUND_EMUX_SYNTH_H + +/* + * Defines for the Emu-series WaveTable chip + * + * Copyright (C) 2000 Takashi Iwai <tiwai@suse.de> + */ + +#include <sound/seq_kernel.h> +#include <sound/seq_device.h> +#include <sound/soundfont.h> +#include <sound/seq_midi_emul.h> +#include <sound/seq_oss.h> +#include <sound/emux_legacy.h> +#include <sound/seq_virmidi.h> + +/* + * compile flags + */ +#define SNDRV_EMUX_USE_RAW_EFFECT + +struct snd_emux; +struct snd_emux_port; +struct snd_emux_voice; +struct snd_emux_effect_table; + +/* + * operators + */ +struct snd_emux_operators { + struct module *owner; + struct snd_emux_voice *(*get_voice)(struct snd_emux *emu, + struct snd_emux_port *port); + int (*prepare)(struct snd_emux_voice *vp); + void (*trigger)(struct snd_emux_voice *vp); + void (*release)(struct snd_emux_voice *vp); + void (*update)(struct snd_emux_voice *vp, int update); + void (*terminate)(struct snd_emux_voice *vp); + void (*free_voice)(struct snd_emux_voice *vp); + void (*reset)(struct snd_emux *emu, int ch); + /* the first parameters are struct snd_emux */ + int (*sample_new)(struct snd_emux *emu, struct snd_sf_sample *sp, + struct snd_util_memhdr *hdr, + const void __user *data, long count); + int (*sample_free)(struct snd_emux *emu, struct snd_sf_sample *sp, + struct snd_util_memhdr *hdr); + void (*sample_reset)(struct snd_emux *emu); + int (*load_fx)(struct snd_emux *emu, int type, int arg, + const void __user *data, long count); + void (*sysex)(struct snd_emux *emu, char *buf, int len, int parsed, + struct snd_midi_channel_set *chset); +#if IS_ENABLED(CONFIG_SND_SEQUENCER_OSS) + int (*oss_ioctl)(struct snd_emux *emu, int cmd, int p1, int p2); +#endif +}; + + +/* + * constant values + */ +#define SNDRV_EMUX_MAX_PORTS 32 /* max # of sequencer ports */ +#define SNDRV_EMUX_MAX_VOICES 64 /* max # of voices */ +#define SNDRV_EMUX_MAX_MULTI_VOICES 16 /* max # of playable voices + * simultineously + */ + +/* + * flags + */ +#define SNDRV_EMUX_ACCEPT_ROM (1<<0) + +/* + * emuX wavetable + */ +struct snd_emux { + + struct snd_card *card; /* assigned card */ + + /* following should be initialized before registration */ + int max_voices; /* Number of voices */ + int mem_size; /* memory size (in byte) */ + int num_ports; /* number of ports to be created */ + int pitch_shift; /* pitch shift value (for Emu10k1) */ + struct snd_emux_operators ops; /* operators */ + void *hw; /* hardware */ + unsigned long flags; /* other conditions */ + int midi_ports; /* number of virtual midi devices */ + int midi_devidx; /* device offset of virtual midi */ + unsigned int linear_panning: 1; /* panning is linear (sbawe = 1, emu10k1 = 0) */ + int hwdep_idx; /* hwdep device index */ + struct snd_hwdep *hwdep; /* hwdep device */ + + /* private */ + int num_voices; /* current number of voices */ + struct snd_sf_list *sflist; /* root of SoundFont list */ + struct snd_emux_voice *voices; /* Voices (EMU 'channel') */ + int use_time; /* allocation counter */ + spinlock_t voice_lock; /* Lock for voice access */ + struct mutex register_mutex; + int client; /* For the sequencer client */ + int ports[SNDRV_EMUX_MAX_PORTS]; /* The ports for this device */ + struct snd_emux_port *portptrs[SNDRV_EMUX_MAX_PORTS]; + int used; /* use counter */ + char *name; /* name of the device (internal) */ + struct snd_rawmidi **vmidi; + struct timer_list tlist; /* for pending note-offs */ + int timer_active; + + struct snd_util_memhdr *memhdr; /* memory chunk information */ + +#ifdef CONFIG_SND_PROC_FS + struct snd_info_entry *proc; +#endif + +#if IS_ENABLED(CONFIG_SND_SEQUENCER_OSS) + struct snd_seq_device *oss_synth; +#endif +}; + + +/* + * sequencer port information + */ +struct snd_emux_port { + + struct snd_midi_channel_set chset; + struct snd_emux *emu; + + char port_mode; /* operation mode */ + int volume_atten; /* emuX raw attenuation */ + unsigned long drum_flags; /* drum bitmaps */ + int ctrls[EMUX_MD_END]; /* control parameters */ +#ifdef SNDRV_EMUX_USE_RAW_EFFECT + struct snd_emux_effect_table *effect; +#endif +#if IS_ENABLED(CONFIG_SND_SEQUENCER_OSS) + struct snd_seq_oss_arg *oss_arg; +#endif +}; + +/* port_mode */ +#define SNDRV_EMUX_PORT_MODE_MIDI 0 /* normal MIDI port */ +#define SNDRV_EMUX_PORT_MODE_OSS_SYNTH 1 /* OSS synth port */ +#define SNDRV_EMUX_PORT_MODE_OSS_MIDI 2 /* OSS multi channel synth port */ + +/* + * A structure to keep track of each hardware voice + */ +struct snd_emux_voice { + int ch; /* Hardware channel number */ + + int state; /* status */ +#define SNDRV_EMUX_ST_OFF 0x00 /* Not playing, and inactive */ +#define SNDRV_EMUX_ST_ON 0x01 /* Note on */ +#define SNDRV_EMUX_ST_RELEASED (0x02|SNDRV_EMUX_ST_ON) /* Note released */ +#define SNDRV_EMUX_ST_SUSTAINED (0x04|SNDRV_EMUX_ST_ON) /* Note sustained */ +#define SNDRV_EMUX_ST_STANDBY (0x08|SNDRV_EMUX_ST_ON) /* Waiting to be triggered */ +#define SNDRV_EMUX_ST_PENDING (0x10|SNDRV_EMUX_ST_ON) /* Note will be released */ +#define SNDRV_EMUX_ST_LOCKED 0x100 /* Not accessible */ + + unsigned int time; /* An allocation time */ + unsigned char note; /* Note currently assigned to this voice */ + unsigned char key; + unsigned char velocity; /* Velocity of current note */ + + struct snd_sf_zone *zone; /* Zone assigned to this note */ + void *block; /* sample block pointer (optional) */ + struct snd_midi_channel *chan; /* Midi channel for this note */ + struct snd_emux_port *port; /* associated port */ + struct snd_emux *emu; /* assigned root info */ + void *hw; /* hardware pointer (emu8000 or emu10k1) */ + unsigned long ontime; /* jiffies at note triggered */ + + /* Emu8k/Emu10k1 registers */ + struct soundfont_voice_info reg; + + /* additional registers */ + int avol; /* volume attenuation */ + int acutoff; /* cutoff target */ + int apitch; /* pitch offset */ + int apan; /* pan/aux pair */ + int aaux; + int ptarget; /* pitch target */ + int vtarget; /* volume target */ + int ftarget; /* filter target */ + +}; + +/* + * update flags (can be combined) + */ +#define SNDRV_EMUX_UPDATE_VOLUME (1<<0) +#define SNDRV_EMUX_UPDATE_PITCH (1<<1) +#define SNDRV_EMUX_UPDATE_PAN (1<<2) +#define SNDRV_EMUX_UPDATE_FMMOD (1<<3) +#define SNDRV_EMUX_UPDATE_TREMFREQ (1<<4) +#define SNDRV_EMUX_UPDATE_FM2FRQ2 (1<<5) +#define SNDRV_EMUX_UPDATE_Q (1<<6) + + +#ifdef SNDRV_EMUX_USE_RAW_EFFECT +/* + * effect table + */ +struct snd_emux_effect_table { + /* Emu8000 specific effects */ + short val[EMUX_NUM_EFFECTS]; + unsigned char flag[EMUX_NUM_EFFECTS]; +}; +#endif /* SNDRV_EMUX_USE_RAW_EFFECT */ + + +/* + * prototypes - interface to Emu10k1 and Emu8k routines + */ +int snd_emux_new(struct snd_emux **remu); +int snd_emux_register(struct snd_emux *emu, struct snd_card *card, int index, char *name); +int snd_emux_free(struct snd_emux *emu); + +/* + * exported functions + */ +void snd_emux_terminate_all(struct snd_emux *emu); +void snd_emux_lock_voice(struct snd_emux *emu, int voice); +void snd_emux_unlock_voice(struct snd_emux *emu, int voice); + +#endif /* __SOUND_EMUX_SYNTH_H */ diff --git a/include/sound/es1688.h b/include/sound/es1688.h new file mode 100644 index 000000000..099569c31 --- /dev/null +++ b/include/sound/es1688.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_ES1688_H +#define __SOUND_ES1688_H + +/* + * Header file for ES488/ES1688 + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + */ + +#include <sound/control.h> +#include <sound/pcm.h> +#include <linux/interrupt.h> + +#define ES1688_HW_AUTO 0x0000 +#define ES1688_HW_688 0x0001 +#define ES1688_HW_1688 0x0002 +#define ES1688_HW_UNDEF 0x0003 + +struct snd_es1688 { + unsigned long port; /* port of ESS chip */ + struct resource *res_port; + unsigned long mpu_port; /* MPU-401 port of ESS chip */ + int irq; /* IRQ number of ESS chip */ + int mpu_irq; /* MPU IRQ */ + int dma8; /* 8-bit DMA */ + unsigned short version; /* version of ESS chip */ + unsigned short hardware; /* see to ES1688_HW_XXXX */ + + unsigned short trigger_value; + unsigned char pad; + unsigned int dma_size; + + struct snd_pcm *pcm; + struct snd_pcm_substream *playback_substream; + struct snd_pcm_substream *capture_substream; + + spinlock_t reg_lock; + spinlock_t mixer_lock; +}; + +/* I/O ports */ + +#define ES1688P(codec, x) ((codec)->port + e_s_s_ESS1688##x) + +#define e_s_s_ESS1688RESET 0x6 +#define e_s_s_ESS1688READ 0xa +#define e_s_s_ESS1688WRITE 0xc +#define e_s_s_ESS1688COMMAND 0xc +#define e_s_s_ESS1688STATUS 0xc +#define e_s_s_ESS1688DATA_AVAIL 0xe +#define e_s_s_ESS1688DATA_AVAIL_16 0xf +#define e_s_s_ESS1688MIXER_ADDR 0x4 +#define e_s_s_ESS1688MIXER_DATA 0x5 +#define e_s_s_ESS1688OPL3_LEFT 0x0 +#define e_s_s_ESS1688OPL3_RIGHT 0x2 +#define e_s_s_ESS1688OPL3_BOTH 0x8 +#define e_s_s_ESS1688ENABLE0 0x0 +#define e_s_s_ESS1688ENABLE1 0x9 +#define e_s_s_ESS1688ENABLE2 0xb +#define e_s_s_ESS1688INIT1 0x7 + +#define ES1688_DSP_CMD_DMAOFF 0xd0 +#define ES1688_DSP_CMD_SPKON 0xd1 +#define ES1688_DSP_CMD_SPKOFF 0xd3 +#define ES1688_DSP_CMD_DMAON 0xd4 + +#define ES1688_PCM_DEV 0x14 +#define ES1688_MIC_DEV 0x1a +#define ES1688_REC_DEV 0x1c +#define ES1688_MASTER_DEV 0x32 +#define ES1688_FM_DEV 0x36 +#define ES1688_CD_DEV 0x38 +#define ES1688_AUX_DEV 0x3a +#define ES1688_SPEAKER_DEV 0x3c +#define ES1688_LINE_DEV 0x3e +#define ES1688_RECLEV_DEV 0xb4 + +#define ES1688_MIXS_MASK 0x17 +#define ES1688_MIXS_MIC 0x00 +#define ES1688_MIXS_MIC_MASTER 0x01 +#define ES1688_MIXS_CD 0x02 +#define ES1688_MIXS_AOUT 0x03 +#define ES1688_MIXS_MIC1 0x04 +#define ES1688_MIXS_REC_MIX 0x05 +#define ES1688_MIXS_LINE 0x06 +#define ES1688_MIXS_MASTER 0x07 +#define ES1688_MIXS_MUTE 0x10 + +/* + + */ + +void snd_es1688_mixer_write(struct snd_es1688 *chip, unsigned char reg, unsigned char data); + +int snd_es1688_create(struct snd_card *card, + struct snd_es1688 *chip, + unsigned long port, + unsigned long mpu_port, + int irq, + int mpu_irq, + int dma8, + unsigned short hardware); +int snd_es1688_pcm(struct snd_card *card, struct snd_es1688 *chip, int device); +int snd_es1688_mixer(struct snd_card *card, struct snd_es1688 *chip); +int snd_es1688_reset(struct snd_es1688 *chip); + +#endif /* __SOUND_ES1688_H */ diff --git a/include/sound/graph_card.h b/include/sound/graph_card.h new file mode 100644 index 000000000..4c8b94c77 --- /dev/null +++ b/include/sound/graph_card.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * ASoC audio graph card support + * + */ + +#ifndef __GRAPH_CARD_H +#define __GRAPH_CARD_H + +#include <sound/simple_card_utils.h> + +typedef int (*GRAPH2_CUSTOM)(struct asoc_simple_priv *priv, + struct device_node *lnk, + struct link_info *li); + +struct graph2_custom_hooks { + int (*hook_pre)(struct asoc_simple_priv *priv); + int (*hook_post)(struct asoc_simple_priv *priv); + GRAPH2_CUSTOM custom_normal; + GRAPH2_CUSTOM custom_dpcm; + GRAPH2_CUSTOM custom_c2c; +}; + +int audio_graph_parse_of(struct asoc_simple_priv *priv, struct device *dev); +int audio_graph2_parse_of(struct asoc_simple_priv *priv, struct device *dev, + struct graph2_custom_hooks *hooks); + +int audio_graph2_link_normal(struct asoc_simple_priv *priv, + struct device_node *lnk, struct link_info *li); +int audio_graph2_link_dpcm(struct asoc_simple_priv *priv, + struct device_node *lnk, struct link_info *li); +int audio_graph2_link_c2c(struct asoc_simple_priv *priv, + struct device_node *lnk, struct link_info *li); + +#endif /* __GRAPH_CARD_H */ diff --git a/include/sound/gus.h b/include/sound/gus.h new file mode 100644 index 000000000..cd8da68ca --- /dev/null +++ b/include/sound/gus.h @@ -0,0 +1,620 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_GUS_H +#define __SOUND_GUS_H + +/* + * Global structures used for GUS part of ALSA driver + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + */ + +#include <sound/pcm.h> +#include <sound/rawmidi.h> +#include <sound/timer.h> +#include <sound/seq_midi_emul.h> +#include <sound/seq_device.h> +#include <linux/io.h> + +/* IO ports */ + +#define GUSP(gus, x) ((gus)->gf1.port + SNDRV_g_u_s_##x) + +#define SNDRV_g_u_s_MIDICTRL (0x320-0x220) +#define SNDRV_g_u_s_MIDISTAT (0x320-0x220) +#define SNDRV_g_u_s_MIDIDATA (0x321-0x220) + +#define SNDRV_g_u_s_GF1PAGE (0x322-0x220) +#define SNDRV_g_u_s_GF1REGSEL (0x323-0x220) +#define SNDRV_g_u_s_GF1DATALOW (0x324-0x220) +#define SNDRV_g_u_s_GF1DATAHIGH (0x325-0x220) +#define SNDRV_g_u_s_IRQSTAT (0x226-0x220) +#define SNDRV_g_u_s_TIMERCNTRL (0x228-0x220) +#define SNDRV_g_u_s_TIMERDATA (0x229-0x220) +#define SNDRV_g_u_s_DRAM (0x327-0x220) +#define SNDRV_g_u_s_MIXCNTRLREG (0x220-0x220) +#define SNDRV_g_u_s_IRQDMACNTRLREG (0x22b-0x220) +#define SNDRV_g_u_s_REGCNTRLS (0x22f-0x220) +#define SNDRV_g_u_s_BOARDVERSION (0x726-0x220) +#define SNDRV_g_u_s_MIXCNTRLPORT (0x726-0x220) +#define SNDRV_g_u_s_IVER (0x325-0x220) +#define SNDRV_g_u_s_MIXDATAPORT (0x326-0x220) +#define SNDRV_g_u_s_MAXCNTRLPORT (0x326-0x220) + +/* GF1 registers */ + +/* global registers */ +#define SNDRV_GF1_GB_ACTIVE_VOICES 0x0e +#define SNDRV_GF1_GB_VOICES_IRQ 0x0f +#define SNDRV_GF1_GB_GLOBAL_MODE 0x19 +#define SNDRV_GF1_GW_LFO_BASE 0x1a +#define SNDRV_GF1_GB_VOICES_IRQ_READ 0x1f +#define SNDRV_GF1_GB_DRAM_DMA_CONTROL 0x41 +#define SNDRV_GF1_GW_DRAM_DMA_LOW 0x42 +#define SNDRV_GF1_GW_DRAM_IO_LOW 0x43 +#define SNDRV_GF1_GB_DRAM_IO_HIGH 0x44 +#define SNDRV_GF1_GB_SOUND_BLASTER_CONTROL 0x45 +#define SNDRV_GF1_GB_ADLIB_TIMER_1 0x46 +#define SNDRV_GF1_GB_ADLIB_TIMER_2 0x47 +#define SNDRV_GF1_GB_RECORD_RATE 0x48 +#define SNDRV_GF1_GB_REC_DMA_CONTROL 0x49 +#define SNDRV_GF1_GB_JOYSTICK_DAC_LEVEL 0x4b +#define SNDRV_GF1_GB_RESET 0x4c +#define SNDRV_GF1_GB_DRAM_DMA_HIGH 0x50 +#define SNDRV_GF1_GW_DRAM_IO16 0x51 +#define SNDRV_GF1_GW_MEMORY_CONFIG 0x52 +#define SNDRV_GF1_GB_MEMORY_CONTROL 0x53 +#define SNDRV_GF1_GW_FIFO_RECORD_BASE_ADDR 0x54 +#define SNDRV_GF1_GW_FIFO_PLAY_BASE_ADDR 0x55 +#define SNDRV_GF1_GW_FIFO_SIZE 0x56 +#define SNDRV_GF1_GW_INTERLEAVE 0x57 +#define SNDRV_GF1_GB_COMPATIBILITY 0x59 +#define SNDRV_GF1_GB_DECODE_CONTROL 0x5a +#define SNDRV_GF1_GB_VERSION_NUMBER 0x5b +#define SNDRV_GF1_GB_MPU401_CONTROL_A 0x5c +#define SNDRV_GF1_GB_MPU401_CONTROL_B 0x5d +#define SNDRV_GF1_GB_EMULATION_IRQ 0x60 +/* voice specific registers */ +#define SNDRV_GF1_VB_ADDRESS_CONTROL 0x00 +#define SNDRV_GF1_VW_FREQUENCY 0x01 +#define SNDRV_GF1_VW_START_HIGH 0x02 +#define SNDRV_GF1_VW_START_LOW 0x03 +#define SNDRV_GF1_VA_START SNDRV_GF1_VW_START_HIGH +#define SNDRV_GF1_VW_END_HIGH 0x04 +#define SNDRV_GF1_VW_END_LOW 0x05 +#define SNDRV_GF1_VA_END SNDRV_GF1_VW_END_HIGH +#define SNDRV_GF1_VB_VOLUME_RATE 0x06 +#define SNDRV_GF1_VB_VOLUME_START 0x07 +#define SNDRV_GF1_VB_VOLUME_END 0x08 +#define SNDRV_GF1_VW_VOLUME 0x09 +#define SNDRV_GF1_VW_CURRENT_HIGH 0x0a +#define SNDRV_GF1_VW_CURRENT_LOW 0x0b +#define SNDRV_GF1_VA_CURRENT SNDRV_GF1_VW_CURRENT_HIGH +#define SNDRV_GF1_VB_PAN 0x0c +#define SNDRV_GF1_VW_OFFSET_RIGHT 0x0c +#define SNDRV_GF1_VB_VOLUME_CONTROL 0x0d +#define SNDRV_GF1_VB_UPPER_ADDRESS 0x10 +#define SNDRV_GF1_VW_EFFECT_HIGH 0x11 +#define SNDRV_GF1_VW_EFFECT_LOW 0x12 +#define SNDRV_GF1_VA_EFFECT SNDRV_GF1_VW_EFFECT_HIGH +#define SNDRV_GF1_VW_OFFSET_LEFT 0x13 +#define SNDRV_GF1_VB_ACCUMULATOR 0x14 +#define SNDRV_GF1_VB_MODE 0x15 +#define SNDRV_GF1_VW_EFFECT_VOLUME 0x16 +#define SNDRV_GF1_VB_FREQUENCY_LFO 0x17 +#define SNDRV_GF1_VB_VOLUME_LFO 0x18 +#define SNDRV_GF1_VW_OFFSET_RIGHT_FINAL 0x1b +#define SNDRV_GF1_VW_OFFSET_LEFT_FINAL 0x1c +#define SNDRV_GF1_VW_EFFECT_VOLUME_FINAL 0x1d + +/* ICS registers */ + +#define SNDRV_ICS_MIC_DEV 0 +#define SNDRV_ICS_LINE_DEV 1 +#define SNDRV_ICS_CD_DEV 2 +#define SNDRV_ICS_GF1_DEV 3 +#define SNDRV_ICS_NONE_DEV 4 +#define SNDRV_ICS_MASTER_DEV 5 + +/* LFO */ + +#define SNDRV_LFO_TREMOLO 0 +#define SNDRV_LFO_VIBRATO 1 + +/* misc */ + +#define SNDRV_GF1_DMA_UNSIGNED 0x80 +#define SNDRV_GF1_DMA_16BIT 0x40 +#define SNDRV_GF1_DMA_IRQ 0x20 +#define SNDRV_GF1_DMA_WIDTH16 0x04 +#define SNDRV_GF1_DMA_READ 0x02 /* read from GUS's DRAM */ +#define SNDRV_GF1_DMA_ENABLE 0x01 + +/* ramp ranges */ + +#define SNDRV_GF1_ATTEN(x) (snd_gf1_atten_table[x]) +#define SNDRV_GF1_MIN_VOLUME 1800 +#define SNDRV_GF1_MAX_VOLUME 4095 +#define SNDRV_GF1_MIN_OFFSET (SNDRV_GF1_MIN_VOLUME>>4) +#define SNDRV_GF1_MAX_OFFSET 255 +#define SNDRV_GF1_MAX_TDEPTH 90 + +/* defines for memory manager */ + +#define SNDRV_GF1_MEM_BLOCK_16BIT 0x0001 + +#define SNDRV_GF1_MEM_OWNER_DRIVER 0x0001 +#define SNDRV_GF1_MEM_OWNER_WAVE_SIMPLE 0x0002 +#define SNDRV_GF1_MEM_OWNER_WAVE_GF1 0x0003 +#define SNDRV_GF1_MEM_OWNER_WAVE_IWFFFF 0x0004 + +/* constants for interrupt handlers */ + +#define SNDRV_GF1_HANDLER_MIDI_OUT 0x00010000 +#define SNDRV_GF1_HANDLER_MIDI_IN 0x00020000 +#define SNDRV_GF1_HANDLER_TIMER1 0x00040000 +#define SNDRV_GF1_HANDLER_TIMER2 0x00080000 +#define SNDRV_GF1_HANDLER_VOICE 0x00100000 +#define SNDRV_GF1_HANDLER_DMA_WRITE 0x00200000 +#define SNDRV_GF1_HANDLER_DMA_READ 0x00400000 +#define SNDRV_GF1_HANDLER_ALL (0xffff0000&~SNDRV_GF1_HANDLER_VOICE) + +/* constants for DMA flags */ + +#define SNDRV_GF1_DMA_TRIGGER 1 + +/* --- */ + +struct snd_gus_card; + +/* GF1 specific structure */ + +struct snd_gf1_bank_info { + unsigned int address; + unsigned int size; +}; + +struct snd_gf1_mem_block { + unsigned short flags; /* flags - SNDRV_GF1_MEM_BLOCK_XXXX */ + unsigned short owner; /* owner - SNDRV_GF1_MEM_OWNER_XXXX */ + unsigned int share; /* share count */ + unsigned int share_id[4]; /* share ID */ + unsigned int ptr; + unsigned int size; + char *name; + struct snd_gf1_mem_block *next; + struct snd_gf1_mem_block *prev; +}; + +struct snd_gf1_mem { + struct snd_gf1_bank_info banks_8[4]; + struct snd_gf1_bank_info banks_16[4]; + struct snd_gf1_mem_block *first; + struct snd_gf1_mem_block *last; + struct mutex memory_mutex; +}; + +struct snd_gf1_dma_block { + void *buffer; /* buffer in computer's RAM */ + unsigned long buf_addr; /* buffer address */ + unsigned int addr; /* address in onboard memory */ + unsigned int count; /* count in bytes */ + unsigned int cmd; /* DMA command (format) */ + void (*ack)(struct snd_gus_card * gus, void *private_data); + void *private_data; + struct snd_gf1_dma_block *next; +}; + +struct snd_gus_port { + struct snd_midi_channel_set * chset; + struct snd_gus_card * gus; + int mode; /* operation mode */ + int client; /* sequencer client number */ + int port; /* sequencer port number */ + unsigned int midi_has_voices: 1; +}; + +struct snd_gus_voice; + +#define SNDRV_GF1_VOICE_TYPE_PCM 0 +#define SNDRV_GF1_VOICE_TYPE_SYNTH 1 +#define SNDRV_GF1_VOICE_TYPE_MIDI 2 + +#define SNDRV_GF1_VFLG_RUNNING (1<<0) +#define SNDRV_GF1_VFLG_EFFECT_TIMER1 (1<<1) +#define SNDRV_GF1_VFLG_PAN (1<<2) + +enum snd_gus_volume_state { + VENV_BEFORE, + VENV_ATTACK, + VENV_SUSTAIN, + VENV_RELEASE, + VENV_DONE, + VENV_VOLUME +}; + +struct snd_gus_voice { + int number; + unsigned int use: 1, + pcm: 1, + synth:1, + midi: 1; + unsigned int flags; + unsigned char client; + unsigned char port; + unsigned char index; + unsigned char pad; + +#ifdef CONFIG_SND_DEBUG + unsigned int interrupt_stat_wave; + unsigned int interrupt_stat_volume; +#endif + void (*handler_wave) (struct snd_gus_card * gus, struct snd_gus_voice * voice); + void (*handler_volume) (struct snd_gus_card * gus, struct snd_gus_voice * voice); + void (*handler_effect) (struct snd_gus_card * gus, struct snd_gus_voice * voice); + void (*volume_change) (struct snd_gus_card * gus); + + struct snd_gus_sample_ops *sample_ops; + + /* running status / registers */ + + unsigned short fc_register; + unsigned short fc_lfo; + unsigned short gf1_volume; + unsigned char control; + unsigned char mode; + unsigned char gf1_pan; + unsigned char effect_accumulator; + unsigned char volume_control; + unsigned char venv_value_next; + enum snd_gus_volume_state venv_state; + enum snd_gus_volume_state venv_state_prev; + unsigned short vlo; + unsigned short vro; + unsigned short gf1_effect_volume; + + /* --- */ + + void *private_data; + void (*private_free)(struct snd_gus_voice *voice); +}; + +struct snd_gf1 { + + unsigned int enh_mode:1, /* enhanced mode (GFA1) */ + hw_lfo:1, /* use hardware LFO */ + sw_lfo:1, /* use software LFO */ + effect:1; /* use effect voices */ + + unsigned long port; /* port of GF1 chip */ + struct resource *res_port1; + struct resource *res_port2; + int irq; /* IRQ number */ + int dma1; /* DMA1 number */ + int dma2; /* DMA2 number */ + unsigned int memory; /* GUS's DRAM size in bytes */ + unsigned int rom_memory; /* GUS's ROM size in bytes */ + unsigned int rom_present; /* bitmask */ + unsigned int rom_banks; /* GUS's ROM banks */ + + struct snd_gf1_mem mem_alloc; + + /* registers */ + unsigned short reg_page; + unsigned short reg_regsel; + unsigned short reg_data8; + unsigned short reg_data16; + unsigned short reg_irqstat; + unsigned short reg_dram; + unsigned short reg_timerctrl; + unsigned short reg_timerdata; + unsigned char ics_regs[6][2]; + /* --------- */ + + unsigned char active_voices; /* active voices */ + unsigned char active_voice; /* selected voice (GF1PAGE register) */ + + struct snd_gus_voice voices[32]; /* GF1 voices */ + + unsigned int default_voice_address; + + unsigned short playback_freq; /* GF1 playback (mixing) frequency */ + unsigned short mode; /* see to SNDRV_GF1_MODE_XXXX */ + unsigned char volume_ramp; + unsigned char smooth_pan; + unsigned char full_range_pan; + unsigned char pad0; + + unsigned char *lfos; + + /* interrupt handlers */ + + void (*interrupt_handler_midi_out) (struct snd_gus_card * gus); + void (*interrupt_handler_midi_in) (struct snd_gus_card * gus); + void (*interrupt_handler_timer1) (struct snd_gus_card * gus); + void (*interrupt_handler_timer2) (struct snd_gus_card * gus); + void (*interrupt_handler_dma_write) (struct snd_gus_card * gus); + void (*interrupt_handler_dma_read) (struct snd_gus_card * gus); + +#ifdef CONFIG_SND_DEBUG + unsigned int interrupt_stat_midi_out; + unsigned int interrupt_stat_midi_in; + unsigned int interrupt_stat_timer1; + unsigned int interrupt_stat_timer2; + unsigned int interrupt_stat_dma_write; + unsigned int interrupt_stat_dma_read; + unsigned int interrupt_stat_voice_lost; +#endif + + /* synthesizer */ + + int seq_client; + struct snd_gus_port seq_ports[4]; + + /* timer */ + + unsigned short timer_enabled; + struct snd_timer *timer1; + struct snd_timer *timer2; + + /* midi */ + + unsigned short uart_cmd; + unsigned int uart_framing; + unsigned int uart_overrun; + + /* dma operations */ + + unsigned int dma_flags; + unsigned int dma_shared; + struct snd_gf1_dma_block *dma_data_pcm; + struct snd_gf1_dma_block *dma_data_pcm_last; + struct snd_gf1_dma_block *dma_data_synth; + struct snd_gf1_dma_block *dma_data_synth_last; + void (*dma_ack)(struct snd_gus_card * gus, void *private_data); + void *dma_private_data; + + /* pcm */ + int pcm_channels; + int pcm_alloc_voices; + unsigned short pcm_volume_level_left; + unsigned short pcm_volume_level_right; + unsigned short pcm_volume_level_left1; + unsigned short pcm_volume_level_right1; + + unsigned char pcm_rcntrl_reg; + unsigned char pad_end; +}; + +/* main structure for GUS card */ + +struct snd_gus_card { + struct snd_card *card; + + unsigned int + initialized: 1, /* resources were initialized */ + equal_irq:1, /* GF1 and CODEC shares IRQ (GUS MAX only) */ + equal_dma:1, /* if dma channels are equal (not valid for daughter board) */ + ics_flag:1, /* have we ICS mixer chip */ + ics_flipped:1, /* ICS mixer have flipped some channels? */ + codec_flag:1, /* have we CODEC chip? */ + max_flag:1, /* have we GUS MAX card? */ + max_ctrl_flag:1, /* have we original GUS MAX card? */ + daughter_flag:1, /* have we daughter board? */ + interwave:1, /* hey - we have InterWave card */ + ess_flag:1, /* ESS chip found... GUS Extreme */ + ace_flag:1, /* GUS ACE detected */ + uart_enable:1; /* enable MIDI UART */ + unsigned short revision; /* revision of chip */ + unsigned short max_cntrl_val; /* GUS MAX control value */ + unsigned short mix_cntrl_reg; /* mixer control register */ + unsigned short joystick_dac; /* joystick DAC level */ + int timer_dev; /* timer device */ + + struct snd_gf1 gf1; /* gf1 specific variables */ + struct snd_pcm *pcm; + struct snd_pcm_substream *pcm_cap_substream; + unsigned int c_dma_size; + unsigned int c_period_size; + unsigned int c_pos; + + struct snd_rawmidi *midi_uart; + struct snd_rawmidi_substream *midi_substream_output; + struct snd_rawmidi_substream *midi_substream_input; + + spinlock_t reg_lock; + spinlock_t voice_alloc; + spinlock_t active_voice_lock; + spinlock_t event_lock; + spinlock_t dma_lock; + spinlock_t pcm_volume_level_lock; + spinlock_t uart_cmd_lock; + struct mutex dma_mutex; + struct mutex register_mutex; +}; + +/* I/O functions for GF1/InterWave chip - gus_io.c */ + +static inline void snd_gf1_select_voice(struct snd_gus_card * gus, int voice) +{ + unsigned long flags; + + spin_lock_irqsave(&gus->active_voice_lock, flags); + if (voice != gus->gf1.active_voice) { + gus->gf1.active_voice = voice; + outb(voice, GUSP(gus, GF1PAGE)); + } + spin_unlock_irqrestore(&gus->active_voice_lock, flags); +} + +static inline void snd_gf1_uart_cmd(struct snd_gus_card * gus, unsigned char b) +{ + outb(gus->gf1.uart_cmd = b, GUSP(gus, MIDICTRL)); +} + +static inline unsigned char snd_gf1_uart_stat(struct snd_gus_card * gus) +{ + return inb(GUSP(gus, MIDISTAT)); +} + +static inline void snd_gf1_uart_put(struct snd_gus_card * gus, unsigned char b) +{ + outb(b, GUSP(gus, MIDIDATA)); +} + +static inline unsigned char snd_gf1_uart_get(struct snd_gus_card * gus) +{ + return inb(GUSP(gus, MIDIDATA)); +} + +extern void snd_gf1_delay(struct snd_gus_card * gus); + +extern void snd_gf1_ctrl_stop(struct snd_gus_card * gus, unsigned char reg); + +extern void snd_gf1_write8(struct snd_gus_card * gus, unsigned char reg, unsigned char data); +extern unsigned char snd_gf1_look8(struct snd_gus_card * gus, unsigned char reg); +static inline unsigned char snd_gf1_read8(struct snd_gus_card * gus, unsigned char reg) +{ + return snd_gf1_look8(gus, reg | 0x80); +} +extern void snd_gf1_write16(struct snd_gus_card * gus, unsigned char reg, unsigned int data); +extern unsigned short snd_gf1_look16(struct snd_gus_card * gus, unsigned char reg); +static inline unsigned short snd_gf1_read16(struct snd_gus_card * gus, unsigned char reg) +{ + return snd_gf1_look16(gus, reg | 0x80); +} +extern void snd_gf1_adlib_write(struct snd_gus_card * gus, unsigned char reg, unsigned char data); +extern void snd_gf1_dram_addr(struct snd_gus_card * gus, unsigned int addr); +extern void snd_gf1_poke(struct snd_gus_card * gus, unsigned int addr, unsigned char data); +extern unsigned char snd_gf1_peek(struct snd_gus_card * gus, unsigned int addr); +extern void snd_gf1_write_addr(struct snd_gus_card * gus, unsigned char reg, unsigned int addr, short w_16bit); +extern unsigned int snd_gf1_read_addr(struct snd_gus_card * gus, unsigned char reg, short w_16bit); +extern void snd_gf1_i_ctrl_stop(struct snd_gus_card * gus, unsigned char reg); +extern void snd_gf1_i_write8(struct snd_gus_card * gus, unsigned char reg, unsigned char data); +extern unsigned char snd_gf1_i_look8(struct snd_gus_card * gus, unsigned char reg); +extern void snd_gf1_i_write16(struct snd_gus_card * gus, unsigned char reg, unsigned int data); +static inline unsigned char snd_gf1_i_read8(struct snd_gus_card * gus, unsigned char reg) +{ + return snd_gf1_i_look8(gus, reg | 0x80); +} +extern unsigned short snd_gf1_i_look16(struct snd_gus_card * gus, unsigned char reg); +static inline unsigned short snd_gf1_i_read16(struct snd_gus_card * gus, unsigned char reg) +{ + return snd_gf1_i_look16(gus, reg | 0x80); +} + +extern void snd_gf1_select_active_voices(struct snd_gus_card * gus); + +/* gus_lfo.c */ + +struct _SND_IW_LFO_PROGRAM { + unsigned short freq_and_control; + unsigned char depth_final; + unsigned char depth_inc; + unsigned short twave; + unsigned short depth; +}; + +#if 0 +extern irqreturn_t snd_gf1_lfo_effect_interrupt(struct snd_gus_card * gus, snd_gf1_voice_t * voice); +#endif +extern void snd_gf1_lfo_init(struct snd_gus_card * gus); +extern void snd_gf1_lfo_done(struct snd_gus_card * gus); +extern void snd_gf1_lfo_program(struct snd_gus_card * gus, int voice, int lfo_type, struct _SND_IW_LFO_PROGRAM *program); +extern void snd_gf1_lfo_enable(struct snd_gus_card * gus, int voice, int lfo_type); +extern void snd_gf1_lfo_disable(struct snd_gus_card * gus, int voice, int lfo_type); +extern void snd_gf1_lfo_change_freq(struct snd_gus_card * gus, int voice, int lfo_type, int freq); +extern void snd_gf1_lfo_change_depth(struct snd_gus_card * gus, int voice, int lfo_type, int depth); +extern void snd_gf1_lfo_setup(struct snd_gus_card * gus, int voice, int lfo_type, int freq, int current_depth, int depth, int sweep, int shape); +extern void snd_gf1_lfo_shutdown(struct snd_gus_card * gus, int voice, int lfo_type); +#if 0 +extern void snd_gf1_lfo_command(struct snd_gus_card * gus, int voice, unsigned char *command); +#endif + +/* gus_mem.c */ + +void snd_gf1_mem_lock(struct snd_gf1_mem * alloc, int xup); +int snd_gf1_mem_xfree(struct snd_gf1_mem * alloc, struct snd_gf1_mem_block * block); +struct snd_gf1_mem_block *snd_gf1_mem_alloc(struct snd_gf1_mem * alloc, int owner, + char *name, int size, int w_16, + int align, unsigned int *share_id); +int snd_gf1_mem_free(struct snd_gf1_mem * alloc, unsigned int address); +int snd_gf1_mem_free_owner(struct snd_gf1_mem * alloc, int owner); +int snd_gf1_mem_init(struct snd_gus_card * gus); +int snd_gf1_mem_done(struct snd_gus_card * gus); + +/* gus_mem_proc.c */ + +int snd_gf1_mem_proc_init(struct snd_gus_card * gus); + +/* gus_dma.c */ + +int snd_gf1_dma_init(struct snd_gus_card * gus); +int snd_gf1_dma_done(struct snd_gus_card * gus); +int snd_gf1_dma_transfer_block(struct snd_gus_card * gus, + struct snd_gf1_dma_block * block, + int atomic, + int synth); + +/* gus_volume.c */ + +unsigned short snd_gf1_lvol_to_gvol_raw(unsigned int vol); +unsigned short snd_gf1_translate_freq(struct snd_gus_card * gus, unsigned int freq2); + +/* gus_reset.c */ + +void snd_gf1_set_default_handlers(struct snd_gus_card * gus, unsigned int what); +void snd_gf1_smart_stop_voice(struct snd_gus_card * gus, unsigned short voice); +void snd_gf1_stop_voice(struct snd_gus_card * gus, unsigned short voice); +void snd_gf1_stop_voices(struct snd_gus_card * gus, unsigned short v_min, unsigned short v_max); +struct snd_gus_voice *snd_gf1_alloc_voice(struct snd_gus_card * gus, int type, int client, int port); +void snd_gf1_free_voice(struct snd_gus_card * gus, struct snd_gus_voice *voice); +int snd_gf1_start(struct snd_gus_card * gus); +int snd_gf1_stop(struct snd_gus_card * gus); + +/* gus_mixer.c */ + +int snd_gf1_new_mixer(struct snd_gus_card * gus); + +/* gus_pcm.c */ + +int snd_gf1_pcm_new(struct snd_gus_card *gus, int pcm_dev, int control_index); + +#ifdef CONFIG_SND_DEBUG +extern void snd_gf1_print_voice_registers(struct snd_gus_card * gus); +#endif + +/* gus.c */ + +int snd_gus_use_inc(struct snd_gus_card * gus); +void snd_gus_use_dec(struct snd_gus_card * gus); +int snd_gus_create(struct snd_card *card, + unsigned long port, + int irq, int dma1, int dma2, + int timer_dev, + int voices, + int pcm_channels, + int effect, + struct snd_gus_card ** rgus); +int snd_gus_initialize(struct snd_gus_card * gus); + +/* gus_irq.c */ + +irqreturn_t snd_gus_interrupt(int irq, void *dev_id); +#ifdef CONFIG_SND_DEBUG +void snd_gus_irq_profile_init(struct snd_gus_card *gus); +#endif + +/* gus_uart.c */ + +int snd_gf1_rawmidi_new(struct snd_gus_card *gus, int device); + +/* gus_dram.c */ +int snd_gus_dram_write(struct snd_gus_card *gus, char __user *ptr, + unsigned int addr, unsigned int size); +int snd_gus_dram_read(struct snd_gus_card *gus, char __user *ptr, + unsigned int addr, unsigned int size, int rom); + +/* gus_timer.c */ +void snd_gf1_timers_init(struct snd_gus_card *gus); +void snd_gf1_timers_done(struct snd_gus_card *gus); + +#endif /* __SOUND_GUS_H */ diff --git a/include/sound/hda_chmap.h b/include/sound/hda_chmap.h new file mode 100644 index 000000000..e508f3192 --- /dev/null +++ b/include/sound/hda_chmap.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * For multichannel support + */ + +#ifndef __SOUND_HDA_CHMAP_H +#define __SOUND_HDA_CHMAP_H + +#include <sound/pcm.h> +#include <sound/hdaudio.h> + + +#define SND_PRINT_CHANNEL_ALLOCATION_ADVISED_BUFSIZE 80 + +struct hdac_cea_channel_speaker_allocation { + int ca_index; + int speakers[8]; + + /* derived values, just for convenience */ + int channels; + int spk_mask; +}; +struct hdac_chmap; + +struct hdac_chmap_ops { + /* + * Helpers for producing the channel map TLVs. These can be overridden + * for devices that have non-standard mapping requirements. + */ + int (*chmap_cea_alloc_validate_get_type)(struct hdac_chmap *chmap, + struct hdac_cea_channel_speaker_allocation *cap, int channels); + void (*cea_alloc_to_tlv_chmap)(struct hdac_chmap *hchmap, + struct hdac_cea_channel_speaker_allocation *cap, + unsigned int *chmap, int channels); + + /* check that the user-given chmap is supported */ + int (*chmap_validate)(struct hdac_chmap *hchmap, int ca, + int channels, unsigned char *chmap); + + int (*get_spk_alloc)(struct hdac_device *hdac, int pcm_idx); + + void (*get_chmap)(struct hdac_device *hdac, int pcm_idx, + unsigned char *chmap); + void (*set_chmap)(struct hdac_device *hdac, int pcm_idx, + unsigned char *chmap, int prepared); + bool (*is_pcm_attached)(struct hdac_device *hdac, int pcm_idx); + + /* get and set channel assigned to each HDMI ASP (audio sample packet) slot */ + int (*pin_get_slot_channel)(struct hdac_device *codec, + hda_nid_t pin_nid, int asp_slot); + int (*pin_set_slot_channel)(struct hdac_device *codec, + hda_nid_t pin_nid, int asp_slot, int channel); + void (*set_channel_count)(struct hdac_device *codec, + hda_nid_t cvt_nid, int chs); +}; + +struct hdac_chmap { + unsigned int channels_max; /* max over all cvts */ + struct hdac_chmap_ops ops; + struct hdac_device *hdac; +}; + +void snd_hdac_register_chmap_ops(struct hdac_device *hdac, + struct hdac_chmap *chmap); +int snd_hdac_channel_allocation(struct hdac_device *hdac, int spk_alloc, + int channels, bool chmap_set, + bool non_pcm, unsigned char *map); +int snd_hdac_get_active_channels(int ca); +void snd_hdac_setup_channel_mapping(struct hdac_chmap *chmap, + hda_nid_t pin_nid, bool non_pcm, int ca, + int channels, unsigned char *map, + bool chmap_set); +void snd_hdac_print_channel_allocation(int spk_alloc, char *buf, int buflen); +struct hdac_cea_channel_speaker_allocation *snd_hdac_get_ch_alloc_from_ca(int ca); +int snd_hdac_chmap_to_spk_mask(unsigned char c); +int snd_hdac_spk_to_chmap(int spk); +int snd_hdac_add_chmap_ctls(struct snd_pcm *pcm, int pcm_idx, + struct hdac_chmap *chmap); +#endif /* __SOUND_HDA_CHMAP_H */ diff --git a/include/sound/hda_codec.h b/include/sound/hda_codec.h new file mode 100644 index 000000000..bbb7805e8 --- /dev/null +++ b/include/sound/hda_codec.h @@ -0,0 +1,543 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Universal Interface for Intel High Definition Audio Codec + * + * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de> + */ + +#ifndef __SOUND_HDA_CODEC_H +#define __SOUND_HDA_CODEC_H + +#include <linux/refcount.h> +#include <linux/mod_devicetable.h> +#include <sound/info.h> +#include <sound/control.h> +#include <sound/pcm.h> +#include <sound/hwdep.h> +#include <sound/hdaudio.h> +#include <sound/hda_verbs.h> +#include <sound/hda_regmap.h> + +#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98) +#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348) + +/* + * Structures + */ + +struct hda_bus; +struct hda_beep; +struct hda_codec; +struct hda_pcm; +struct hda_pcm_stream; + +/* + * codec bus + * + * each controller needs to creata a hda_bus to assign the accessor. + * A hda_bus contains several codecs in the list codec_list. + */ +struct hda_bus { + struct hdac_bus core; + + struct snd_card *card; + + struct pci_dev *pci; + const char *modelname; + + struct mutex prepare_mutex; + + /* assigned PCMs */ + DECLARE_BITMAP(pcm_dev_bits, SNDRV_PCM_DEVICES); + + /* misc op flags */ + unsigned int allow_bus_reset:1; /* allow bus reset at fatal error */ + /* status for codec/controller */ + unsigned int shutdown :1; /* being unloaded */ + unsigned int response_reset:1; /* controller was reset */ + unsigned int in_reset:1; /* during reset operation */ + unsigned int no_response_fallback:1; /* don't fallback at RIRB error */ + unsigned int bus_probing :1; /* during probing process */ + unsigned int keep_power:1; /* keep power up for notification */ + unsigned int jackpoll_in_suspend:1; /* keep jack polling during + * runtime suspend + */ + + int primary_dig_out_type; /* primary digital out PCM type */ + unsigned int mixer_assigned; /* codec addr for mixer name */ +}; + +/* from hdac_bus to hda_bus */ +#define to_hda_bus(bus) container_of(bus, struct hda_bus, core) + +/* + * codec preset + * + * Known codecs have the patch to build and set up the controls/PCMs + * better than the generic parser. + */ +typedef int (*hda_codec_patch_t)(struct hda_codec *); + +#define HDA_CODEC_ID_SKIP_PROBE 0x00000001 +#define HDA_CODEC_ID_GENERIC_HDMI 0x00000101 +#define HDA_CODEC_ID_GENERIC 0x00000201 + +#define HDA_CODEC_REV_ENTRY(_vid, _rev, _name, _patch) \ + { .vendor_id = (_vid), .rev_id = (_rev), .name = (_name), \ + .api_version = HDA_DEV_LEGACY, \ + .driver_data = (unsigned long)(_patch) } +#define HDA_CODEC_ENTRY(_vid, _name, _patch) \ + HDA_CODEC_REV_ENTRY(_vid, 0, _name, _patch) + +struct hda_codec_driver { + struct hdac_driver core; + const struct hda_device_id *id; +}; + +int __hda_codec_driver_register(struct hda_codec_driver *drv, const char *name, + struct module *owner); +#define hda_codec_driver_register(drv) \ + __hda_codec_driver_register(drv, KBUILD_MODNAME, THIS_MODULE) +void hda_codec_driver_unregister(struct hda_codec_driver *drv); +#define module_hda_codec_driver(drv) \ + module_driver(drv, hda_codec_driver_register, \ + hda_codec_driver_unregister) + +/* ops set by the preset patch */ +struct hda_codec_ops { + int (*build_controls)(struct hda_codec *codec); + int (*build_pcms)(struct hda_codec *codec); + int (*init)(struct hda_codec *codec); + void (*free)(struct hda_codec *codec); + void (*unsol_event)(struct hda_codec *codec, unsigned int res); + void (*set_power_state)(struct hda_codec *codec, hda_nid_t fg, + unsigned int power_state); +#ifdef CONFIG_PM + int (*suspend)(struct hda_codec *codec); + int (*resume)(struct hda_codec *codec); + int (*check_power_status)(struct hda_codec *codec, hda_nid_t nid); +#endif + void (*stream_pm)(struct hda_codec *codec, hda_nid_t nid, bool on); +}; + +/* PCM callbacks */ +struct hda_pcm_ops { + int (*open)(struct hda_pcm_stream *info, struct hda_codec *codec, + struct snd_pcm_substream *substream); + int (*close)(struct hda_pcm_stream *info, struct hda_codec *codec, + struct snd_pcm_substream *substream); + int (*prepare)(struct hda_pcm_stream *info, struct hda_codec *codec, + unsigned int stream_tag, unsigned int format, + struct snd_pcm_substream *substream); + int (*cleanup)(struct hda_pcm_stream *info, struct hda_codec *codec, + struct snd_pcm_substream *substream); + unsigned int (*get_delay)(struct hda_pcm_stream *info, + struct hda_codec *codec, + struct snd_pcm_substream *substream); +}; + +/* PCM information for each substream */ +struct hda_pcm_stream { + unsigned int substreams; /* number of substreams, 0 = not exist*/ + unsigned int channels_min; /* min. number of channels */ + unsigned int channels_max; /* max. number of channels */ + hda_nid_t nid; /* default NID to query rates/formats/bps, or set up */ + u32 rates; /* supported rates */ + u64 formats; /* supported formats (SNDRV_PCM_FMTBIT_) */ + unsigned int maxbps; /* supported max. bit per sample */ + const struct snd_pcm_chmap_elem *chmap; /* chmap to override */ + struct hda_pcm_ops ops; +}; + +/* PCM types */ +enum { + HDA_PCM_TYPE_AUDIO, + HDA_PCM_TYPE_SPDIF, + HDA_PCM_TYPE_HDMI, + HDA_PCM_TYPE_MODEM, + HDA_PCM_NTYPES +}; + +#define SNDRV_PCM_INVALID_DEVICE (-1) +/* for PCM creation */ +struct hda_pcm { + char *name; + struct hda_pcm_stream stream[2]; + unsigned int pcm_type; /* HDA_PCM_TYPE_XXX */ + int device; /* device number to assign */ + struct snd_pcm *pcm; /* assigned PCM instance */ + bool own_chmap; /* codec driver provides own channel maps */ + /* private: */ + struct hda_codec *codec; + struct list_head list; + unsigned int disconnected:1; +}; + +/* codec information */ +struct hda_codec { + struct hdac_device core; + struct hda_bus *bus; + struct snd_card *card; + unsigned int addr; /* codec addr*/ + u32 probe_id; /* overridden id for probing */ + + /* detected preset */ + const struct hda_device_id *preset; + const char *modelname; /* model name for preset */ + + /* set by patch */ + struct hda_codec_ops patch_ops; + + /* PCM to create, set by patch_ops.build_pcms callback */ + struct list_head pcm_list_head; + refcount_t pcm_ref; + wait_queue_head_t remove_sleep; + + /* codec specific info */ + void *spec; + + /* beep device */ + struct hda_beep *beep; + unsigned int beep_mode; + + /* widget capabilities cache */ + u32 *wcaps; + + struct snd_array mixers; /* list of assigned mixer elements */ + struct snd_array nids; /* list of mapped mixer elements */ + + struct list_head conn_list; /* linked-list of connection-list */ + + struct mutex spdif_mutex; + struct mutex control_mutex; + struct snd_array spdif_out; + unsigned int spdif_in_enable; /* SPDIF input enable? */ + const hda_nid_t *follower_dig_outs; /* optional digital out follower widgets */ + struct snd_array init_pins; /* initial (BIOS) pin configurations */ + struct snd_array driver_pins; /* pin configs set by codec parser */ + struct snd_array cvt_setups; /* audio convert setups */ + + struct mutex user_mutex; +#ifdef CONFIG_SND_HDA_RECONFIG + struct snd_array init_verbs; /* additional init verbs */ + struct snd_array hints; /* additional hints */ + struct snd_array user_pins; /* default pin configs to override */ +#endif + +#ifdef CONFIG_SND_HDA_HWDEP + struct snd_hwdep *hwdep; /* assigned hwdep device */ +#endif + + /* misc flags */ + unsigned int configured:1; /* codec was configured */ + unsigned int in_freeing:1; /* being released */ + unsigned int display_power_control:1; /* needs display power */ + unsigned int spdif_status_reset :1; /* needs to toggle SPDIF for each + * status change + * (e.g. Realtek codecs) + */ + unsigned int pin_amp_workaround:1; /* pin out-amp takes index + * (e.g. Conexant codecs) + */ + unsigned int single_adc_amp:1; /* adc in-amp takes no index + * (e.g. CX20549 codec) + */ + unsigned int no_sticky_stream:1; /* no sticky-PCM stream assignment */ + unsigned int pins_shutup:1; /* pins are shut up */ + unsigned int no_trigger_sense:1; /* don't trigger at pin-sensing */ + unsigned int no_jack_detect:1; /* Machine has no jack-detection */ + unsigned int inv_eapd:1; /* broken h/w: inverted EAPD control */ + unsigned int inv_jack_detect:1; /* broken h/w: inverted detection bit */ + unsigned int pcm_format_first:1; /* PCM format must be set first */ + unsigned int cached_write:1; /* write only to caches */ + unsigned int dp_mst:1; /* support DP1.2 Multi-stream transport */ + unsigned int dump_coef:1; /* dump processing coefs in codec proc file */ + unsigned int power_save_node:1; /* advanced PM for each widget */ + unsigned int auto_runtime_pm:1; /* enable automatic codec runtime pm */ + unsigned int force_pin_prefix:1; /* Add location prefix */ + unsigned int link_down_at_suspend:1; /* link down at runtime suspend */ + unsigned int relaxed_resume:1; /* don't resume forcibly for jack */ + unsigned int forced_resume:1; /* forced resume for jack */ + unsigned int no_stream_clean_at_suspend:1; /* do not clean streams at suspend */ + unsigned int ctl_dev_id:1; /* old control element id build behaviour */ + +#ifdef CONFIG_PM + unsigned long power_on_acct; + unsigned long power_off_acct; + unsigned long power_jiffies; +#endif + + /* filter the requested power state per nid */ + unsigned int (*power_filter)(struct hda_codec *codec, hda_nid_t nid, + unsigned int power_state); + + /* codec-specific additional proc output */ + void (*proc_widget_hook)(struct snd_info_buffer *buffer, + struct hda_codec *codec, hda_nid_t nid); + + /* jack detection */ + struct snd_array jacktbl; + unsigned long jackpoll_interval; /* In jiffies. Zero means no poll, rely on unsol events */ + struct delayed_work jackpoll_work; + + int depop_delay; /* depop delay in ms, -1 for default delay time */ + + /* fix-up list */ + int fixup_id; + const struct hda_fixup *fixup_list; + const char *fixup_name; + + /* additional init verbs */ + struct snd_array verbs; +}; + +#define dev_to_hda_codec(_dev) container_of(_dev, struct hda_codec, core.dev) +#define hda_codec_dev(_dev) (&(_dev)->core.dev) + +#define hdac_to_hda_codec(_hdac) container_of(_hdac, struct hda_codec, core) + +#define list_for_each_codec(c, bus) \ + list_for_each_entry(c, &(bus)->core.codec_list, core.list) +#define list_for_each_codec_safe(c, n, bus) \ + list_for_each_entry_safe(c, n, &(bus)->core.codec_list, core.list) + +/* snd_hda_codec_read/write optional flags */ +#define HDA_RW_NO_RESPONSE_FALLBACK (1 << 0) + +/* + * constructors + */ +__printf(3, 4) struct hda_codec * +snd_hda_codec_device_init(struct hda_bus *bus, unsigned int codec_addr, + const char *fmt, ...); +int snd_hda_codec_new(struct hda_bus *bus, struct snd_card *card, + unsigned int codec_addr, struct hda_codec **codecp); +int snd_hda_codec_device_new(struct hda_bus *bus, struct snd_card *card, + unsigned int codec_addr, struct hda_codec *codec, + bool snddev_managed); +int snd_hda_codec_configure(struct hda_codec *codec); +int snd_hda_codec_update_widgets(struct hda_codec *codec); +void snd_hda_codec_register(struct hda_codec *codec); +void snd_hda_codec_unregister(struct hda_codec *codec); +void snd_hda_codec_cleanup_for_unbind(struct hda_codec *codec); + +/* + * low level functions + */ +static inline unsigned int +snd_hda_codec_read(struct hda_codec *codec, hda_nid_t nid, + int flags, + unsigned int verb, unsigned int parm) +{ + return snd_hdac_codec_read(&codec->core, nid, flags, verb, parm); +} + +static inline int +snd_hda_codec_write(struct hda_codec *codec, hda_nid_t nid, int flags, + unsigned int verb, unsigned int parm) +{ + return snd_hdac_codec_write(&codec->core, nid, flags, verb, parm); +} + +#define snd_hda_param_read(codec, nid, param) \ + snd_hdac_read_parm(&(codec)->core, nid, param) +#define snd_hda_get_sub_nodes(codec, nid, start_nid) \ + snd_hdac_get_sub_nodes(&(codec)->core, nid, start_nid) +int snd_hda_get_connections(struct hda_codec *codec, hda_nid_t nid, + hda_nid_t *conn_list, int max_conns); +static inline int +snd_hda_get_num_conns(struct hda_codec *codec, hda_nid_t nid) +{ + return snd_hda_get_connections(codec, nid, NULL, 0); +} + +#define snd_hda_get_raw_connections(codec, nid, list, max_conns) \ + snd_hdac_get_connections(&(codec)->core, nid, list, max_conns) +#define snd_hda_get_num_raw_conns(codec, nid) \ + snd_hdac_get_connections(&(codec)->core, nid, NULL, 0) + +int snd_hda_get_conn_list(struct hda_codec *codec, hda_nid_t nid, + const hda_nid_t **listp); +int snd_hda_override_conn_list(struct hda_codec *codec, hda_nid_t nid, int nums, + const hda_nid_t *list); +int snd_hda_get_conn_index(struct hda_codec *codec, hda_nid_t mux, + hda_nid_t nid, int recursive); +unsigned int snd_hda_get_num_devices(struct hda_codec *codec, hda_nid_t nid); +int snd_hda_get_devices(struct hda_codec *codec, hda_nid_t nid, + u8 *dev_list, int max_devices); +int snd_hda_get_dev_select(struct hda_codec *codec, hda_nid_t nid); +int snd_hda_set_dev_select(struct hda_codec *codec, hda_nid_t nid, int dev_id); + +struct hda_verb { + hda_nid_t nid; + u32 verb; + u32 param; +}; + +void snd_hda_sequence_write(struct hda_codec *codec, + const struct hda_verb *seq); + +/* cached write */ +static inline int +snd_hda_codec_write_cache(struct hda_codec *codec, hda_nid_t nid, + int flags, unsigned int verb, unsigned int parm) +{ + return snd_hdac_regmap_write(&codec->core, nid, verb, parm); +} + +/* the struct for codec->pin_configs */ +struct hda_pincfg { + hda_nid_t nid; + unsigned char ctrl; /* original pin control value */ + unsigned char target; /* target pin control value */ + unsigned int cfg; /* default configuration */ +}; + +unsigned int snd_hda_codec_get_pincfg(struct hda_codec *codec, hda_nid_t nid); +int snd_hda_codec_set_pincfg(struct hda_codec *codec, hda_nid_t nid, + unsigned int cfg); +int snd_hda_add_pincfg(struct hda_codec *codec, struct snd_array *list, + hda_nid_t nid, unsigned int cfg); /* for hwdep */ +void snd_hda_shutup_pins(struct hda_codec *codec); + +/* SPDIF controls */ +struct hda_spdif_out { + hda_nid_t nid; /* Converter nid values relate to */ + unsigned int status; /* IEC958 status bits */ + unsigned short ctls; /* SPDIF control bits */ +}; +struct hda_spdif_out *snd_hda_spdif_out_of_nid(struct hda_codec *codec, + hda_nid_t nid); +void snd_hda_spdif_ctls_unassign(struct hda_codec *codec, int idx); +void snd_hda_spdif_ctls_assign(struct hda_codec *codec, int idx, hda_nid_t nid); + +/* + * Mixer + */ +int snd_hda_codec_build_controls(struct hda_codec *codec); + +/* + * PCM + */ +int snd_hda_codec_parse_pcms(struct hda_codec *codec); +int snd_hda_codec_build_pcms(struct hda_codec *codec); + +__printf(2, 3) +struct hda_pcm *snd_hda_codec_pcm_new(struct hda_codec *codec, + const char *fmt, ...); + +void snd_hda_codec_cleanup_for_unbind(struct hda_codec *codec); + +static inline void snd_hda_codec_pcm_get(struct hda_pcm *pcm) +{ + refcount_inc(&pcm->codec->pcm_ref); +} +void snd_hda_codec_pcm_put(struct hda_pcm *pcm); + +int snd_hda_codec_prepare(struct hda_codec *codec, + struct hda_pcm_stream *hinfo, + unsigned int stream, + unsigned int format, + struct snd_pcm_substream *substream); +void snd_hda_codec_cleanup(struct hda_codec *codec, + struct hda_pcm_stream *hinfo, + struct snd_pcm_substream *substream); + +void snd_hda_codec_setup_stream(struct hda_codec *codec, hda_nid_t nid, + u32 stream_tag, + int channel_id, int format); +void __snd_hda_codec_cleanup_stream(struct hda_codec *codec, hda_nid_t nid, + int do_now); +#define snd_hda_codec_cleanup_stream(codec, nid) \ + __snd_hda_codec_cleanup_stream(codec, nid, 0) + +#define snd_hda_query_supported_pcm(codec, nid, ratesp, fmtsp, bpsp) \ + snd_hdac_query_supported_pcm(&(codec)->core, nid, ratesp, fmtsp, bpsp) +#define snd_hda_is_supported_format(codec, nid, fmt) \ + snd_hdac_is_supported_format(&(codec)->core, nid, fmt) + +extern const struct snd_pcm_chmap_elem snd_pcm_2_1_chmaps[]; + +int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec, + struct hda_pcm *cpcm); + +/* + * Misc + */ +void snd_hda_get_codec_name(struct hda_codec *codec, char *name, int namelen); +void snd_hda_codec_set_power_to_all(struct hda_codec *codec, hda_nid_t fg, + unsigned int power_state); + +int snd_hda_lock_devices(struct hda_bus *bus); +void snd_hda_unlock_devices(struct hda_bus *bus); +void snd_hda_bus_reset(struct hda_bus *bus); +void snd_hda_bus_reset_codecs(struct hda_bus *bus); + +int snd_hda_codec_set_name(struct hda_codec *codec, const char *name); + +/* + * power management + */ +extern const struct dev_pm_ops hda_codec_driver_pm; + +static inline +int hda_call_check_power_status(struct hda_codec *codec, hda_nid_t nid) +{ +#ifdef CONFIG_PM + if (codec->patch_ops.check_power_status) + return codec->patch_ops.check_power_status(codec, nid); +#endif + return 0; +} + +/* + * power saving + */ +#define snd_hda_power_up(codec) snd_hdac_power_up(&(codec)->core) +#define snd_hda_power_up_pm(codec) snd_hdac_power_up_pm(&(codec)->core) +#define snd_hda_power_down(codec) snd_hdac_power_down(&(codec)->core) +#define snd_hda_power_down_pm(codec) snd_hdac_power_down_pm(&(codec)->core) +#ifdef CONFIG_PM +void snd_hda_codec_set_power_save(struct hda_codec *codec, int delay); +void snd_hda_set_power_save(struct hda_bus *bus, int delay); +void snd_hda_update_power_acct(struct hda_codec *codec); +#else +static inline void snd_hda_codec_set_power_save(struct hda_codec *codec, int delay) {} +static inline void snd_hda_set_power_save(struct hda_bus *bus, int delay) {} +#endif + +static inline bool hda_codec_need_resume(struct hda_codec *codec) +{ + return !codec->relaxed_resume && codec->jacktbl.used; +} + +#ifdef CONFIG_SND_HDA_PATCH_LOADER +/* + * patch firmware + */ +int snd_hda_load_patch(struct hda_bus *bus, size_t size, const void *buf); +#endif + +#ifdef CONFIG_SND_HDA_DSP_LOADER +int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format, + unsigned int size, + struct snd_dma_buffer *bufp); +void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start); +void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec, + struct snd_dma_buffer *dmab); +#else +static inline int +snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format, + unsigned int size, + struct snd_dma_buffer *bufp) +{ + return -ENOSYS; +} +static inline void +snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start) {} +static inline void +snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec, + struct snd_dma_buffer *dmab) {} +#endif + +#endif /* __SOUND_HDA_CODEC_H */ diff --git a/include/sound/hda_component.h b/include/sound/hda_component.h new file mode 100644 index 000000000..d4804c72d --- /dev/null +++ b/include/sound/hda_component.h @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +// HD-Audio helpers to sync with DRM driver + +#ifndef __SOUND_HDA_COMPONENT_H +#define __SOUND_HDA_COMPONENT_H + +#include <drm/drm_audio_component.h> +#include <sound/hdaudio.h> + +/* virtual idx for controller */ +#define HDA_CODEC_IDX_CONTROLLER HDA_MAX_CODECS + +#ifdef CONFIG_SND_HDA_COMPONENT +int snd_hdac_set_codec_wakeup(struct hdac_bus *bus, bool enable); +void snd_hdac_display_power(struct hdac_bus *bus, unsigned int idx, + bool enable); +int snd_hdac_sync_audio_rate(struct hdac_device *codec, hda_nid_t nid, + int dev_id, int rate); +int snd_hdac_acomp_get_eld(struct hdac_device *codec, hda_nid_t nid, int dev_id, + bool *audio_enabled, char *buffer, int max_bytes); +int snd_hdac_acomp_init(struct hdac_bus *bus, + const struct drm_audio_component_audio_ops *aops, + int (*match_master)(struct device *, int, void *), + size_t extra_size); +int snd_hdac_acomp_exit(struct hdac_bus *bus); +int snd_hdac_acomp_register_notifier(struct hdac_bus *bus, + const struct drm_audio_component_audio_ops *ops); +#else +static inline int snd_hdac_set_codec_wakeup(struct hdac_bus *bus, bool enable) +{ + return 0; +} +static inline void snd_hdac_display_power(struct hdac_bus *bus, + unsigned int idx, bool enable) +{ +} +static inline int snd_hdac_sync_audio_rate(struct hdac_device *codec, + hda_nid_t nid, int dev_id, int rate) +{ + return 0; +} +static inline int snd_hdac_acomp_get_eld(struct hdac_device *codec, hda_nid_t nid, + int dev_id, bool *audio_enabled, + char *buffer, int max_bytes) +{ + return -ENODEV; +} +static inline int snd_hdac_acomp_init(struct hdac_bus *bus, + const struct drm_audio_component_audio_ops *aops, + int (*match_master)(struct device *, + int, void *), + size_t extra_size) +{ + return -ENODEV; +} +static inline int snd_hdac_acomp_exit(struct hdac_bus *bus) +{ + return 0; +} +static inline int snd_hdac_acomp_register_notifier(struct hdac_bus *bus, + const struct drm_audio_component_audio_ops *ops) +{ + return -ENODEV; +} +#endif + +#endif /* __SOUND_HDA_COMPONENT_H */ diff --git a/include/sound/hda_hwdep.h b/include/sound/hda_hwdep.h new file mode 100644 index 000000000..f9b5b05ba --- /dev/null +++ b/include/sound/hda_hwdep.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * HWDEP Interface for HD-audio codec + * + * Copyright (c) 2007 Takashi Iwai <tiwai@suse.de> + */ + +#ifndef __SOUND_HDA_HWDEP_H +#define __SOUND_HDA_HWDEP_H + +#define HDA_HWDEP_VERSION ((1 << 16) | (0 << 8) | (0 << 0)) /* 1.0.0 */ + +/* verb */ +#define HDA_REG_NID_SHIFT 24 +#define HDA_REG_VERB_SHIFT 8 +#define HDA_REG_VAL_SHIFT 0 +#define HDA_VERB(nid,verb,param) ((nid)<<24 | (verb)<<8 | (param)) + +struct hda_verb_ioctl { + u32 verb; /* HDA_VERB() */ + u32 res; /* response */ +}; + +/* + * ioctls + */ +#define HDA_IOCTL_PVERSION _IOR('H', 0x10, int) +#define HDA_IOCTL_VERB_WRITE _IOWR('H', 0x11, struct hda_verb_ioctl) +#define HDA_IOCTL_GET_WCAP _IOWR('H', 0x12, struct hda_verb_ioctl) + +#endif diff --git a/include/sound/hda_i915.h b/include/sound/hda_i915.h new file mode 100644 index 000000000..6b79614a8 --- /dev/null +++ b/include/sound/hda_i915.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * HD-Audio helpers to sync with i915 driver + */ +#ifndef __SOUND_HDA_I915_H +#define __SOUND_HDA_I915_H + +#include "hda_component.h" + +#ifdef CONFIG_SND_HDA_I915 +void snd_hdac_i915_set_bclk(struct hdac_bus *bus); +int snd_hdac_i915_init(struct hdac_bus *bus); +#else +static inline void snd_hdac_i915_set_bclk(struct hdac_bus *bus) +{ +} +static inline int snd_hdac_i915_init(struct hdac_bus *bus) +{ + return -ENODEV; +} +#endif +static inline int snd_hdac_i915_exit(struct hdac_bus *bus) +{ + return snd_hdac_acomp_exit(bus); +} + +#endif /* __SOUND_HDA_I915_H */ diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h new file mode 100644 index 000000000..d37cf4354 --- /dev/null +++ b/include/sound/hda_register.h @@ -0,0 +1,328 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * HD-audio controller (Azalia) registers and helpers + * + * For traditional reasons, we still use azx_ prefix here + */ + +#ifndef __SOUND_HDA_REGISTER_H +#define __SOUND_HDA_REGISTER_H + +#include <linux/io.h> +#include <sound/hdaudio.h> + +#define AZX_REG_GCAP 0x00 +#define AZX_GCAP_64OK (1 << 0) /* 64bit address support */ +#define AZX_GCAP_NSDO (3 << 1) /* # of serial data out signals */ +#define AZX_GCAP_BSS (31 << 3) /* # of bidirectional streams */ +#define AZX_GCAP_ISS (15 << 8) /* # of input streams */ +#define AZX_GCAP_OSS (15 << 12) /* # of output streams */ +#define AZX_REG_VMIN 0x02 +#define AZX_REG_VMAJ 0x03 +#define AZX_REG_OUTPAY 0x04 +#define AZX_REG_INPAY 0x06 +#define AZX_REG_GCTL 0x08 +#define AZX_GCTL_RESET (1 << 0) /* controller reset */ +#define AZX_GCTL_FCNTRL (1 << 1) /* flush control */ +#define AZX_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ +#define AZX_REG_WAKEEN 0x0c +#define AZX_REG_STATESTS 0x0e +#define AZX_REG_GSTS 0x10 +#define AZX_GSTS_FSTS (1 << 1) /* flush status */ +#define AZX_REG_GCAP2 0x12 +#define AZX_REG_LLCH 0x14 +#define AZX_REG_OUTSTRMPAY 0x18 +#define AZX_REG_INSTRMPAY 0x1A +#define AZX_REG_INTCTL 0x20 +#define AZX_REG_INTSTS 0x24 +#define AZX_REG_WALLCLK 0x30 /* 24Mhz source */ +#define AZX_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */ +#define AZX_REG_SSYNC 0x38 +#define AZX_REG_CORBLBASE 0x40 +#define AZX_REG_CORBUBASE 0x44 +#define AZX_REG_CORBWP 0x48 +#define AZX_REG_CORBRP 0x4a +#define AZX_CORBRP_RST (1 << 15) /* read pointer reset */ +#define AZX_REG_CORBCTL 0x4c +#define AZX_CORBCTL_RUN (1 << 1) /* enable DMA */ +#define AZX_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ +#define AZX_REG_CORBSTS 0x4d +#define AZX_CORBSTS_CMEI (1 << 0) /* memory error indication */ +#define AZX_REG_CORBSIZE 0x4e + +#define AZX_REG_RIRBLBASE 0x50 +#define AZX_REG_RIRBUBASE 0x54 +#define AZX_REG_RIRBWP 0x58 +#define AZX_RIRBWP_RST (1 << 15) /* write pointer reset */ +#define AZX_REG_RINTCNT 0x5a +#define AZX_REG_RIRBCTL 0x5c +#define AZX_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ +#define AZX_RBCTL_DMA_EN (1 << 1) /* enable DMA */ +#define AZX_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ +#define AZX_REG_RIRBSTS 0x5d +#define AZX_RBSTS_IRQ (1 << 0) /* response irq */ +#define AZX_RBSTS_OVERRUN (1 << 2) /* overrun irq */ +#define AZX_REG_RIRBSIZE 0x5e + +#define AZX_REG_IC 0x60 +#define AZX_REG_IR 0x64 +#define AZX_REG_IRS 0x68 +#define AZX_IRS_VALID (1<<1) +#define AZX_IRS_BUSY (1<<0) + +#define AZX_REG_DPLBASE 0x70 +#define AZX_REG_DPUBASE 0x74 +#define AZX_DPLBASE_ENABLE 0x1 /* Enable position buffer */ + +/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ +enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; + +/* stream register offsets from stream base */ +#define AZX_REG_SD_CTL 0x00 +#define AZX_REG_SD_CTL_3B 0x02 /* 3rd byte of SD_CTL register */ +#define AZX_REG_SD_STS 0x03 +#define AZX_REG_SD_LPIB 0x04 +#define AZX_REG_SD_CBL 0x08 +#define AZX_REG_SD_LVI 0x0c +#define AZX_REG_SD_FIFOW 0x0e +#define AZX_REG_SD_FIFOSIZE 0x10 +#define AZX_REG_SD_FORMAT 0x12 +#define AZX_REG_SD_FIFOL 0x14 +#define AZX_REG_SD_BDLPL 0x18 +#define AZX_REG_SD_BDLPU 0x1c + +/* GTS registers */ +#define AZX_REG_LLCH 0x14 + +#define AZX_REG_GTS_BASE 0x520 + +#define AZX_REG_GTSCC (AZX_REG_GTS_BASE + 0x00) +#define AZX_REG_WALFCC (AZX_REG_GTS_BASE + 0x04) +#define AZX_REG_TSCCL (AZX_REG_GTS_BASE + 0x08) +#define AZX_REG_TSCCU (AZX_REG_GTS_BASE + 0x0C) +#define AZX_REG_LLPFOC (AZX_REG_GTS_BASE + 0x14) +#define AZX_REG_LLPCL (AZX_REG_GTS_BASE + 0x18) +#define AZX_REG_LLPCU (AZX_REG_GTS_BASE + 0x1C) + +/* Haswell/Broadwell display HD-A controller Extended Mode registers */ +#define AZX_REG_HSW_EM4 0x100c +#define AZX_REG_HSW_EM5 0x1010 + +/* Skylake/Broxton vendor-specific registers */ +#define AZX_REG_VS_EM1 0x1000 +#define AZX_REG_VS_INRC 0x1004 +#define AZX_REG_VS_OUTRC 0x1008 +#define AZX_REG_VS_FIFOTRK 0x100C +#define AZX_REG_VS_FIFOTRK2 0x1010 +#define AZX_REG_VS_EM2 0x1030 +#define AZX_REG_VS_EM3L 0x1038 +#define AZX_REG_VS_EM3U 0x103C +#define AZX_REG_VS_EM4L 0x1040 +#define AZX_REG_VS_EM4U 0x1044 +#define AZX_REG_VS_LTRP 0x1048 +#define AZX_REG_VS_D0I3C 0x104A +#define AZX_REG_VS_PCE 0x104B +#define AZX_REG_VS_L2MAGC 0x1050 +#define AZX_REG_VS_L2LAHPT 0x1054 +#define AZX_REG_VS_SDXDPIB_XBASE 0x1084 +#define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20 +#define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094 +#define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20 + +/* PCI space */ +#define AZX_PCIREG_TCSEL 0x44 + +/* + * other constants + */ + +/* max number of fragments - we may use more if allocating more pages for BDL */ +#define BDL_SIZE 4096 +#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) +#define AZX_MAX_FRAG 32 +/* + * max buffer size - artificial 4MB limit per stream to avoid big allocations + * In theory it can be really big, but as it is per stream on systems with many streams memory could + * be quickly saturated if userspace requests maximum buffer size for each of them. + */ +#define AZX_MAX_BUF_SIZE (4*1024*1024) + +/* RIRB int mask: overrun[2], response[0] */ +#define RIRB_INT_RESPONSE 0x01 +#define RIRB_INT_OVERRUN 0x04 +#define RIRB_INT_MASK 0x05 + +/* STATESTS int mask: S3,SD2,SD1,SD0 */ +#define STATESTS_INT_MASK ((1 << HDA_MAX_CODECS) - 1) + +/* SD_CTL bits */ +#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ +#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ +#define SD_CTL_STRIPE (3 << 16) /* stripe control */ +#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ +#define SD_CTL_DIR (1 << 19) /* bi-directional stream */ +#define SD_CTL_STREAM_TAG_MASK (0xf << 20) +#define SD_CTL_STREAM_TAG_SHIFT 20 + +/* SD_CTL and SD_STS */ +#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ +#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ +#define SD_INT_COMPLETE 0x04 /* completion interrupt */ +#define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ + SD_INT_COMPLETE) +#define SD_CTL_STRIPE_MASK 0x3 /* stripe control mask */ + +/* SD_STS */ +#define SD_STS_FIFO_READY 0x20 /* FIFO ready */ + +/* INTCTL and INTSTS */ +#define AZX_INT_ALL_STREAM 0xff /* all stream interrupts */ +#define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ +#define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ + +/* below are so far hardcoded - should read registers in future */ +#define AZX_MAX_CORB_ENTRIES 256 +#define AZX_MAX_RIRB_ENTRIES 256 + +/* Capability header Structure */ +#define AZX_REG_CAP_HDR 0x0 +#define AZX_CAP_HDR_VER_OFF 28 +#define AZX_CAP_HDR_VER_MASK (0xF << AZX_CAP_HDR_VER_OFF) +#define AZX_CAP_HDR_ID_OFF 16 +#define AZX_CAP_HDR_ID_MASK (0xFFF << AZX_CAP_HDR_ID_OFF) +#define AZX_CAP_HDR_NXT_PTR_MASK 0xFFFF + +/* registers of Software Position Based FIFO Capability Structure */ +#define AZX_SPB_CAP_ID 0x4 +#define AZX_REG_SPB_BASE_ADDR 0x700 +#define AZX_REG_SPB_SPBFCH 0x00 +#define AZX_REG_SPB_SPBFCCTL 0x04 +/* Base used to calculate the iterating register offset */ +#define AZX_SPB_BASE 0x08 +/* Interval used to calculate the iterating register offset */ +#define AZX_SPB_INTERVAL 0x08 +/* SPIB base */ +#define AZX_SPB_SPIB 0x00 +/* SPIB MAXFIFO base*/ +#define AZX_SPB_MAXFIFO 0x04 + +/* registers of Global Time Synchronization Capability Structure */ +#define AZX_GTS_CAP_ID 0x1 +#define AZX_REG_GTS_GTSCH 0x00 +#define AZX_REG_GTS_GTSCD 0x04 +#define AZX_REG_GTS_GTSCTLAC 0x0C +#define AZX_GTS_BASE 0x20 +#define AZX_GTS_INTERVAL 0x20 + +/* registers for Processing Pipe Capability Structure */ +#define AZX_PP_CAP_ID 0x3 +#define AZX_REG_PP_PPCH 0x10 +#define AZX_REG_PP_PPCTL 0x04 +#define AZX_PPCTL_PIE (1<<31) +#define AZX_PPCTL_GPROCEN (1<<30) +/* _X_ = dma engine # and cannot * exceed 29 (per spec max 30 dma engines) */ +#define AZX_PPCTL_PROCEN(_X_) (1<<(_X_)) + +#define AZX_REG_PP_PPSTS 0x08 + +#define AZX_PPHC_BASE 0x10 +#define AZX_PPHC_INTERVAL 0x10 + +#define AZX_REG_PPHCLLPL 0x0 +#define AZX_REG_PPHCLLPU 0x4 +#define AZX_REG_PPHCLDPL 0x8 +#define AZX_REG_PPHCLDPU 0xC + +#define AZX_PPLC_BASE 0x10 +#define AZX_PPLC_MULTI 0x10 +#define AZX_PPLC_INTERVAL 0x10 + +#define AZX_REG_PPLCCTL 0x0 +#define AZX_PPLCCTL_STRM_BITS 4 +#define AZX_PPLCCTL_STRM_SHIFT 20 +#define AZX_REG_MASK(bit_num, offset) \ + (((1 << (bit_num)) - 1) << (offset)) +#define AZX_PPLCCTL_STRM_MASK \ + AZX_REG_MASK(AZX_PPLCCTL_STRM_BITS, AZX_PPLCCTL_STRM_SHIFT) +#define AZX_PPLCCTL_RUN (1<<1) +#define AZX_PPLCCTL_STRST (1<<0) + +#define AZX_REG_PPLCFMT 0x4 +#define AZX_REG_PPLCLLPL 0x8 +#define AZX_REG_PPLCLLPU 0xC + +/* registers for Multiple Links Capability Structure */ +#define AZX_ML_CAP_ID 0x2 +#define AZX_REG_ML_MLCH 0x00 +#define AZX_REG_ML_MLCD 0x04 +#define AZX_ML_BASE 0x40 +#define AZX_ML_INTERVAL 0x40 + +#define AZX_REG_ML_LCAP 0x00 +#define AZX_REG_ML_LCTL 0x04 + +#define AZX_ML_LCTL_CPA BIT(23) +#define AZX_ML_LCTL_CPA_SHIFT 23 +#define AZX_ML_LCTL_SPA BIT(16) +#define AZX_ML_LCTL_SPA_SHIFT 16 +#define AZX_ML_LCTL_SCF GENMASK(3, 0) + +#define AZX_REG_ML_LOSIDV 0x08 + +/* bit0 is reserved, with BIT(1) mapping to stream1 */ +#define AZX_ML_LOSIDV_STREAM_MASK 0xFFFE + +#define AZX_REG_ML_LSDIID 0x0C +#define AZX_REG_ML_LPSOO 0x10 +#define AZX_REG_ML_LPSIO 0x12 +#define AZX_REG_ML_LWALFC 0x18 +#define AZX_REG_ML_LOUTPAY 0x20 +#define AZX_REG_ML_LINPAY 0x30 + +/* registers for DMA Resume Capability Structure */ +#define AZX_DRSM_CAP_ID 0x5 +#define AZX_REG_DRSM_CTL 0x4 +/* Base used to calculate the iterating register offset */ +#define AZX_DRSM_BASE 0x08 +/* Interval used to calculate the iterating register offset */ +#define AZX_DRSM_INTERVAL 0x08 + +/* Global time synchronization registers */ +#define GTSCC_TSCCD_MASK 0x80000000 +#define GTSCC_TSCCD_SHIFT BIT(31) +#define GTSCC_TSCCI_MASK 0x20 +#define GTSCC_CDMAS_DMA_DIR_SHIFT 4 + +#define WALFCC_CIF_MASK 0x1FF +#define WALFCC_FN_SHIFT 9 +#define HDA_CLK_CYCLES_PER_FRAME 512 + +/* + * An error occurs near frame "rollover". The clocks in frame value indicates + * whether this error may have occurred. Here we use the value of 10. Please + * see the errata for the right number [<10] + */ +#define HDA_MAX_CYCLE_VALUE 499 +#define HDA_MAX_CYCLE_OFFSET 10 +#define HDA_MAX_CYCLE_READ_RETRY 10 + +#define TSCCU_CCU_SHIFT 32 +#define LLPC_CCU_SHIFT 32 + + +/* + * helpers to read the stream position + */ +static inline unsigned int +snd_hdac_stream_get_pos_lpib(struct hdac_stream *stream) +{ + return snd_hdac_stream_readl(stream, SD_LPIB); +} + +static inline unsigned int +snd_hdac_stream_get_pos_posbuf(struct hdac_stream *stream) +{ + return le32_to_cpu(*stream->posbuf); +} + +#endif /* __SOUND_HDA_REGISTER_H */ diff --git a/include/sound/hda_regmap.h b/include/sound/hda_regmap.h new file mode 100644 index 000000000..4c1b9bebb --- /dev/null +++ b/include/sound/hda_regmap.h @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * HD-audio regmap helpers + */ + +#ifndef __SOUND_HDA_REGMAP_H +#define __SOUND_HDA_REGMAP_H + +#include <linux/regmap.h> +#include <sound/core.h> +#include <sound/hdaudio.h> + +#define AC_AMP_FAKE_MUTE 0x10 /* fake mute bit set to amp verbs */ + +int snd_hdac_regmap_init(struct hdac_device *codec); +void snd_hdac_regmap_exit(struct hdac_device *codec); +int snd_hdac_regmap_add_vendor_verb(struct hdac_device *codec, + unsigned int verb); +int snd_hdac_regmap_read_raw(struct hdac_device *codec, unsigned int reg, + unsigned int *val); +int snd_hdac_regmap_read_raw_uncached(struct hdac_device *codec, + unsigned int reg, unsigned int *val); +int snd_hdac_regmap_write_raw(struct hdac_device *codec, unsigned int reg, + unsigned int val); +int snd_hdac_regmap_update_raw(struct hdac_device *codec, unsigned int reg, + unsigned int mask, unsigned int val); +int snd_hdac_regmap_update_raw_once(struct hdac_device *codec, unsigned int reg, + unsigned int mask, unsigned int val); +void snd_hdac_regmap_sync(struct hdac_device *codec); + +/** + * snd_hdac_regmap_encode_verb - encode the verb to a pseudo register + * @nid: widget NID + * @verb: codec verb + * + * Returns an encoded pseudo register. + */ +#define snd_hdac_regmap_encode_verb(nid, verb) \ + (((verb) << 8) | 0x80000 | ((unsigned int)(nid) << 20)) + +/** + * snd_hdac_regmap_encode_amp - encode the AMP verb to a pseudo register + * @nid: widget NID + * @ch: channel (left = 0, right = 1) + * @dir: direction (#HDA_INPUT, #HDA_OUTPUT) + * @idx: input index value + * + * Returns an encoded pseudo register. + */ +#define snd_hdac_regmap_encode_amp(nid, ch, dir, idx) \ + (snd_hdac_regmap_encode_verb(nid, AC_VERB_GET_AMP_GAIN_MUTE) | \ + ((ch) ? AC_AMP_GET_RIGHT : AC_AMP_GET_LEFT) | \ + ((dir) == HDA_OUTPUT ? AC_AMP_GET_OUTPUT : AC_AMP_GET_INPUT) | \ + (idx)) + +/** + * snd_hdac_regmap_encode_amp_stereo - encode a pseudo register for stereo AMPs + * @nid: widget NID + * @dir: direction (#HDA_INPUT, #HDA_OUTPUT) + * @idx: input index value + * + * Returns an encoded pseudo register. + */ +#define snd_hdac_regmap_encode_amp_stereo(nid, dir, idx) \ + (snd_hdac_regmap_encode_verb(nid, AC_VERB_GET_AMP_GAIN_MUTE) | \ + AC_AMP_SET_LEFT | AC_AMP_SET_RIGHT | /* both bits set! */ \ + ((dir) == HDA_OUTPUT ? AC_AMP_GET_OUTPUT : AC_AMP_GET_INPUT) | \ + (idx)) + +/** + * snd_hdac_regmap_write - Write a verb with caching + * @nid: codec NID + * @reg: verb to write + * @val: value to write + * + * For writing an amp value, use snd_hdac_regmap_update_amp(). + */ +static inline int +snd_hdac_regmap_write(struct hdac_device *codec, hda_nid_t nid, + unsigned int verb, unsigned int val) +{ + unsigned int cmd = snd_hdac_regmap_encode_verb(nid, verb); + + return snd_hdac_regmap_write_raw(codec, cmd, val); +} + +/** + * snd_hda_regmap_update - Update a verb value with caching + * @nid: codec NID + * @verb: verb to update + * @mask: bit mask to update + * @val: value to update + * + * For updating an amp value, use snd_hdac_regmap_update_amp(). + */ +static inline int +snd_hdac_regmap_update(struct hdac_device *codec, hda_nid_t nid, + unsigned int verb, unsigned int mask, + unsigned int val) +{ + unsigned int cmd = snd_hdac_regmap_encode_verb(nid, verb); + + return snd_hdac_regmap_update_raw(codec, cmd, mask, val); +} + +/** + * snd_hda_regmap_read - Read a verb with caching + * @nid: codec NID + * @verb: verb to read + * @val: pointer to store the value + * + * For reading an amp value, use snd_hda_regmap_get_amp(). + */ +static inline int +snd_hdac_regmap_read(struct hdac_device *codec, hda_nid_t nid, + unsigned int verb, unsigned int *val) +{ + unsigned int cmd = snd_hdac_regmap_encode_verb(nid, verb); + + return snd_hdac_regmap_read_raw(codec, cmd, val); +} + +/** + * snd_hdac_regmap_get_amp - Read AMP value + * @codec: HD-audio codec + * @nid: NID to read the AMP value + * @ch: channel (left=0 or right=1) + * @direction: #HDA_INPUT or #HDA_OUTPUT + * @index: the index value (only for input direction) + * @val: the pointer to store the value + * + * Read AMP value. The volume is between 0 to 0x7f, 0x80 = mute bit. + * Returns the value or a negative error. + */ +static inline int +snd_hdac_regmap_get_amp(struct hdac_device *codec, hda_nid_t nid, + int ch, int dir, int idx) +{ + unsigned int cmd = snd_hdac_regmap_encode_amp(nid, ch, dir, idx); + int err, val; + + err = snd_hdac_regmap_read_raw(codec, cmd, &val); + return err < 0 ? err : val; +} + +/** + * snd_hdac_regmap_update_amp - update the AMP value + * @codec: HD-audio codec + * @nid: NID to read the AMP value + * @ch: channel (left=0 or right=1) + * @direction: #HDA_INPUT or #HDA_OUTPUT + * @idx: the index value (only for input direction) + * @mask: bit mask to set + * @val: the bits value to set + * + * Update the AMP value with a bit mask. + * Returns 0 if the value is unchanged, 1 if changed, or a negative error. + */ +static inline int +snd_hdac_regmap_update_amp(struct hdac_device *codec, hda_nid_t nid, + int ch, int dir, int idx, int mask, int val) +{ + unsigned int cmd = snd_hdac_regmap_encode_amp(nid, ch, dir, idx); + + return snd_hdac_regmap_update_raw(codec, cmd, mask, val); +} + +/** + * snd_hdac_regmap_get_amp_stereo - Read stereo AMP values + * @codec: HD-audio codec + * @nid: NID to read the AMP value + * @ch: channel (left=0 or right=1) + * @direction: #HDA_INPUT or #HDA_OUTPUT + * @index: the index value (only for input direction) + * @val: the pointer to store the value + * + * Read stereo AMP values. The lower byte is left, the upper byte is right. + * Returns the value or a negative error. + */ +static inline int +snd_hdac_regmap_get_amp_stereo(struct hdac_device *codec, hda_nid_t nid, + int dir, int idx) +{ + unsigned int cmd = snd_hdac_regmap_encode_amp_stereo(nid, dir, idx); + int err, val; + + err = snd_hdac_regmap_read_raw(codec, cmd, &val); + return err < 0 ? err : val; +} + +/** + * snd_hdac_regmap_update_amp_stereo - update the stereo AMP value + * @codec: HD-audio codec + * @nid: NID to read the AMP value + * @direction: #HDA_INPUT or #HDA_OUTPUT + * @idx: the index value (only for input direction) + * @mask: bit mask to set + * @val: the bits value to set + * + * Update the stereo AMP value with a bit mask. + * The lower byte is left, the upper byte is right. + * Returns 0 if the value is unchanged, 1 if changed, or a negative error. + */ +static inline int +snd_hdac_regmap_update_amp_stereo(struct hdac_device *codec, hda_nid_t nid, + int dir, int idx, int mask, int val) +{ + unsigned int cmd = snd_hdac_regmap_encode_amp_stereo(nid, dir, idx); + + return snd_hdac_regmap_update_raw(codec, cmd, mask, val); +} + +/** + * snd_hdac_regmap_sync_node - sync the widget node attributes + * @codec: HD-audio codec + * @nid: NID to sync + */ +static inline void +snd_hdac_regmap_sync_node(struct hdac_device *codec, hda_nid_t nid) +{ + regcache_mark_dirty(codec->regmap); + regcache_sync_region(codec->regmap, nid << 20, ((nid + 1) << 20) - 1); +} + +#endif /* __SOUND_HDA_REGMAP_H */ diff --git a/include/sound/hda_verbs.h b/include/sound/hda_verbs.h new file mode 100644 index 000000000..006d358ac --- /dev/null +++ b/include/sound/hda_verbs.h @@ -0,0 +1,558 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * HD-audio codec verbs + */ + +#ifndef __SOUND_HDA_VERBS_H +#define __SOUND_HDA_VERBS_H + +/* + * nodes + */ +#define AC_NODE_ROOT 0x00 + +/* + * function group types + */ +enum { + AC_GRP_AUDIO_FUNCTION = 0x01, + AC_GRP_MODEM_FUNCTION = 0x02, +}; + +/* + * widget types + */ +enum { + AC_WID_AUD_OUT, /* Audio Out */ + AC_WID_AUD_IN, /* Audio In */ + AC_WID_AUD_MIX, /* Audio Mixer */ + AC_WID_AUD_SEL, /* Audio Selector */ + AC_WID_PIN, /* Pin Complex */ + AC_WID_POWER, /* Power */ + AC_WID_VOL_KNB, /* Volume Knob */ + AC_WID_BEEP, /* Beep Generator */ + AC_WID_VENDOR = 0x0f /* Vendor specific */ +}; + +/* + * GET verbs + */ +#define AC_VERB_GET_STREAM_FORMAT 0x0a00 +#define AC_VERB_GET_AMP_GAIN_MUTE 0x0b00 +#define AC_VERB_GET_PROC_COEF 0x0c00 +#define AC_VERB_GET_COEF_INDEX 0x0d00 +#define AC_VERB_PARAMETERS 0x0f00 +#define AC_VERB_GET_CONNECT_SEL 0x0f01 +#define AC_VERB_GET_CONNECT_LIST 0x0f02 +#define AC_VERB_GET_PROC_STATE 0x0f03 +#define AC_VERB_GET_SDI_SELECT 0x0f04 +#define AC_VERB_GET_POWER_STATE 0x0f05 +#define AC_VERB_GET_CONV 0x0f06 +#define AC_VERB_GET_PIN_WIDGET_CONTROL 0x0f07 +#define AC_VERB_GET_UNSOLICITED_RESPONSE 0x0f08 +#define AC_VERB_GET_PIN_SENSE 0x0f09 +#define AC_VERB_GET_BEEP_CONTROL 0x0f0a +#define AC_VERB_GET_EAPD_BTLENABLE 0x0f0c +#define AC_VERB_GET_DIGI_CONVERT_1 0x0f0d +#define AC_VERB_GET_DIGI_CONVERT_2 0x0f0e /* unused */ +#define AC_VERB_GET_VOLUME_KNOB_CONTROL 0x0f0f +/* f10-f1a: GPIO */ +#define AC_VERB_GET_GPIO_DATA 0x0f15 +#define AC_VERB_GET_GPIO_MASK 0x0f16 +#define AC_VERB_GET_GPIO_DIRECTION 0x0f17 +#define AC_VERB_GET_GPIO_WAKE_MASK 0x0f18 +#define AC_VERB_GET_GPIO_UNSOLICITED_RSP_MASK 0x0f19 +#define AC_VERB_GET_GPIO_STICKY_MASK 0x0f1a +#define AC_VERB_GET_CONFIG_DEFAULT 0x0f1c +/* f20: AFG/MFG */ +#define AC_VERB_GET_SUBSYSTEM_ID 0x0f20 +#define AC_VERB_GET_STRIPE_CONTROL 0x0f24 +#define AC_VERB_GET_CVT_CHAN_COUNT 0x0f2d +#define AC_VERB_GET_HDMI_DIP_SIZE 0x0f2e +#define AC_VERB_GET_HDMI_ELDD 0x0f2f +#define AC_VERB_GET_HDMI_DIP_INDEX 0x0f30 +#define AC_VERB_GET_HDMI_DIP_DATA 0x0f31 +#define AC_VERB_GET_HDMI_DIP_XMIT 0x0f32 +#define AC_VERB_GET_HDMI_CP_CTRL 0x0f33 +#define AC_VERB_GET_HDMI_CHAN_SLOT 0x0f34 +#define AC_VERB_GET_DEVICE_SEL 0xf35 +#define AC_VERB_GET_DEVICE_LIST 0xf36 + +/* + * SET verbs + */ +#define AC_VERB_SET_STREAM_FORMAT 0x200 +#define AC_VERB_SET_AMP_GAIN_MUTE 0x300 +#define AC_VERB_SET_PROC_COEF 0x400 +#define AC_VERB_SET_COEF_INDEX 0x500 +#define AC_VERB_SET_CONNECT_SEL 0x701 +#define AC_VERB_SET_PROC_STATE 0x703 +#define AC_VERB_SET_SDI_SELECT 0x704 +#define AC_VERB_SET_POWER_STATE 0x705 +#define AC_VERB_SET_CHANNEL_STREAMID 0x706 +#define AC_VERB_SET_PIN_WIDGET_CONTROL 0x707 +#define AC_VERB_SET_UNSOLICITED_ENABLE 0x708 +#define AC_VERB_SET_PIN_SENSE 0x709 +#define AC_VERB_SET_BEEP_CONTROL 0x70a +#define AC_VERB_SET_EAPD_BTLENABLE 0x70c +#define AC_VERB_SET_DIGI_CONVERT_1 0x70d +#define AC_VERB_SET_DIGI_CONVERT_2 0x70e +#define AC_VERB_SET_DIGI_CONVERT_3 0x73e +#define AC_VERB_SET_VOLUME_KNOB_CONTROL 0x70f +#define AC_VERB_SET_GPIO_DATA 0x715 +#define AC_VERB_SET_GPIO_MASK 0x716 +#define AC_VERB_SET_GPIO_DIRECTION 0x717 +#define AC_VERB_SET_GPIO_WAKE_MASK 0x718 +#define AC_VERB_SET_GPIO_UNSOLICITED_RSP_MASK 0x719 +#define AC_VERB_SET_GPIO_STICKY_MASK 0x71a +#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_0 0x71c +#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_1 0x71d +#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_2 0x71e +#define AC_VERB_SET_CONFIG_DEFAULT_BYTES_3 0x71f +#define AC_VERB_SET_EAPD 0x788 +#define AC_VERB_SET_CODEC_RESET 0x7ff +#define AC_VERB_SET_STRIPE_CONTROL 0x724 +#define AC_VERB_SET_CVT_CHAN_COUNT 0x72d +#define AC_VERB_SET_HDMI_DIP_INDEX 0x730 +#define AC_VERB_SET_HDMI_DIP_DATA 0x731 +#define AC_VERB_SET_HDMI_DIP_XMIT 0x732 +#define AC_VERB_SET_HDMI_CP_CTRL 0x733 +#define AC_VERB_SET_HDMI_CHAN_SLOT 0x734 +#define AC_VERB_SET_DEVICE_SEL 0x735 + +/* + * Parameter IDs + */ +#define AC_PAR_VENDOR_ID 0x00 +#define AC_PAR_SUBSYSTEM_ID 0x01 +#define AC_PAR_REV_ID 0x02 +#define AC_PAR_NODE_COUNT 0x04 +#define AC_PAR_FUNCTION_TYPE 0x05 +#define AC_PAR_AUDIO_FG_CAP 0x08 +#define AC_PAR_AUDIO_WIDGET_CAP 0x09 +#define AC_PAR_PCM 0x0a +#define AC_PAR_STREAM 0x0b +#define AC_PAR_PIN_CAP 0x0c +#define AC_PAR_AMP_IN_CAP 0x0d +#define AC_PAR_CONNLIST_LEN 0x0e +#define AC_PAR_POWER_STATE 0x0f +#define AC_PAR_PROC_CAP 0x10 +#define AC_PAR_GPIO_CAP 0x11 +#define AC_PAR_AMP_OUT_CAP 0x12 +#define AC_PAR_VOL_KNB_CAP 0x13 +#define AC_PAR_DEVLIST_LEN 0x15 +#define AC_PAR_HDMI_LPCM_CAP 0x20 + +/* + * AC_VERB_PARAMETERS results (32bit) + */ + +/* Function Group Type */ +#define AC_FGT_TYPE (0xff<<0) +#define AC_FGT_TYPE_SHIFT 0 +#define AC_FGT_UNSOL_CAP (1<<8) + +/* Audio Function Group Capabilities */ +#define AC_AFG_OUT_DELAY (0xf<<0) +#define AC_AFG_IN_DELAY (0xf<<8) +#define AC_AFG_BEEP_GEN (1<<16) + +/* Audio Widget Capabilities */ +#define AC_WCAP_STEREO (1<<0) /* stereo I/O */ +#define AC_WCAP_IN_AMP (1<<1) /* AMP-in present */ +#define AC_WCAP_OUT_AMP (1<<2) /* AMP-out present */ +#define AC_WCAP_AMP_OVRD (1<<3) /* AMP-parameter override */ +#define AC_WCAP_FORMAT_OVRD (1<<4) /* format override */ +#define AC_WCAP_STRIPE (1<<5) /* stripe */ +#define AC_WCAP_PROC_WID (1<<6) /* Proc Widget */ +#define AC_WCAP_UNSOL_CAP (1<<7) /* Unsol capable */ +#define AC_WCAP_CONN_LIST (1<<8) /* connection list */ +#define AC_WCAP_DIGITAL (1<<9) /* digital I/O */ +#define AC_WCAP_POWER (1<<10) /* power control */ +#define AC_WCAP_LR_SWAP (1<<11) /* L/R swap */ +#define AC_WCAP_CP_CAPS (1<<12) /* content protection */ +#define AC_WCAP_CHAN_CNT_EXT (7<<13) /* channel count ext */ +#define AC_WCAP_DELAY (0xf<<16) +#define AC_WCAP_DELAY_SHIFT 16 +#define AC_WCAP_TYPE (0xf<<20) +#define AC_WCAP_TYPE_SHIFT 20 + +/* supported PCM rates and bits */ +#define AC_SUPPCM_RATES (0xfff << 0) +#define AC_SUPPCM_BITS_8 (1<<16) +#define AC_SUPPCM_BITS_16 (1<<17) +#define AC_SUPPCM_BITS_20 (1<<18) +#define AC_SUPPCM_BITS_24 (1<<19) +#define AC_SUPPCM_BITS_32 (1<<20) + +/* supported PCM stream format */ +#define AC_SUPFMT_PCM (1<<0) +#define AC_SUPFMT_FLOAT32 (1<<1) +#define AC_SUPFMT_AC3 (1<<2) + +/* GP I/O count */ +#define AC_GPIO_IO_COUNT (0xff<<0) +#define AC_GPIO_O_COUNT (0xff<<8) +#define AC_GPIO_O_COUNT_SHIFT 8 +#define AC_GPIO_I_COUNT (0xff<<16) +#define AC_GPIO_I_COUNT_SHIFT 16 +#define AC_GPIO_UNSOLICITED (1<<30) +#define AC_GPIO_WAKE (1<<31) + +/* Converter stream, channel */ +#define AC_CONV_CHANNEL (0xf<<0) +#define AC_CONV_STREAM (0xf<<4) +#define AC_CONV_STREAM_SHIFT 4 + +/* Input converter SDI select */ +#define AC_SDI_SELECT (0xf<<0) + +/* stream format id */ +#define AC_FMT_CHAN_SHIFT 0 +#define AC_FMT_CHAN_MASK (0x0f << 0) +#define AC_FMT_BITS_SHIFT 4 +#define AC_FMT_BITS_MASK (7 << 4) +#define AC_FMT_BITS_8 (0 << 4) +#define AC_FMT_BITS_16 (1 << 4) +#define AC_FMT_BITS_20 (2 << 4) +#define AC_FMT_BITS_24 (3 << 4) +#define AC_FMT_BITS_32 (4 << 4) +#define AC_FMT_DIV_SHIFT 8 +#define AC_FMT_DIV_MASK (7 << 8) +#define AC_FMT_MULT_SHIFT 11 +#define AC_FMT_MULT_MASK (7 << 11) +#define AC_FMT_BASE_SHIFT 14 +#define AC_FMT_BASE_48K (0 << 14) +#define AC_FMT_BASE_44K (1 << 14) +#define AC_FMT_TYPE_SHIFT 15 +#define AC_FMT_TYPE_PCM (0 << 15) +#define AC_FMT_TYPE_NON_PCM (1 << 15) + +/* Unsolicited response control */ +#define AC_UNSOL_TAG (0x3f<<0) +#define AC_UNSOL_ENABLED (1<<7) +#define AC_USRSP_EN AC_UNSOL_ENABLED + +/* Unsolicited responses */ +#define AC_UNSOL_RES_TAG (0x3f<<26) +#define AC_UNSOL_RES_TAG_SHIFT 26 +#define AC_UNSOL_RES_SUBTAG (0x1f<<21) +#define AC_UNSOL_RES_SUBTAG_SHIFT 21 +#define AC_UNSOL_RES_DE (0x3f<<15) /* Device Entry + * (for DP1.2 MST) + */ +#define AC_UNSOL_RES_DE_SHIFT 15 +#define AC_UNSOL_RES_IA (1<<2) /* Inactive (for DP1.2 MST) */ +#define AC_UNSOL_RES_ELDV (1<<1) /* ELD Data valid (for HDMI) */ +#define AC_UNSOL_RES_PD (1<<0) /* pinsense detect */ +#define AC_UNSOL_RES_CP_STATE (1<<1) /* content protection */ +#define AC_UNSOL_RES_CP_READY (1<<0) /* content protection */ + +/* Pin widget capabilies */ +#define AC_PINCAP_IMP_SENSE (1<<0) /* impedance sense capable */ +#define AC_PINCAP_TRIG_REQ (1<<1) /* trigger required */ +#define AC_PINCAP_PRES_DETECT (1<<2) /* presence detect capable */ +#define AC_PINCAP_HP_DRV (1<<3) /* headphone drive capable */ +#define AC_PINCAP_OUT (1<<4) /* output capable */ +#define AC_PINCAP_IN (1<<5) /* input capable */ +#define AC_PINCAP_BALANCE (1<<6) /* balanced I/O capable */ +/* Note: This LR_SWAP pincap is defined in the Realtek ALC883 specification, + * but is marked reserved in the Intel HDA specification. + */ +#define AC_PINCAP_LR_SWAP (1<<7) /* L/R swap */ +/* Note: The same bit as LR_SWAP is newly defined as HDMI capability + * in HD-audio specification + */ +#define AC_PINCAP_HDMI (1<<7) /* HDMI pin */ +#define AC_PINCAP_DP (1<<24) /* DisplayPort pin, can + * coexist with AC_PINCAP_HDMI + */ +#define AC_PINCAP_VREF (0x37<<8) +#define AC_PINCAP_VREF_SHIFT 8 +#define AC_PINCAP_EAPD (1<<16) /* EAPD capable */ +#define AC_PINCAP_HBR (1<<27) /* High Bit Rate */ +/* Vref status (used in pin cap) */ +#define AC_PINCAP_VREF_HIZ (1<<0) /* Hi-Z */ +#define AC_PINCAP_VREF_50 (1<<1) /* 50% */ +#define AC_PINCAP_VREF_GRD (1<<2) /* ground */ +#define AC_PINCAP_VREF_80 (1<<4) /* 80% */ +#define AC_PINCAP_VREF_100 (1<<5) /* 100% */ + +/* Amplifier capabilities */ +#define AC_AMPCAP_OFFSET (0x7f<<0) /* 0dB offset */ +#define AC_AMPCAP_OFFSET_SHIFT 0 +#define AC_AMPCAP_NUM_STEPS (0x7f<<8) /* number of steps */ +#define AC_AMPCAP_NUM_STEPS_SHIFT 8 +#define AC_AMPCAP_STEP_SIZE (0x7f<<16) /* step size 0-32dB + * in 0.25dB + */ +#define AC_AMPCAP_STEP_SIZE_SHIFT 16 +#define AC_AMPCAP_MUTE (1<<31) /* mute capable */ +#define AC_AMPCAP_MUTE_SHIFT 31 + +/* driver-specific amp-caps: using bits 24-30 */ +#define AC_AMPCAP_MIN_MUTE (1 << 30) /* min-volume = mute */ + +/* Connection list */ +#define AC_CLIST_LENGTH (0x7f<<0) +#define AC_CLIST_LONG (1<<7) + +/* Supported power status */ +#define AC_PWRST_D0SUP (1<<0) +#define AC_PWRST_D1SUP (1<<1) +#define AC_PWRST_D2SUP (1<<2) +#define AC_PWRST_D3SUP (1<<3) +#define AC_PWRST_D3COLDSUP (1<<4) +#define AC_PWRST_S3D3COLDSUP (1<<29) +#define AC_PWRST_CLKSTOP (1<<30) +#define AC_PWRST_EPSS (1U<<31) + +/* Power state values */ +#define AC_PWRST_SETTING (0xf<<0) +#define AC_PWRST_ACTUAL (0xf<<4) +#define AC_PWRST_ACTUAL_SHIFT 4 +#define AC_PWRST_D0 0x00 +#define AC_PWRST_D1 0x01 +#define AC_PWRST_D2 0x02 +#define AC_PWRST_D3 0x03 +#define AC_PWRST_ERROR (1<<8) +#define AC_PWRST_CLK_STOP_OK (1<<9) +#define AC_PWRST_SETTING_RESET (1<<10) + +/* Processing capabilies */ +#define AC_PCAP_BENIGN (1<<0) +#define AC_PCAP_NUM_COEF (0xff<<8) +#define AC_PCAP_NUM_COEF_SHIFT 8 + +/* Volume knobs capabilities */ +#define AC_KNBCAP_NUM_STEPS (0x7f<<0) +#define AC_KNBCAP_DELTA (1<<7) + +/* HDMI LPCM capabilities */ +#define AC_LPCMCAP_48K_CP_CHNS (0x0f<<0) /* max channels w/ CP-on */ +#define AC_LPCMCAP_48K_NO_CHNS (0x0f<<4) /* max channels w/o CP-on */ +#define AC_LPCMCAP_48K_20BIT (1<<8) /* 20b bitrate supported */ +#define AC_LPCMCAP_48K_24BIT (1<<9) /* 24b bitrate supported */ +#define AC_LPCMCAP_96K_CP_CHNS (0x0f<<10) /* max channels w/ CP-on */ +#define AC_LPCMCAP_96K_NO_CHNS (0x0f<<14) /* max channels w/o CP-on */ +#define AC_LPCMCAP_96K_20BIT (1<<18) /* 20b bitrate supported */ +#define AC_LPCMCAP_96K_24BIT (1<<19) /* 24b bitrate supported */ +#define AC_LPCMCAP_192K_CP_CHNS (0x0f<<20) /* max channels w/ CP-on */ +#define AC_LPCMCAP_192K_NO_CHNS (0x0f<<24) /* max channels w/o CP-on */ +#define AC_LPCMCAP_192K_20BIT (1<<28) /* 20b bitrate supported */ +#define AC_LPCMCAP_192K_24BIT (1<<29) /* 24b bitrate supported */ +#define AC_LPCMCAP_44K (1<<30) /* 44.1kHz support */ +#define AC_LPCMCAP_44K_MS (1<<31) /* 44.1kHz-multiplies support */ + +/* Display pin's device list length */ +#define AC_DEV_LIST_LEN_MASK 0x3f +#define AC_MAX_DEV_LIST_LEN 64 + +/* + * Control Parameters + */ + +/* Amp gain/mute */ +#define AC_AMP_MUTE (1<<7) +#define AC_AMP_GAIN (0x7f) +#define AC_AMP_GET_INDEX (0xf<<0) + +#define AC_AMP_GET_LEFT (1<<13) +#define AC_AMP_GET_RIGHT (0<<13) +#define AC_AMP_GET_OUTPUT (1<<15) +#define AC_AMP_GET_INPUT (0<<15) + +#define AC_AMP_SET_INDEX (0xf<<8) +#define AC_AMP_SET_INDEX_SHIFT 8 +#define AC_AMP_SET_RIGHT (1<<12) +#define AC_AMP_SET_LEFT (1<<13) +#define AC_AMP_SET_INPUT (1<<14) +#define AC_AMP_SET_OUTPUT (1<<15) + +/* DIGITAL1 bits */ +#define AC_DIG1_ENABLE (1<<0) +#define AC_DIG1_V (1<<1) +#define AC_DIG1_VCFG (1<<2) +#define AC_DIG1_EMPHASIS (1<<3) +#define AC_DIG1_COPYRIGHT (1<<4) +#define AC_DIG1_NONAUDIO (1<<5) +#define AC_DIG1_PROFESSIONAL (1<<6) +#define AC_DIG1_LEVEL (1<<7) + +/* DIGITAL2 bits */ +#define AC_DIG2_CC (0x7f<<0) + +/* DIGITAL3 bits */ +#define AC_DIG3_ICT (0xf<<0) +#define AC_DIG3_KAE (1<<7) + +/* Pin widget control - 8bit */ +#define AC_PINCTL_EPT (0x3<<0) +#define AC_PINCTL_EPT_NATIVE 0 +#define AC_PINCTL_EPT_HBR 3 +#define AC_PINCTL_VREFEN (0x7<<0) +#define AC_PINCTL_VREF_HIZ 0 /* Hi-Z */ +#define AC_PINCTL_VREF_50 1 /* 50% */ +#define AC_PINCTL_VREF_GRD 2 /* ground */ +#define AC_PINCTL_VREF_80 4 /* 80% */ +#define AC_PINCTL_VREF_100 5 /* 100% */ +#define AC_PINCTL_IN_EN (1<<5) +#define AC_PINCTL_OUT_EN (1<<6) +#define AC_PINCTL_HP_EN (1<<7) + +/* Pin sense - 32bit */ +#define AC_PINSENSE_IMPEDANCE_MASK (0x7fffffff) +#define AC_PINSENSE_PRESENCE (1<<31) +#define AC_PINSENSE_ELDV (1<<30) /* ELD valid (HDMI) */ + +/* EAPD/BTL enable - 32bit */ +#define AC_EAPDBTL_BALANCED (1<<0) +#define AC_EAPDBTL_EAPD (1<<1) +#define AC_EAPDBTL_LR_SWAP (1<<2) + +/* HDMI ELD data */ +#define AC_ELDD_ELD_VALID (1<<31) +#define AC_ELDD_ELD_DATA 0xff + +/* HDMI DIP size */ +#define AC_DIPSIZE_ELD_BUF (1<<3) /* ELD buf size of packet size */ +#define AC_DIPSIZE_PACK_IDX (0x07<<0) /* packet index */ + +/* HDMI DIP index */ +#define AC_DIPIDX_PACK_IDX (0x07<<5) /* packet idnex */ +#define AC_DIPIDX_BYTE_IDX (0x1f<<0) /* byte index */ + +/* HDMI DIP xmit (transmit) control */ +#define AC_DIPXMIT_MASK (0x3<<6) +#define AC_DIPXMIT_DISABLE (0x0<<6) /* disable xmit */ +#define AC_DIPXMIT_ONCE (0x2<<6) /* xmit once then disable */ +#define AC_DIPXMIT_BEST (0x3<<6) /* best effort */ + +/* HDMI content protection (CP) control */ +#define AC_CPCTRL_CES (1<<9) /* current encryption state */ +#define AC_CPCTRL_READY (1<<8) /* ready bit */ +#define AC_CPCTRL_SUBTAG (0x1f<<3) /* subtag for unsol-resp */ +#define AC_CPCTRL_STATE (3<<0) /* current CP request state */ + +/* Converter channel <-> HDMI slot mapping */ +#define AC_CVTMAP_HDMI_SLOT (0xf<<0) /* HDMI slot number */ +#define AC_CVTMAP_CHAN (0xf<<4) /* converter channel number */ + +/* configuration default - 32bit */ +#define AC_DEFCFG_SEQUENCE (0xf<<0) +#define AC_DEFCFG_DEF_ASSOC (0xf<<4) +#define AC_DEFCFG_ASSOC_SHIFT 4 +#define AC_DEFCFG_MISC (0xf<<8) +#define AC_DEFCFG_MISC_SHIFT 8 +#define AC_DEFCFG_MISC_NO_PRESENCE (1<<0) +#define AC_DEFCFG_COLOR (0xf<<12) +#define AC_DEFCFG_COLOR_SHIFT 12 +#define AC_DEFCFG_CONN_TYPE (0xf<<16) +#define AC_DEFCFG_CONN_TYPE_SHIFT 16 +#define AC_DEFCFG_DEVICE (0xf<<20) +#define AC_DEFCFG_DEVICE_SHIFT 20 +#define AC_DEFCFG_LOCATION (0x3f<<24) +#define AC_DEFCFG_LOCATION_SHIFT 24 +#define AC_DEFCFG_PORT_CONN (0x3<<30) +#define AC_DEFCFG_PORT_CONN_SHIFT 30 + +/* Display pin's device list entry */ +#define AC_DE_PD (1<<0) +#define AC_DE_ELDV (1<<1) +#define AC_DE_IA (1<<2) + +/* device types (0x0-0xf) */ +enum { + AC_JACK_LINE_OUT, + AC_JACK_SPEAKER, + AC_JACK_HP_OUT, + AC_JACK_CD, + AC_JACK_SPDIF_OUT, + AC_JACK_DIG_OTHER_OUT, + AC_JACK_MODEM_LINE_SIDE, + AC_JACK_MODEM_HAND_SIDE, + AC_JACK_LINE_IN, + AC_JACK_AUX, + AC_JACK_MIC_IN, + AC_JACK_TELEPHONY, + AC_JACK_SPDIF_IN, + AC_JACK_DIG_OTHER_IN, + AC_JACK_OTHER = 0xf, +}; + +/* jack connection types (0x0-0xf) */ +enum { + AC_JACK_CONN_UNKNOWN, + AC_JACK_CONN_1_8, + AC_JACK_CONN_1_4, + AC_JACK_CONN_ATAPI, + AC_JACK_CONN_RCA, + AC_JACK_CONN_OPTICAL, + AC_JACK_CONN_OTHER_DIGITAL, + AC_JACK_CONN_OTHER_ANALOG, + AC_JACK_CONN_DIN, + AC_JACK_CONN_XLR, + AC_JACK_CONN_RJ11, + AC_JACK_CONN_COMB, + AC_JACK_CONN_OTHER = 0xf, +}; + +/* jack colors (0x0-0xf) */ +enum { + AC_JACK_COLOR_UNKNOWN, + AC_JACK_COLOR_BLACK, + AC_JACK_COLOR_GREY, + AC_JACK_COLOR_BLUE, + AC_JACK_COLOR_GREEN, + AC_JACK_COLOR_RED, + AC_JACK_COLOR_ORANGE, + AC_JACK_COLOR_YELLOW, + AC_JACK_COLOR_PURPLE, + AC_JACK_COLOR_PINK, + AC_JACK_COLOR_WHITE = 0xe, + AC_JACK_COLOR_OTHER, +}; + +/* Jack location (0x0-0x3f) */ +/* common case */ +enum { + AC_JACK_LOC_NONE, + AC_JACK_LOC_REAR, + AC_JACK_LOC_FRONT, + AC_JACK_LOC_LEFT, + AC_JACK_LOC_RIGHT, + AC_JACK_LOC_TOP, + AC_JACK_LOC_BOTTOM, +}; +/* bits 4-5 */ +enum { + AC_JACK_LOC_EXTERNAL = 0x00, + AC_JACK_LOC_INTERNAL = 0x10, + AC_JACK_LOC_SEPARATE = 0x20, + AC_JACK_LOC_OTHER = 0x30, +}; +enum { + /* external on primary chasis */ + AC_JACK_LOC_REAR_PANEL = 0x07, + AC_JACK_LOC_DRIVE_BAY, + /* internal */ + AC_JACK_LOC_RISER = 0x17, + AC_JACK_LOC_HDMI, + AC_JACK_LOC_ATAPI, + /* others */ + AC_JACK_LOC_MOBILE_IN = 0x37, + AC_JACK_LOC_MOBILE_OUT, +}; + +/* Port connectivity (0-3) */ +enum { + AC_JACK_PORT_COMPLEX, + AC_JACK_PORT_NONE, + AC_JACK_PORT_FIXED, + AC_JACK_PORT_BOTH, +}; + +/* max. codec address */ +#define HDA_MAX_CODEC_ADDRESS 0x0f + +#endif /* __SOUND_HDA_VERBS_H */ diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h new file mode 100644 index 000000000..35778f953 --- /dev/null +++ b/include/sound/hdaudio.h @@ -0,0 +1,678 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * HD-audio core stuff + */ + +#ifndef __SOUND_HDAUDIO_H +#define __SOUND_HDAUDIO_H + +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/io.h> +#include <linux/io-64-nonatomic-lo-hi.h> +#include <linux/iopoll.h> +#include <linux/pm_runtime.h> +#include <linux/timecounter.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/memalloc.h> +#include <sound/hda_verbs.h> +#include <drm/i915_component.h> + +/* codec node id */ +typedef u16 hda_nid_t; + +struct hdac_bus; +struct hdac_stream; +struct hdac_device; +struct hdac_driver; +struct hdac_widget_tree; +struct hda_device_id; + +/* + * exported bus type + */ +extern struct bus_type snd_hda_bus_type; + +/* + * generic arrays + */ +struct snd_array { + unsigned int used; + unsigned int alloced; + unsigned int elem_size; + unsigned int alloc_align; + void *list; +}; + +/* + * HD-audio codec base device + */ +struct hdac_device { + struct device dev; + int type; + struct hdac_bus *bus; + unsigned int addr; /* codec address */ + struct list_head list; /* list point for bus codec_list */ + + hda_nid_t afg; /* AFG node id */ + hda_nid_t mfg; /* MFG node id */ + + /* ids */ + unsigned int vendor_id; + unsigned int subsystem_id; + unsigned int revision_id; + unsigned int afg_function_id; + unsigned int mfg_function_id; + unsigned int afg_unsol:1; + unsigned int mfg_unsol:1; + + unsigned int power_caps; /* FG power caps */ + + const char *vendor_name; /* codec vendor name */ + const char *chip_name; /* codec chip name */ + + /* verb exec op override */ + int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, + unsigned int flags, unsigned int *res); + + /* widgets */ + unsigned int num_nodes; + hda_nid_t start_nid, end_nid; + + /* misc flags */ + atomic_t in_pm; /* suspend/resume being performed */ + + /* sysfs */ + struct mutex widget_lock; + struct hdac_widget_tree *widgets; + + /* regmap */ + struct regmap *regmap; + struct mutex regmap_lock; + struct snd_array vendor_verbs; + bool lazy_cache:1; /* don't wake up for writes */ + bool caps_overwriting:1; /* caps overwrite being in process */ + bool cache_coef:1; /* cache COEF read/write too */ + unsigned int registered:1; /* codec was registered */ +}; + +/* device/driver type used for matching */ +enum { + HDA_DEV_CORE, + HDA_DEV_LEGACY, + HDA_DEV_ASOC, +}; + +enum { + SND_SKL_PCI_BIND_AUTO, /* automatic selection based on pci class */ + SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */ + SND_SKL_PCI_BIND_ASOC /* bind only with ASoC driver */ +}; + +/* direction */ +enum { + HDA_INPUT, HDA_OUTPUT +}; + +#define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev) + +int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus, + const char *name, unsigned int addr); +void snd_hdac_device_exit(struct hdac_device *dev); +int snd_hdac_device_register(struct hdac_device *codec); +void snd_hdac_device_unregister(struct hdac_device *codec); +int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name); +int snd_hdac_codec_modalias(struct hdac_device *hdac, char *buf, size_t size); + +int snd_hdac_refresh_widgets(struct hdac_device *codec); + +int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid, + unsigned int verb, unsigned int parm, unsigned int *res); +int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm, + unsigned int *res); +int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid, + int parm); +int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid, + unsigned int parm, unsigned int val); +int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid, + hda_nid_t *conn_list, int max_conns); +int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid, + hda_nid_t *start_id); +unsigned int snd_hdac_calc_stream_format(unsigned int rate, + unsigned int channels, + snd_pcm_format_t format, + unsigned int maxbps, + unsigned short spdif_ctls); +int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid, + u32 *ratesp, u64 *formatsp, unsigned int *bpsp); +bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid, + unsigned int format); + +int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid, + int flags, unsigned int verb, unsigned int parm); +int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid, + int flags, unsigned int verb, unsigned int parm); +bool snd_hdac_check_power_state(struct hdac_device *hdac, + hda_nid_t nid, unsigned int target_state); +unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac, + hda_nid_t nid, unsigned int target_state); +/** + * snd_hdac_read_parm - read a codec parameter + * @codec: the codec object + * @nid: NID to read a parameter + * @parm: parameter to read + * + * Returns -1 for error. If you need to distinguish the error more + * strictly, use _snd_hdac_read_parm() directly. + */ +static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, + int parm) +{ + unsigned int val; + + return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val; +} + +#ifdef CONFIG_PM +int snd_hdac_power_up(struct hdac_device *codec); +int snd_hdac_power_down(struct hdac_device *codec); +int snd_hdac_power_up_pm(struct hdac_device *codec); +int snd_hdac_power_down_pm(struct hdac_device *codec); +int snd_hdac_keep_power_up(struct hdac_device *codec); + +/* call this at entering into suspend/resume callbacks in codec driver */ +static inline void snd_hdac_enter_pm(struct hdac_device *codec) +{ + atomic_inc(&codec->in_pm); +} + +/* call this at leaving from suspend/resume callbacks in codec driver */ +static inline void snd_hdac_leave_pm(struct hdac_device *codec) +{ + atomic_dec(&codec->in_pm); +} + +static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) +{ + return atomic_read(&codec->in_pm); +} + +static inline bool snd_hdac_is_power_on(struct hdac_device *codec) +{ + return !pm_runtime_suspended(&codec->dev); +} +#else +static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; } +static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; } +static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; } +static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; } +static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; } +static inline void snd_hdac_enter_pm(struct hdac_device *codec) {} +static inline void snd_hdac_leave_pm(struct hdac_device *codec) {} +static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return false; } +static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return true; } +#endif + +/* + * HD-audio codec base driver + */ +struct hdac_driver { + struct device_driver driver; + int type; + const struct hda_device_id *id_table; + int (*match)(struct hdac_device *dev, struct hdac_driver *drv); + void (*unsol_event)(struct hdac_device *dev, unsigned int event); + + /* fields used by ext bus APIs */ + int (*probe)(struct hdac_device *dev); + int (*remove)(struct hdac_device *dev); + void (*shutdown)(struct hdac_device *dev); +}; + +#define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver) + +const struct hda_device_id * +hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv); + +/* + * Bus verb operators + */ +struct hdac_bus_ops { + /* send a single command */ + int (*command)(struct hdac_bus *bus, unsigned int cmd); + /* get a response from the last command */ + int (*get_response)(struct hdac_bus *bus, unsigned int addr, + unsigned int *res); + /* notify of codec link power-up/down */ + void (*link_power)(struct hdac_device *hdev, bool enable); +}; + +/* + * ops used for ASoC HDA codec drivers + */ +struct hdac_ext_bus_ops { + int (*hdev_attach)(struct hdac_device *hdev); + int (*hdev_detach)(struct hdac_device *hdev); +}; + +#define HDA_UNSOL_QUEUE_SIZE 64 +#define HDA_MAX_CODECS 8 /* limit by controller side */ + +/* + * CORB/RIRB + * + * Each CORB entry is 4byte, RIRB is 8byte + */ +struct hdac_rb { + __le32 *buf; /* virtual address of CORB/RIRB buffer */ + dma_addr_t addr; /* physical address of CORB/RIRB buffer */ + unsigned short rp, wp; /* RIRB read/write pointers */ + int cmds[HDA_MAX_CODECS]; /* number of pending requests */ + u32 res[HDA_MAX_CODECS]; /* last read value */ +}; + +/* + * HD-audio bus base driver + * + * @ppcap: pp capabilities pointer + * @spbcap: SPIB capabilities pointer + * @mlcap: MultiLink capabilities pointer + * @gtscap: gts capabilities pointer + * @drsmcap: dma resume capabilities pointer + * @num_streams: streams supported + * @idx: HDA link index + * @hlink_list: link list of HDA links + * @lock: lock for link and display power mgmt + * @cmd_dma_state: state of cmd DMAs: CORB and RIRB + */ +struct hdac_bus { + struct device *dev; + const struct hdac_bus_ops *ops; + const struct hdac_ext_bus_ops *ext_ops; + + /* h/w resources */ + unsigned long addr; + void __iomem *remap_addr; + int irq; + + void __iomem *ppcap; + void __iomem *spbcap; + void __iomem *mlcap; + void __iomem *gtscap; + void __iomem *drsmcap; + + /* codec linked list */ + struct list_head codec_list; + unsigned int num_codecs; + + /* link caddr -> codec */ + struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1]; + + /* unsolicited event queue */ + u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */ + unsigned int unsol_rp, unsol_wp; + struct work_struct unsol_work; + + /* bit flags of detected codecs */ + unsigned long codec_mask; + + /* bit flags of powered codecs */ + unsigned long codec_powered; + + /* CORB/RIRB */ + struct hdac_rb corb; + struct hdac_rb rirb; + unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */ + wait_queue_head_t rirb_wq; + + /* CORB/RIRB and position buffers */ + struct snd_dma_buffer rb; + struct snd_dma_buffer posbuf; + int dma_type; /* SNDRV_DMA_TYPE_XXX for CORB/RIRB */ + + /* hdac_stream linked list */ + struct list_head stream_list; + + /* operation state */ + bool chip_init:1; /* h/w initialized */ + + /* behavior flags */ + bool aligned_mmio:1; /* aligned MMIO access */ + bool sync_write:1; /* sync after verb write */ + bool use_posbuf:1; /* use position buffer */ + bool snoop:1; /* enable snooping */ + bool align_bdle_4k:1; /* BDLE align 4K boundary */ + bool reverse_assign:1; /* assign devices in reverse order */ + bool corbrp_self_clear:1; /* CORBRP clears itself after reset */ + bool polling_mode:1; + bool needs_damn_long_delay:1; + + int poll_count; + + int bdl_pos_adj; /* BDL position adjustment */ + + /* delay time in us for dma stop */ + unsigned int dma_stop_delay; + + /* locks */ + spinlock_t reg_lock; + struct mutex cmd_mutex; + struct mutex lock; + + /* DRM component interface */ + struct drm_audio_component *audio_component; + long display_power_status; + unsigned long display_power_active; + + /* parameters required for enhanced capabilities */ + int num_streams; + int idx; + + /* link management */ + struct list_head hlink_list; + bool cmd_dma_state; + + /* factor used to derive STRIPE control value */ + unsigned int sdo_limit; +}; + +int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev, + const struct hdac_bus_ops *ops); +void snd_hdac_bus_exit(struct hdac_bus *bus); +int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr, + unsigned int cmd, unsigned int *res); + +void snd_hdac_codec_link_up(struct hdac_device *codec); +void snd_hdac_codec_link_down(struct hdac_device *codec); + +int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val); +int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, + unsigned int *res); +int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus); + +bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset); +void snd_hdac_bus_stop_chip(struct hdac_bus *bus); +void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus); +void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus); +void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus); +void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus); +int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset); +void snd_hdac_bus_link_power(struct hdac_device *hdev, bool enable); + +void snd_hdac_bus_update_rirb(struct hdac_bus *bus); +int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, + void (*ack)(struct hdac_bus *, + struct hdac_stream *)); + +int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus); +void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus); + +#ifdef CONFIG_SND_HDA_ALIGNED_MMIO +unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask); +void snd_hdac_aligned_write(unsigned int val, void __iomem *addr, + unsigned int mask); +#define snd_hdac_aligned_mmio(bus) (bus)->aligned_mmio +#else +#define snd_hdac_aligned_mmio(bus) false +#define snd_hdac_aligned_read(addr, mask) 0 +#define snd_hdac_aligned_write(val, addr, mask) do {} while (0) +#endif + +static inline void snd_hdac_reg_writeb(struct hdac_bus *bus, void __iomem *addr, + u8 val) +{ + if (snd_hdac_aligned_mmio(bus)) + snd_hdac_aligned_write(val, addr, 0xff); + else + writeb(val, addr); +} + +static inline void snd_hdac_reg_writew(struct hdac_bus *bus, void __iomem *addr, + u16 val) +{ + if (snd_hdac_aligned_mmio(bus)) + snd_hdac_aligned_write(val, addr, 0xffff); + else + writew(val, addr); +} + +static inline u8 snd_hdac_reg_readb(struct hdac_bus *bus, void __iomem *addr) +{ + return snd_hdac_aligned_mmio(bus) ? + snd_hdac_aligned_read(addr, 0xff) : readb(addr); +} + +static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr) +{ + return snd_hdac_aligned_mmio(bus) ? + snd_hdac_aligned_read(addr, 0xffff) : readw(addr); +} + +#define snd_hdac_reg_writel(bus, addr, val) writel(val, addr) +#define snd_hdac_reg_readl(bus, addr) readl(addr) +#define snd_hdac_reg_writeq(bus, addr, val) writeq(val, addr) +#define snd_hdac_reg_readq(bus, addr) readq(addr) + +/* + * macros for easy use + */ +#define _snd_hdac_chip_writeb(chip, reg, value) \ + snd_hdac_reg_writeb(chip, (chip)->remap_addr + (reg), value) +#define _snd_hdac_chip_readb(chip, reg) \ + snd_hdac_reg_readb(chip, (chip)->remap_addr + (reg)) +#define _snd_hdac_chip_writew(chip, reg, value) \ + snd_hdac_reg_writew(chip, (chip)->remap_addr + (reg), value) +#define _snd_hdac_chip_readw(chip, reg) \ + snd_hdac_reg_readw(chip, (chip)->remap_addr + (reg)) +#define _snd_hdac_chip_writel(chip, reg, value) \ + snd_hdac_reg_writel(chip, (chip)->remap_addr + (reg), value) +#define _snd_hdac_chip_readl(chip, reg) \ + snd_hdac_reg_readl(chip, (chip)->remap_addr + (reg)) + +/* read/write a register, pass without AZX_REG_ prefix */ +#define snd_hdac_chip_writel(chip, reg, value) \ + _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value) +#define snd_hdac_chip_writew(chip, reg, value) \ + _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value) +#define snd_hdac_chip_writeb(chip, reg, value) \ + _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value) +#define snd_hdac_chip_readl(chip, reg) \ + _snd_hdac_chip_readl(chip, AZX_REG_ ## reg) +#define snd_hdac_chip_readw(chip, reg) \ + _snd_hdac_chip_readw(chip, AZX_REG_ ## reg) +#define snd_hdac_chip_readb(chip, reg) \ + _snd_hdac_chip_readb(chip, AZX_REG_ ## reg) + +/* update a register, pass without AZX_REG_ prefix */ +#define snd_hdac_chip_updatel(chip, reg, mask, val) \ + snd_hdac_chip_writel(chip, reg, \ + (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val)) +#define snd_hdac_chip_updatew(chip, reg, mask, val) \ + snd_hdac_chip_writew(chip, reg, \ + (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val)) +#define snd_hdac_chip_updateb(chip, reg, mask, val) \ + snd_hdac_chip_writeb(chip, reg, \ + (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val)) + +/* + * HD-audio stream + */ +struct hdac_stream { + struct hdac_bus *bus; + struct snd_dma_buffer bdl; /* BDL buffer */ + __le32 *posbuf; /* position buffer pointer */ + int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */ + + unsigned int bufsize; /* size of the play buffer in bytes */ + unsigned int period_bytes; /* size of the period in bytes */ + unsigned int frags; /* number for period in the play buffer */ + unsigned int fifo_size; /* FIFO size */ + + void __iomem *sd_addr; /* stream descriptor pointer */ + + u32 sd_int_sta_mask; /* stream int status mask */ + + /* pcm support */ + struct snd_pcm_substream *substream; /* assigned substream, + * set in PCM open + */ + struct snd_compr_stream *cstream; + unsigned int format_val; /* format value to be set in the + * controller and the codec + */ + unsigned char stream_tag; /* assigned stream */ + unsigned char index; /* stream index */ + int assigned_key; /* last device# key assigned to */ + + bool opened:1; + bool running:1; + bool prepared:1; + bool no_period_wakeup:1; + bool locked:1; + bool stripe:1; /* apply stripe control */ + + u64 curr_pos; + /* timestamp */ + unsigned long start_wallclk; /* start + minimum wallclk */ + unsigned long period_wallclk; /* wallclk for period */ + struct timecounter tc; + struct cyclecounter cc; + int delay_negative_threshold; + + struct list_head list; +#ifdef CONFIG_SND_HDA_DSP_LOADER + /* DSP access mutex */ + struct mutex dsp_mutex; +#endif +}; + +void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, + int idx, int direction, int tag); +struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, + struct snd_pcm_substream *substream); +void snd_hdac_stream_release_locked(struct hdac_stream *azx_dev); +void snd_hdac_stream_release(struct hdac_stream *azx_dev); +struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, + int dir, int stream_tag); + +int snd_hdac_stream_setup(struct hdac_stream *azx_dev); +void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev); +int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev); +int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, + unsigned int format_val); +void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start); +void snd_hdac_stream_stop(struct hdac_stream *azx_dev); +void snd_hdac_stop_streams(struct hdac_bus *bus); +void snd_hdac_stop_streams_and_chip(struct hdac_bus *bus); +void snd_hdac_stream_reset(struct hdac_stream *azx_dev); +void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, + unsigned int streams, unsigned int reg); +void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, + unsigned int streams); +void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, + unsigned int streams); +int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, + struct snd_pcm_substream *substream); + +/* + * macros for easy use + */ +/* read/write a register, pass without AZX_REG_ prefix */ +#define snd_hdac_stream_writel(dev, reg, value) \ + snd_hdac_reg_writel((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) +#define snd_hdac_stream_writew(dev, reg, value) \ + snd_hdac_reg_writew((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) +#define snd_hdac_stream_writeb(dev, reg, value) \ + snd_hdac_reg_writeb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) +#define snd_hdac_stream_readl(dev, reg) \ + snd_hdac_reg_readl((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) +#define snd_hdac_stream_readw(dev, reg) \ + snd_hdac_reg_readw((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) +#define snd_hdac_stream_readb(dev, reg) \ + snd_hdac_reg_readb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) +#define snd_hdac_stream_readb_poll(dev, reg, val, cond, delay_us, timeout_us) \ + read_poll_timeout_atomic(snd_hdac_reg_readb, val, cond, delay_us, timeout_us, \ + false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) +#define snd_hdac_stream_readl_poll(dev, reg, val, cond, delay_us, timeout_us) \ + read_poll_timeout_atomic(snd_hdac_reg_readl, val, cond, delay_us, timeout_us, \ + false, (dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) + +/* update a register, pass without AZX_REG_ prefix */ +#define snd_hdac_stream_updatel(dev, reg, mask, val) \ + snd_hdac_stream_writel(dev, reg, \ + (snd_hdac_stream_readl(dev, reg) & \ + ~(mask)) | (val)) +#define snd_hdac_stream_updatew(dev, reg, mask, val) \ + snd_hdac_stream_writew(dev, reg, \ + (snd_hdac_stream_readw(dev, reg) & \ + ~(mask)) | (val)) +#define snd_hdac_stream_updateb(dev, reg, mask, val) \ + snd_hdac_stream_writeb(dev, reg, \ + (snd_hdac_stream_readb(dev, reg) & \ + ~(mask)) | (val)) + +#ifdef CONFIG_SND_HDA_DSP_LOADER +/* DSP lock helpers */ +#define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) +#define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) +#define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) +#define snd_hdac_stream_is_locked(dev) ((dev)->locked) +/* DSP loader helpers */ +int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, + unsigned int byte_size, struct snd_dma_buffer *bufp); +void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start); +void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, + struct snd_dma_buffer *dmab); +#else /* CONFIG_SND_HDA_DSP_LOADER */ +#define snd_hdac_dsp_lock_init(dev) do {} while (0) +#define snd_hdac_dsp_lock(dev) do {} while (0) +#define snd_hdac_dsp_unlock(dev) do {} while (0) +#define snd_hdac_stream_is_locked(dev) 0 + +static inline int +snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, + unsigned int byte_size, struct snd_dma_buffer *bufp) +{ + return 0; +} + +static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) +{ +} + +static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, + struct snd_dma_buffer *dmab) +{ +} +#endif /* CONFIG_SND_HDA_DSP_LOADER */ + + +/* + * generic array helpers + */ +void *snd_array_new(struct snd_array *array); +void snd_array_free(struct snd_array *array); +static inline void snd_array_init(struct snd_array *array, unsigned int size, + unsigned int align) +{ + array->elem_size = size; + array->alloc_align = align; +} + +static inline void *snd_array_elem(struct snd_array *array, unsigned int idx) +{ + return array->list + idx * array->elem_size; +} + +static inline unsigned int snd_array_index(struct snd_array *array, void *ptr) +{ + return (unsigned long)(ptr - array->list) / array->elem_size; +} + +/* a helper macro to iterate for each snd_array element */ +#define snd_array_for_each(array, idx, ptr) \ + for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \ + (ptr) = snd_array_elem(array, ++(idx))) + +#endif /* __SOUND_HDAUDIO_H */ diff --git a/include/sound/hdaudio_ext.h b/include/sound/hdaudio_ext.h new file mode 100644 index 000000000..83aed26ab --- /dev/null +++ b/include/sound/hdaudio_ext.h @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SOUND_HDAUDIO_EXT_H +#define __SOUND_HDAUDIO_EXT_H + +#include <linux/io-64-nonatomic-lo-hi.h> +#include <linux/iopoll.h> +#include <sound/hdaudio.h> + +int snd_hdac_ext_bus_init(struct hdac_bus *bus, struct device *dev, + const struct hdac_bus_ops *ops, + const struct hdac_ext_bus_ops *ext_ops); + +void snd_hdac_ext_bus_exit(struct hdac_bus *bus); +void snd_hdac_ext_bus_device_remove(struct hdac_bus *bus); + +#define HDA_CODEC_REV_EXT_ENTRY(_vid, _rev, _name, drv_data) \ + { .vendor_id = (_vid), .rev_id = (_rev), .name = (_name), \ + .api_version = HDA_DEV_ASOC, \ + .driver_data = (unsigned long)(drv_data) } +#define HDA_CODEC_EXT_ENTRY(_vid, _revid, _name, _drv_data) \ + HDA_CODEC_REV_EXT_ENTRY(_vid, _revid, _name, _drv_data) + +void snd_hdac_ext_bus_ppcap_enable(struct hdac_bus *chip, bool enable); +void snd_hdac_ext_bus_ppcap_int_enable(struct hdac_bus *chip, bool enable); + +void snd_hdac_ext_stream_spbcap_enable(struct hdac_bus *chip, + bool enable, int index); + +int snd_hdac_ext_bus_get_ml_capabilities(struct hdac_bus *bus); +struct hdac_ext_link *snd_hdac_ext_bus_link_at(struct hdac_bus *bus, int addr); +struct hdac_ext_link *snd_hdac_ext_bus_get_link(struct hdac_bus *bus, + const char *codec_name); + +enum hdac_ext_stream_type { + HDAC_EXT_STREAM_TYPE_COUPLED = 0, + HDAC_EXT_STREAM_TYPE_HOST, + HDAC_EXT_STREAM_TYPE_LINK +}; + +/** + * hdac_ext_stream: HDAC extended stream for extended HDA caps + * + * @hstream: hdac_stream + * @pphc_addr: processing pipe host stream pointer + * @pplc_addr: processing pipe link stream pointer + * @spib_addr: software position in buffers stream pointer + * @fifo_addr: software position Max fifos stream pointer + * @dpibr_addr: DMA position in buffer resume pointer + * @dpib: DMA position in buffer + * @lpib: Linear position in buffer + * @decoupled: stream host and link is decoupled + * @link_locked: link is locked + * @link_prepared: link is prepared + * @link_substream: link substream + */ +struct hdac_ext_stream { + struct hdac_stream hstream; + + void __iomem *pphc_addr; + void __iomem *pplc_addr; + + void __iomem *spib_addr; + void __iomem *fifo_addr; + + void __iomem *dpibr_addr; + + u32 dpib; + u32 lpib; + bool decoupled:1; + bool link_locked:1; + bool link_prepared; + + struct snd_pcm_substream *link_substream; +}; + +#define hdac_stream(s) (&(s)->hstream) +#define stream_to_hdac_ext_stream(s) \ + container_of(s, struct hdac_ext_stream, hstream) + +int snd_hdac_ext_stream_init_all(struct hdac_bus *bus, int start_idx, + int num_stream, int dir); +void snd_hdac_ext_stream_free_all(struct hdac_bus *bus); +void snd_hdac_link_free_all(struct hdac_bus *bus); +struct hdac_ext_stream *snd_hdac_ext_stream_assign(struct hdac_bus *bus, + struct snd_pcm_substream *substream, + int type); +void snd_hdac_ext_stream_release(struct hdac_ext_stream *hext_stream, int type); +void snd_hdac_ext_stream_decouple_locked(struct hdac_bus *bus, + struct hdac_ext_stream *hext_stream, bool decouple); +void snd_hdac_ext_stream_decouple(struct hdac_bus *bus, + struct hdac_ext_stream *azx_dev, bool decouple); + +int snd_hdac_ext_stream_set_spib(struct hdac_bus *bus, + struct hdac_ext_stream *hext_stream, u32 value); +int snd_hdac_ext_stream_get_spbmaxfifo(struct hdac_bus *bus, + struct hdac_ext_stream *hext_stream); +void snd_hdac_ext_stream_drsm_enable(struct hdac_bus *bus, + bool enable, int index); +int snd_hdac_ext_stream_set_dpibr(struct hdac_bus *bus, + struct hdac_ext_stream *hext_stream, u32 value); +int snd_hdac_ext_stream_set_lpib(struct hdac_ext_stream *hext_stream, u32 value); + +void snd_hdac_ext_link_stream_start(struct hdac_ext_stream *hext_stream); +void snd_hdac_ext_link_stream_clear(struct hdac_ext_stream *hext_stream); +void snd_hdac_ext_link_stream_reset(struct hdac_ext_stream *hext_stream); +int snd_hdac_ext_link_stream_setup(struct hdac_ext_stream *hext_stream, int fmt); + +struct hdac_ext_link { + struct hdac_bus *bus; + int index; + void __iomem *ml_addr; /* link output stream reg pointer */ + u32 lcaps; /* link capablities */ + u16 lsdiid; /* link sdi identifier */ + + int ref_count; + + struct list_head list; +}; + +int snd_hdac_ext_bus_link_power_up(struct hdac_ext_link *link); +int snd_hdac_ext_bus_link_power_down(struct hdac_ext_link *link); +int snd_hdac_ext_bus_link_power_up_all(struct hdac_bus *bus); +int snd_hdac_ext_bus_link_power_down_all(struct hdac_bus *bus); +void snd_hdac_ext_link_set_stream_id(struct hdac_ext_link *link, + int stream); +void snd_hdac_ext_link_clear_stream_id(struct hdac_ext_link *link, + int stream); + +int snd_hdac_ext_bus_link_get(struct hdac_bus *bus, struct hdac_ext_link *link); +int snd_hdac_ext_bus_link_put(struct hdac_bus *bus, struct hdac_ext_link *link); + +void snd_hdac_ext_bus_link_power(struct hdac_device *codec, bool enable); + +/* update register macro */ +#define snd_hdac_updatel(addr, reg, mask, val) \ + writel(((readl(addr + reg) & ~(mask)) | (val)), \ + addr + reg) + +#define snd_hdac_updatew(addr, reg, mask, val) \ + writew(((readw(addr + reg) & ~(mask)) | (val)), \ + addr + reg) + +#define snd_hdac_adsp_writeb(chip, reg, value) \ + snd_hdac_reg_writeb(chip, (chip)->dsp_ba + (reg), value) +#define snd_hdac_adsp_readb(chip, reg) \ + snd_hdac_reg_readb(chip, (chip)->dsp_ba + (reg)) +#define snd_hdac_adsp_writew(chip, reg, value) \ + snd_hdac_reg_writew(chip, (chip)->dsp_ba + (reg), value) +#define snd_hdac_adsp_readw(chip, reg) \ + snd_hdac_reg_readw(chip, (chip)->dsp_ba + (reg)) +#define snd_hdac_adsp_writel(chip, reg, value) \ + snd_hdac_reg_writel(chip, (chip)->dsp_ba + (reg), value) +#define snd_hdac_adsp_readl(chip, reg) \ + snd_hdac_reg_readl(chip, (chip)->dsp_ba + (reg)) +#define snd_hdac_adsp_writeq(chip, reg, value) \ + snd_hdac_reg_writeq(chip, (chip)->dsp_ba + (reg), value) +#define snd_hdac_adsp_readq(chip, reg) \ + snd_hdac_reg_readq(chip, (chip)->dsp_ba + (reg)) + +#define snd_hdac_adsp_updateb(chip, reg, mask, val) \ + snd_hdac_adsp_writeb(chip, reg, \ + (snd_hdac_adsp_readb(chip, reg) & ~(mask)) | (val)) +#define snd_hdac_adsp_updatew(chip, reg, mask, val) \ + snd_hdac_adsp_writew(chip, reg, \ + (snd_hdac_adsp_readw(chip, reg) & ~(mask)) | (val)) +#define snd_hdac_adsp_updatel(chip, reg, mask, val) \ + snd_hdac_adsp_writel(chip, reg, \ + (snd_hdac_adsp_readl(chip, reg) & ~(mask)) | (val)) +#define snd_hdac_adsp_updateq(chip, reg, mask, val) \ + snd_hdac_adsp_writeq(chip, reg, \ + (snd_hdac_adsp_readq(chip, reg) & ~(mask)) | (val)) + +#define snd_hdac_adsp_readb_poll(chip, reg, val, cond, delay_us, timeout_us) \ + readb_poll_timeout((chip)->dsp_ba + (reg), val, cond, \ + delay_us, timeout_us) +#define snd_hdac_adsp_readw_poll(chip, reg, val, cond, delay_us, timeout_us) \ + readw_poll_timeout((chip)->dsp_ba + (reg), val, cond, \ + delay_us, timeout_us) +#define snd_hdac_adsp_readl_poll(chip, reg, val, cond, delay_us, timeout_us) \ + readl_poll_timeout((chip)->dsp_ba + (reg), val, cond, \ + delay_us, timeout_us) +#define snd_hdac_adsp_readq_poll(chip, reg, val, cond, delay_us, timeout_us) \ + readq_poll_timeout((chip)->dsp_ba + (reg), val, cond, \ + delay_us, timeout_us) + +struct hdac_ext_device; + +/* ops common to all codec drivers */ +struct hdac_ext_codec_ops { + int (*build_controls)(struct hdac_ext_device *dev); + int (*init)(struct hdac_ext_device *dev); + void (*free)(struct hdac_ext_device *dev); +}; + +struct hda_dai_map { + char *dai_name; + hda_nid_t nid; + u32 maxbps; +}; + +struct hdac_ext_dma_params { + u32 format; + u8 stream_tag; +}; + +int snd_hda_ext_driver_register(struct hdac_driver *drv); +void snd_hda_ext_driver_unregister(struct hdac_driver *drv); + +#endif /* __SOUND_HDAUDIO_EXT_H */ diff --git a/include/sound/hdmi-codec.h b/include/sound/hdmi-codec.h new file mode 100644 index 000000000..48ad33aba --- /dev/null +++ b/include/sound/hdmi-codec.h @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * hdmi-codec.h - HDMI Codec driver API + * + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com + * + * Author: Jyri Sarha <jsarha@ti.com> + */ + +#ifndef __HDMI_CODEC_H__ +#define __HDMI_CODEC_H__ + +#include <linux/of_graph.h> +#include <linux/hdmi.h> +#include <drm/drm_edid.h> +#include <sound/asoundef.h> +#include <sound/soc.h> +#include <uapi/sound/asound.h> + +/* + * Protocol between ASoC cpu-dai and HDMI-encoder + */ +struct hdmi_codec_daifmt { + enum { + HDMI_I2S, + HDMI_RIGHT_J, + HDMI_LEFT_J, + HDMI_DSP_A, + HDMI_DSP_B, + HDMI_AC97, + HDMI_SPDIF, + } fmt; + unsigned int bit_clk_inv:1; + unsigned int frame_clk_inv:1; + unsigned int bit_clk_provider:1; + unsigned int frame_clk_provider:1; + /* bit_fmt could be standard PCM format or + * IEC958 encoded format. ALSA IEC958 plugin will pass + * IEC958_SUBFRAME format to the underneath driver. + */ + snd_pcm_format_t bit_fmt; +}; + +/* + * HDMI audio parameters + */ +struct hdmi_codec_params { + struct hdmi_audio_infoframe cea; + struct snd_aes_iec958 iec; + int sample_rate; + int sample_width; + int channels; +}; + +typedef void (*hdmi_codec_plugged_cb)(struct device *dev, + bool plugged); + +struct hdmi_codec_pdata; +struct hdmi_codec_ops { + /* + * Called when ASoC starts an audio stream setup. + * Optional + */ + int (*audio_startup)(struct device *dev, void *data); + + /* + * Configures HDMI-encoder for audio stream. + * Having either prepare or hw_params is mandatory. + */ + int (*hw_params)(struct device *dev, void *data, + struct hdmi_codec_daifmt *fmt, + struct hdmi_codec_params *hparms); + + /* + * Configures HDMI-encoder for audio stream. Can be called + * multiple times for each setup. + * + * Having either prepare or hw_params is mandatory. + */ + int (*prepare)(struct device *dev, void *data, + struct hdmi_codec_daifmt *fmt, + struct hdmi_codec_params *hparms); + + /* + * Shuts down the audio stream. + * Mandatory + */ + void (*audio_shutdown)(struct device *dev, void *data); + + /* + * Mute/unmute HDMI audio stream. + * Optional + */ + int (*mute_stream)(struct device *dev, void *data, + bool enable, int direction); + + /* + * Provides EDID-Like-Data from connected HDMI device. + * Optional + */ + int (*get_eld)(struct device *dev, void *data, + uint8_t *buf, size_t len); + + /* + * Getting DAI ID + * Optional + */ + int (*get_dai_id)(struct snd_soc_component *comment, + struct device_node *endpoint); + + /* + * Hook callback function to handle connector plug event. + * Optional + */ + int (*hook_plugged_cb)(struct device *dev, void *data, + hdmi_codec_plugged_cb fn, + struct device *codec_dev); + + /* bit field */ + unsigned int no_capture_mute:1; +}; + +/* HDMI codec initalization data */ +struct hdmi_codec_pdata { + const struct hdmi_codec_ops *ops; + uint i2s:1; + uint spdif:1; + int max_i2s_channels; + void *data; +}; + +struct snd_soc_component; +struct snd_soc_jack; + +#define HDMI_CODEC_DRV_NAME "hdmi-audio-codec" + +#endif /* __HDMI_CODEC_H__ */ diff --git a/include/sound/hwdep.h b/include/sound/hwdep.h new file mode 100644 index 000000000..8d6cdb254 --- /dev/null +++ b/include/sound/hwdep.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_HWDEP_H +#define __SOUND_HWDEP_H + +/* + * Hardware dependent layer + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + */ + +#include <sound/asound.h> +#include <linux/poll.h> + +struct snd_hwdep; + +/* hwdep file ops; all ops can be NULL */ +struct snd_hwdep_ops { + long long (*llseek)(struct snd_hwdep *hw, struct file *file, + long long offset, int orig); + long (*read)(struct snd_hwdep *hw, char __user *buf, + long count, loff_t *offset); + long (*write)(struct snd_hwdep *hw, const char __user *buf, + long count, loff_t *offset); + int (*open)(struct snd_hwdep *hw, struct file * file); + int (*release)(struct snd_hwdep *hw, struct file * file); + __poll_t (*poll)(struct snd_hwdep *hw, struct file *file, + poll_table *wait); + int (*ioctl)(struct snd_hwdep *hw, struct file *file, + unsigned int cmd, unsigned long arg); + int (*ioctl_compat)(struct snd_hwdep *hw, struct file *file, + unsigned int cmd, unsigned long arg); + int (*mmap)(struct snd_hwdep *hw, struct file *file, + struct vm_area_struct *vma); + int (*dsp_status)(struct snd_hwdep *hw, + struct snd_hwdep_dsp_status *status); + int (*dsp_load)(struct snd_hwdep *hw, + struct snd_hwdep_dsp_image *image); +}; + +struct snd_hwdep { + struct snd_card *card; + struct list_head list; + int device; + char id[32]; + char name[80]; + int iface; + +#ifdef CONFIG_SND_OSSEMUL + int oss_type; + int ossreg; +#endif + + struct snd_hwdep_ops ops; + wait_queue_head_t open_wait; + void *private_data; + void (*private_free) (struct snd_hwdep *hwdep); + struct device dev; + + struct mutex open_mutex; + int used; /* reference counter */ + unsigned int dsp_loaded; /* bit fields of loaded dsp indices */ + unsigned int exclusive:1; /* exclusive access mode */ +}; + +extern int snd_hwdep_new(struct snd_card *card, char *id, int device, + struct snd_hwdep **rhwdep); + +#endif /* __SOUND_HWDEP_H */ diff --git a/include/sound/i2c.h b/include/sound/i2c.h new file mode 100644 index 000000000..6f0162ae9 --- /dev/null +++ b/include/sound/i2c.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_I2C_H +#define __SOUND_I2C_H + +/* + */ + +#define SND_I2C_DEVICE_ADDRTEN (1<<0) /* 10-bit I2C address */ + +struct snd_i2c_device { + struct list_head list; + struct snd_i2c_bus *bus; /* I2C bus */ + char name[32]; /* some useful device name */ + unsigned short flags; /* device flags */ + unsigned short addr; /* device address (might be 10-bit) */ + unsigned long private_value; + void *private_data; + void (*private_free)(struct snd_i2c_device *device); +}; + +#define snd_i2c_device(n) list_entry(n, struct snd_i2c_device, list) + +struct snd_i2c_bit_ops { + void (*start)(struct snd_i2c_bus *bus); /* transfer start */ + void (*stop)(struct snd_i2c_bus *bus); /* transfer stop */ + void (*direction)(struct snd_i2c_bus *bus, int clock, int data); /* set line direction (0 = write, 1 = read) */ + void (*setlines)(struct snd_i2c_bus *bus, int clock, int data); + int (*getclock)(struct snd_i2c_bus *bus); + int (*getdata)(struct snd_i2c_bus *bus, int ack); +}; + +struct snd_i2c_ops { + int (*sendbytes)(struct snd_i2c_device *device, unsigned char *bytes, int count); + int (*readbytes)(struct snd_i2c_device *device, unsigned char *bytes, int count); + int (*probeaddr)(struct snd_i2c_bus *bus, unsigned short addr); +}; + +struct snd_i2c_bus { + struct snd_card *card; /* card which I2C belongs to */ + char name[32]; /* some useful label */ + + struct mutex lock_mutex; + + struct snd_i2c_bus *master; /* master bus when SCK/SCL is shared */ + struct list_head buses; /* master: slave buses sharing SCK/SCL, slave: link list */ + + struct list_head devices; /* attached devices to this bus */ + + union { + struct snd_i2c_bit_ops *bit; + void *ops; + } hw_ops; /* lowlevel operations */ + const struct snd_i2c_ops *ops; /* midlevel operations */ + + unsigned long private_value; + void *private_data; + void (*private_free)(struct snd_i2c_bus *bus); +}; + +#define snd_i2c_slave_bus(n) list_entry(n, struct snd_i2c_bus, buses) + +int snd_i2c_bus_create(struct snd_card *card, const char *name, + struct snd_i2c_bus *master, struct snd_i2c_bus **ri2c); +int snd_i2c_device_create(struct snd_i2c_bus *bus, const char *name, + unsigned char addr, struct snd_i2c_device **rdevice); +int snd_i2c_device_free(struct snd_i2c_device *device); + +static inline void snd_i2c_lock(struct snd_i2c_bus *bus) +{ + if (bus->master) + mutex_lock(&bus->master->lock_mutex); + else + mutex_lock(&bus->lock_mutex); +} + +static inline void snd_i2c_unlock(struct snd_i2c_bus *bus) +{ + if (bus->master) + mutex_unlock(&bus->master->lock_mutex); + else + mutex_unlock(&bus->lock_mutex); +} + +int snd_i2c_sendbytes(struct snd_i2c_device *device, unsigned char *bytes, int count); +int snd_i2c_readbytes(struct snd_i2c_device *device, unsigned char *bytes, int count); +int snd_i2c_probeaddr(struct snd_i2c_bus *bus, unsigned short addr); + +#endif /* __SOUND_I2C_H */ diff --git a/include/sound/info.h b/include/sound/info.h new file mode 100644 index 000000000..7c13bf52c --- /dev/null +++ b/include/sound/info.h @@ -0,0 +1,234 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_INFO_H +#define __SOUND_INFO_H + +/* + * Header file for info interface + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + */ + +#include <linux/poll.h> +#include <linux/seq_file.h> +#include <sound/core.h> + +/* buffer for information */ +struct snd_info_buffer { + char *buffer; /* pointer to begin of buffer */ + unsigned int curr; /* current position in buffer */ + unsigned int size; /* current size */ + unsigned int len; /* total length of buffer */ + int stop; /* stop flag */ + int error; /* error code */ +}; + +#define SNDRV_INFO_CONTENT_TEXT 0 +#define SNDRV_INFO_CONTENT_DATA 1 + +struct snd_info_entry; + +struct snd_info_entry_text { + void (*read)(struct snd_info_entry *entry, + struct snd_info_buffer *buffer); + void (*write)(struct snd_info_entry *entry, + struct snd_info_buffer *buffer); +}; + +struct snd_info_entry_ops { + int (*open)(struct snd_info_entry *entry, + unsigned short mode, void **file_private_data); + int (*release)(struct snd_info_entry *entry, + unsigned short mode, void *file_private_data); + ssize_t (*read)(struct snd_info_entry *entry, void *file_private_data, + struct file *file, char __user *buf, + size_t count, loff_t pos); + ssize_t (*write)(struct snd_info_entry *entry, void *file_private_data, + struct file *file, const char __user *buf, + size_t count, loff_t pos); + loff_t (*llseek)(struct snd_info_entry *entry, + void *file_private_data, struct file *file, + loff_t offset, int orig); + __poll_t (*poll)(struct snd_info_entry *entry, + void *file_private_data, struct file *file, + poll_table *wait); + int (*ioctl)(struct snd_info_entry *entry, void *file_private_data, + struct file *file, unsigned int cmd, unsigned long arg); + int (*mmap)(struct snd_info_entry *entry, void *file_private_data, + struct inode *inode, struct file *file, + struct vm_area_struct *vma); +}; + +struct snd_info_entry { + const char *name; + umode_t mode; + long size; + unsigned short content; + union { + struct snd_info_entry_text text; + const struct snd_info_entry_ops *ops; + } c; + struct snd_info_entry *parent; + struct module *module; + void *private_data; + void (*private_free)(struct snd_info_entry *entry); + struct proc_dir_entry *p; + struct mutex access; + struct list_head children; + struct list_head list; +}; + +#if defined(CONFIG_SND_OSSEMUL) && defined(CONFIG_SND_PROC_FS) +int snd_info_minor_register(void); +#else +#define snd_info_minor_register() 0 +#endif + + +#ifdef CONFIG_SND_PROC_FS + +extern struct snd_info_entry *snd_seq_root; +#ifdef CONFIG_SND_OSSEMUL +extern struct snd_info_entry *snd_oss_root; +void snd_card_info_read_oss(struct snd_info_buffer *buffer); +#else +#define snd_oss_root NULL +static inline void snd_card_info_read_oss(struct snd_info_buffer *buffer) {} +#endif + +/** + * snd_iprintf - printf on the procfs buffer + * @buf: the procfs buffer + * @fmt: the printf format + * + * Outputs the string on the procfs buffer just like printf(). + * + * Return: zero for success, or a negative error code. + */ +#define snd_iprintf(buf, fmt, args...) \ + seq_printf((struct seq_file *)(buf)->buffer, fmt, ##args) + +int snd_info_init(void); +int snd_info_done(void); + +int snd_info_get_line(struct snd_info_buffer *buffer, char *line, int len); +const char *snd_info_get_str(char *dest, const char *src, int len); +struct snd_info_entry *snd_info_create_module_entry(struct module *module, + const char *name, + struct snd_info_entry *parent); +struct snd_info_entry *snd_info_create_card_entry(struct snd_card *card, + const char *name, + struct snd_info_entry *parent); +void snd_info_free_entry(struct snd_info_entry *entry); +int snd_info_store_text(struct snd_info_entry *entry); +int snd_info_restore_text(struct snd_info_entry *entry); + +int snd_info_card_create(struct snd_card *card); +int snd_info_card_register(struct snd_card *card); +int snd_info_card_free(struct snd_card *card); +void snd_info_card_disconnect(struct snd_card *card); +void snd_info_card_id_change(struct snd_card *card); +int snd_info_register(struct snd_info_entry *entry); + +/* for card drivers */ +static inline int snd_card_proc_new(struct snd_card *card, const char *name, + struct snd_info_entry **entryp) +{ + *entryp = snd_info_create_card_entry(card, name, card->proc_root); + return *entryp ? 0 : -ENOMEM; +} + +static inline void snd_info_set_text_ops(struct snd_info_entry *entry, + void *private_data, + void (*read)(struct snd_info_entry *, struct snd_info_buffer *)) +{ + entry->private_data = private_data; + entry->c.text.read = read; +} + +int snd_card_rw_proc_new(struct snd_card *card, const char *name, + void *private_data, + void (*read)(struct snd_info_entry *, + struct snd_info_buffer *), + void (*write)(struct snd_info_entry *entry, + struct snd_info_buffer *buffer)); + +int snd_info_check_reserved_words(const char *str); + +#else + +#define snd_seq_root NULL +#define snd_oss_root NULL + +static inline int snd_iprintf(struct snd_info_buffer *buffer, char *fmt, ...) { return 0; } +static inline int snd_info_init(void) { return 0; } +static inline int snd_info_done(void) { return 0; } + +static inline int snd_info_get_line(struct snd_info_buffer *buffer, char *line, int len) { return 0; } +static inline char *snd_info_get_str(char *dest, char *src, int len) { return NULL; } +static inline struct snd_info_entry *snd_info_create_module_entry(struct module *module, const char *name, struct snd_info_entry *parent) { return NULL; } +static inline struct snd_info_entry *snd_info_create_card_entry(struct snd_card *card, const char *name, struct snd_info_entry *parent) { return NULL; } +static inline void snd_info_free_entry(struct snd_info_entry *entry) { ; } + +static inline int snd_info_card_create(struct snd_card *card) { return 0; } +static inline int snd_info_card_register(struct snd_card *card) { return 0; } +static inline int snd_info_card_free(struct snd_card *card) { return 0; } +static inline void snd_info_card_disconnect(struct snd_card *card) { } +static inline void snd_info_card_id_change(struct snd_card *card) { } +static inline int snd_info_register(struct snd_info_entry *entry) { return 0; } + +static inline int snd_card_proc_new(struct snd_card *card, const char *name, + struct snd_info_entry **entryp) { return -EINVAL; } +static inline void snd_info_set_text_ops(struct snd_info_entry *entry __attribute__((unused)), + void *private_data, + void (*read)(struct snd_info_entry *, struct snd_info_buffer *)) {} +static inline int snd_card_rw_proc_new(struct snd_card *card, const char *name, + void *private_data, + void (*read)(struct snd_info_entry *, + struct snd_info_buffer *), + void (*write)(struct snd_info_entry *entry, + struct snd_info_buffer *buffer)) +{ + return 0; +} +static inline int snd_info_check_reserved_words(const char *str) { return 1; } + +#endif + +/** + * snd_card_ro_proc_new - Create a read-only text proc file entry for the card + * @card: the card instance + * @name: the file name + * @private_data: the arbitrary private data + * @read: the read callback + * + * This proc file entry will be registered via snd_card_register() call, and + * it will be removed automatically at the card removal, too. + */ +static inline int +snd_card_ro_proc_new(struct snd_card *card, const char *name, + void *private_data, + void (*read)(struct snd_info_entry *, + struct snd_info_buffer *)) +{ + return snd_card_rw_proc_new(card, name, private_data, read, NULL); +} + +/* + * OSS info part + */ + +#if defined(CONFIG_SND_OSSEMUL) && defined(CONFIG_SND_PROC_FS) + +#define SNDRV_OSS_INFO_DEV_AUDIO 0 +#define SNDRV_OSS_INFO_DEV_SYNTH 1 +#define SNDRV_OSS_INFO_DEV_MIDI 2 +#define SNDRV_OSS_INFO_DEV_TIMERS 4 +#define SNDRV_OSS_INFO_DEV_MIXERS 5 + +#define SNDRV_OSS_INFO_DEV_COUNT 6 + +int snd_oss_info_register(int dev, int num, char *string); +#define snd_oss_info_unregister(dev, num) snd_oss_info_register(dev, num, NULL) + +#endif /* CONFIG_SND_OSSEMUL && CONFIG_SND_PROC_FS */ + +#endif /* __SOUND_INFO_H */ diff --git a/include/sound/initval.h b/include/sound/initval.h new file mode 100644 index 000000000..a1ff3b486 --- /dev/null +++ b/include/sound/initval.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_INITVAL_H +#define __SOUND_INITVAL_H + +/* + * Init values for soundcard modules + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + */ + +#define SNDRV_AUTO_PORT 1 +#define SNDRV_AUTO_IRQ 0xffff +#define SNDRV_AUTO_DMA 0xffff +#define SNDRV_AUTO_DMA_SIZE (0x7fffffff) + +#define SNDRV_DEFAULT_IDX1 (-1) +#define SNDRV_DEFAULT_STR1 NULL +#define SNDRV_DEFAULT_ENABLE1 1 +#define SNDRV_DEFAULT_PORT1 SNDRV_AUTO_PORT +#define SNDRV_DEFAULT_IRQ1 SNDRV_AUTO_IRQ +#define SNDRV_DEFAULT_DMA1 SNDRV_AUTO_DMA +#define SNDRV_DEFAULT_DMA_SIZE1 SNDRV_AUTO_DMA_SIZE +#define SNDRV_DEFAULT_PTR1 SNDRV_DEFAULT_STR1 + +#define SNDRV_DEFAULT_IDX { [0 ... (SNDRV_CARDS-1)] = -1 } +#define SNDRV_DEFAULT_STR { [0 ... (SNDRV_CARDS-1)] = NULL } +#define SNDRV_DEFAULT_ENABLE { 1, [1 ... (SNDRV_CARDS-1)] = 0 } +#define SNDRV_DEFAULT_ENABLE_PNP { [0 ... (SNDRV_CARDS-1)] = 1 } +#ifdef CONFIG_PNP +#define SNDRV_DEFAULT_ENABLE_ISAPNP SNDRV_DEFAULT_ENABLE_PNP +#else +#define SNDRV_DEFAULT_ENABLE_ISAPNP SNDRV_DEFAULT_ENABLE +#endif +#define SNDRV_DEFAULT_PORT { [0 ... (SNDRV_CARDS-1)] = SNDRV_AUTO_PORT } +#define SNDRV_DEFAULT_IRQ { [0 ... (SNDRV_CARDS-1)] = SNDRV_AUTO_IRQ } +#define SNDRV_DEFAULT_DMA { [0 ... (SNDRV_CARDS-1)] = SNDRV_AUTO_DMA } +#define SNDRV_DEFAULT_DMA_SIZE { [0 ... (SNDRV_CARDS-1)] = SNDRV_AUTO_DMA_SIZE } +#define SNDRV_DEFAULT_PTR SNDRV_DEFAULT_STR + +#ifdef SNDRV_LEGACY_FIND_FREE_IOPORT +static long snd_legacy_find_free_ioport(const long *port_table, long size) +{ + while (*port_table != -1) { + if (request_region(*port_table, size, "ALSA test")) { + release_region(*port_table, size); + return *port_table; + } + port_table++; + } + return -1; +} +#endif + +#ifdef SNDRV_LEGACY_FIND_FREE_IRQ +#include <linux/interrupt.h> + +static irqreturn_t snd_legacy_empty_irq_handler(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + +static int snd_legacy_find_free_irq(const int *irq_table) +{ + while (*irq_table != -1) { + if (!request_irq(*irq_table, snd_legacy_empty_irq_handler, + IRQF_PROBE_SHARED, "ALSA Test IRQ", + (void *) irq_table)) { + free_irq(*irq_table, (void *) irq_table); + return *irq_table; + } + irq_table++; + } + return -1; +} +#endif + +#ifdef SNDRV_LEGACY_FIND_FREE_DMA +static int snd_legacy_find_free_dma(const int *dma_table) +{ + while (*dma_table != -1) { + if (!request_dma(*dma_table, "ALSA Test DMA")) { + free_dma(*dma_table); + return *dma_table; + } + dma_table++; + } + return -1; +} +#endif + +#endif /* __SOUND_INITVAL_H */ diff --git a/include/sound/intel-dsp-config.h b/include/sound/intel-dsp-config.h new file mode 100644 index 000000000..34c975910 --- /dev/null +++ b/include/sound/intel-dsp-config.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * intel-dsp-config.h - Intel DSP config + * + * Copyright (c) 2019 Jaroslav Kysela <perex@perex.cz> + */ + +#ifndef __INTEL_DSP_CONFIG_H__ +#define __INTEL_DSP_CONFIG_H__ + +struct pci_dev; + +enum { + SND_INTEL_DSP_DRIVER_ANY = 0, + SND_INTEL_DSP_DRIVER_LEGACY, + SND_INTEL_DSP_DRIVER_SST, + SND_INTEL_DSP_DRIVER_SOF, + SND_INTEL_DSP_DRIVER_AVS, + SND_INTEL_DSP_DRIVER_LAST = SND_INTEL_DSP_DRIVER_AVS +}; + +#if IS_ENABLED(CONFIG_SND_INTEL_DSP_CONFIG) + +int snd_intel_dsp_driver_probe(struct pci_dev *pci); +int snd_intel_acpi_dsp_driver_probe(struct device *dev, const u8 acpi_hid[ACPI_ID_LEN]); + +#else + +static inline int snd_intel_dsp_driver_probe(struct pci_dev *pci) +{ + return SND_INTEL_DSP_DRIVER_ANY; +} + +static inline +int snd_intel_acpi_dsp_driver_probe(struct device *dev, const u8 acpi_hid[ACPI_ID_LEN]) +{ + return SND_INTEL_DSP_DRIVER_ANY; +} + +#endif + +#endif diff --git a/include/sound/intel-nhlt.h b/include/sound/intel-nhlt.h new file mode 100644 index 000000000..53470d6a2 --- /dev/null +++ b/include/sound/intel-nhlt.h @@ -0,0 +1,189 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * intel-nhlt.h - Intel HDA Platform NHLT header + * + * Copyright (c) 2015-2019 Intel Corporation + */ + +#ifndef __INTEL_NHLT_H__ +#define __INTEL_NHLT_H__ + +#include <linux/acpi.h> + +enum nhlt_link_type { + NHLT_LINK_HDA = 0, + NHLT_LINK_DSP = 1, + NHLT_LINK_DMIC = 2, + NHLT_LINK_SSP = 3, + NHLT_LINK_INVALID +}; + +enum nhlt_device_type { + NHLT_DEVICE_BT = 0, + NHLT_DEVICE_DMIC = 1, + NHLT_DEVICE_I2S = 4, + NHLT_DEVICE_INVALID +}; + +struct wav_fmt { + u16 fmt_tag; + u16 channels; + u32 samples_per_sec; + u32 avg_bytes_per_sec; + u16 block_align; + u16 bits_per_sample; + u16 cb_size; +} __packed; + +struct wav_fmt_ext { + struct wav_fmt fmt; + union samples { + u16 valid_bits_per_sample; + u16 samples_per_block; + u16 reserved; + } sample; + u32 channel_mask; + u8 sub_fmt[16]; +} __packed; + +struct nhlt_specific_cfg { + u32 size; + u8 caps[]; +} __packed; + +struct nhlt_fmt_cfg { + struct wav_fmt_ext fmt_ext; + struct nhlt_specific_cfg config; +} __packed; + +struct nhlt_fmt { + u8 fmt_count; + struct nhlt_fmt_cfg fmt_config[]; +} __packed; + +struct nhlt_endpoint { + u32 length; + u8 linktype; + u8 instance_id; + u16 vendor_id; + u16 device_id; + u16 revision_id; + u32 subsystem_id; + u8 device_type; + u8 direction; + u8 virtual_bus_id; + struct nhlt_specific_cfg config; +} __packed; + +struct nhlt_acpi_table { + struct acpi_table_header header; + u8 endpoint_count; + struct nhlt_endpoint desc[]; +} __packed; + +struct nhlt_resource_desc { + u32 extra; + u16 flags; + u64 addr_spc_gra; + u64 min_addr; + u64 max_addr; + u64 addr_trans_offset; + u64 length; +} __packed; + +#define MIC_ARRAY_2CH 2 +#define MIC_ARRAY_4CH 4 + +struct nhlt_device_specific_config { + u8 virtual_slot; + u8 config_type; +} __packed; + +struct nhlt_dmic_array_config { + struct nhlt_device_specific_config device_config; + u8 array_type; +} __packed; + +struct nhlt_vendor_dmic_array_config { + struct nhlt_dmic_array_config dmic_config; + u8 nb_mics; + /* TODO add vendor mic config */ +} __packed; + +enum { + NHLT_CONFIG_TYPE_GENERIC = 0, + NHLT_CONFIG_TYPE_MIC_ARRAY = 1 +}; + +enum { + NHLT_MIC_ARRAY_2CH_SMALL = 0xa, + NHLT_MIC_ARRAY_2CH_BIG = 0xb, + NHLT_MIC_ARRAY_4CH_1ST_GEOM = 0xc, + NHLT_MIC_ARRAY_4CH_L_SHAPED = 0xd, + NHLT_MIC_ARRAY_4CH_2ND_GEOM = 0xe, + NHLT_MIC_ARRAY_VENDOR_DEFINED = 0xf, +}; + +#if IS_ENABLED(CONFIG_ACPI) && IS_ENABLED(CONFIG_SND_INTEL_NHLT) + +struct nhlt_acpi_table *intel_nhlt_init(struct device *dev); + +void intel_nhlt_free(struct nhlt_acpi_table *addr); + +int intel_nhlt_get_dmic_geo(struct device *dev, struct nhlt_acpi_table *nhlt); + +bool intel_nhlt_has_endpoint_type(struct nhlt_acpi_table *nhlt, u8 link_type); + +int intel_nhlt_ssp_endpoint_mask(struct nhlt_acpi_table *nhlt, u8 device_type); + +int intel_nhlt_ssp_mclk_mask(struct nhlt_acpi_table *nhlt, int ssp_num); + +struct nhlt_specific_cfg * +intel_nhlt_get_endpoint_blob(struct device *dev, struct nhlt_acpi_table *nhlt, + u32 bus_id, u8 link_type, u8 vbps, u8 bps, + u8 num_ch, u32 rate, u8 dir, u8 dev_type); + +#else + +static inline struct nhlt_acpi_table *intel_nhlt_init(struct device *dev) +{ + return NULL; +} + +static inline void intel_nhlt_free(struct nhlt_acpi_table *addr) +{ +} + +static inline int intel_nhlt_get_dmic_geo(struct device *dev, + struct nhlt_acpi_table *nhlt) +{ + return 0; +} + +static inline bool intel_nhlt_has_endpoint_type(struct nhlt_acpi_table *nhlt, + u8 link_type) +{ + return false; +} + +static inline int intel_nhlt_ssp_endpoint_mask(struct nhlt_acpi_table *nhlt, u8 device_type) +{ + return 0; +} + +static inline int intel_nhlt_ssp_mclk_mask(struct nhlt_acpi_table *nhlt, int ssp_num) +{ + return 0; +} + +static inline struct nhlt_specific_cfg * +intel_nhlt_get_endpoint_blob(struct device *dev, struct nhlt_acpi_table *nhlt, + u32 bus_id, u8 link_type, u8 vbps, u8 bps, + u8 num_ch, u32 rate, u8 dir, u8 dev_type) +{ + return NULL; +} + +#endif + +#endif diff --git a/include/sound/jack.h b/include/sound/jack.h new file mode 100644 index 000000000..1ed90e210 --- /dev/null +++ b/include/sound/jack.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_JACK_H +#define __SOUND_JACK_H + +/* + * Jack abstraction layer + * + * Copyright 2008 Wolfson Microelectronics plc + */ + +#include <sound/core.h> + +struct input_dev; + +/** + * enum snd_jack_types - Jack types which can be reported + * @SND_JACK_HEADPHONE: Headphone + * @SND_JACK_MICROPHONE: Microphone + * @SND_JACK_HEADSET: Headset + * @SND_JACK_LINEOUT: Line out + * @SND_JACK_MECHANICAL: Mechanical switch + * @SND_JACK_VIDEOOUT: Video out + * @SND_JACK_AVOUT: AV (Audio Video) out + * @SND_JACK_LINEIN: Line in + * @SND_JACK_BTN_0: Button 0 + * @SND_JACK_BTN_1: Button 1 + * @SND_JACK_BTN_2: Button 2 + * @SND_JACK_BTN_3: Button 3 + * @SND_JACK_BTN_4: Button 4 + * @SND_JACK_BTN_5: Button 5 + * + * These values are used as a bitmask. + * + * Note that this must be kept in sync with the lookup table in + * sound/core/jack.c. + */ +enum snd_jack_types { + SND_JACK_HEADPHONE = 0x0001, + SND_JACK_MICROPHONE = 0x0002, + SND_JACK_HEADSET = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE, + SND_JACK_LINEOUT = 0x0004, + SND_JACK_MECHANICAL = 0x0008, /* If detected separately */ + SND_JACK_VIDEOOUT = 0x0010, + SND_JACK_AVOUT = SND_JACK_LINEOUT | SND_JACK_VIDEOOUT, + SND_JACK_LINEIN = 0x0020, + + /* Kept separate from switches to facilitate implementation */ + SND_JACK_BTN_0 = 0x4000, + SND_JACK_BTN_1 = 0x2000, + SND_JACK_BTN_2 = 0x1000, + SND_JACK_BTN_3 = 0x0800, + SND_JACK_BTN_4 = 0x0400, + SND_JACK_BTN_5 = 0x0200, +}; + +/* Keep in sync with definitions above */ +#define SND_JACK_SWITCH_TYPES 6 + +struct snd_jack { + struct list_head kctl_list; + struct snd_card *card; + const char *id; +#ifdef CONFIG_SND_JACK_INPUT_DEV + struct input_dev *input_dev; + struct mutex input_dev_lock; + int registered; + int type; + char name[100]; + unsigned int key[6]; /* Keep in sync with definitions above */ +#endif /* CONFIG_SND_JACK_INPUT_DEV */ + int hw_status_cache; + void *private_data; + void (*private_free)(struct snd_jack *); +}; + +#ifdef CONFIG_SND_JACK + +int snd_jack_new(struct snd_card *card, const char *id, int type, + struct snd_jack **jack, bool initial_kctl, bool phantom_jack); +int snd_jack_add_new_kctl(struct snd_jack *jack, const char * name, int mask); +#ifdef CONFIG_SND_JACK_INPUT_DEV +void snd_jack_set_parent(struct snd_jack *jack, struct device *parent); +int snd_jack_set_key(struct snd_jack *jack, enum snd_jack_types type, + int keytype); +#endif +void snd_jack_report(struct snd_jack *jack, int status); + +#else +static inline int snd_jack_new(struct snd_card *card, const char *id, int type, + struct snd_jack **jack, bool initial_kctl, bool phantom_jack) +{ + return 0; +} + +static inline int snd_jack_add_new_kctl(struct snd_jack *jack, const char * name, int mask) +{ + return 0; +} + +static inline void snd_jack_report(struct snd_jack *jack, int status) +{ +} + +#endif + +#if !defined(CONFIG_SND_JACK) || !defined(CONFIG_SND_JACK_INPUT_DEV) +static inline void snd_jack_set_parent(struct snd_jack *jack, + struct device *parent) +{ +} + +static inline int snd_jack_set_key(struct snd_jack *jack, + enum snd_jack_types type, + int keytype) +{ + return 0; +} +#endif /* !CONFIG_SND_JACK || !CONFIG_SND_JACK_INPUT_DEV */ + +#endif diff --git a/include/sound/l3.h b/include/sound/l3.h new file mode 100644 index 000000000..b6f580722 --- /dev/null +++ b/include/sound/l3.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _L3_H_ +#define _L3_H_ 1 + +struct l3_pins { + void (*setdat)(struct l3_pins *, int); + void (*setclk)(struct l3_pins *, int); + void (*setmode)(struct l3_pins *, int); + + int gpio_data; + int gpio_clk; + int gpio_mode; + int use_gpios; + + int data_hold; + int data_setup; + int clock_high; + int mode_hold; + int mode; + int mode_setup; +}; + +struct device; + +int l3_write(struct l3_pins *adap, u8 addr, u8 *data, int len); +int l3_set_gpio_ops(struct device *dev, struct l3_pins *adap); + +#endif diff --git a/include/sound/madera-pdata.h b/include/sound/madera-pdata.h new file mode 100644 index 000000000..58398d80c --- /dev/null +++ b/include/sound/madera-pdata.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Platform data for Madera codec driver + * + * Copyright (C) 2016-2019 Cirrus Logic, Inc. and + * Cirrus Logic International Semiconductor Ltd. + */ + +#ifndef MADERA_CODEC_PDATA_H +#define MADERA_CODEC_PDATA_H + +#include <linux/types.h> + +#define MADERA_MAX_INPUT 6 +#define MADERA_MAX_MUXED_CHANNELS 4 +#define MADERA_MAX_OUTPUT 6 +#define MADERA_MAX_AIF 4 +#define MADERA_MAX_PDM_SPK 2 +#define MADERA_MAX_DSP 7 + +/** + * struct madera_codec_pdata + * + * @max_channels_clocked: Maximum number of channels that I2S clocks will be + * generated for. Useful when clock master for systems + * where the I2S bus has multiple data lines. + * @dmic_ref: Indicates how the MICBIAS pins have been externally + * connected to DMICs on each input. A value of 0 + * indicates MICVDD and is the default. Other values are: + * For CS47L35 one of the CS47L35_DMIC_REF_xxx values + * For all other codecs one of the MADERA_DMIC_REF_xxx + * Also see the datasheet for a description of the + * INn_DMIC_SUP field. + * @inmode: Mode for the ADC inputs. One of the MADERA_INMODE_xxx + * values. Two-dimensional array + * [input_number][channel number], with four slots per + * input in the order + * [n][0]=INnAL [n][1]=INnAR [n][2]=INnBL [n][3]=INnBR + * @out_mono: For each output set the value to TRUE to indicate that + * the output is mono. [0]=OUT1, [1]=OUT2, ... + * @pdm_fmt: PDM speaker data format. See the PDM_SPKn_FMT field in + * the datasheet for a description of this value. + * @pdm_mute: PDM mute format. See the PDM_SPKn_CTRL_1 register + * in the datasheet for a description of this value. + */ +struct madera_codec_pdata { + u32 max_channels_clocked[MADERA_MAX_AIF]; + + u32 dmic_ref[MADERA_MAX_INPUT]; + + u32 inmode[MADERA_MAX_INPUT][MADERA_MAX_MUXED_CHANNELS]; + + bool out_mono[MADERA_MAX_OUTPUT]; + + u32 pdm_fmt[MADERA_MAX_PDM_SPK]; + u32 pdm_mute[MADERA_MAX_PDM_SPK]; +}; + +#endif diff --git a/include/sound/max9768.h b/include/sound/max9768.h new file mode 100644 index 000000000..0f78b41d0 --- /dev/null +++ b/include/sound/max9768.h @@ -0,0 +1,24 @@ +/* + * Platform data for MAX9768 + * Copyright (C) 2011, 2012 by Wolfram Sang, Pengutronix e.K. + * same licence as the driver + */ + +#ifndef __SOUND_MAX9768_PDATA_H__ +#define __SOUND_MAX9768_PDATA_H__ + +/** + * struct max9768_pdata - optional platform specific MAX9768 configuration + * @shdn_gpio: GPIO to SHDN pin. If not valid, pin must be hardwired HIGH + * @mute_gpio: GPIO to MUTE pin. If not valid, control for mute won't be added + * @flags: configuration flags, e.g. set classic PWM mode (check datasheet + * regarding "filterless modulation" which is default). + */ +struct max9768_pdata { + int shdn_gpio; + int mute_gpio; + unsigned flags; +#define MAX9768_FLAG_CLASSIC_PWM (1 << 0) +}; + +#endif /* __SOUND_MAX9768_PDATA_H__*/ diff --git a/include/sound/max98088.h b/include/sound/max98088.h new file mode 100644 index 000000000..76b376919 --- /dev/null +++ b/include/sound/max98088.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Platform data for MAX98088 + * + * Copyright 2010 Maxim Integrated Products + */ + +#ifndef __SOUND_MAX98088_PDATA_H__ +#define __SOUND_MAX98088_PDATA_H__ + +/* Equalizer filter response configuration */ +struct max98088_eq_cfg { + const char *name; + unsigned int rate; + u16 band1[5]; + u16 band2[5]; + u16 band3[5]; + u16 band4[5]; + u16 band5[5]; +}; + +/* codec platform data */ +struct max98088_pdata { + + /* Equalizers for DAI1 and DAI2 */ + struct max98088_eq_cfg *eq_cfg; + unsigned int eq_cfgcnt; + + /* Receiver output can be configured as power amplifier or LINE out */ + /* Set receiver_mode to: + * 0 = amplifier output, or + * 1 = LINE level output + */ + unsigned int receiver_mode:1; + + /* Analog/digital microphone configuration: + * 0 = analog microphone input (normal setting) + * 1 = digital microphone input + */ + unsigned int digmic_left_mode:1; + unsigned int digmic_right_mode:1; + +}; + +#endif diff --git a/include/sound/max98090.h b/include/sound/max98090.h new file mode 100644 index 000000000..6bc1b014f --- /dev/null +++ b/include/sound/max98090.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Platform data for MAX98090 + * + * Copyright 2011-2012 Maxim Integrated Products + */ + +#ifndef __SOUND_MAX98090_PDATA_H__ +#define __SOUND_MAX98090_PDATA_H__ + +/* codec platform data */ +struct max98090_pdata { + + /* Analog/digital microphone configuration: + * 0 = analog microphone input (normal setting) + * 1 = digital microphone input + */ + unsigned int digmic_left_mode:1; + unsigned int digmic_right_mode:1; + unsigned int digmic_3_mode:1; + unsigned int digmic_4_mode:1; +}; + +#endif diff --git a/include/sound/max98095.h b/include/sound/max98095.h new file mode 100644 index 000000000..731c88551 --- /dev/null +++ b/include/sound/max98095.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Platform data for MAX98095 + * + * Copyright 2011 Maxim Integrated Products + */ + +#ifndef __SOUND_MAX98095_PDATA_H__ +#define __SOUND_MAX98095_PDATA_H__ + +/* Equalizer filter response configuration */ +struct max98095_eq_cfg { + const char *name; + unsigned int rate; + u16 band1[5]; + u16 band2[5]; + u16 band3[5]; + u16 band4[5]; + u16 band5[5]; +}; + +/* Biquad filter response configuration */ +struct max98095_biquad_cfg { + const char *name; + unsigned int rate; + u16 band1[5]; + u16 band2[5]; +}; + +/* codec platform data */ +struct max98095_pdata { + + /* Equalizers for DAI1 and DAI2 */ + struct max98095_eq_cfg *eq_cfg; + unsigned int eq_cfgcnt; + + /* Biquad filter for DAI1 and DAI2 */ + struct max98095_biquad_cfg *bq_cfg; + unsigned int bq_cfgcnt; + + /* Analog/digital microphone configuration: + * 0 = analog microphone input (normal setting) + * 1 = digital microphone input + */ + unsigned int digmic_left_mode:1; + unsigned int digmic_right_mode:1; + + /* Pin5 is the mechanical method of sensing jack insertion + * but it is something that might not be supported. + * 0 = PIN5 not supported + * 1 = PIN5 supported + */ + unsigned int jack_detect_pin5en:1; + + /* Slew amount for jack detection. Calculated as 4 * (delay + 1). + * Default delay is 24 to get a time of 100ms. + */ + unsigned int jack_detect_delay; +}; + +#endif diff --git a/include/sound/memalloc.h b/include/sound/memalloc.h new file mode 100644 index 000000000..43d524580 --- /dev/null +++ b/include/sound/memalloc.h @@ -0,0 +1,125 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + * Takashi Iwai <tiwai@suse.de> + * + * Generic memory allocators + */ + +#ifndef __SOUND_MEMALLOC_H +#define __SOUND_MEMALLOC_H + +#include <linux/dma-direction.h> +#include <asm/page.h> + +struct device; +struct vm_area_struct; +struct sg_table; + +/* + * buffer device info + */ +struct snd_dma_device { + int type; /* SNDRV_DMA_TYPE_XXX */ + enum dma_data_direction dir; /* DMA direction */ + bool need_sync; /* explicit sync needed? */ + struct device *dev; /* generic device */ +}; + +/* + * buffer types + */ +#define SNDRV_DMA_TYPE_UNKNOWN 0 /* not defined */ +#define SNDRV_DMA_TYPE_CONTINUOUS 1 /* continuous no-DMA memory */ +#define SNDRV_DMA_TYPE_DEV 2 /* generic device continuous */ +#define SNDRV_DMA_TYPE_DEV_WC 5 /* continuous write-combined */ +#ifdef CONFIG_GENERIC_ALLOCATOR +#define SNDRV_DMA_TYPE_DEV_IRAM 4 /* generic device iram-buffer */ +#else +#define SNDRV_DMA_TYPE_DEV_IRAM SNDRV_DMA_TYPE_DEV +#endif +#define SNDRV_DMA_TYPE_VMALLOC 7 /* vmalloc'ed buffer */ +#define SNDRV_DMA_TYPE_NONCONTIG 8 /* non-coherent SG buffer */ +#define SNDRV_DMA_TYPE_NONCOHERENT 9 /* non-coherent buffer */ +#ifdef CONFIG_SND_DMA_SGBUF +#define SNDRV_DMA_TYPE_DEV_SG SNDRV_DMA_TYPE_NONCONTIG +#define SNDRV_DMA_TYPE_DEV_WC_SG 6 /* SG write-combined */ +#else +#define SNDRV_DMA_TYPE_DEV_SG SNDRV_DMA_TYPE_DEV /* no SG-buf support */ +#define SNDRV_DMA_TYPE_DEV_WC_SG SNDRV_DMA_TYPE_DEV_WC +#endif +/* fallback types, don't use those directly */ +#ifdef CONFIG_SND_DMA_SGBUF +#define SNDRV_DMA_TYPE_DEV_SG_FALLBACK 10 +#define SNDRV_DMA_TYPE_DEV_WC_SG_FALLBACK 11 +#endif + +/* + * info for buffer allocation + */ +struct snd_dma_buffer { + struct snd_dma_device dev; /* device type */ + unsigned char *area; /* virtual pointer */ + dma_addr_t addr; /* physical address */ + size_t bytes; /* buffer size in bytes */ + void *private_data; /* private for allocator; don't touch */ +}; + +/* + * return the pages matching with the given byte size + */ +static inline unsigned int snd_sgbuf_aligned_pages(size_t size) +{ + return (size + PAGE_SIZE - 1) >> PAGE_SHIFT; +} + +/* allocate/release a buffer */ +int snd_dma_alloc_dir_pages(int type, struct device *dev, + enum dma_data_direction dir, size_t size, + struct snd_dma_buffer *dmab); + +static inline int snd_dma_alloc_pages(int type, struct device *dev, + size_t size, struct snd_dma_buffer *dmab) +{ + return snd_dma_alloc_dir_pages(type, dev, DMA_BIDIRECTIONAL, size, dmab); +} + +int snd_dma_alloc_pages_fallback(int type, struct device *dev, size_t size, + struct snd_dma_buffer *dmab); +void snd_dma_free_pages(struct snd_dma_buffer *dmab); +int snd_dma_buffer_mmap(struct snd_dma_buffer *dmab, + struct vm_area_struct *area); + +enum snd_dma_sync_mode { SNDRV_DMA_SYNC_CPU, SNDRV_DMA_SYNC_DEVICE }; +#ifdef CONFIG_HAS_DMA +void snd_dma_buffer_sync(struct snd_dma_buffer *dmab, + enum snd_dma_sync_mode mode); +#else +static inline void snd_dma_buffer_sync(struct snd_dma_buffer *dmab, + enum snd_dma_sync_mode mode) {} +#endif + +dma_addr_t snd_sgbuf_get_addr(struct snd_dma_buffer *dmab, size_t offset); +struct page *snd_sgbuf_get_page(struct snd_dma_buffer *dmab, size_t offset); +unsigned int snd_sgbuf_get_chunk_size(struct snd_dma_buffer *dmab, + unsigned int ofs, unsigned int size); + +/* device-managed memory allocator */ +struct snd_dma_buffer *snd_devm_alloc_dir_pages(struct device *dev, int type, + enum dma_data_direction dir, + size_t size); + +static inline struct snd_dma_buffer * +snd_devm_alloc_pages(struct device *dev, int type, size_t size) +{ + return snd_devm_alloc_dir_pages(dev, type, DMA_BIDIRECTIONAL, size); +} + +static inline struct sg_table * +snd_dma_noncontig_sg_table(struct snd_dma_buffer *dmab) +{ + return dmab->private_data; +} + +#endif /* __SOUND_MEMALLOC_H */ + diff --git a/include/sound/minors.h b/include/sound/minors.h new file mode 100644 index 000000000..2b0395693 --- /dev/null +++ b/include/sound/minors.h @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_MINORS_H +#define __SOUND_MINORS_H + +/* + * MINOR numbers + */ + +#define SNDRV_OS_MINORS 256 + +#define SNDRV_MINOR_DEVICES 32 +#define SNDRV_MINOR_CARD(minor) ((minor) >> 5) +#define SNDRV_MINOR_DEVICE(minor) ((minor) & 0x001f) +#define SNDRV_MINOR(card, dev) (((card) << 5) | (dev)) + +/* these minors can still be used for autoloading devices (/dev/aload*) */ +#define SNDRV_MINOR_CONTROL 0 /* 0 */ +#define SNDRV_MINOR_GLOBAL 1 /* 1 */ +#define SNDRV_MINOR_SEQUENCER 1 /* SNDRV_MINOR_GLOBAL + 0 * 32 */ +#define SNDRV_MINOR_TIMER 33 /* SNDRV_MINOR_GLOBAL + 1 * 32 */ + +#ifndef CONFIG_SND_DYNAMIC_MINORS +#define SNDRV_MINOR_COMPRESS 2 /* 2 - 3 */ +#define SNDRV_MINOR_HWDEP 4 /* 4 - 7 */ +#define SNDRV_MINOR_RAWMIDI 8 /* 8 - 15 */ +#define SNDRV_MINOR_PCM_PLAYBACK 16 /* 16 - 23 */ +#define SNDRV_MINOR_PCM_CAPTURE 24 /* 24 - 31 */ + +/* same as first respective minor number to make minor allocation easier */ +#define SNDRV_DEVICE_TYPE_CONTROL SNDRV_MINOR_CONTROL +#define SNDRV_DEVICE_TYPE_HWDEP SNDRV_MINOR_HWDEP +#define SNDRV_DEVICE_TYPE_RAWMIDI SNDRV_MINOR_RAWMIDI +#define SNDRV_DEVICE_TYPE_PCM_PLAYBACK SNDRV_MINOR_PCM_PLAYBACK +#define SNDRV_DEVICE_TYPE_PCM_CAPTURE SNDRV_MINOR_PCM_CAPTURE +#define SNDRV_DEVICE_TYPE_SEQUENCER SNDRV_MINOR_SEQUENCER +#define SNDRV_DEVICE_TYPE_TIMER SNDRV_MINOR_TIMER +#define SNDRV_DEVICE_TYPE_COMPRESS SNDRV_MINOR_COMPRESS + +#else /* CONFIG_SND_DYNAMIC_MINORS */ + +enum { + SNDRV_DEVICE_TYPE_CONTROL, + SNDRV_DEVICE_TYPE_SEQUENCER, + SNDRV_DEVICE_TYPE_TIMER, + SNDRV_DEVICE_TYPE_HWDEP, + SNDRV_DEVICE_TYPE_RAWMIDI, + SNDRV_DEVICE_TYPE_PCM_PLAYBACK, + SNDRV_DEVICE_TYPE_PCM_CAPTURE, + SNDRV_DEVICE_TYPE_COMPRESS, +}; + +#endif /* CONFIG_SND_DYNAMIC_MINORS */ + +#define SNDRV_MINOR_HWDEPS 4 +#define SNDRV_MINOR_RAWMIDIS 8 +#define SNDRV_MINOR_PCMS 8 + + +#ifdef CONFIG_SND_OSSEMUL + +#define SNDRV_MINOR_OSS_DEVICES 16 +#define SNDRV_MINOR_OSS_CARD(minor) ((minor) >> 4) +#define SNDRV_MINOR_OSS_DEVICE(minor) ((minor) & 0x000f) +#define SNDRV_MINOR_OSS(card, dev) (((card) << 4) | (dev)) + +#define SNDRV_MINOR_OSS_MIXER 0 /* /dev/mixer - OSS 3.XX compatible */ +#define SNDRV_MINOR_OSS_SEQUENCER 1 /* /dev/sequencer - OSS 3.XX compatible */ +#define SNDRV_MINOR_OSS_MIDI 2 /* /dev/midi - native midi interface - OSS 3.XX compatible - UART */ +#define SNDRV_MINOR_OSS_PCM 3 /* alias */ +#define SNDRV_MINOR_OSS_PCM_8 3 /* /dev/dsp - 8bit PCM - OSS 3.XX compatible */ +#define SNDRV_MINOR_OSS_AUDIO 4 /* /dev/audio - SunSparc compatible */ +#define SNDRV_MINOR_OSS_PCM_16 5 /* /dev/dsp16 - 16bit PCM - OSS 3.XX compatible */ +#define SNDRV_MINOR_OSS_SNDSTAT 6 /* /dev/sndstat - for compatibility with OSS */ +#define SNDRV_MINOR_OSS_RESERVED7 7 /* reserved for future use */ +#define SNDRV_MINOR_OSS_MUSIC 8 /* /dev/music - OSS 3.XX compatible */ +#define SNDRV_MINOR_OSS_DMMIDI 9 /* /dev/dmmidi0 - this device can have another minor # with OSS */ +#define SNDRV_MINOR_OSS_DMFM 10 /* /dev/dmfm0 - this device can have another minor # with OSS */ +#define SNDRV_MINOR_OSS_MIXER1 11 /* alternate mixer */ +#define SNDRV_MINOR_OSS_PCM1 12 /* alternate PCM (GF-A-1) */ +#define SNDRV_MINOR_OSS_MIDI1 13 /* alternate midi - SYNTH */ +#define SNDRV_MINOR_OSS_DMMIDI1 14 /* alternate dmmidi - SYNTH */ +#define SNDRV_MINOR_OSS_RESERVED15 15 /* reserved for future use */ + +#define SNDRV_OSS_DEVICE_TYPE_MIXER 0 +#define SNDRV_OSS_DEVICE_TYPE_SEQUENCER 1 +#define SNDRV_OSS_DEVICE_TYPE_PCM 2 +#define SNDRV_OSS_DEVICE_TYPE_MIDI 3 +#define SNDRV_OSS_DEVICE_TYPE_DMFM 4 +#define SNDRV_OSS_DEVICE_TYPE_SNDSTAT 5 +#define SNDRV_OSS_DEVICE_TYPE_MUSIC 6 + +#define MODULE_ALIAS_SNDRV_MINOR(type) \ + MODULE_ALIAS("sound-service-?-" __stringify(type)) + +#endif + +#endif /* __SOUND_MINORS_H */ diff --git a/include/sound/mixer_oss.h b/include/sound/mixer_oss.h new file mode 100644 index 000000000..9a212c0ce --- /dev/null +++ b/include/sound/mixer_oss.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_MIXER_OSS_H +#define __SOUND_MIXER_OSS_H + +/* + * OSS MIXER API + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + */ + +#if IS_ENABLED(CONFIG_SND_MIXER_OSS) + +#define SNDRV_OSS_MAX_MIXERS 32 + +struct snd_mixer_oss_file; + +struct snd_mixer_oss_slot { + int number; + unsigned int stereo: 1; + int (*get_volume)(struct snd_mixer_oss_file *fmixer, + struct snd_mixer_oss_slot *chn, + int *left, int *right); + int (*put_volume)(struct snd_mixer_oss_file *fmixer, + struct snd_mixer_oss_slot *chn, + int left, int right); + int (*get_recsrc)(struct snd_mixer_oss_file *fmixer, + struct snd_mixer_oss_slot *chn, + int *active); + int (*put_recsrc)(struct snd_mixer_oss_file *fmixer, + struct snd_mixer_oss_slot *chn, + int active); + unsigned long private_value; + void *private_data; + void (*private_free)(struct snd_mixer_oss_slot *slot); + int volume[2]; +}; + +struct snd_mixer_oss { + struct snd_card *card; + char id[16]; + char name[32]; + struct snd_mixer_oss_slot slots[SNDRV_OSS_MAX_MIXERS]; /* OSS mixer slots */ + unsigned int mask_recsrc; /* exclusive recsrc mask */ + int (*get_recsrc)(struct snd_mixer_oss_file *fmixer, + unsigned int *active_index); + int (*put_recsrc)(struct snd_mixer_oss_file *fmixer, + unsigned int active_index); + void *private_data_recsrc; + void (*private_free_recsrc)(struct snd_mixer_oss *mixer); + struct mutex reg_mutex; + struct snd_info_entry *proc_entry; + int oss_dev_alloc; + /* --- */ + int oss_recsrc; +}; + +struct snd_mixer_oss_file { + struct snd_card *card; + struct snd_mixer_oss *mixer; +}; + +int snd_mixer_oss_ioctl_card(struct snd_card *card, + unsigned int cmd, unsigned long arg); + +#endif /* CONFIG_SND_MIXER_OSS */ + +#endif /* __SOUND_MIXER_OSS_H */ diff --git a/include/sound/mpu401.h b/include/sound/mpu401.h new file mode 100644 index 000000000..d4c915a37 --- /dev/null +++ b/include/sound/mpu401.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_MPU401_H +#define __SOUND_MPU401_H + +/* + * Header file for MPU-401 and compatible cards + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + */ + +#include <sound/rawmidi.h> +#include <linux/interrupt.h> + +#define MPU401_HW_MPU401 1 /* native MPU401 */ +#define MPU401_HW_SB 2 /* SoundBlaster MPU-401 UART */ +#define MPU401_HW_ES1688 3 /* AudioDrive ES1688 MPU-401 UART */ +#define MPU401_HW_OPL3SA2 4 /* Yamaha OPL3-SA2 */ +#define MPU401_HW_SONICVIBES 5 /* S3 SonicVibes */ +#define MPU401_HW_CS4232 6 /* CS4232 */ +#define MPU401_HW_ES18XX 7 /* AudioDrive ES18XX MPU-401 UART */ +#define MPU401_HW_FM801 8 /* ForteMedia FM801 */ +#define MPU401_HW_TRID4DWAVE 9 /* Trident 4DWave */ +#define MPU401_HW_AZT2320 10 /* Aztech AZT2320 */ +#define MPU401_HW_ALS100 11 /* Avance Logic ALS100 */ +#define MPU401_HW_ICE1712 12 /* Envy24 */ +#define MPU401_HW_VIA686A 13 /* VIA 82C686A */ +#define MPU401_HW_YMFPCI 14 /* YMF DS-XG PCI */ +#define MPU401_HW_CMIPCI 15 /* CMIPCI MPU-401 UART */ +#define MPU401_HW_ALS4000 16 /* Avance Logic ALS4000 */ +#define MPU401_HW_INTEL8X0 17 /* Intel8x0 driver */ +#define MPU401_HW_PC98II 18 /* Roland PC98II */ +#define MPU401_HW_AUREAL 19 /* Aureal Vortex */ + +#define MPU401_INFO_INPUT (1 << 0) /* input stream */ +#define MPU401_INFO_OUTPUT (1 << 1) /* output stream */ +#define MPU401_INFO_INTEGRATED (1 << 2) /* integrated h/w port */ +#define MPU401_INFO_MMIO (1 << 3) /* MMIO access */ +#define MPU401_INFO_TX_IRQ (1 << 4) /* independent TX irq */ +#define MPU401_INFO_IRQ_HOOK (1 << 5) /* mpu401 irq handler is called + from driver irq handler */ +#define MPU401_INFO_NO_ACK (1 << 6) /* No ACK cmd needed */ +#define MPU401_INFO_USE_TIMER (1 << 15) /* internal */ + +#define MPU401_MODE_BIT_INPUT 0 +#define MPU401_MODE_BIT_OUTPUT 1 +#define MPU401_MODE_BIT_INPUT_TRIGGER 2 +#define MPU401_MODE_BIT_OUTPUT_TRIGGER 3 + +#define MPU401_MODE_INPUT (1<<MPU401_MODE_BIT_INPUT) +#define MPU401_MODE_OUTPUT (1<<MPU401_MODE_BIT_OUTPUT) +#define MPU401_MODE_INPUT_TRIGGER (1<<MPU401_MODE_BIT_INPUT_TRIGGER) +#define MPU401_MODE_OUTPUT_TRIGGER (1<<MPU401_MODE_BIT_OUTPUT_TRIGGER) + +#define MPU401_MODE_INPUT_TIMER (1<<0) +#define MPU401_MODE_OUTPUT_TIMER (1<<1) + +struct snd_mpu401 { + struct snd_rawmidi *rmidi; + + unsigned short hardware; /* MPU401_HW_XXXX */ + unsigned int info_flags; /* MPU401_INFO_XXX */ + unsigned long port; /* base port of MPU-401 chip */ + unsigned long cport; /* port + 1 (usually) */ + struct resource *res; /* port resource */ + int irq; /* IRQ number of MPU-401 chip */ + + unsigned long mode; /* MPU401_MODE_XXXX */ + int timer_invoked; + + int (*open_input) (struct snd_mpu401 * mpu); + void (*close_input) (struct snd_mpu401 * mpu); + int (*open_output) (struct snd_mpu401 * mpu); + void (*close_output) (struct snd_mpu401 * mpu); + void *private_data; + + struct snd_rawmidi_substream *substream_input; + struct snd_rawmidi_substream *substream_output; + + spinlock_t input_lock; + spinlock_t output_lock; + spinlock_t timer_lock; + + struct timer_list timer; + + void (*write) (struct snd_mpu401 * mpu, unsigned char data, unsigned long addr); + unsigned char (*read) (struct snd_mpu401 *mpu, unsigned long addr); +}; + +/* I/O ports */ + +#define MPU401C(mpu) (mpu)->cport +#define MPU401D(mpu) (mpu)->port + +/* + * control register bits + */ +/* read MPU401C() */ +#define MPU401_RX_EMPTY 0x80 +#define MPU401_TX_FULL 0x40 + +/* write MPU401C() */ +#define MPU401_RESET 0xff +#define MPU401_ENTER_UART 0x3f + +/* read MPU401D() */ +#define MPU401_ACK 0xfe + + +/* + + */ + +irqreturn_t snd_mpu401_uart_interrupt(int irq, void *dev_id); +irqreturn_t snd_mpu401_uart_interrupt_tx(int irq, void *dev_id); + +int snd_mpu401_uart_new(struct snd_card *card, + int device, + unsigned short hardware, + unsigned long port, + unsigned int info_flags, + int irq, + struct snd_rawmidi ** rrawmidi); + +#endif /* __SOUND_MPU401_H */ diff --git a/include/sound/omap-hdmi-audio.h b/include/sound/omap-hdmi-audio.h new file mode 100644 index 000000000..e5f82044a --- /dev/null +++ b/include/sound/omap-hdmi-audio.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * hdmi-audio.c -- OMAP4+ DSS HDMI audio support library + * + * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com + * + * Author: Jyri Sarha <jsarha@ti.com> + */ + +#ifndef __OMAP_HDMI_AUDIO_H__ +#define __OMAP_HDMI_AUDIO_H__ + +#include <linux/platform_data/omapdss.h> + +struct omap_dss_audio { + struct snd_aes_iec958 *iec; + struct snd_cea_861_aud_if *cea; +}; + +struct omap_hdmi_audio_ops { + int (*audio_startup)(struct device *dev, + void (*abort_cb)(struct device *dev)); + int (*audio_shutdown)(struct device *dev); + int (*audio_start)(struct device *dev); + void (*audio_stop)(struct device *dev); + int (*audio_config)(struct device *dev, + struct omap_dss_audio *dss_audio); +}; + +/* HDMI audio initalization data */ +struct omap_hdmi_audio_pdata { + struct device *dev; + unsigned int version; + phys_addr_t audio_dma_addr; + + const struct omap_hdmi_audio_ops *ops; +}; + +#endif /* __OMAP_HDMI_AUDIO_H__ */ diff --git a/include/sound/opl3.h b/include/sound/opl3.h new file mode 100644 index 000000000..ebf3852da --- /dev/null +++ b/include/sound/opl3.h @@ -0,0 +1,375 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_OPL3_H +#define __SOUND_OPL3_H + +/* + * Definitions of the OPL-3 registers. + * + * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, + * Hannu Savolainen 1993-1996 + * + * The OPL-3 mode is switched on by writing 0x01, to the offset 5 + * of the right side. + * + * Another special register at the right side is at offset 4. It contains + * a bit mask defining which voices are used as 4 OP voices. + * + * The percussive mode is implemented in the left side only. + * + * With the above exceptions the both sides can be operated independently. + * + * A 4 OP voice can be created by setting the corresponding + * bit at offset 4 of the right side. + * + * For example setting the rightmost bit (0x01) changes the + * first voice on the right side to the 4 OP mode. The fourth + * voice is made inaccessible. + * + * If a voice is set to the 2 OP mode, it works like 2 OP modes + * of the original YM3812 (AdLib). In addition the voice can + * be connected the left, right or both stereo channels. It can + * even be left unconnected. This works with 4 OP voices also. + * + * The stereo connection bits are located in the FEEDBACK_CONNECTION + * register of the voice (0xC0-0xC8). In 4 OP voices these bits are + * in the second half of the voice. + */ + +#include <sound/core.h> +#include <sound/hwdep.h> +#include <sound/timer.h> +#include <sound/seq_midi_emul.h> +#include <sound/seq_oss.h> +#include <sound/seq_oss_legacy.h> +#include <sound/seq_device.h> +#include <sound/asound_fm.h> + +/* + * Register numbers for the global registers + */ + +#define OPL3_REG_TEST 0x01 +#define OPL3_ENABLE_WAVE_SELECT 0x20 + +#define OPL3_REG_TIMER1 0x02 +#define OPL3_REG_TIMER2 0x03 +#define OPL3_REG_TIMER_CONTROL 0x04 /* Left side */ +#define OPL3_IRQ_RESET 0x80 +#define OPL3_TIMER1_MASK 0x40 +#define OPL3_TIMER2_MASK 0x20 +#define OPL3_TIMER1_START 0x01 +#define OPL3_TIMER2_START 0x02 + +#define OPL3_REG_CONNECTION_SELECT 0x04 /* Right side */ +#define OPL3_LEFT_4OP_0 0x01 +#define OPL3_LEFT_4OP_1 0x02 +#define OPL3_LEFT_4OP_2 0x04 +#define OPL3_RIGHT_4OP_0 0x08 +#define OPL3_RIGHT_4OP_1 0x10 +#define OPL3_RIGHT_4OP_2 0x20 + +#define OPL3_REG_MODE 0x05 /* Right side */ +#define OPL3_OPL3_ENABLE 0x01 /* OPL3 mode */ +#define OPL3_OPL4_ENABLE 0x02 /* OPL4 mode */ + +#define OPL3_REG_KBD_SPLIT 0x08 /* Left side */ +#define OPL3_COMPOSITE_SINE_WAVE_MODE 0x80 /* Don't use with OPL-3? */ +#define OPL3_KEYBOARD_SPLIT 0x40 + +#define OPL3_REG_PERCUSSION 0xbd /* Left side only */ +#define OPL3_TREMOLO_DEPTH 0x80 +#define OPL3_VIBRATO_DEPTH 0x40 +#define OPL3_PERCUSSION_ENABLE 0x20 +#define OPL3_BASSDRUM_ON 0x10 +#define OPL3_SNAREDRUM_ON 0x08 +#define OPL3_TOMTOM_ON 0x04 +#define OPL3_CYMBAL_ON 0x02 +#define OPL3_HIHAT_ON 0x01 + +/* + * Offsets to the register banks for operators. To get the + * register number just add the operator offset to the bank offset + * + * AM/VIB/EG/KSR/Multiple (0x20 to 0x35) + */ +#define OPL3_REG_AM_VIB 0x20 +#define OPL3_TREMOLO_ON 0x80 +#define OPL3_VIBRATO_ON 0x40 +#define OPL3_SUSTAIN_ON 0x20 +#define OPL3_KSR 0x10 /* Key scaling rate */ +#define OPL3_MULTIPLE_MASK 0x0f /* Frequency multiplier */ + + /* + * KSL/Total level (0x40 to 0x55) + */ +#define OPL3_REG_KSL_LEVEL 0x40 +#define OPL3_KSL_MASK 0xc0 /* Envelope scaling bits */ +#define OPL3_TOTAL_LEVEL_MASK 0x3f /* Strength (volume) of OP */ + +/* + * Attack / Decay rate (0x60 to 0x75) + */ +#define OPL3_REG_ATTACK_DECAY 0x60 +#define OPL3_ATTACK_MASK 0xf0 +#define OPL3_DECAY_MASK 0x0f + +/* + * Sustain level / Release rate (0x80 to 0x95) + */ +#define OPL3_REG_SUSTAIN_RELEASE 0x80 +#define OPL3_SUSTAIN_MASK 0xf0 +#define OPL3_RELEASE_MASK 0x0f + +/* + * Wave select (0xE0 to 0xF5) + */ +#define OPL3_REG_WAVE_SELECT 0xe0 +#define OPL3_WAVE_SELECT_MASK 0x07 + +/* + * Offsets to the register banks for voices. Just add to the + * voice number to get the register number. + * + * F-Number low bits (0xA0 to 0xA8). + */ +#define OPL3_REG_FNUM_LOW 0xa0 + +/* + * F-number high bits / Key on / Block (octave) (0xB0 to 0xB8) + */ +#define OPL3_REG_KEYON_BLOCK 0xb0 +#define OPL3_KEYON_BIT 0x20 +#define OPL3_BLOCKNUM_MASK 0x1c +#define OPL3_FNUM_HIGH_MASK 0x03 + +/* + * Feedback / Connection (0xc0 to 0xc8) + * + * These registers have two new bits when the OPL-3 mode + * is selected. These bits controls connecting the voice + * to the stereo channels. For 4 OP voices this bit is + * defined in the second half of the voice (add 3 to the + * register offset). + * + * For 4 OP voices the connection bit is used in the + * both halves (gives 4 ways to connect the operators). + */ +#define OPL3_REG_FEEDBACK_CONNECTION 0xc0 +#define OPL3_FEEDBACK_MASK 0x0e /* Valid just for 1st OP of a voice */ +#define OPL3_CONNECTION_BIT 0x01 +/* + * In the 4 OP mode there is four possible configurations how the + * operators can be connected together (in 2 OP modes there is just + * AM or FM). The 4 OP connection mode is defined by the rightmost + * bit of the FEEDBACK_CONNECTION (0xC0-0xC8) on the both halves. + * + * First half Second half Mode + * + * +---+ + * v | + * 0 0 >+-1-+--2--3--4--> + * + * + * + * +---+ + * | | + * 0 1 >+-1-+--2-+ + * |-> + * >--3----4-+ + * + * +---+ + * | | + * 1 0 >+-1-+-----+ + * |-> + * >--2--3--4-+ + * + * +---+ + * | | + * 1 1 >+-1-+--+ + * | + * >--2--3-+-> + * | + * >--4----+ + */ +#define OPL3_STEREO_BITS 0x30 /* OPL-3 only */ +#define OPL3_VOICE_TO_LEFT 0x10 +#define OPL3_VOICE_TO_RIGHT 0x20 + +/* + + */ + +#define OPL3_LEFT 0x0000 +#define OPL3_RIGHT 0x0100 + +#define OPL3_HW_AUTO 0x0000 +#define OPL3_HW_OPL2 0x0200 +#define OPL3_HW_OPL3 0x0300 +#define OPL3_HW_OPL3_SV 0x0301 /* S3 SonicVibes */ +#define OPL3_HW_OPL3_CS 0x0302 /* CS4232/CS4236+ */ +#define OPL3_HW_OPL3_FM801 0x0303 /* FM801 */ +#define OPL3_HW_OPL3_CS4281 0x0304 /* CS4281 */ +#define OPL3_HW_OPL4 0x0400 /* YMF278B/YMF295 */ +#define OPL3_HW_OPL4_ML 0x0401 /* YMF704/YMF721 */ +#define OPL3_HW_MASK 0xff00 + +#define MAX_OPL2_VOICES 9 +#define MAX_OPL3_VOICES 18 + +struct snd_opl3; + +/* + * Instrument record, aka "Patch" + */ + +/* FM operator */ +struct fm_operator { + unsigned char am_vib; + unsigned char ksl_level; + unsigned char attack_decay; + unsigned char sustain_release; + unsigned char wave_select; +} __attribute__((packed)); + +/* Instrument data */ +struct fm_instrument { + struct fm_operator op[4]; + unsigned char feedback_connection[2]; + unsigned char echo_delay; + unsigned char echo_atten; + unsigned char chorus_spread; + unsigned char trnsps; + unsigned char fix_dur; + unsigned char modes; + unsigned char fix_key; +}; + +/* type */ +#define FM_PATCH_OPL2 0x01 /* OPL2 2 operators FM instrument */ +#define FM_PATCH_OPL3 0x02 /* OPL3 4 operators FM instrument */ + +/* Instrument record */ +struct fm_patch { + unsigned char prog; + unsigned char bank; + unsigned char type; + struct fm_instrument inst; + char name[24]; + struct fm_patch *next; +}; + + +/* + * A structure to keep track of each hardware voice + */ +struct snd_opl3_voice { + int state; /* status */ +#define SNDRV_OPL3_ST_OFF 0 /* Not playing */ +#define SNDRV_OPL3_ST_ON_2OP 1 /* 2op voice is allocated */ +#define SNDRV_OPL3_ST_ON_4OP 2 /* 4op voice is allocated */ +#define SNDRV_OPL3_ST_NOT_AVAIL -1 /* voice is not available */ + + unsigned int time; /* An allocation time */ + unsigned char note; /* Note currently assigned to this voice */ + + unsigned long note_off; /* note-off time */ + int note_off_check; /* check note-off time */ + + unsigned char keyon_reg; /* KON register shadow */ + + struct snd_midi_channel *chan; /* Midi channel for this note */ +}; + +struct snd_opl3 { + unsigned long l_port; + unsigned long r_port; + struct resource *res_l_port; + struct resource *res_r_port; + unsigned short hardware; + /* hardware access */ + void (*command) (struct snd_opl3 * opl3, unsigned short cmd, unsigned char val); + unsigned short timer_enable; + int seq_dev_num; /* sequencer device number */ + struct snd_timer *timer1; + struct snd_timer *timer2; + spinlock_t timer_lock; + + void *private_data; + void (*private_free)(struct snd_opl3 *); + + struct snd_hwdep *hwdep; + spinlock_t reg_lock; + struct snd_card *card; /* The card that this belongs to */ + unsigned char fm_mode; /* OPL mode, see SNDRV_DM_FM_MODE_XXX */ + unsigned char rhythm; /* percussion mode flag */ + unsigned char max_voices; /* max number of voices */ +#if IS_ENABLED(CONFIG_SND_SEQUENCER) +#define SNDRV_OPL3_MODE_SYNTH 0 /* OSS - voices allocated by application */ +#define SNDRV_OPL3_MODE_SEQ 1 /* ALSA - driver handles voice allocation */ + int synth_mode; /* synth mode */ + int seq_client; + + struct snd_seq_device *seq_dev; /* sequencer device */ + struct snd_midi_channel_set * chset; + +#if IS_ENABLED(CONFIG_SND_SEQUENCER_OSS) + struct snd_seq_device *oss_seq_dev; /* OSS sequencer device */ + struct snd_midi_channel_set * oss_chset; +#endif + +#define OPL3_PATCH_HASH_SIZE 32 + struct fm_patch *patch_table[OPL3_PATCH_HASH_SIZE]; + + struct snd_opl3_voice voices[MAX_OPL3_VOICES]; /* Voices (OPL3 'channel') */ + int use_time; /* allocation counter */ + + unsigned short connection_reg; /* connection reg shadow */ + unsigned char drum_reg; /* percussion reg shadow */ + + spinlock_t voice_lock; /* Lock for voice access */ + + struct timer_list tlist; /* timer for note-offs and effects */ + int sys_timer_status; /* system timer run status */ + spinlock_t sys_timer_lock; /* Lock for system timer access */ +#endif +}; + +/* opl3.c */ +void snd_opl3_interrupt(struct snd_hwdep * hw); +int snd_opl3_new(struct snd_card *card, unsigned short hardware, + struct snd_opl3 **ropl3); +int snd_opl3_init(struct snd_opl3 *opl3); +int snd_opl3_create(struct snd_card *card, + unsigned long l_port, unsigned long r_port, + unsigned short hardware, + int integrated, + struct snd_opl3 ** opl3); +int snd_opl3_timer_new(struct snd_opl3 * opl3, int timer1_dev, int timer2_dev); +int snd_opl3_hwdep_new(struct snd_opl3 * opl3, int device, int seq_device, + struct snd_hwdep ** rhwdep); + +/* opl3_synth */ +int snd_opl3_open(struct snd_hwdep * hw, struct file *file); +int snd_opl3_ioctl(struct snd_hwdep * hw, struct file *file, + unsigned int cmd, unsigned long arg); +int snd_opl3_release(struct snd_hwdep * hw, struct file *file); + +void snd_opl3_reset(struct snd_opl3 * opl3); + +#if IS_ENABLED(CONFIG_SND_SEQUENCER) +long snd_opl3_write(struct snd_hwdep *hw, const char __user *buf, long count, + loff_t *offset); +int snd_opl3_load_patch(struct snd_opl3 *opl3, + int prog, int bank, int type, + const char *name, + const unsigned char *ext, + const unsigned char *data); +struct fm_patch *snd_opl3_find_patch(struct snd_opl3 *opl3, int prog, int bank, + int create_patch); +void snd_opl3_clear_patches(struct snd_opl3 *opl3); +#else +#define snd_opl3_write NULL +static inline void snd_opl3_clear_patches(struct snd_opl3 *opl3) {} +#endif + +#endif /* __SOUND_OPL3_H */ diff --git a/include/sound/opl4.h b/include/sound/opl4.h new file mode 100644 index 000000000..9f337148c --- /dev/null +++ b/include/sound/opl4.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_OPL4_H +#define __SOUND_OPL4_H + +/* + * Global definitions for the OPL4 driver + * Copyright (c) 2003 by Clemens Ladisch <clemens@ladisch.de> + */ + +#include <sound/opl3.h> + +struct snd_opl4; + +extern int snd_opl4_create(struct snd_card *card, + unsigned long fm_port, unsigned long pcm_port, + int seq_device, + struct snd_opl3 **opl3, struct snd_opl4 **opl4); + +#endif /* __SOUND_OPL4_H */ diff --git a/include/sound/pcm-indirect.h b/include/sound/pcm-indirect.h new file mode 100644 index 000000000..04127686e --- /dev/null +++ b/include/sound/pcm-indirect.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Helper functions for indirect PCM data transfer + * + * Copyright (c) by Takashi Iwai <tiwai@suse.de> + * Jaroslav Kysela <perex@perex.cz> + */ + +#ifndef __SOUND_PCM_INDIRECT_H +#define __SOUND_PCM_INDIRECT_H + +#include <sound/pcm.h> + +struct snd_pcm_indirect { + unsigned int hw_buffer_size; /* Byte size of hardware buffer */ + unsigned int hw_queue_size; /* Max queue size of hw buffer (0 = buffer size) */ + unsigned int hw_data; /* Offset to next dst (or src) in hw ring buffer */ + unsigned int hw_io; /* Ring buffer hw pointer */ + int hw_ready; /* Bytes ready for play (or captured) in hw ring buffer */ + unsigned int sw_buffer_size; /* Byte size of software buffer */ + unsigned int sw_data; /* Offset to next dst (or src) in sw ring buffer */ + unsigned int sw_io; /* Current software pointer in bytes */ + int sw_ready; /* Bytes ready to be transferred to/from hw */ + snd_pcm_uframes_t appl_ptr; /* Last seen appl_ptr */ +}; + +typedef void (*snd_pcm_indirect_copy_t)(struct snd_pcm_substream *substream, + struct snd_pcm_indirect *rec, size_t bytes); + +/* + * helper function for playback ack callback + */ +static inline int +snd_pcm_indirect_playback_transfer(struct snd_pcm_substream *substream, + struct snd_pcm_indirect *rec, + snd_pcm_indirect_copy_t copy) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + snd_pcm_uframes_t appl_ptr = runtime->control->appl_ptr; + snd_pcm_sframes_t diff = appl_ptr - rec->appl_ptr; + int qsize; + + if (diff) { + if (diff < -(snd_pcm_sframes_t) (runtime->boundary / 2)) + diff += runtime->boundary; + if (diff < 0) + return -EINVAL; + rec->sw_ready += (int)frames_to_bytes(runtime, diff); + rec->appl_ptr = appl_ptr; + } + qsize = rec->hw_queue_size ? rec->hw_queue_size : rec->hw_buffer_size; + while (rec->hw_ready < qsize && rec->sw_ready > 0) { + unsigned int hw_to_end = rec->hw_buffer_size - rec->hw_data; + unsigned int sw_to_end = rec->sw_buffer_size - rec->sw_data; + unsigned int bytes = qsize - rec->hw_ready; + if (rec->sw_ready < (int)bytes) + bytes = rec->sw_ready; + if (hw_to_end < bytes) + bytes = hw_to_end; + if (sw_to_end < bytes) + bytes = sw_to_end; + if (! bytes) + break; + copy(substream, rec, bytes); + rec->hw_data += bytes; + if (rec->hw_data == rec->hw_buffer_size) + rec->hw_data = 0; + rec->sw_data += bytes; + if (rec->sw_data == rec->sw_buffer_size) + rec->sw_data = 0; + rec->hw_ready += bytes; + rec->sw_ready -= bytes; + } + return 0; +} + +/* + * helper function for playback pointer callback + * ptr = current byte pointer + */ +static inline snd_pcm_uframes_t +snd_pcm_indirect_playback_pointer(struct snd_pcm_substream *substream, + struct snd_pcm_indirect *rec, unsigned int ptr) +{ + int bytes = ptr - rec->hw_io; + if (bytes < 0) + bytes += rec->hw_buffer_size; + rec->hw_io = ptr; + rec->hw_ready -= bytes; + rec->sw_io += bytes; + if (rec->sw_io >= rec->sw_buffer_size) + rec->sw_io -= rec->sw_buffer_size; + if (substream->ops->ack) + substream->ops->ack(substream); + return bytes_to_frames(substream->runtime, rec->sw_io); +} + + +/* + * helper function for capture ack callback + */ +static inline int +snd_pcm_indirect_capture_transfer(struct snd_pcm_substream *substream, + struct snd_pcm_indirect *rec, + snd_pcm_indirect_copy_t copy) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + snd_pcm_uframes_t appl_ptr = runtime->control->appl_ptr; + snd_pcm_sframes_t diff = appl_ptr - rec->appl_ptr; + + if (diff) { + if (diff < -(snd_pcm_sframes_t) (runtime->boundary / 2)) + diff += runtime->boundary; + if (diff < 0) + return -EINVAL; + rec->sw_ready -= frames_to_bytes(runtime, diff); + rec->appl_ptr = appl_ptr; + } + while (rec->hw_ready > 0 && + rec->sw_ready < (int)rec->sw_buffer_size) { + size_t hw_to_end = rec->hw_buffer_size - rec->hw_data; + size_t sw_to_end = rec->sw_buffer_size - rec->sw_data; + size_t bytes = rec->sw_buffer_size - rec->sw_ready; + if (rec->hw_ready < (int)bytes) + bytes = rec->hw_ready; + if (hw_to_end < bytes) + bytes = hw_to_end; + if (sw_to_end < bytes) + bytes = sw_to_end; + if (! bytes) + break; + copy(substream, rec, bytes); + rec->hw_data += bytes; + if ((int)rec->hw_data == rec->hw_buffer_size) + rec->hw_data = 0; + rec->sw_data += bytes; + if (rec->sw_data == rec->sw_buffer_size) + rec->sw_data = 0; + rec->hw_ready -= bytes; + rec->sw_ready += bytes; + } + return 0; +} + +/* + * helper function for capture pointer callback, + * ptr = current byte pointer + */ +static inline snd_pcm_uframes_t +snd_pcm_indirect_capture_pointer(struct snd_pcm_substream *substream, + struct snd_pcm_indirect *rec, unsigned int ptr) +{ + int qsize; + int bytes = ptr - rec->hw_io; + if (bytes < 0) + bytes += rec->hw_buffer_size; + rec->hw_io = ptr; + rec->hw_ready += bytes; + qsize = rec->hw_queue_size ? rec->hw_queue_size : rec->hw_buffer_size; + if (rec->hw_ready > qsize) + return SNDRV_PCM_POS_XRUN; + rec->sw_io += bytes; + if (rec->sw_io >= rec->sw_buffer_size) + rec->sw_io -= rec->sw_buffer_size; + if (substream->ops->ack) + substream->ops->ack(substream); + return bytes_to_frames(substream->runtime, rec->sw_io); +} + +#endif /* __SOUND_PCM_INDIRECT_H */ diff --git a/include/sound/pcm.h b/include/sound/pcm.h new file mode 100644 index 000000000..27040b472 --- /dev/null +++ b/include/sound/pcm.h @@ -0,0 +1,1610 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_PCM_H +#define __SOUND_PCM_H + +/* + * Digital Audio (PCM) abstract layer + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + * Abramo Bagnara <abramo@alsa-project.org> + */ + +#include <sound/asound.h> +#include <sound/memalloc.h> +#include <sound/minors.h> +#include <linux/poll.h> +#include <linux/mm.h> +#include <linux/bitops.h> +#include <linux/pm_qos.h> +#include <linux/refcount.h> + +#define snd_pcm_substream_chip(substream) ((substream)->private_data) +#define snd_pcm_chip(pcm) ((pcm)->private_data) + +#if IS_ENABLED(CONFIG_SND_PCM_OSS) +#include <sound/pcm_oss.h> +#endif + +/* + * Hardware (lowlevel) section + */ + +struct snd_pcm_hardware { + unsigned int info; /* SNDRV_PCM_INFO_* */ + u64 formats; /* SNDRV_PCM_FMTBIT_* */ + unsigned int rates; /* SNDRV_PCM_RATE_* */ + unsigned int rate_min; /* min rate */ + unsigned int rate_max; /* max rate */ + unsigned int channels_min; /* min channels */ + unsigned int channels_max; /* max channels */ + size_t buffer_bytes_max; /* max buffer size */ + size_t period_bytes_min; /* min period size */ + size_t period_bytes_max; /* max period size */ + unsigned int periods_min; /* min # of periods */ + unsigned int periods_max; /* max # of periods */ + size_t fifo_size; /* fifo size in bytes */ +}; + +struct snd_pcm_status64; +struct snd_pcm_substream; + +struct snd_pcm_audio_tstamp_config; /* definitions further down */ +struct snd_pcm_audio_tstamp_report; + +struct snd_pcm_ops { + int (*open)(struct snd_pcm_substream *substream); + int (*close)(struct snd_pcm_substream *substream); + int (*ioctl)(struct snd_pcm_substream * substream, + unsigned int cmd, void *arg); + int (*hw_params)(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); + int (*hw_free)(struct snd_pcm_substream *substream); + int (*prepare)(struct snd_pcm_substream *substream); + int (*trigger)(struct snd_pcm_substream *substream, int cmd); + int (*sync_stop)(struct snd_pcm_substream *substream); + snd_pcm_uframes_t (*pointer)(struct snd_pcm_substream *substream); + int (*get_time_info)(struct snd_pcm_substream *substream, + struct timespec64 *system_ts, struct timespec64 *audio_ts, + struct snd_pcm_audio_tstamp_config *audio_tstamp_config, + struct snd_pcm_audio_tstamp_report *audio_tstamp_report); + int (*fill_silence)(struct snd_pcm_substream *substream, int channel, + unsigned long pos, unsigned long bytes); + int (*copy_user)(struct snd_pcm_substream *substream, int channel, + unsigned long pos, void __user *buf, + unsigned long bytes); + int (*copy_kernel)(struct snd_pcm_substream *substream, int channel, + unsigned long pos, void *buf, unsigned long bytes); + struct page *(*page)(struct snd_pcm_substream *substream, + unsigned long offset); + int (*mmap)(struct snd_pcm_substream *substream, struct vm_area_struct *vma); + int (*ack)(struct snd_pcm_substream *substream); +}; + +/* + * + */ + +#if defined(CONFIG_SND_DYNAMIC_MINORS) +#define SNDRV_PCM_DEVICES (SNDRV_OS_MINORS-2) +#else +#define SNDRV_PCM_DEVICES 8 +#endif + +#define SNDRV_PCM_IOCTL1_RESET 0 +/* 1 is absent slot. */ +#define SNDRV_PCM_IOCTL1_CHANNEL_INFO 2 +/* 3 is absent slot. */ +#define SNDRV_PCM_IOCTL1_FIFO_SIZE 4 + +#define SNDRV_PCM_TRIGGER_STOP 0 +#define SNDRV_PCM_TRIGGER_START 1 +#define SNDRV_PCM_TRIGGER_PAUSE_PUSH 3 +#define SNDRV_PCM_TRIGGER_PAUSE_RELEASE 4 +#define SNDRV_PCM_TRIGGER_SUSPEND 5 +#define SNDRV_PCM_TRIGGER_RESUME 6 +#define SNDRV_PCM_TRIGGER_DRAIN 7 + +#define SNDRV_PCM_POS_XRUN ((snd_pcm_uframes_t)-1) + +/* If you change this don't forget to change rates[] table in pcm_native.c */ +#define SNDRV_PCM_RATE_5512 (1U<<0) /* 5512Hz */ +#define SNDRV_PCM_RATE_8000 (1U<<1) /* 8000Hz */ +#define SNDRV_PCM_RATE_11025 (1U<<2) /* 11025Hz */ +#define SNDRV_PCM_RATE_16000 (1U<<3) /* 16000Hz */ +#define SNDRV_PCM_RATE_22050 (1U<<4) /* 22050Hz */ +#define SNDRV_PCM_RATE_32000 (1U<<5) /* 32000Hz */ +#define SNDRV_PCM_RATE_44100 (1U<<6) /* 44100Hz */ +#define SNDRV_PCM_RATE_48000 (1U<<7) /* 48000Hz */ +#define SNDRV_PCM_RATE_64000 (1U<<8) /* 64000Hz */ +#define SNDRV_PCM_RATE_88200 (1U<<9) /* 88200Hz */ +#define SNDRV_PCM_RATE_96000 (1U<<10) /* 96000Hz */ +#define SNDRV_PCM_RATE_176400 (1U<<11) /* 176400Hz */ +#define SNDRV_PCM_RATE_192000 (1U<<12) /* 192000Hz */ +#define SNDRV_PCM_RATE_352800 (1U<<13) /* 352800Hz */ +#define SNDRV_PCM_RATE_384000 (1U<<14) /* 384000Hz */ + +#define SNDRV_PCM_RATE_CONTINUOUS (1U<<30) /* continuous range */ +#define SNDRV_PCM_RATE_KNOT (1U<<31) /* supports more non-continuos rates */ + +#define SNDRV_PCM_RATE_8000_44100 (SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_11025|\ + SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_22050|\ + SNDRV_PCM_RATE_32000|SNDRV_PCM_RATE_44100) +#define SNDRV_PCM_RATE_8000_48000 (SNDRV_PCM_RATE_8000_44100|SNDRV_PCM_RATE_48000) +#define SNDRV_PCM_RATE_8000_96000 (SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_64000|\ + SNDRV_PCM_RATE_88200|SNDRV_PCM_RATE_96000) +#define SNDRV_PCM_RATE_8000_192000 (SNDRV_PCM_RATE_8000_96000|SNDRV_PCM_RATE_176400|\ + SNDRV_PCM_RATE_192000) +#define SNDRV_PCM_RATE_8000_384000 (SNDRV_PCM_RATE_8000_192000|\ + SNDRV_PCM_RATE_352800|\ + SNDRV_PCM_RATE_384000) +#define _SNDRV_PCM_FMTBIT(fmt) (1ULL << (__force int)SNDRV_PCM_FORMAT_##fmt) +#define SNDRV_PCM_FMTBIT_S8 _SNDRV_PCM_FMTBIT(S8) +#define SNDRV_PCM_FMTBIT_U8 _SNDRV_PCM_FMTBIT(U8) +#define SNDRV_PCM_FMTBIT_S16_LE _SNDRV_PCM_FMTBIT(S16_LE) +#define SNDRV_PCM_FMTBIT_S16_BE _SNDRV_PCM_FMTBIT(S16_BE) +#define SNDRV_PCM_FMTBIT_U16_LE _SNDRV_PCM_FMTBIT(U16_LE) +#define SNDRV_PCM_FMTBIT_U16_BE _SNDRV_PCM_FMTBIT(U16_BE) +#define SNDRV_PCM_FMTBIT_S24_LE _SNDRV_PCM_FMTBIT(S24_LE) +#define SNDRV_PCM_FMTBIT_S24_BE _SNDRV_PCM_FMTBIT(S24_BE) +#define SNDRV_PCM_FMTBIT_U24_LE _SNDRV_PCM_FMTBIT(U24_LE) +#define SNDRV_PCM_FMTBIT_U24_BE _SNDRV_PCM_FMTBIT(U24_BE) +// For S32/U32 formats, 'msbits' hardware parameter is often used to deliver information about the +// available bit count in most significant bit. It's for the case of so-called 'left-justified' or +// `right-padding` sample which has less width than 32 bit. +#define SNDRV_PCM_FMTBIT_S32_LE _SNDRV_PCM_FMTBIT(S32_LE) +#define SNDRV_PCM_FMTBIT_S32_BE _SNDRV_PCM_FMTBIT(S32_BE) +#define SNDRV_PCM_FMTBIT_U32_LE _SNDRV_PCM_FMTBIT(U32_LE) +#define SNDRV_PCM_FMTBIT_U32_BE _SNDRV_PCM_FMTBIT(U32_BE) +#define SNDRV_PCM_FMTBIT_FLOAT_LE _SNDRV_PCM_FMTBIT(FLOAT_LE) +#define SNDRV_PCM_FMTBIT_FLOAT_BE _SNDRV_PCM_FMTBIT(FLOAT_BE) +#define SNDRV_PCM_FMTBIT_FLOAT64_LE _SNDRV_PCM_FMTBIT(FLOAT64_LE) +#define SNDRV_PCM_FMTBIT_FLOAT64_BE _SNDRV_PCM_FMTBIT(FLOAT64_BE) +#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE _SNDRV_PCM_FMTBIT(IEC958_SUBFRAME_LE) +#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE _SNDRV_PCM_FMTBIT(IEC958_SUBFRAME_BE) +#define SNDRV_PCM_FMTBIT_MU_LAW _SNDRV_PCM_FMTBIT(MU_LAW) +#define SNDRV_PCM_FMTBIT_A_LAW _SNDRV_PCM_FMTBIT(A_LAW) +#define SNDRV_PCM_FMTBIT_IMA_ADPCM _SNDRV_PCM_FMTBIT(IMA_ADPCM) +#define SNDRV_PCM_FMTBIT_MPEG _SNDRV_PCM_FMTBIT(MPEG) +#define SNDRV_PCM_FMTBIT_GSM _SNDRV_PCM_FMTBIT(GSM) +#define SNDRV_PCM_FMTBIT_S20_LE _SNDRV_PCM_FMTBIT(S20_LE) +#define SNDRV_PCM_FMTBIT_U20_LE _SNDRV_PCM_FMTBIT(U20_LE) +#define SNDRV_PCM_FMTBIT_S20_BE _SNDRV_PCM_FMTBIT(S20_BE) +#define SNDRV_PCM_FMTBIT_U20_BE _SNDRV_PCM_FMTBIT(U20_BE) +#define SNDRV_PCM_FMTBIT_SPECIAL _SNDRV_PCM_FMTBIT(SPECIAL) +#define SNDRV_PCM_FMTBIT_S24_3LE _SNDRV_PCM_FMTBIT(S24_3LE) +#define SNDRV_PCM_FMTBIT_U24_3LE _SNDRV_PCM_FMTBIT(U24_3LE) +#define SNDRV_PCM_FMTBIT_S24_3BE _SNDRV_PCM_FMTBIT(S24_3BE) +#define SNDRV_PCM_FMTBIT_U24_3BE _SNDRV_PCM_FMTBIT(U24_3BE) +#define SNDRV_PCM_FMTBIT_S20_3LE _SNDRV_PCM_FMTBIT(S20_3LE) +#define SNDRV_PCM_FMTBIT_U20_3LE _SNDRV_PCM_FMTBIT(U20_3LE) +#define SNDRV_PCM_FMTBIT_S20_3BE _SNDRV_PCM_FMTBIT(S20_3BE) +#define SNDRV_PCM_FMTBIT_U20_3BE _SNDRV_PCM_FMTBIT(U20_3BE) +#define SNDRV_PCM_FMTBIT_S18_3LE _SNDRV_PCM_FMTBIT(S18_3LE) +#define SNDRV_PCM_FMTBIT_U18_3LE _SNDRV_PCM_FMTBIT(U18_3LE) +#define SNDRV_PCM_FMTBIT_S18_3BE _SNDRV_PCM_FMTBIT(S18_3BE) +#define SNDRV_PCM_FMTBIT_U18_3BE _SNDRV_PCM_FMTBIT(U18_3BE) +#define SNDRV_PCM_FMTBIT_G723_24 _SNDRV_PCM_FMTBIT(G723_24) +#define SNDRV_PCM_FMTBIT_G723_24_1B _SNDRV_PCM_FMTBIT(G723_24_1B) +#define SNDRV_PCM_FMTBIT_G723_40 _SNDRV_PCM_FMTBIT(G723_40) +#define SNDRV_PCM_FMTBIT_G723_40_1B _SNDRV_PCM_FMTBIT(G723_40_1B) +#define SNDRV_PCM_FMTBIT_DSD_U8 _SNDRV_PCM_FMTBIT(DSD_U8) +#define SNDRV_PCM_FMTBIT_DSD_U16_LE _SNDRV_PCM_FMTBIT(DSD_U16_LE) +#define SNDRV_PCM_FMTBIT_DSD_U32_LE _SNDRV_PCM_FMTBIT(DSD_U32_LE) +#define SNDRV_PCM_FMTBIT_DSD_U16_BE _SNDRV_PCM_FMTBIT(DSD_U16_BE) +#define SNDRV_PCM_FMTBIT_DSD_U32_BE _SNDRV_PCM_FMTBIT(DSD_U32_BE) + +#ifdef SNDRV_LITTLE_ENDIAN +#define SNDRV_PCM_FMTBIT_S16 SNDRV_PCM_FMTBIT_S16_LE +#define SNDRV_PCM_FMTBIT_U16 SNDRV_PCM_FMTBIT_U16_LE +#define SNDRV_PCM_FMTBIT_S24 SNDRV_PCM_FMTBIT_S24_LE +#define SNDRV_PCM_FMTBIT_U24 SNDRV_PCM_FMTBIT_U24_LE +#define SNDRV_PCM_FMTBIT_S32 SNDRV_PCM_FMTBIT_S32_LE +#define SNDRV_PCM_FMTBIT_U32 SNDRV_PCM_FMTBIT_U32_LE +#define SNDRV_PCM_FMTBIT_FLOAT SNDRV_PCM_FMTBIT_FLOAT_LE +#define SNDRV_PCM_FMTBIT_FLOAT64 SNDRV_PCM_FMTBIT_FLOAT64_LE +#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE +#define SNDRV_PCM_FMTBIT_S20 SNDRV_PCM_FMTBIT_S20_LE +#define SNDRV_PCM_FMTBIT_U20 SNDRV_PCM_FMTBIT_U20_LE +#endif +#ifdef SNDRV_BIG_ENDIAN +#define SNDRV_PCM_FMTBIT_S16 SNDRV_PCM_FMTBIT_S16_BE +#define SNDRV_PCM_FMTBIT_U16 SNDRV_PCM_FMTBIT_U16_BE +#define SNDRV_PCM_FMTBIT_S24 SNDRV_PCM_FMTBIT_S24_BE +#define SNDRV_PCM_FMTBIT_U24 SNDRV_PCM_FMTBIT_U24_BE +#define SNDRV_PCM_FMTBIT_S32 SNDRV_PCM_FMTBIT_S32_BE +#define SNDRV_PCM_FMTBIT_U32 SNDRV_PCM_FMTBIT_U32_BE +#define SNDRV_PCM_FMTBIT_FLOAT SNDRV_PCM_FMTBIT_FLOAT_BE +#define SNDRV_PCM_FMTBIT_FLOAT64 SNDRV_PCM_FMTBIT_FLOAT64_BE +#define SNDRV_PCM_FMTBIT_IEC958_SUBFRAME SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE +#define SNDRV_PCM_FMTBIT_S20 SNDRV_PCM_FMTBIT_S20_BE +#define SNDRV_PCM_FMTBIT_U20 SNDRV_PCM_FMTBIT_U20_BE +#endif + +struct snd_pcm_file { + struct snd_pcm_substream *substream; + int no_compat_mmap; + unsigned int user_pversion; /* supported protocol version */ +}; + +struct snd_pcm_hw_rule; +typedef int (*snd_pcm_hw_rule_func_t)(struct snd_pcm_hw_params *params, + struct snd_pcm_hw_rule *rule); + +struct snd_pcm_hw_rule { + unsigned int cond; + int var; + int deps[5]; + + snd_pcm_hw_rule_func_t func; + void *private; +}; + +struct snd_pcm_hw_constraints { + struct snd_mask masks[SNDRV_PCM_HW_PARAM_LAST_MASK - + SNDRV_PCM_HW_PARAM_FIRST_MASK + 1]; + struct snd_interval intervals[SNDRV_PCM_HW_PARAM_LAST_INTERVAL - + SNDRV_PCM_HW_PARAM_FIRST_INTERVAL + 1]; + unsigned int rules_num; + unsigned int rules_all; + struct snd_pcm_hw_rule *rules; +}; + +static inline struct snd_mask *constrs_mask(struct snd_pcm_hw_constraints *constrs, + snd_pcm_hw_param_t var) +{ + return &constrs->masks[var - SNDRV_PCM_HW_PARAM_FIRST_MASK]; +} + +static inline struct snd_interval *constrs_interval(struct snd_pcm_hw_constraints *constrs, + snd_pcm_hw_param_t var) +{ + return &constrs->intervals[var - SNDRV_PCM_HW_PARAM_FIRST_INTERVAL]; +} + +struct snd_ratnum { + unsigned int num; + unsigned int den_min, den_max, den_step; +}; + +struct snd_ratden { + unsigned int num_min, num_max, num_step; + unsigned int den; +}; + +struct snd_pcm_hw_constraint_ratnums { + int nrats; + const struct snd_ratnum *rats; +}; + +struct snd_pcm_hw_constraint_ratdens { + int nrats; + const struct snd_ratden *rats; +}; + +struct snd_pcm_hw_constraint_list { + const unsigned int *list; + unsigned int count; + unsigned int mask; +}; + +struct snd_pcm_hw_constraint_ranges { + unsigned int count; + const struct snd_interval *ranges; + unsigned int mask; +}; + +/* + * userspace-provided audio timestamp config to kernel, + * structure is for internal use only and filled with dedicated unpack routine + */ +struct snd_pcm_audio_tstamp_config { + /* 5 of max 16 bits used */ + u32 type_requested:4; + u32 report_delay:1; /* add total delay to A/D or D/A */ +}; + +static inline void snd_pcm_unpack_audio_tstamp_config(__u32 data, + struct snd_pcm_audio_tstamp_config *config) +{ + config->type_requested = data & 0xF; + config->report_delay = (data >> 4) & 1; +} + +/* + * kernel-provided audio timestamp report to user-space + * structure is for internal use only and read by dedicated pack routine + */ +struct snd_pcm_audio_tstamp_report { + /* 6 of max 16 bits used for bit-fields */ + + /* for backwards compatibility */ + u32 valid:1; + + /* actual type if hardware could not support requested timestamp */ + u32 actual_type:4; + + /* accuracy represented in ns units */ + u32 accuracy_report:1; /* 0 if accuracy unknown, 1 if accuracy field is valid */ + u32 accuracy; /* up to 4.29s, will be packed in separate field */ +}; + +static inline void snd_pcm_pack_audio_tstamp_report(__u32 *data, __u32 *accuracy, + const struct snd_pcm_audio_tstamp_report *report) +{ + u32 tmp; + + tmp = report->accuracy_report; + tmp <<= 4; + tmp |= report->actual_type; + tmp <<= 1; + tmp |= report->valid; + + *data &= 0xffff; /* zero-clear MSBs */ + *data |= (tmp << 16); + *accuracy = report->accuracy; +} + + +struct snd_pcm_runtime { + /* -- Status -- */ + snd_pcm_state_t state; /* stream state */ + snd_pcm_state_t suspended_state; /* suspended stream state */ + struct snd_pcm_substream *trigger_master; + struct timespec64 trigger_tstamp; /* trigger timestamp */ + bool trigger_tstamp_latched; /* trigger timestamp latched in low-level driver/hardware */ + int overrange; + snd_pcm_uframes_t avail_max; + snd_pcm_uframes_t hw_ptr_base; /* Position at buffer restart */ + snd_pcm_uframes_t hw_ptr_interrupt; /* Position at interrupt time */ + unsigned long hw_ptr_jiffies; /* Time when hw_ptr is updated */ + unsigned long hw_ptr_buffer_jiffies; /* buffer time in jiffies */ + snd_pcm_sframes_t delay; /* extra delay; typically FIFO size */ + u64 hw_ptr_wrap; /* offset for hw_ptr due to boundary wrap-around */ + + /* -- HW params -- */ + snd_pcm_access_t access; /* access mode */ + snd_pcm_format_t format; /* SNDRV_PCM_FORMAT_* */ + snd_pcm_subformat_t subformat; /* subformat */ + unsigned int rate; /* rate in Hz */ + unsigned int channels; /* channels */ + snd_pcm_uframes_t period_size; /* period size */ + unsigned int periods; /* periods */ + snd_pcm_uframes_t buffer_size; /* buffer size */ + snd_pcm_uframes_t min_align; /* Min alignment for the format */ + size_t byte_align; + unsigned int frame_bits; + unsigned int sample_bits; + unsigned int info; + unsigned int rate_num; + unsigned int rate_den; + unsigned int no_period_wakeup: 1; + + /* -- SW params -- */ + int tstamp_mode; /* mmap timestamp is updated */ + unsigned int period_step; + snd_pcm_uframes_t start_threshold; + snd_pcm_uframes_t stop_threshold; + snd_pcm_uframes_t silence_threshold; /* Silence filling happens when + noise is nearest than this */ + snd_pcm_uframes_t silence_size; /* Silence filling size */ + snd_pcm_uframes_t boundary; /* pointers wrap point */ + + snd_pcm_uframes_t silence_start; /* starting pointer to silence area */ + snd_pcm_uframes_t silence_filled; /* size filled with silence */ + + union snd_pcm_sync_id sync; /* hardware synchronization ID */ + + /* -- mmap -- */ + struct snd_pcm_mmap_status *status; + struct snd_pcm_mmap_control *control; + + /* -- locking / scheduling -- */ + snd_pcm_uframes_t twake; /* do transfer (!poll) wakeup if non-zero */ + wait_queue_head_t sleep; /* poll sleep */ + wait_queue_head_t tsleep; /* transfer sleep */ + struct snd_fasync *fasync; + bool stop_operating; /* sync_stop will be called */ + struct mutex buffer_mutex; /* protect for buffer changes */ + atomic_t buffer_accessing; /* >0: in r/w operation, <0: blocked */ + + /* -- private section -- */ + void *private_data; + void (*private_free)(struct snd_pcm_runtime *runtime); + + /* -- hardware description -- */ + struct snd_pcm_hardware hw; + struct snd_pcm_hw_constraints hw_constraints; + + /* -- timer -- */ + unsigned int timer_resolution; /* timer resolution */ + int tstamp_type; /* timestamp type */ + + /* -- DMA -- */ + unsigned char *dma_area; /* DMA area */ + dma_addr_t dma_addr; /* physical bus address (not accessible from main CPU) */ + size_t dma_bytes; /* size of DMA area */ + + struct snd_dma_buffer *dma_buffer_p; /* allocated buffer */ + unsigned int buffer_changed:1; /* buffer allocation changed; set only in managed mode */ + + /* -- audio timestamp config -- */ + struct snd_pcm_audio_tstamp_config audio_tstamp_config; + struct snd_pcm_audio_tstamp_report audio_tstamp_report; + struct timespec64 driver_tstamp; + +#if IS_ENABLED(CONFIG_SND_PCM_OSS) + /* -- OSS things -- */ + struct snd_pcm_oss_runtime oss; +#endif +}; + +struct snd_pcm_group { /* keep linked substreams */ + spinlock_t lock; + struct mutex mutex; + struct list_head substreams; + refcount_t refs; +}; + +struct pid; + +struct snd_pcm_substream { + struct snd_pcm *pcm; + struct snd_pcm_str *pstr; + void *private_data; /* copied from pcm->private_data */ + int number; + char name[32]; /* substream name */ + int stream; /* stream (direction) */ + struct pm_qos_request latency_pm_qos_req; /* pm_qos request */ + size_t buffer_bytes_max; /* limit ring buffer size */ + struct snd_dma_buffer dma_buffer; + size_t dma_max; + /* -- hardware operations -- */ + const struct snd_pcm_ops *ops; + /* -- runtime information -- */ + struct snd_pcm_runtime *runtime; + /* -- timer section -- */ + struct snd_timer *timer; /* timer */ + unsigned timer_running: 1; /* time is running */ + long wait_time; /* time in ms for R/W to wait for avail */ + /* -- next substream -- */ + struct snd_pcm_substream *next; + /* -- linked substreams -- */ + struct list_head link_list; /* linked list member */ + struct snd_pcm_group self_group; /* fake group for non linked substream (with substream lock inside) */ + struct snd_pcm_group *group; /* pointer to current group */ + /* -- assigned files -- */ + int ref_count; + atomic_t mmap_count; + unsigned int f_flags; + void (*pcm_release)(struct snd_pcm_substream *); + struct pid *pid; +#if IS_ENABLED(CONFIG_SND_PCM_OSS) + /* -- OSS things -- */ + struct snd_pcm_oss_substream oss; +#endif +#ifdef CONFIG_SND_VERBOSE_PROCFS + struct snd_info_entry *proc_root; +#endif /* CONFIG_SND_VERBOSE_PROCFS */ + /* misc flags */ + unsigned int hw_opened: 1; + unsigned int managed_buffer_alloc:1; +}; + +#define SUBSTREAM_BUSY(substream) ((substream)->ref_count > 0) + + +struct snd_pcm_str { + int stream; /* stream (direction) */ + struct snd_pcm *pcm; + /* -- substreams -- */ + unsigned int substream_count; + unsigned int substream_opened; + struct snd_pcm_substream *substream; +#if IS_ENABLED(CONFIG_SND_PCM_OSS) + /* -- OSS things -- */ + struct snd_pcm_oss_stream oss; +#endif +#ifdef CONFIG_SND_VERBOSE_PROCFS + struct snd_info_entry *proc_root; +#ifdef CONFIG_SND_PCM_XRUN_DEBUG + unsigned int xrun_debug; /* 0 = disabled, 1 = verbose, 2 = stacktrace */ +#endif +#endif + struct snd_kcontrol *chmap_kctl; /* channel-mapping controls */ + struct device dev; +}; + +struct snd_pcm { + struct snd_card *card; + struct list_head list; + int device; /* device number */ + unsigned int info_flags; + unsigned short dev_class; + unsigned short dev_subclass; + char id[64]; + char name[80]; + struct snd_pcm_str streams[2]; + struct mutex open_mutex; + wait_queue_head_t open_wait; + void *private_data; + void (*private_free) (struct snd_pcm *pcm); + bool internal; /* pcm is for internal use only */ + bool nonatomic; /* whole PCM operations are in non-atomic context */ + bool no_device_suspend; /* don't invoke device PM suspend */ +#if IS_ENABLED(CONFIG_SND_PCM_OSS) + struct snd_pcm_oss oss; +#endif +}; + +/* + * Registering + */ + +extern const struct file_operations snd_pcm_f_ops[2]; + +int snd_pcm_new(struct snd_card *card, const char *id, int device, + int playback_count, int capture_count, + struct snd_pcm **rpcm); +int snd_pcm_new_internal(struct snd_card *card, const char *id, int device, + int playback_count, int capture_count, + struct snd_pcm **rpcm); +int snd_pcm_new_stream(struct snd_pcm *pcm, int stream, int substream_count); + +#if IS_ENABLED(CONFIG_SND_PCM_OSS) +struct snd_pcm_notify { + int (*n_register) (struct snd_pcm * pcm); + int (*n_disconnect) (struct snd_pcm * pcm); + int (*n_unregister) (struct snd_pcm * pcm); + struct list_head list; +}; +int snd_pcm_notify(struct snd_pcm_notify *notify, int nfree); +#endif + +/* + * Native I/O + */ + +int snd_pcm_info(struct snd_pcm_substream *substream, struct snd_pcm_info *info); +int snd_pcm_info_user(struct snd_pcm_substream *substream, + struct snd_pcm_info __user *info); +int snd_pcm_status64(struct snd_pcm_substream *substream, + struct snd_pcm_status64 *status); +int snd_pcm_start(struct snd_pcm_substream *substream); +int snd_pcm_stop(struct snd_pcm_substream *substream, snd_pcm_state_t status); +int snd_pcm_drain_done(struct snd_pcm_substream *substream); +int snd_pcm_stop_xrun(struct snd_pcm_substream *substream); +#ifdef CONFIG_PM +int snd_pcm_suspend_all(struct snd_pcm *pcm); +#else +static inline int snd_pcm_suspend_all(struct snd_pcm *pcm) +{ + return 0; +} +#endif +int snd_pcm_kernel_ioctl(struct snd_pcm_substream *substream, unsigned int cmd, void *arg); +int snd_pcm_open_substream(struct snd_pcm *pcm, int stream, struct file *file, + struct snd_pcm_substream **rsubstream); +void snd_pcm_release_substream(struct snd_pcm_substream *substream); +int snd_pcm_attach_substream(struct snd_pcm *pcm, int stream, struct file *file, + struct snd_pcm_substream **rsubstream); +void snd_pcm_detach_substream(struct snd_pcm_substream *substream); +int snd_pcm_mmap_data(struct snd_pcm_substream *substream, struct file *file, struct vm_area_struct *area); + + +#ifdef CONFIG_SND_DEBUG +void snd_pcm_debug_name(struct snd_pcm_substream *substream, + char *name, size_t len); +#else +static inline void +snd_pcm_debug_name(struct snd_pcm_substream *substream, char *buf, size_t size) +{ + *buf = 0; +} +#endif + +/* + * PCM library + */ + +/** + * snd_pcm_stream_linked - Check whether the substream is linked with others + * @substream: substream to check + * + * Return: true if the given substream is being linked with others + */ +static inline int snd_pcm_stream_linked(struct snd_pcm_substream *substream) +{ + return substream->group != &substream->self_group; +} + +void snd_pcm_stream_lock(struct snd_pcm_substream *substream); +void snd_pcm_stream_unlock(struct snd_pcm_substream *substream); +void snd_pcm_stream_lock_irq(struct snd_pcm_substream *substream); +void snd_pcm_stream_unlock_irq(struct snd_pcm_substream *substream); +unsigned long _snd_pcm_stream_lock_irqsave(struct snd_pcm_substream *substream); +unsigned long _snd_pcm_stream_lock_irqsave_nested(struct snd_pcm_substream *substream); + +/** + * snd_pcm_stream_lock_irqsave - Lock the PCM stream + * @substream: PCM substream + * @flags: irq flags + * + * This locks the PCM stream like snd_pcm_stream_lock() but with the local + * IRQ (only when nonatomic is false). In nonatomic case, this is identical + * as snd_pcm_stream_lock(). + */ +#define snd_pcm_stream_lock_irqsave(substream, flags) \ + do { \ + typecheck(unsigned long, flags); \ + flags = _snd_pcm_stream_lock_irqsave(substream); \ + } while (0) +void snd_pcm_stream_unlock_irqrestore(struct snd_pcm_substream *substream, + unsigned long flags); + +/** + * snd_pcm_stream_lock_irqsave_nested - Single-nested PCM stream locking + * @substream: PCM substream + * @flags: irq flags + * + * This locks the PCM stream like snd_pcm_stream_lock_irqsave() but with + * the single-depth lockdep subclass. + */ +#define snd_pcm_stream_lock_irqsave_nested(substream, flags) \ + do { \ + typecheck(unsigned long, flags); \ + flags = _snd_pcm_stream_lock_irqsave_nested(substream); \ + } while (0) + +/** + * snd_pcm_group_for_each_entry - iterate over the linked substreams + * @s: the iterator + * @substream: the substream + * + * Iterate over the all linked substreams to the given @substream. + * When @substream isn't linked with any others, this gives returns @substream + * itself once. + */ +#define snd_pcm_group_for_each_entry(s, substream) \ + list_for_each_entry(s, &substream->group->substreams, link_list) + +#define for_each_pcm_streams(stream) \ + for (stream = SNDRV_PCM_STREAM_PLAYBACK; \ + stream <= SNDRV_PCM_STREAM_LAST; \ + stream++) + +/** + * snd_pcm_running - Check whether the substream is in a running state + * @substream: substream to check + * + * Return: true if the given substream is in the state RUNNING, or in the + * state DRAINING for playback. + */ +static inline int snd_pcm_running(struct snd_pcm_substream *substream) +{ + return (substream->runtime->state == SNDRV_PCM_STATE_RUNNING || + (substream->runtime->state == SNDRV_PCM_STATE_DRAINING && + substream->stream == SNDRV_PCM_STREAM_PLAYBACK)); +} + +/** + * __snd_pcm_set_state - Change the current PCM state + * @runtime: PCM runtime to set + * @state: the current state to set + * + * Call within the stream lock + */ +static inline void __snd_pcm_set_state(struct snd_pcm_runtime *runtime, + snd_pcm_state_t state) +{ + runtime->state = state; + runtime->status->state = state; /* copy for mmap */ +} + +/** + * bytes_to_samples - Unit conversion of the size from bytes to samples + * @runtime: PCM runtime instance + * @size: size in bytes + * + * Return: the size in samples + */ +static inline ssize_t bytes_to_samples(struct snd_pcm_runtime *runtime, ssize_t size) +{ + return size * 8 / runtime->sample_bits; +} + +/** + * bytes_to_frames - Unit conversion of the size from bytes to frames + * @runtime: PCM runtime instance + * @size: size in bytes + * + * Return: the size in frames + */ +static inline snd_pcm_sframes_t bytes_to_frames(struct snd_pcm_runtime *runtime, ssize_t size) +{ + return size * 8 / runtime->frame_bits; +} + +/** + * samples_to_bytes - Unit conversion of the size from samples to bytes + * @runtime: PCM runtime instance + * @size: size in samples + * + * Return: the byte size + */ +static inline ssize_t samples_to_bytes(struct snd_pcm_runtime *runtime, ssize_t size) +{ + return size * runtime->sample_bits / 8; +} + +/** + * frames_to_bytes - Unit conversion of the size from frames to bytes + * @runtime: PCM runtime instance + * @size: size in frames + * + * Return: the byte size + */ +static inline ssize_t frames_to_bytes(struct snd_pcm_runtime *runtime, snd_pcm_sframes_t size) +{ + return size * runtime->frame_bits / 8; +} + +/** + * frame_aligned - Check whether the byte size is aligned to frames + * @runtime: PCM runtime instance + * @bytes: size in bytes + * + * Return: true if aligned, or false if not + */ +static inline int frame_aligned(struct snd_pcm_runtime *runtime, ssize_t bytes) +{ + return bytes % runtime->byte_align == 0; +} + +/** + * snd_pcm_lib_buffer_bytes - Get the buffer size of the current PCM in bytes + * @substream: PCM substream + * + * Return: buffer byte size + */ +static inline size_t snd_pcm_lib_buffer_bytes(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + return frames_to_bytes(runtime, runtime->buffer_size); +} + +/** + * snd_pcm_lib_period_bytes - Get the period size of the current PCM in bytes + * @substream: PCM substream + * + * Return: period byte size + */ +static inline size_t snd_pcm_lib_period_bytes(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + return frames_to_bytes(runtime, runtime->period_size); +} + +/** + * snd_pcm_playback_avail - Get the available (writable) space for playback + * @runtime: PCM runtime instance + * + * Result is between 0 ... (boundary - 1) + * + * Return: available frame size + */ +static inline snd_pcm_uframes_t snd_pcm_playback_avail(struct snd_pcm_runtime *runtime) +{ + snd_pcm_sframes_t avail = runtime->status->hw_ptr + runtime->buffer_size - runtime->control->appl_ptr; + if (avail < 0) + avail += runtime->boundary; + else if ((snd_pcm_uframes_t) avail >= runtime->boundary) + avail -= runtime->boundary; + return avail; +} + +/** + * snd_pcm_capture_avail - Get the available (readable) space for capture + * @runtime: PCM runtime instance + * + * Result is between 0 ... (boundary - 1) + * + * Return: available frame size + */ +static inline snd_pcm_uframes_t snd_pcm_capture_avail(struct snd_pcm_runtime *runtime) +{ + snd_pcm_sframes_t avail = runtime->status->hw_ptr - runtime->control->appl_ptr; + if (avail < 0) + avail += runtime->boundary; + return avail; +} + +/** + * snd_pcm_playback_hw_avail - Get the queued space for playback + * @runtime: PCM runtime instance + * + * Return: available frame size + */ +static inline snd_pcm_sframes_t snd_pcm_playback_hw_avail(struct snd_pcm_runtime *runtime) +{ + return runtime->buffer_size - snd_pcm_playback_avail(runtime); +} + +/** + * snd_pcm_capture_hw_avail - Get the free space for capture + * @runtime: PCM runtime instance + * + * Return: available frame size + */ +static inline snd_pcm_sframes_t snd_pcm_capture_hw_avail(struct snd_pcm_runtime *runtime) +{ + return runtime->buffer_size - snd_pcm_capture_avail(runtime); +} + +/** + * snd_pcm_playback_ready - check whether the playback buffer is available + * @substream: the pcm substream instance + * + * Checks whether enough free space is available on the playback buffer. + * + * Return: Non-zero if available, or zero if not. + */ +static inline int snd_pcm_playback_ready(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + return snd_pcm_playback_avail(runtime) >= runtime->control->avail_min; +} + +/** + * snd_pcm_capture_ready - check whether the capture buffer is available + * @substream: the pcm substream instance + * + * Checks whether enough capture data is available on the capture buffer. + * + * Return: Non-zero if available, or zero if not. + */ +static inline int snd_pcm_capture_ready(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + return snd_pcm_capture_avail(runtime) >= runtime->control->avail_min; +} + +/** + * snd_pcm_playback_data - check whether any data exists on the playback buffer + * @substream: the pcm substream instance + * + * Checks whether any data exists on the playback buffer. + * + * Return: Non-zero if any data exists, or zero if not. If stop_threshold + * is bigger or equal to boundary, then this function returns always non-zero. + */ +static inline int snd_pcm_playback_data(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + + if (runtime->stop_threshold >= runtime->boundary) + return 1; + return snd_pcm_playback_avail(runtime) < runtime->buffer_size; +} + +/** + * snd_pcm_playback_empty - check whether the playback buffer is empty + * @substream: the pcm substream instance + * + * Checks whether the playback buffer is empty. + * + * Return: Non-zero if empty, or zero if not. + */ +static inline int snd_pcm_playback_empty(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + return snd_pcm_playback_avail(runtime) >= runtime->buffer_size; +} + +/** + * snd_pcm_capture_empty - check whether the capture buffer is empty + * @substream: the pcm substream instance + * + * Checks whether the capture buffer is empty. + * + * Return: Non-zero if empty, or zero if not. + */ +static inline int snd_pcm_capture_empty(struct snd_pcm_substream *substream) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + return snd_pcm_capture_avail(runtime) == 0; +} + +/** + * snd_pcm_trigger_done - Mark the master substream + * @substream: the pcm substream instance + * @master: the linked master substream + * + * When multiple substreams of the same card are linked and the hardware + * supports the single-shot operation, the driver calls this in the loop + * in snd_pcm_group_for_each_entry() for marking the substream as "done". + * Then most of trigger operations are performed only to the given master + * substream. + * + * The trigger_master mark is cleared at timestamp updates at the end + * of trigger operations. + */ +static inline void snd_pcm_trigger_done(struct snd_pcm_substream *substream, + struct snd_pcm_substream *master) +{ + substream->runtime->trigger_master = master; +} + +static inline int hw_is_mask(int var) +{ + return var >= SNDRV_PCM_HW_PARAM_FIRST_MASK && + var <= SNDRV_PCM_HW_PARAM_LAST_MASK; +} + +static inline int hw_is_interval(int var) +{ + return var >= SNDRV_PCM_HW_PARAM_FIRST_INTERVAL && + var <= SNDRV_PCM_HW_PARAM_LAST_INTERVAL; +} + +static inline struct snd_mask *hw_param_mask(struct snd_pcm_hw_params *params, + snd_pcm_hw_param_t var) +{ + return ¶ms->masks[var - SNDRV_PCM_HW_PARAM_FIRST_MASK]; +} + +static inline struct snd_interval *hw_param_interval(struct snd_pcm_hw_params *params, + snd_pcm_hw_param_t var) +{ + return ¶ms->intervals[var - SNDRV_PCM_HW_PARAM_FIRST_INTERVAL]; +} + +static inline const struct snd_mask *hw_param_mask_c(const struct snd_pcm_hw_params *params, + snd_pcm_hw_param_t var) +{ + return ¶ms->masks[var - SNDRV_PCM_HW_PARAM_FIRST_MASK]; +} + +static inline const struct snd_interval *hw_param_interval_c(const struct snd_pcm_hw_params *params, + snd_pcm_hw_param_t var) +{ + return ¶ms->intervals[var - SNDRV_PCM_HW_PARAM_FIRST_INTERVAL]; +} + +/** + * params_channels - Get the number of channels from the hw params + * @p: hw params + * + * Return: the number of channels + */ +static inline unsigned int params_channels(const struct snd_pcm_hw_params *p) +{ + return hw_param_interval_c(p, SNDRV_PCM_HW_PARAM_CHANNELS)->min; +} + +/** + * params_rate - Get the sample rate from the hw params + * @p: hw params + * + * Return: the sample rate + */ +static inline unsigned int params_rate(const struct snd_pcm_hw_params *p) +{ + return hw_param_interval_c(p, SNDRV_PCM_HW_PARAM_RATE)->min; +} + +/** + * params_period_size - Get the period size (in frames) from the hw params + * @p: hw params + * + * Return: the period size in frames + */ +static inline unsigned int params_period_size(const struct snd_pcm_hw_params *p) +{ + return hw_param_interval_c(p, SNDRV_PCM_HW_PARAM_PERIOD_SIZE)->min; +} + +/** + * params_periods - Get the number of periods from the hw params + * @p: hw params + * + * Return: the number of periods + */ +static inline unsigned int params_periods(const struct snd_pcm_hw_params *p) +{ + return hw_param_interval_c(p, SNDRV_PCM_HW_PARAM_PERIODS)->min; +} + +/** + * params_buffer_size - Get the buffer size (in frames) from the hw params + * @p: hw params + * + * Return: the buffer size in frames + */ +static inline unsigned int params_buffer_size(const struct snd_pcm_hw_params *p) +{ + return hw_param_interval_c(p, SNDRV_PCM_HW_PARAM_BUFFER_SIZE)->min; +} + +/** + * params_buffer_bytes - Get the buffer size (in bytes) from the hw params + * @p: hw params + * + * Return: the buffer size in bytes + */ +static inline unsigned int params_buffer_bytes(const struct snd_pcm_hw_params *p) +{ + return hw_param_interval_c(p, SNDRV_PCM_HW_PARAM_BUFFER_BYTES)->min; +} + +int snd_interval_refine(struct snd_interval *i, const struct snd_interval *v); +int snd_interval_list(struct snd_interval *i, unsigned int count, + const unsigned int *list, unsigned int mask); +int snd_interval_ranges(struct snd_interval *i, unsigned int count, + const struct snd_interval *list, unsigned int mask); +int snd_interval_ratnum(struct snd_interval *i, + unsigned int rats_count, const struct snd_ratnum *rats, + unsigned int *nump, unsigned int *denp); + +void _snd_pcm_hw_params_any(struct snd_pcm_hw_params *params); +void _snd_pcm_hw_param_setempty(struct snd_pcm_hw_params *params, snd_pcm_hw_param_t var); + +int snd_pcm_hw_refine(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params); + +int snd_pcm_hw_constraint_mask64(struct snd_pcm_runtime *runtime, snd_pcm_hw_param_t var, + u_int64_t mask); +int snd_pcm_hw_constraint_minmax(struct snd_pcm_runtime *runtime, snd_pcm_hw_param_t var, + unsigned int min, unsigned int max); +int snd_pcm_hw_constraint_integer(struct snd_pcm_runtime *runtime, snd_pcm_hw_param_t var); +int snd_pcm_hw_constraint_list(struct snd_pcm_runtime *runtime, + unsigned int cond, + snd_pcm_hw_param_t var, + const struct snd_pcm_hw_constraint_list *l); +int snd_pcm_hw_constraint_ranges(struct snd_pcm_runtime *runtime, + unsigned int cond, + snd_pcm_hw_param_t var, + const struct snd_pcm_hw_constraint_ranges *r); +int snd_pcm_hw_constraint_ratnums(struct snd_pcm_runtime *runtime, + unsigned int cond, + snd_pcm_hw_param_t var, + const struct snd_pcm_hw_constraint_ratnums *r); +int snd_pcm_hw_constraint_ratdens(struct snd_pcm_runtime *runtime, + unsigned int cond, + snd_pcm_hw_param_t var, + const struct snd_pcm_hw_constraint_ratdens *r); +int snd_pcm_hw_constraint_msbits(struct snd_pcm_runtime *runtime, + unsigned int cond, + unsigned int width, + unsigned int msbits); +int snd_pcm_hw_constraint_step(struct snd_pcm_runtime *runtime, + unsigned int cond, + snd_pcm_hw_param_t var, + unsigned long step); +int snd_pcm_hw_constraint_pow2(struct snd_pcm_runtime *runtime, + unsigned int cond, + snd_pcm_hw_param_t var); +int snd_pcm_hw_rule_noresample(struct snd_pcm_runtime *runtime, + unsigned int base_rate); +int snd_pcm_hw_rule_add(struct snd_pcm_runtime *runtime, + unsigned int cond, + int var, + snd_pcm_hw_rule_func_t func, void *private, + int dep, ...); + +/** + * snd_pcm_hw_constraint_single() - Constrain parameter to a single value + * @runtime: PCM runtime instance + * @var: The hw_params variable to constrain + * @val: The value to constrain to + * + * Return: Positive if the value is changed, zero if it's not changed, or a + * negative error code. + */ +static inline int snd_pcm_hw_constraint_single( + struct snd_pcm_runtime *runtime, snd_pcm_hw_param_t var, + unsigned int val) +{ + return snd_pcm_hw_constraint_minmax(runtime, var, val, val); +} + +int snd_pcm_format_signed(snd_pcm_format_t format); +int snd_pcm_format_unsigned(snd_pcm_format_t format); +int snd_pcm_format_linear(snd_pcm_format_t format); +int snd_pcm_format_little_endian(snd_pcm_format_t format); +int snd_pcm_format_big_endian(snd_pcm_format_t format); +#if 0 /* just for kernel-doc */ +/** + * snd_pcm_format_cpu_endian - Check the PCM format is CPU-endian + * @format: the format to check + * + * Return: 1 if the given PCM format is CPU-endian, 0 if + * opposite, or a negative error code if endian not specified. + */ +int snd_pcm_format_cpu_endian(snd_pcm_format_t format); +#endif /* DocBook */ +#ifdef SNDRV_LITTLE_ENDIAN +#define snd_pcm_format_cpu_endian(format) snd_pcm_format_little_endian(format) +#else +#define snd_pcm_format_cpu_endian(format) snd_pcm_format_big_endian(format) +#endif +int snd_pcm_format_width(snd_pcm_format_t format); /* in bits */ +int snd_pcm_format_physical_width(snd_pcm_format_t format); /* in bits */ +ssize_t snd_pcm_format_size(snd_pcm_format_t format, size_t samples); +const unsigned char *snd_pcm_format_silence_64(snd_pcm_format_t format); +int snd_pcm_format_set_silence(snd_pcm_format_t format, void *buf, unsigned int frames); + +void snd_pcm_set_ops(struct snd_pcm * pcm, int direction, + const struct snd_pcm_ops *ops); +void snd_pcm_set_sync(struct snd_pcm_substream *substream); +int snd_pcm_lib_ioctl(struct snd_pcm_substream *substream, + unsigned int cmd, void *arg); +void snd_pcm_period_elapsed_under_stream_lock(struct snd_pcm_substream *substream); +void snd_pcm_period_elapsed(struct snd_pcm_substream *substream); +snd_pcm_sframes_t __snd_pcm_lib_xfer(struct snd_pcm_substream *substream, + void *buf, bool interleaved, + snd_pcm_uframes_t frames, bool in_kernel); + +static inline snd_pcm_sframes_t +snd_pcm_lib_write(struct snd_pcm_substream *substream, + const void __user *buf, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, (void __force *)buf, true, frames, false); +} + +static inline snd_pcm_sframes_t +snd_pcm_lib_read(struct snd_pcm_substream *substream, + void __user *buf, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, (void __force *)buf, true, frames, false); +} + +static inline snd_pcm_sframes_t +snd_pcm_lib_writev(struct snd_pcm_substream *substream, + void __user **bufs, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, (void *)bufs, false, frames, false); +} + +static inline snd_pcm_sframes_t +snd_pcm_lib_readv(struct snd_pcm_substream *substream, + void __user **bufs, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, (void *)bufs, false, frames, false); +} + +static inline snd_pcm_sframes_t +snd_pcm_kernel_write(struct snd_pcm_substream *substream, + const void *buf, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, (void *)buf, true, frames, true); +} + +static inline snd_pcm_sframes_t +snd_pcm_kernel_read(struct snd_pcm_substream *substream, + void *buf, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, buf, true, frames, true); +} + +static inline snd_pcm_sframes_t +snd_pcm_kernel_writev(struct snd_pcm_substream *substream, + void **bufs, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, bufs, false, frames, true); +} + +static inline snd_pcm_sframes_t +snd_pcm_kernel_readv(struct snd_pcm_substream *substream, + void **bufs, snd_pcm_uframes_t frames) +{ + return __snd_pcm_lib_xfer(substream, bufs, false, frames, true); +} + +int snd_pcm_hw_limit_rates(struct snd_pcm_hardware *hw); + +static inline int +snd_pcm_limit_hw_rates(struct snd_pcm_runtime *runtime) +{ + return snd_pcm_hw_limit_rates(&runtime->hw); +} + +unsigned int snd_pcm_rate_to_rate_bit(unsigned int rate); +unsigned int snd_pcm_rate_bit_to_rate(unsigned int rate_bit); +unsigned int snd_pcm_rate_mask_intersect(unsigned int rates_a, + unsigned int rates_b); +unsigned int snd_pcm_rate_range_to_bits(unsigned int rate_min, + unsigned int rate_max); + +/** + * snd_pcm_set_runtime_buffer - Set the PCM runtime buffer + * @substream: PCM substream to set + * @bufp: the buffer information, NULL to clear + * + * Copy the buffer information to runtime->dma_buffer when @bufp is non-NULL. + * Otherwise it clears the current buffer information. + */ +static inline void snd_pcm_set_runtime_buffer(struct snd_pcm_substream *substream, + struct snd_dma_buffer *bufp) +{ + struct snd_pcm_runtime *runtime = substream->runtime; + if (bufp) { + runtime->dma_buffer_p = bufp; + runtime->dma_area = bufp->area; + runtime->dma_addr = bufp->addr; + runtime->dma_bytes = bufp->bytes; + } else { + runtime->dma_buffer_p = NULL; + runtime->dma_area = NULL; + runtime->dma_addr = 0; + runtime->dma_bytes = 0; + } +} + +/** + * snd_pcm_gettime - Fill the timespec64 depending on the timestamp mode + * @runtime: PCM runtime instance + * @tv: timespec64 to fill + */ +static inline void snd_pcm_gettime(struct snd_pcm_runtime *runtime, + struct timespec64 *tv) +{ + switch (runtime->tstamp_type) { + case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC: + ktime_get_ts64(tv); + break; + case SNDRV_PCM_TSTAMP_TYPE_MONOTONIC_RAW: + ktime_get_raw_ts64(tv); + break; + default: + ktime_get_real_ts64(tv); + break; + } +} + +/* + * Memory + */ + +void snd_pcm_lib_preallocate_free(struct snd_pcm_substream *substream); +void snd_pcm_lib_preallocate_free_for_all(struct snd_pcm *pcm); +void snd_pcm_lib_preallocate_pages(struct snd_pcm_substream *substream, + int type, struct device *data, + size_t size, size_t max); +void snd_pcm_lib_preallocate_pages_for_all(struct snd_pcm *pcm, + int type, void *data, + size_t size, size_t max); +int snd_pcm_lib_malloc_pages(struct snd_pcm_substream *substream, size_t size); +int snd_pcm_lib_free_pages(struct snd_pcm_substream *substream); + +int snd_pcm_set_managed_buffer(struct snd_pcm_substream *substream, int type, + struct device *data, size_t size, size_t max); +int snd_pcm_set_managed_buffer_all(struct snd_pcm *pcm, int type, + struct device *data, + size_t size, size_t max); + +/** + * snd_pcm_set_fixed_buffer - Preallocate and set up the fixed size PCM buffer + * @substream: the pcm substream instance + * @type: DMA type (SNDRV_DMA_TYPE_*) + * @data: DMA type dependent data + * @size: the requested pre-allocation size in bytes + * + * This is a variant of snd_pcm_set_managed_buffer(), but this pre-allocates + * only the given sized buffer and doesn't allow re-allocation nor dynamic + * allocation of a larger buffer unlike the standard one. + * The function may return -ENOMEM error, hence the caller must check it. + * + * Return: zero if successful, or a negative error code + */ +static inline int __must_check +snd_pcm_set_fixed_buffer(struct snd_pcm_substream *substream, int type, + struct device *data, size_t size) +{ + return snd_pcm_set_managed_buffer(substream, type, data, size, 0); +} + +/** + * snd_pcm_set_fixed_buffer_all - Preallocate and set up the fixed size PCM buffer + * @pcm: the pcm instance + * @type: DMA type (SNDRV_DMA_TYPE_*) + * @data: DMA type dependent data + * @size: the requested pre-allocation size in bytes + * + * Apply the set up of the fixed buffer via snd_pcm_set_fixed_buffer() for + * all substream. If any of allocation fails, it returns -ENOMEM, hence the + * caller must check the return value. + * + * Return: zero if successful, or a negative error code + */ +static inline int __must_check +snd_pcm_set_fixed_buffer_all(struct snd_pcm *pcm, int type, + struct device *data, size_t size) +{ + return snd_pcm_set_managed_buffer_all(pcm, type, data, size, 0); +} + +int _snd_pcm_lib_alloc_vmalloc_buffer(struct snd_pcm_substream *substream, + size_t size, gfp_t gfp_flags); +int snd_pcm_lib_free_vmalloc_buffer(struct snd_pcm_substream *substream); +struct page *snd_pcm_lib_get_vmalloc_page(struct snd_pcm_substream *substream, + unsigned long offset); +/** + * snd_pcm_lib_alloc_vmalloc_buffer - allocate virtual DMA buffer + * @substream: the substream to allocate the buffer to + * @size: the requested buffer size, in bytes + * + * Allocates the PCM substream buffer using vmalloc(), i.e., the memory is + * contiguous in kernel virtual space, but not in physical memory. Use this + * if the buffer is accessed by kernel code but not by device DMA. + * + * Return: 1 if the buffer was changed, 0 if not changed, or a negative error + * code. + */ +static inline int snd_pcm_lib_alloc_vmalloc_buffer + (struct snd_pcm_substream *substream, size_t size) +{ + return _snd_pcm_lib_alloc_vmalloc_buffer(substream, size, + GFP_KERNEL | __GFP_HIGHMEM | __GFP_ZERO); +} + +/** + * snd_pcm_lib_alloc_vmalloc_32_buffer - allocate 32-bit-addressable buffer + * @substream: the substream to allocate the buffer to + * @size: the requested buffer size, in bytes + * + * This function works like snd_pcm_lib_alloc_vmalloc_buffer(), but uses + * vmalloc_32(), i.e., the pages are allocated from 32-bit-addressable memory. + * + * Return: 1 if the buffer was changed, 0 if not changed, or a negative error + * code. + */ +static inline int snd_pcm_lib_alloc_vmalloc_32_buffer + (struct snd_pcm_substream *substream, size_t size) +{ + return _snd_pcm_lib_alloc_vmalloc_buffer(substream, size, + GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); +} + +#define snd_pcm_get_dma_buf(substream) ((substream)->runtime->dma_buffer_p) + +/** + * snd_pcm_sgbuf_get_addr - Get the DMA address at the corresponding offset + * @substream: PCM substream + * @ofs: byte offset + * + * Return: DMA address + */ +static inline dma_addr_t +snd_pcm_sgbuf_get_addr(struct snd_pcm_substream *substream, unsigned int ofs) +{ + return snd_sgbuf_get_addr(snd_pcm_get_dma_buf(substream), ofs); +} + +/** + * snd_pcm_sgbuf_get_chunk_size - Compute the max size that fits within the + * contig. page from the given size + * @substream: PCM substream + * @ofs: byte offset + * @size: byte size to examine + * + * Return: chunk size + */ +static inline unsigned int +snd_pcm_sgbuf_get_chunk_size(struct snd_pcm_substream *substream, + unsigned int ofs, unsigned int size) +{ + return snd_sgbuf_get_chunk_size(snd_pcm_get_dma_buf(substream), ofs, size); +} + +/** + * snd_pcm_mmap_data_open - increase the mmap counter + * @area: VMA + * + * PCM mmap callback should handle this counter properly + */ +static inline void snd_pcm_mmap_data_open(struct vm_area_struct *area) +{ + struct snd_pcm_substream *substream = (struct snd_pcm_substream *)area->vm_private_data; + atomic_inc(&substream->mmap_count); +} + +/** + * snd_pcm_mmap_data_close - decrease the mmap counter + * @area: VMA + * + * PCM mmap callback should handle this counter properly + */ +static inline void snd_pcm_mmap_data_close(struct vm_area_struct *area) +{ + struct snd_pcm_substream *substream = (struct snd_pcm_substream *)area->vm_private_data; + atomic_dec(&substream->mmap_count); +} + +int snd_pcm_lib_default_mmap(struct snd_pcm_substream *substream, + struct vm_area_struct *area); +/* mmap for io-memory area */ +#if defined(CONFIG_X86) || defined(CONFIG_PPC) || defined(CONFIG_ALPHA) +#define SNDRV_PCM_INFO_MMAP_IOMEM SNDRV_PCM_INFO_MMAP +int snd_pcm_lib_mmap_iomem(struct snd_pcm_substream *substream, struct vm_area_struct *area); +#else +#define SNDRV_PCM_INFO_MMAP_IOMEM 0 +#define snd_pcm_lib_mmap_iomem NULL +#endif + +/** + * snd_pcm_limit_isa_dma_size - Get the max size fitting with ISA DMA transfer + * @dma: DMA number + * @max: pointer to store the max size + */ +static inline void snd_pcm_limit_isa_dma_size(int dma, size_t *max) +{ + *max = dma < 4 ? 64 * 1024 : 128 * 1024; +} + +/* + * Misc + */ + +#define SNDRV_PCM_DEFAULT_CON_SPDIF (IEC958_AES0_CON_EMPHASIS_NONE|\ + (IEC958_AES1_CON_ORIGINAL<<8)|\ + (IEC958_AES1_CON_PCM_CODER<<8)|\ + (IEC958_AES3_CON_FS_48000<<24)) + +const char *snd_pcm_format_name(snd_pcm_format_t format); + +/** + * snd_pcm_direction_name - Get a string naming the direction of a stream + * @direction: Stream's direction, one of SNDRV_PCM_STREAM_XXX + * + * Returns a string naming the direction of the stream. + */ +static inline const char *snd_pcm_direction_name(int direction) +{ + if (direction == SNDRV_PCM_STREAM_PLAYBACK) + return "Playback"; + else + return "Capture"; +} + +/** + * snd_pcm_stream_str - Get a string naming the direction of a stream + * @substream: the pcm substream instance + * + * Return: A string naming the direction of the stream. + */ +static inline const char *snd_pcm_stream_str(struct snd_pcm_substream *substream) +{ + return snd_pcm_direction_name(substream->stream); +} + +/* + * PCM channel-mapping control API + */ +/* array element of channel maps */ +struct snd_pcm_chmap_elem { + unsigned char channels; + unsigned char map[15]; +}; + +/* channel map information; retrieved via snd_kcontrol_chip() */ +struct snd_pcm_chmap { + struct snd_pcm *pcm; /* assigned PCM instance */ + int stream; /* PLAYBACK or CAPTURE */ + struct snd_kcontrol *kctl; + const struct snd_pcm_chmap_elem *chmap; + unsigned int max_channels; + unsigned int channel_mask; /* optional: active channels bitmask */ + void *private_data; /* optional: private data pointer */ +}; + +/** + * snd_pcm_chmap_substream - get the PCM substream assigned to the given chmap info + * @info: chmap information + * @idx: the substream number index + * + * Return: the matched PCM substream, or NULL if not found + */ +static inline struct snd_pcm_substream * +snd_pcm_chmap_substream(struct snd_pcm_chmap *info, unsigned int idx) +{ + struct snd_pcm_substream *s; + for (s = info->pcm->streams[info->stream].substream; s; s = s->next) + if (s->number == idx) + return s; + return NULL; +} + +/* ALSA-standard channel maps (RL/RR prior to C/LFE) */ +extern const struct snd_pcm_chmap_elem snd_pcm_std_chmaps[]; +/* Other world's standard channel maps (C/LFE prior to RL/RR) */ +extern const struct snd_pcm_chmap_elem snd_pcm_alt_chmaps[]; + +/* bit masks to be passed to snd_pcm_chmap.channel_mask field */ +#define SND_PCM_CHMAP_MASK_24 ((1U << 2) | (1U << 4)) +#define SND_PCM_CHMAP_MASK_246 (SND_PCM_CHMAP_MASK_24 | (1U << 6)) +#define SND_PCM_CHMAP_MASK_2468 (SND_PCM_CHMAP_MASK_246 | (1U << 8)) + +int snd_pcm_add_chmap_ctls(struct snd_pcm *pcm, int stream, + const struct snd_pcm_chmap_elem *chmap, + int max_channels, + unsigned long private_value, + struct snd_pcm_chmap **info_ret); + +/** + * pcm_format_to_bits - Strong-typed conversion of pcm_format to bitwise + * @pcm_format: PCM format + * + * Return: 64bit mask corresponding to the given PCM format + */ +static inline u64 pcm_format_to_bits(snd_pcm_format_t pcm_format) +{ + return 1ULL << (__force int) pcm_format; +} + +/** + * pcm_for_each_format - helper to iterate for each format type + * @f: the iterator variable in snd_pcm_format_t type + */ +#define pcm_for_each_format(f) \ + for ((f) = SNDRV_PCM_FORMAT_FIRST; \ + (__force int)(f) <= (__force int)SNDRV_PCM_FORMAT_LAST; \ + (f) = (__force snd_pcm_format_t)((__force int)(f) + 1)) + +/* printk helpers */ +#define pcm_err(pcm, fmt, args...) \ + dev_err((pcm)->card->dev, fmt, ##args) +#define pcm_warn(pcm, fmt, args...) \ + dev_warn((pcm)->card->dev, fmt, ##args) +#define pcm_dbg(pcm, fmt, args...) \ + dev_dbg((pcm)->card->dev, fmt, ##args) + +struct snd_pcm_status64 { + snd_pcm_state_t state; /* stream state */ + u8 rsvd[4]; + s64 trigger_tstamp_sec; /* time when stream was started/stopped/paused */ + s64 trigger_tstamp_nsec; + s64 tstamp_sec; /* reference timestamp */ + s64 tstamp_nsec; + snd_pcm_uframes_t appl_ptr; /* appl ptr */ + snd_pcm_uframes_t hw_ptr; /* hw ptr */ + snd_pcm_sframes_t delay; /* current delay in frames */ + snd_pcm_uframes_t avail; /* number of frames available */ + snd_pcm_uframes_t avail_max; /* max frames available on hw since last status */ + snd_pcm_uframes_t overrange; /* count of ADC (capture) overrange detections from last status */ + snd_pcm_state_t suspended_state; /* suspended stream state */ + __u32 audio_tstamp_data; /* needed for 64-bit alignment, used for configs/report to/from userspace */ + s64 audio_tstamp_sec; /* sample counter, wall clock, PHC or on-demand sync'ed */ + s64 audio_tstamp_nsec; + s64 driver_tstamp_sec; /* useful in case reference system tstamp is reported with delay */ + s64 driver_tstamp_nsec; + __u32 audio_tstamp_accuracy; /* in ns units, only valid if indicated in audio_tstamp_data */ + unsigned char reserved[52-4*sizeof(s64)]; /* must be filled with zero */ +}; + +#define SNDRV_PCM_IOCTL_STATUS64 _IOR('A', 0x20, struct snd_pcm_status64) +#define SNDRV_PCM_IOCTL_STATUS_EXT64 _IOWR('A', 0x24, struct snd_pcm_status64) + +struct snd_pcm_status32 { + snd_pcm_state_t state; /* stream state */ + s32 trigger_tstamp_sec; /* time when stream was started/stopped/paused */ + s32 trigger_tstamp_nsec; + s32 tstamp_sec; /* reference timestamp */ + s32 tstamp_nsec; + u32 appl_ptr; /* appl ptr */ + u32 hw_ptr; /* hw ptr */ + s32 delay; /* current delay in frames */ + u32 avail; /* number of frames available */ + u32 avail_max; /* max frames available on hw since last status */ + u32 overrange; /* count of ADC (capture) overrange detections from last status */ + snd_pcm_state_t suspended_state; /* suspended stream state */ + u32 audio_tstamp_data; /* needed for 64-bit alignment, used for configs/report to/from userspace */ + s32 audio_tstamp_sec; /* sample counter, wall clock, PHC or on-demand sync'ed */ + s32 audio_tstamp_nsec; + s32 driver_tstamp_sec; /* useful in case reference system tstamp is reported with delay */ + s32 driver_tstamp_nsec; + u32 audio_tstamp_accuracy; /* in ns units, only valid if indicated in audio_tstamp_data */ + unsigned char reserved[52-4*sizeof(s32)]; /* must be filled with zero */ +}; + +#define SNDRV_PCM_IOCTL_STATUS32 _IOR('A', 0x20, struct snd_pcm_status32) +#define SNDRV_PCM_IOCTL_STATUS_EXT32 _IOWR('A', 0x24, struct snd_pcm_status32) + +#endif /* __SOUND_PCM_H */ diff --git a/include/sound/pcm_drm_eld.h b/include/sound/pcm_drm_eld.h new file mode 100644 index 000000000..28a55a8be --- /dev/null +++ b/include/sound/pcm_drm_eld.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SOUND_PCM_DRM_ELD_H +#define __SOUND_PCM_DRM_ELD_H + +int snd_pcm_hw_constraint_eld(struct snd_pcm_runtime *runtime, void *eld); + +#endif diff --git a/include/sound/pcm_iec958.h b/include/sound/pcm_iec958.h new file mode 100644 index 000000000..64e84441c --- /dev/null +++ b/include/sound/pcm_iec958.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SOUND_PCM_IEC958_H +#define __SOUND_PCM_IEC958_H + +#include <linux/types.h> + +int snd_pcm_create_iec958_consumer_default(u8 *cs, size_t len); + +int snd_pcm_fill_iec958_consumer(struct snd_pcm_runtime *runtime, u8 *cs, + size_t len); + +int snd_pcm_fill_iec958_consumer_hw_params(struct snd_pcm_hw_params *params, + u8 *cs, size_t len); + +int snd_pcm_create_iec958_consumer(struct snd_pcm_runtime *runtime, u8 *cs, + size_t len); + +int snd_pcm_create_iec958_consumer_hw_params(struct snd_pcm_hw_params *params, + u8 *cs, size_t len); +#endif diff --git a/include/sound/pcm_oss.h b/include/sound/pcm_oss.h new file mode 100644 index 000000000..c96f23c77 --- /dev/null +++ b/include/sound/pcm_oss.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_PCM_OSS_H +#define __SOUND_PCM_OSS_H + +/* + * Digital Audio (PCM) - OSS compatibility abstract layer + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + */ + +struct snd_pcm_oss_setup { + char *task_name; + unsigned int disable:1, + direct:1, + block:1, + nonblock:1, + partialfrag:1, + nosilence:1, + buggyptr:1; + unsigned int periods; + unsigned int period_size; + struct snd_pcm_oss_setup *next; +}; + +struct snd_pcm_oss_runtime { + unsigned params: 1, /* format/parameter change */ + prepare: 1, /* need to prepare the operation */ + trigger: 1, /* trigger flag */ + sync_trigger: 1; /* sync trigger flag */ + int rate; /* requested rate */ + int format; /* requested OSS format */ + unsigned int channels; /* requested channels */ + unsigned int fragshift; + unsigned int maxfrags; + unsigned int subdivision; /* requested subdivision */ + size_t period_bytes; /* requested period size */ + size_t period_frames; /* period frames for poll */ + size_t period_ptr; /* actual write pointer to period */ + unsigned int periods; + size_t buffer_bytes; /* requested buffer size */ + size_t bytes; /* total # bytes processed */ + size_t mmap_bytes; + char *buffer; /* vmallocated period */ + size_t buffer_used; /* used length from period buffer */ + struct mutex params_lock; + atomic_t rw_ref; /* concurrent read/write accesses */ +#ifdef CONFIG_SND_PCM_OSS_PLUGINS + struct snd_pcm_plugin *plugin_first; + struct snd_pcm_plugin *plugin_last; +#endif + unsigned int prev_hw_ptr_period; +}; + +struct snd_pcm_oss_file { + struct snd_pcm_substream *streams[2]; +}; + +struct snd_pcm_oss_substream { + unsigned oss: 1; /* oss mode */ + struct snd_pcm_oss_setup setup; /* active setup */ +}; + +struct snd_pcm_oss_stream { + struct snd_pcm_oss_setup *setup_list; /* setup list */ + struct mutex setup_mutex; +#ifdef CONFIG_SND_VERBOSE_PROCFS + struct snd_info_entry *proc_entry; +#endif +}; + +struct snd_pcm_oss { + int reg; + unsigned int reg_mask; +}; + +#endif /* __SOUND_PCM_OSS_H */ diff --git a/include/sound/pcm_params.h b/include/sound/pcm_params.h new file mode 100644 index 000000000..ba184f49f --- /dev/null +++ b/include/sound/pcm_params.h @@ -0,0 +1,371 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_PCM_PARAMS_H +#define __SOUND_PCM_PARAMS_H + +/* + * PCM params helpers + * Copyright (c) by Abramo Bagnara <abramo@alsa-project.org> + */ + +#include <sound/pcm.h> + +int snd_pcm_hw_param_first(struct snd_pcm_substream *pcm, + struct snd_pcm_hw_params *params, + snd_pcm_hw_param_t var, int *dir); +int snd_pcm_hw_param_last(struct snd_pcm_substream *pcm, + struct snd_pcm_hw_params *params, + snd_pcm_hw_param_t var, int *dir); +int snd_pcm_hw_param_value(const struct snd_pcm_hw_params *params, + snd_pcm_hw_param_t var, int *dir); + +#define SNDRV_MASK_BITS 64 /* we use so far 64bits only */ +#define SNDRV_MASK_SIZE (SNDRV_MASK_BITS / 32) +#define MASK_OFS(i) ((i) >> 5) +#define MASK_BIT(i) (1U << ((i) & 31)) + +static inline void snd_mask_none(struct snd_mask *mask) +{ + memset(mask, 0, sizeof(*mask)); +} + +static inline void snd_mask_any(struct snd_mask *mask) +{ + memset(mask, 0xff, SNDRV_MASK_SIZE * sizeof(u_int32_t)); +} + +static inline int snd_mask_empty(const struct snd_mask *mask) +{ + int i; + for (i = 0; i < SNDRV_MASK_SIZE; i++) + if (mask->bits[i]) + return 0; + return 1; +} + +static inline unsigned int snd_mask_min(const struct snd_mask *mask) +{ + int i; + for (i = 0; i < SNDRV_MASK_SIZE; i++) { + if (mask->bits[i]) + return __ffs(mask->bits[i]) + (i << 5); + } + return 0; +} + +static inline unsigned int snd_mask_max(const struct snd_mask *mask) +{ + int i; + for (i = SNDRV_MASK_SIZE - 1; i >= 0; i--) { + if (mask->bits[i]) + return __fls(mask->bits[i]) + (i << 5); + } + return 0; +} + +static inline void snd_mask_set(struct snd_mask *mask, unsigned int val) +{ + mask->bits[MASK_OFS(val)] |= MASK_BIT(val); +} + +/* Most of drivers need only this one */ +static inline void snd_mask_set_format(struct snd_mask *mask, + snd_pcm_format_t format) +{ + snd_mask_set(mask, (__force unsigned int)format); +} + +static inline void snd_mask_reset(struct snd_mask *mask, unsigned int val) +{ + mask->bits[MASK_OFS(val)] &= ~MASK_BIT(val); +} + +static inline void snd_mask_set_range(struct snd_mask *mask, + unsigned int from, unsigned int to) +{ + unsigned int i; + for (i = from; i <= to; i++) + mask->bits[MASK_OFS(i)] |= MASK_BIT(i); +} + +static inline void snd_mask_reset_range(struct snd_mask *mask, + unsigned int from, unsigned int to) +{ + unsigned int i; + for (i = from; i <= to; i++) + mask->bits[MASK_OFS(i)] &= ~MASK_BIT(i); +} + +static inline void snd_mask_leave(struct snd_mask *mask, unsigned int val) +{ + unsigned int v; + v = mask->bits[MASK_OFS(val)] & MASK_BIT(val); + snd_mask_none(mask); + mask->bits[MASK_OFS(val)] = v; +} + +static inline void snd_mask_intersect(struct snd_mask *mask, + const struct snd_mask *v) +{ + int i; + for (i = 0; i < SNDRV_MASK_SIZE; i++) + mask->bits[i] &= v->bits[i]; +} + +static inline int snd_mask_eq(const struct snd_mask *mask, + const struct snd_mask *v) +{ + return ! memcmp(mask, v, SNDRV_MASK_SIZE * sizeof(u_int32_t)); +} + +static inline void snd_mask_copy(struct snd_mask *mask, + const struct snd_mask *v) +{ + *mask = *v; +} + +static inline int snd_mask_test(const struct snd_mask *mask, unsigned int val) +{ + return mask->bits[MASK_OFS(val)] & MASK_BIT(val); +} + +/* Most of drivers need only this one */ +static inline int snd_mask_test_format(const struct snd_mask *mask, + snd_pcm_format_t format) +{ + return snd_mask_test(mask, (__force unsigned int)format); +} + +static inline int snd_mask_single(const struct snd_mask *mask) +{ + int i, c = 0; + for (i = 0; i < SNDRV_MASK_SIZE; i++) { + if (! mask->bits[i]) + continue; + if (mask->bits[i] & (mask->bits[i] - 1)) + return 0; + if (c) + return 0; + c++; + } + return 1; +} + +static inline int snd_mask_refine(struct snd_mask *mask, + const struct snd_mask *v) +{ + struct snd_mask old; + snd_mask_copy(&old, mask); + snd_mask_intersect(mask, v); + if (snd_mask_empty(mask)) + return -EINVAL; + return !snd_mask_eq(mask, &old); +} + +static inline int snd_mask_refine_first(struct snd_mask *mask) +{ + if (snd_mask_single(mask)) + return 0; + snd_mask_leave(mask, snd_mask_min(mask)); + return 1; +} + +static inline int snd_mask_refine_last(struct snd_mask *mask) +{ + if (snd_mask_single(mask)) + return 0; + snd_mask_leave(mask, snd_mask_max(mask)); + return 1; +} + +static inline int snd_mask_refine_min(struct snd_mask *mask, unsigned int val) +{ + if (snd_mask_min(mask) >= val) + return 0; + snd_mask_reset_range(mask, 0, val - 1); + if (snd_mask_empty(mask)) + return -EINVAL; + return 1; +} + +static inline int snd_mask_refine_max(struct snd_mask *mask, unsigned int val) +{ + if (snd_mask_max(mask) <= val) + return 0; + snd_mask_reset_range(mask, val + 1, SNDRV_MASK_BITS); + if (snd_mask_empty(mask)) + return -EINVAL; + return 1; +} + +static inline int snd_mask_refine_set(struct snd_mask *mask, unsigned int val) +{ + int changed; + changed = !snd_mask_single(mask); + snd_mask_leave(mask, val); + if (snd_mask_empty(mask)) + return -EINVAL; + return changed; +} + +static inline int snd_mask_value(const struct snd_mask *mask) +{ + return snd_mask_min(mask); +} + +static inline void snd_interval_any(struct snd_interval *i) +{ + i->min = 0; + i->openmin = 0; + i->max = UINT_MAX; + i->openmax = 0; + i->integer = 0; + i->empty = 0; +} + +static inline void snd_interval_none(struct snd_interval *i) +{ + i->empty = 1; +} + +static inline int snd_interval_checkempty(const struct snd_interval *i) +{ + return (i->min > i->max || + (i->min == i->max && (i->openmin || i->openmax))); +} + +static inline int snd_interval_empty(const struct snd_interval *i) +{ + return i->empty; +} + +static inline int snd_interval_single(const struct snd_interval *i) +{ + return (i->min == i->max || + (i->min + 1 == i->max && (i->openmin || i->openmax))); +} + +static inline int snd_interval_value(const struct snd_interval *i) +{ + if (i->openmin && !i->openmax) + return i->max; + return i->min; +} + +static inline int snd_interval_min(const struct snd_interval *i) +{ + return i->min; +} + +static inline int snd_interval_max(const struct snd_interval *i) +{ + unsigned int v; + v = i->max; + if (i->openmax) + v--; + return v; +} + +static inline int snd_interval_test(const struct snd_interval *i, unsigned int val) +{ + return !((i->min > val || (i->min == val && i->openmin) || + i->max < val || (i->max == val && i->openmax))); +} + +static inline void snd_interval_copy(struct snd_interval *d, const struct snd_interval *s) +{ + *d = *s; +} + +static inline int snd_interval_setinteger(struct snd_interval *i) +{ + if (i->integer) + return 0; + if (i->openmin && i->openmax && i->min == i->max) + return -EINVAL; + i->integer = 1; + return 1; +} + +static inline int snd_interval_eq(const struct snd_interval *i1, const struct snd_interval *i2) +{ + if (i1->empty) + return i2->empty; + if (i2->empty) + return i1->empty; + return i1->min == i2->min && i1->openmin == i2->openmin && + i1->max == i2->max && i1->openmax == i2->openmax; +} + +/** + * params_access - get the access type from the hw params + * @p: hw params + */ +static inline snd_pcm_access_t params_access(const struct snd_pcm_hw_params *p) +{ + return (__force snd_pcm_access_t)snd_mask_min(hw_param_mask_c(p, + SNDRV_PCM_HW_PARAM_ACCESS)); +} + +/** + * params_format - get the sample format from the hw params + * @p: hw params + */ +static inline snd_pcm_format_t params_format(const struct snd_pcm_hw_params *p) +{ + return (__force snd_pcm_format_t)snd_mask_min(hw_param_mask_c(p, + SNDRV_PCM_HW_PARAM_FORMAT)); +} + +/** + * params_subformat - get the sample subformat from the hw params + * @p: hw params + */ +static inline snd_pcm_subformat_t +params_subformat(const struct snd_pcm_hw_params *p) +{ + return (__force snd_pcm_subformat_t)snd_mask_min(hw_param_mask_c(p, + SNDRV_PCM_HW_PARAM_SUBFORMAT)); +} + +/** + * params_period_bytes - get the period size (in bytes) from the hw params + * @p: hw params + */ +static inline unsigned int +params_period_bytes(const struct snd_pcm_hw_params *p) +{ + return hw_param_interval_c(p, SNDRV_PCM_HW_PARAM_PERIOD_BYTES)->min; +} + +/** + * params_width - get the number of bits of the sample format from the hw params + * @p: hw params + * + * This function returns the number of bits per sample that the selected sample + * format of the hw params has. + */ +static inline int params_width(const struct snd_pcm_hw_params *p) +{ + return snd_pcm_format_width(params_format(p)); +} + +/* + * params_physical_width - get the storage size of the sample format from the hw params + * @p: hw params + * + * This functions returns the number of bits per sample that the selected sample + * format of the hw params takes up in memory. This will be equal or larger than + * params_width(). + */ +static inline int params_physical_width(const struct snd_pcm_hw_params *p) +{ + return snd_pcm_format_physical_width(params_format(p)); +} + +static inline void +params_set_format(struct snd_pcm_hw_params *p, snd_pcm_format_t fmt) +{ + snd_mask_set_format(hw_param_mask(p, SNDRV_PCM_HW_PARAM_FORMAT), fmt); +} + +#endif /* __SOUND_PCM_PARAMS_H */ diff --git a/include/sound/pt2258.h b/include/sound/pt2258.h new file mode 100644 index 000000000..8c32e71cd --- /dev/null +++ b/include/sound/pt2258.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * ALSA Driver for the PT2258 volume controller. + * + * Copyright (c) 2006 Jochen Voss <voss@seehuhn.de> + */ + +#ifndef __SOUND_PT2258_H +#define __SOUND_PT2258_H + +struct snd_pt2258 { + struct snd_card *card; + struct snd_i2c_bus *i2c_bus; + struct snd_i2c_device *i2c_dev; + + unsigned char volume[6]; + int mute; +}; + +extern int snd_pt2258_reset(struct snd_pt2258 *pt); +extern int snd_pt2258_build_controls(struct snd_pt2258 *pt); + +#endif /* __SOUND_PT2258_H */ diff --git a/include/sound/pxa2xx-lib.h b/include/sound/pxa2xx-lib.h new file mode 100644 index 000000000..0a6f8dabf --- /dev/null +++ b/include/sound/pxa2xx-lib.h @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef PXA2XX_LIB_H +#define PXA2XX_LIB_H + +#include <uapi/sound/asound.h> +#include <linux/platform_device.h> + +/* PCM */ +struct snd_pcm_substream; +struct snd_pcm_hw_params; +struct snd_soc_pcm_runtime; +struct snd_pcm; +struct snd_soc_component; + +extern int pxa2xx_pcm_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +extern int pxa2xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd); +extern snd_pcm_uframes_t pxa2xx_pcm_pointer(struct snd_pcm_substream *substream); +extern int pxa2xx_pcm_prepare(struct snd_pcm_substream *substream); +extern int pxa2xx_pcm_open(struct snd_pcm_substream *substream); +extern int pxa2xx_pcm_close(struct snd_pcm_substream *substream); +extern int pxa2xx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm); +extern int pxa2xx_soc_pcm_new(struct snd_soc_component *component, + struct snd_soc_pcm_runtime *rtd); +extern int pxa2xx_soc_pcm_open(struct snd_soc_component *component, + struct snd_pcm_substream *substream); +extern int pxa2xx_soc_pcm_close(struct snd_soc_component *component, + struct snd_pcm_substream *substream); +extern int pxa2xx_soc_pcm_hw_params(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +extern int pxa2xx_soc_pcm_prepare(struct snd_soc_component *component, + struct snd_pcm_substream *substream); +extern int pxa2xx_soc_pcm_trigger(struct snd_soc_component *component, + struct snd_pcm_substream *substream, int cmd); +extern snd_pcm_uframes_t +pxa2xx_soc_pcm_pointer(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + +/* AC97 */ + +extern int pxa2xx_ac97_read(int slot, unsigned short reg); +extern int pxa2xx_ac97_write(int slot, unsigned short reg, unsigned short val); + +extern bool pxa2xx_ac97_try_warm_reset(void); +extern bool pxa2xx_ac97_try_cold_reset(void); +extern void pxa2xx_ac97_finish_reset(void); + +extern int pxa2xx_ac97_hw_suspend(void); +extern int pxa2xx_ac97_hw_resume(void); + +extern int pxa2xx_ac97_hw_probe(struct platform_device *dev); +extern void pxa2xx_ac97_hw_remove(struct platform_device *dev); + +/* modem registers, used by touchscreen driver */ +u32 pxa2xx_ac97_read_modr(void); +u32 pxa2xx_ac97_read_misr(void); + +#endif diff --git a/include/sound/rawmidi.h b/include/sound/rawmidi.h new file mode 100644 index 000000000..e1f59b294 --- /dev/null +++ b/include/sound/rawmidi.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_RAWMIDI_H +#define __SOUND_RAWMIDI_H + +/* + * Abstract layer for MIDI v1.0 stream + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + */ + +#include <sound/asound.h> +#include <linux/interrupt.h> +#include <linux/spinlock.h> +#include <linux/wait.h> +#include <linux/mutex.h> +#include <linux/workqueue.h> +#include <linux/device.h> + +#if IS_ENABLED(CONFIG_SND_SEQUENCER) +#include <sound/seq_device.h> +#endif + +/* + * Raw MIDI interface + */ + +#define SNDRV_RAWMIDI_DEVICES 8 + +#define SNDRV_RAWMIDI_LFLG_OUTPUT (1<<0) +#define SNDRV_RAWMIDI_LFLG_INPUT (1<<1) +#define SNDRV_RAWMIDI_LFLG_OPEN (3<<0) +#define SNDRV_RAWMIDI_LFLG_APPEND (1<<2) + +struct snd_rawmidi; +struct snd_rawmidi_substream; +struct snd_seq_port_info; +struct pid; + +struct snd_rawmidi_ops { + int (*open) (struct snd_rawmidi_substream * substream); + int (*close) (struct snd_rawmidi_substream * substream); + void (*trigger) (struct snd_rawmidi_substream * substream, int up); + void (*drain) (struct snd_rawmidi_substream * substream); +}; + +struct snd_rawmidi_global_ops { + int (*dev_register) (struct snd_rawmidi * rmidi); + int (*dev_unregister) (struct snd_rawmidi * rmidi); + void (*get_port_info)(struct snd_rawmidi *rmidi, int number, + struct snd_seq_port_info *info); +}; + +struct snd_rawmidi_runtime { + struct snd_rawmidi_substream *substream; + unsigned int drain: 1, /* drain stage */ + oss: 1; /* OSS compatible mode */ + /* midi stream buffer */ + unsigned char *buffer; /* buffer for MIDI data */ + size_t buffer_size; /* size of buffer */ + size_t appl_ptr; /* application pointer */ + size_t hw_ptr; /* hardware pointer */ + size_t avail_min; /* min avail for wakeup */ + size_t avail; /* max used buffer for wakeup */ + size_t xruns; /* over/underruns counter */ + int buffer_ref; /* buffer reference count */ + /* misc */ + wait_queue_head_t sleep; + /* event handler (new bytes, input only) */ + void (*event)(struct snd_rawmidi_substream *substream); + /* defers calls to event [input] or ops->trigger [output] */ + struct work_struct event_work; + /* private data */ + void *private_data; + void (*private_free)(struct snd_rawmidi_substream *substream); +}; + +struct snd_rawmidi_substream { + struct list_head list; /* list of all substream for given stream */ + int stream; /* direction */ + int number; /* substream number */ + bool opened; /* open flag */ + bool append; /* append flag (merge more streams) */ + bool active_sensing; /* send active sensing when close */ + unsigned int framing; /* whether to frame input data */ + unsigned int clock_type; /* clock source to use for input framing */ + int use_count; /* use counter (for output) */ + size_t bytes; + spinlock_t lock; + struct snd_rawmidi *rmidi; + struct snd_rawmidi_str *pstr; + char name[32]; + struct snd_rawmidi_runtime *runtime; + struct pid *pid; + /* hardware layer */ + const struct snd_rawmidi_ops *ops; +}; + +struct snd_rawmidi_file { + struct snd_rawmidi *rmidi; + struct snd_rawmidi_substream *input; + struct snd_rawmidi_substream *output; + unsigned int user_pversion; /* supported protocol version */ +}; + +struct snd_rawmidi_str { + unsigned int substream_count; + unsigned int substream_opened; + struct list_head substreams; +}; + +struct snd_rawmidi { + struct snd_card *card; + struct list_head list; + unsigned int device; /* device number */ + unsigned int info_flags; /* SNDRV_RAWMIDI_INFO_XXXX */ + char id[64]; + char name[80]; + +#ifdef CONFIG_SND_OSSEMUL + int ossreg; +#endif + + const struct snd_rawmidi_global_ops *ops; + + struct snd_rawmidi_str streams[2]; + + void *private_data; + void (*private_free) (struct snd_rawmidi *rmidi); + + struct mutex open_mutex; + wait_queue_head_t open_wait; + + struct device dev; + + struct snd_info_entry *proc_entry; + +#if IS_ENABLED(CONFIG_SND_SEQUENCER) + struct snd_seq_device *seq_dev; +#endif +}; + +/* main rawmidi functions */ + +int snd_rawmidi_new(struct snd_card *card, char *id, int device, + int output_count, int input_count, + struct snd_rawmidi **rmidi); +void snd_rawmidi_set_ops(struct snd_rawmidi *rmidi, int stream, + const struct snd_rawmidi_ops *ops); + +/* callbacks */ + +int snd_rawmidi_receive(struct snd_rawmidi_substream *substream, + const unsigned char *buffer, int count); +int snd_rawmidi_transmit_empty(struct snd_rawmidi_substream *substream); +int snd_rawmidi_transmit_peek(struct snd_rawmidi_substream *substream, + unsigned char *buffer, int count); +int snd_rawmidi_transmit_ack(struct snd_rawmidi_substream *substream, int count); +int snd_rawmidi_transmit(struct snd_rawmidi_substream *substream, + unsigned char *buffer, int count); +int snd_rawmidi_proceed(struct snd_rawmidi_substream *substream); + +/* main midi functions */ + +int snd_rawmidi_info_select(struct snd_card *card, struct snd_rawmidi_info *info); +int snd_rawmidi_kernel_open(struct snd_card *card, int device, int subdevice, + int mode, struct snd_rawmidi_file *rfile); +int snd_rawmidi_kernel_release(struct snd_rawmidi_file *rfile); +int snd_rawmidi_output_params(struct snd_rawmidi_substream *substream, + struct snd_rawmidi_params *params); +int snd_rawmidi_input_params(struct snd_rawmidi_substream *substream, + struct snd_rawmidi_params *params); +int snd_rawmidi_drop_output(struct snd_rawmidi_substream *substream); +int snd_rawmidi_drain_output(struct snd_rawmidi_substream *substream); +int snd_rawmidi_drain_input(struct snd_rawmidi_substream *substream); +long snd_rawmidi_kernel_read(struct snd_rawmidi_substream *substream, + unsigned char *buf, long count); +long snd_rawmidi_kernel_write(struct snd_rawmidi_substream *substream, + const unsigned char *buf, long count); + +#endif /* __SOUND_RAWMIDI_H */ diff --git a/include/sound/rt1015.h b/include/sound/rt1015.h new file mode 100644 index 000000000..70a7538d4 --- /dev/null +++ b/include/sound/rt1015.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt1015.h -- Platform data for RT1015 + * + * Copyright 2020 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT1015_H +#define __LINUX_SND_RT1015_H + +struct rt1015_platform_data { + unsigned int power_up_delay_ms; +}; + +#endif diff --git a/include/sound/rt286.h b/include/sound/rt286.h new file mode 100644 index 000000000..df1269a39 --- /dev/null +++ b/include/sound/rt286.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt286.h -- Platform data for RT286 + * + * Copyright 2013 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT286_H +#define __LINUX_SND_RT286_H + +struct rt286_platform_data { + bool cbj_en; /*combo jack enable*/ + bool gpio2_en; /*GPIO2 enable*/ +}; + +#endif diff --git a/include/sound/rt298.h b/include/sound/rt298.h new file mode 100644 index 000000000..cc8053878 --- /dev/null +++ b/include/sound/rt298.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt286.h -- Platform data for RT286 + * + * Copyright 2013 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT298_H +#define __LINUX_SND_RT298_H + +struct rt298_platform_data { + bool cbj_en; /*combo jack enable*/ + bool gpio2_en; /*GPIO2 enable*/ + bool suspend_power_off; /* power is off during suspend */ +}; + +#endif diff --git a/include/sound/rt5514.h b/include/sound/rt5514.h new file mode 100644 index 000000000..3e155e7d8 --- /dev/null +++ b/include/sound/rt5514.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5514.h -- Platform data for RT5514 + * + * Copyright 2016 Realtek Semiconductor Corp. + * Author: Oder Chiou <oder_chiou@realtek.com> + */ + +#ifndef __LINUX_SND_RT5514_H +#define __LINUX_SND_RT5514_H + +struct rt5514_platform_data { + unsigned int dmic_init_delay; + const char *dsp_calib_clk_name; + unsigned int dsp_calib_clk_rate; +}; + +#endif + diff --git a/include/sound/rt5659.h b/include/sound/rt5659.h new file mode 100644 index 000000000..d495311df --- /dev/null +++ b/include/sound/rt5659.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5659.h -- Platform data for RT5659 + * + * Copyright 2013 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT5659_H +#define __LINUX_SND_RT5659_H + +enum rt5659_dmic1_data_pin { + RT5659_DMIC1_NULL, + RT5659_DMIC1_DATA_IN2N, + RT5659_DMIC1_DATA_GPIO5, + RT5659_DMIC1_DATA_GPIO9, + RT5659_DMIC1_DATA_GPIO11, +}; + +enum rt5659_dmic2_data_pin { + RT5659_DMIC2_NULL, + RT5659_DMIC2_DATA_IN2P, + RT5659_DMIC2_DATA_GPIO6, + RT5659_DMIC2_DATA_GPIO10, + RT5659_DMIC2_DATA_GPIO12, +}; + +enum rt5659_jd_src { + RT5659_JD_NULL, + RT5659_JD3, + RT5659_JD_HDA_HEADER, +}; + +struct rt5659_platform_data { + bool in1_diff; + bool in3_diff; + bool in4_diff; + + int ldo1_en; /* GPIO for LDO1_EN */ + int reset; /* GPIO for RESET */ + + enum rt5659_dmic1_data_pin dmic1_data_pin; + enum rt5659_dmic2_data_pin dmic2_data_pin; + enum rt5659_jd_src jd_src; +}; + +#endif + diff --git a/include/sound/rt5660.h b/include/sound/rt5660.h new file mode 100644 index 000000000..7e8656cec --- /dev/null +++ b/include/sound/rt5660.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5660.h -- Platform data for RT5660 + * + * Copyright 2016 Realtek Semiconductor Corp. + * Author: Oder Chiou <oder_chiou@realtek.com> + */ + +#ifndef __LINUX_SND_RT5660_H +#define __LINUX_SND_RT5660_H + +enum rt5660_dmic1_data_pin { + RT5660_DMIC1_NULL, + RT5660_DMIC1_DATA_GPIO2, + RT5660_DMIC1_DATA_IN1P, +}; + +struct rt5660_platform_data { + /* IN1 & IN3 can optionally be differential */ + bool in1_diff; + bool in3_diff; + bool use_ldo2; + bool poweroff_codec_in_suspend; + + enum rt5660_dmic1_data_pin dmic1_data_pin; +}; + +#endif diff --git a/include/sound/rt5663.h b/include/sound/rt5663.h new file mode 100644 index 000000000..a864cb5c2 --- /dev/null +++ b/include/sound/rt5663.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5663.h -- Platform data for RT5663 + * + * Copyright 2017 Realtek Semiconductor Corp. + */ + +#ifndef __LINUX_SND_RT5663_H +#define __LINUX_SND_RT5663_H + +struct rt5663_platform_data { + unsigned int dc_offset_l_manual; + unsigned int dc_offset_r_manual; + unsigned int dc_offset_l_manual_mic; + unsigned int dc_offset_r_manual_mic; + + unsigned int impedance_sensing_num; + unsigned int *impedance_sensing_table; +}; + +#endif + diff --git a/include/sound/rt5665.h b/include/sound/rt5665.h new file mode 100644 index 000000000..3b3d6a19c --- /dev/null +++ b/include/sound/rt5665.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5665.h -- Platform data for RT5665 + * + * Copyright 2016 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT5665_H +#define __LINUX_SND_RT5665_H + +enum rt5665_dmic1_data_pin { + RT5665_DMIC1_NULL, + RT5665_DMIC1_DATA_GPIO4, + RT5665_DMIC1_DATA_IN2N, +}; + +enum rt5665_dmic2_data_pin { + RT5665_DMIC2_NULL, + RT5665_DMIC2_DATA_GPIO5, + RT5665_DMIC2_DATA_IN2P, +}; + +enum rt5665_jd_src { + RT5665_JD_NULL, + RT5665_JD1, +}; + +struct rt5665_platform_data { + bool in1_diff; + bool in2_diff; + bool in3_diff; + bool in4_diff; + + int ldo1_en; /* GPIO for LDO1_EN */ + + enum rt5665_dmic1_data_pin dmic1_data_pin; + enum rt5665_dmic2_data_pin dmic2_data_pin; + enum rt5665_jd_src jd_src; + + unsigned int sar_hs_type; +}; + +#endif + diff --git a/include/sound/rt5668.h b/include/sound/rt5668.h new file mode 100644 index 000000000..182edfbc9 --- /dev/null +++ b/include/sound/rt5668.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5668.h -- Platform data for RT5668 + * + * Copyright 2018 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT5668_H +#define __LINUX_SND_RT5668_H + +enum rt5668_dmic1_data_pin { + RT5668_DMIC1_NULL, + RT5668_DMIC1_DATA_GPIO2, + RT5668_DMIC1_DATA_GPIO5, +}; + +enum rt5668_dmic1_clk_pin { + RT5668_DMIC1_CLK_GPIO1, + RT5668_DMIC1_CLK_GPIO3, +}; + +enum rt5668_jd_src { + RT5668_JD_NULL, + RT5668_JD1, +}; + +struct rt5668_platform_data { + + int ldo1_en; /* GPIO for LDO1_EN */ + + enum rt5668_dmic1_data_pin dmic1_data_pin; + enum rt5668_dmic1_clk_pin dmic1_clk_pin; + enum rt5668_jd_src jd_src; +}; + +#endif + diff --git a/include/sound/rt5682.h b/include/sound/rt5682.h new file mode 100644 index 000000000..3900a07e3 --- /dev/null +++ b/include/sound/rt5682.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5682.h -- Platform data for RT5682 + * + * Copyright 2018 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT5682_H +#define __LINUX_SND_RT5682_H + +enum rt5682_dmic1_data_pin { + RT5682_DMIC1_NULL, + RT5682_DMIC1_DATA_GPIO2, + RT5682_DMIC1_DATA_GPIO5, +}; + +enum rt5682_dmic1_clk_pin { + RT5682_DMIC1_CLK_GPIO1, + RT5682_DMIC1_CLK_GPIO3, +}; + +enum rt5682_jd_src { + RT5682_JD_NULL, + RT5682_JD1, +}; + +enum rt5682_dai_clks { + RT5682_DAI_WCLK_IDX, + RT5682_DAI_BCLK_IDX, + RT5682_DAI_NUM_CLKS, +}; + +struct rt5682_platform_data { + + int ldo1_en; /* GPIO for LDO1_EN */ + + enum rt5682_dmic1_data_pin dmic1_data_pin; + enum rt5682_dmic1_clk_pin dmic1_clk_pin; + enum rt5682_jd_src jd_src; + unsigned int btndet_delay; + unsigned int dmic_clk_rate; + unsigned int dmic_delay; + bool dmic_clk_driving_high; + + const char *dai_clk_names[RT5682_DAI_NUM_CLKS]; +}; + +#endif + diff --git a/include/sound/rt5682s.h b/include/sound/rt5682s.h new file mode 100644 index 000000000..f18d91308 --- /dev/null +++ b/include/sound/rt5682s.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/rt5682s.h -- Platform data for RT5682I-VS + * + * Copyright 2021 Realtek Microelectronics + */ + +#ifndef __LINUX_SND_RT5682S_H +#define __LINUX_SND_RT5682S_H + +enum rt5682s_dmic1_data_pin { + RT5682S_DMIC1_DATA_NULL, + RT5682S_DMIC1_DATA_GPIO2, + RT5682S_DMIC1_DATA_GPIO5, +}; + +enum rt5682s_dmic1_clk_pin { + RT5682S_DMIC1_CLK_NULL, + RT5682S_DMIC1_CLK_GPIO1, + RT5682S_DMIC1_CLK_GPIO3, +}; + +enum rt5682s_jd_src { + RT5682S_JD_NULL, + RT5682S_JD1, +}; + +enum rt5682s_dai_clks { + RT5682S_DAI_WCLK_IDX, + RT5682S_DAI_BCLK_IDX, + RT5682S_DAI_NUM_CLKS, +}; + +struct rt5682s_platform_data { + + int ldo1_en; /* GPIO for LDO1_EN */ + + enum rt5682s_dmic1_data_pin dmic1_data_pin; + enum rt5682s_dmic1_clk_pin dmic1_clk_pin; + enum rt5682s_jd_src jd_src; + unsigned int dmic_clk_rate; + unsigned int dmic_delay; + unsigned int amic_delay; + bool dmic_clk_driving_high; + + const char *dai_clk_names[RT5682S_DAI_NUM_CLKS]; +}; + +#endif diff --git a/include/sound/s3c24xx_uda134x.h b/include/sound/s3c24xx_uda134x.h new file mode 100644 index 000000000..0232b80ff --- /dev/null +++ b/include/sound/s3c24xx_uda134x.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _S3C24XX_UDA134X_H_ +#define _S3C24XX_UDA134X_H_ 1 + +#include <sound/uda134x.h> + +struct s3c24xx_uda134x_platform_data { + int l3_clk; + int l3_mode; + int l3_data; + int model; +}; + +#endif diff --git a/include/sound/sb.h b/include/sound/sb.h new file mode 100644 index 000000000..f540339fb --- /dev/null +++ b/include/sound/sb.h @@ -0,0 +1,360 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SB_H +#define __SOUND_SB_H + +/* + * Header file for SoundBlaster cards + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + */ + +#include <sound/pcm.h> +#include <sound/rawmidi.h> +#include <linux/interrupt.h> +#include <linux/io.h> + +enum sb_hw_type { + SB_HW_AUTO, + SB_HW_10, + SB_HW_20, + SB_HW_201, + SB_HW_PRO, + SB_HW_JAZZ16, /* Media Vision Jazz16 */ + SB_HW_16, + SB_HW_16CSP, /* SB16 with CSP chip */ + SB_HW_ALS100, /* Avance Logic ALS100 chip */ + SB_HW_ALS4000, /* Avance Logic ALS4000 chip */ + SB_HW_DT019X, /* Diamond Tech. DT-019X / Avance Logic ALS-007 */ + SB_HW_CS5530, /* Cyrix/NatSemi 5530 VSA1 */ +}; + +#define SB_OPEN_PCM 0x01 +#define SB_OPEN_MIDI_INPUT 0x02 +#define SB_OPEN_MIDI_OUTPUT 0x04 +#define SB_OPEN_MIDI_INPUT_TRIGGER 0x08 +#define SB_OPEN_MIDI_OUTPUT_TRIGGER 0x10 + +#define SB_MODE_HALT 0x00 +#define SB_MODE_PLAYBACK_8 0x01 +#define SB_MODE_PLAYBACK_16 0x02 +#define SB_MODE_PLAYBACK (SB_MODE_PLAYBACK_8 | SB_MODE_PLAYBACK_16) +#define SB_MODE_CAPTURE_8 0x04 +#define SB_MODE_CAPTURE_16 0x08 +#define SB_MODE_CAPTURE (SB_MODE_CAPTURE_8 | SB_MODE_CAPTURE_16) + +#define SB_RATE_LOCK_PLAYBACK 0x10 +#define SB_RATE_LOCK_CAPTURE 0x20 +#define SB_RATE_LOCK (SB_RATE_LOCK_PLAYBACK | SB_RATE_LOCK_CAPTURE) + +#define SB_MPU_INPUT 1 + +struct snd_sb { + unsigned long port; /* base port of DSP chip */ + struct resource *res_port; + unsigned long mpu_port; /* MPU port for SB DSP 4.0+ */ + int irq; /* IRQ number of DSP chip */ + int dma8; /* 8-bit DMA */ + int dma16; /* 16-bit DMA */ + unsigned short version; /* version of DSP chip */ + enum sb_hw_type hardware; /* see to SB_HW_XXXX */ + + unsigned long alt_port; /* alternate port (ALS4000) */ + struct pci_dev *pci; /* ALS4000 */ + + unsigned int open; /* see to SB_OPEN_XXXX for sb8 */ + /* also SNDRV_SB_CSP_MODE_XXX for sb16_csp */ + unsigned int mode; /* current mode of stream */ + unsigned int force_mode16; /* force 16-bit mode of streams */ + unsigned int locked_rate; /* sb16 duplex */ + unsigned int playback_format; + unsigned int capture_format; + struct timer_list midi_timer; + unsigned int p_dma_size; + unsigned int p_period_size; + unsigned int c_dma_size; + unsigned int c_period_size; + + spinlock_t mixer_lock; + + char name[32]; + + void *csp; /* used only when CONFIG_SND_SB16_CSP is set */ + + struct snd_card *card; + struct snd_pcm *pcm; + struct snd_pcm_substream *playback_substream; + struct snd_pcm_substream *capture_substream; + + struct snd_rawmidi *rmidi; + struct snd_rawmidi_substream *midi_substream_input; + struct snd_rawmidi_substream *midi_substream_output; + irq_handler_t rmidi_callback; + + spinlock_t reg_lock; + spinlock_t open_lock; + spinlock_t midi_input_lock; + + struct snd_info_entry *proc_entry; + +#ifdef CONFIG_PM + unsigned char saved_regs[0x20]; +#endif +}; + +/* I/O ports */ + +#define SBP(chip, x) ((chip)->port + s_b_SB_##x) +#define SBP1(port, x) ((port) + s_b_SB_##x) + +#define s_b_SB_RESET 0x6 +#define s_b_SB_READ 0xa +#define s_b_SB_WRITE 0xc +#define s_b_SB_COMMAND 0xc +#define s_b_SB_STATUS 0xc +#define s_b_SB_DATA_AVAIL 0xe +#define s_b_SB_DATA_AVAIL_16 0xf +#define s_b_SB_MIXER_ADDR 0x4 +#define s_b_SB_MIXER_DATA 0x5 +#define s_b_SB_OPL3_LEFT 0x0 +#define s_b_SB_OPL3_RIGHT 0x2 +#define s_b_SB_OPL3_BOTH 0x8 + +#define SB_DSP_OUTPUT 0x14 +#define SB_DSP_INPUT 0x24 +#define SB_DSP_BLOCK_SIZE 0x48 +#define SB_DSP_HI_OUTPUT 0x91 +#define SB_DSP_HI_INPUT 0x99 +#define SB_DSP_LO_OUTPUT_AUTO 0x1c +#define SB_DSP_LO_INPUT_AUTO 0x2c +#define SB_DSP_HI_OUTPUT_AUTO 0x90 +#define SB_DSP_HI_INPUT_AUTO 0x98 +#define SB_DSP_IMMED_INT 0xf2 +#define SB_DSP_GET_VERSION 0xe1 +#define SB_DSP_SPEAKER_ON 0xd1 +#define SB_DSP_SPEAKER_OFF 0xd3 +#define SB_DSP_DMA8_OFF 0xd0 +#define SB_DSP_DMA8_ON 0xd4 +#define SB_DSP_DMA8_EXIT 0xda +#define SB_DSP_DMA16_OFF 0xd5 +#define SB_DSP_DMA16_ON 0xd6 +#define SB_DSP_DMA16_EXIT 0xd9 +#define SB_DSP_SAMPLE_RATE 0x40 +#define SB_DSP_SAMPLE_RATE_OUT 0x41 +#define SB_DSP_SAMPLE_RATE_IN 0x42 +#define SB_DSP_MONO_8BIT 0xa0 +#define SB_DSP_MONO_16BIT 0xa4 +#define SB_DSP_STEREO_8BIT 0xa8 +#define SB_DSP_STEREO_16BIT 0xac + +#define SB_DSP_MIDI_INPUT_IRQ 0x31 +#define SB_DSP_MIDI_UART_IRQ 0x35 +#define SB_DSP_MIDI_OUTPUT 0x38 + +#define SB_DSP4_OUT8_AI 0xc6 +#define SB_DSP4_IN8_AI 0xce +#define SB_DSP4_OUT16_AI 0xb6 +#define SB_DSP4_IN16_AI 0xbe +#define SB_DSP4_MODE_UNS_MONO 0x00 +#define SB_DSP4_MODE_SIGN_MONO 0x10 +#define SB_DSP4_MODE_UNS_STEREO 0x20 +#define SB_DSP4_MODE_SIGN_STEREO 0x30 + +#define SB_DSP4_OUTPUT 0x3c +#define SB_DSP4_INPUT_LEFT 0x3d +#define SB_DSP4_INPUT_RIGHT 0x3e + +/* registers for SB 2.0 mixer */ +#define SB_DSP20_MASTER_DEV 0x02 +#define SB_DSP20_PCM_DEV 0x0A +#define SB_DSP20_CD_DEV 0x08 +#define SB_DSP20_FM_DEV 0x06 + +/* registers for SB PRO mixer */ +#define SB_DSP_MASTER_DEV 0x22 +#define SB_DSP_PCM_DEV 0x04 +#define SB_DSP_LINE_DEV 0x2e +#define SB_DSP_CD_DEV 0x28 +#define SB_DSP_FM_DEV 0x26 +#define SB_DSP_MIC_DEV 0x0a +#define SB_DSP_CAPTURE_SOURCE 0x0c +#define SB_DSP_CAPTURE_FILT 0x0c +#define SB_DSP_PLAYBACK_FILT 0x0e +#define SB_DSP_STEREO_SW 0x0e + +#define SB_DSP_MIXS_MIC0 0x00 /* same as MIC */ +#define SB_DSP_MIXS_CD 0x01 +#define SB_DSP_MIXS_MIC 0x02 +#define SB_DSP_MIXS_LINE 0x03 + +/* registers (only for left channel) for SB 16 mixer */ +#define SB_DSP4_MASTER_DEV 0x30 +#define SB_DSP4_BASS_DEV 0x46 +#define SB_DSP4_TREBLE_DEV 0x44 +#define SB_DSP4_SYNTH_DEV 0x34 +#define SB_DSP4_PCM_DEV 0x32 +#define SB_DSP4_SPEAKER_DEV 0x3b +#define SB_DSP4_LINE_DEV 0x38 +#define SB_DSP4_MIC_DEV 0x3a +#define SB_DSP4_OUTPUT_SW 0x3c +#define SB_DSP4_CD_DEV 0x36 +#define SB_DSP4_IGAIN_DEV 0x3f +#define SB_DSP4_OGAIN_DEV 0x41 +#define SB_DSP4_MIC_AGC 0x43 + +/* additional registers for SB 16 mixer */ +#define SB_DSP4_IRQSETUP 0x80 +#define SB_DSP4_DMASETUP 0x81 +#define SB_DSP4_IRQSTATUS 0x82 +#define SB_DSP4_MPUSETUP 0x84 + +#define SB_DSP4_3DSE 0x90 + +/* Registers for DT-019x / ALS-007 mixer */ +#define SB_DT019X_MASTER_DEV 0x62 +#define SB_DT019X_PCM_DEV 0x64 +#define SB_DT019X_SYNTH_DEV 0x66 +#define SB_DT019X_CD_DEV 0x68 +#define SB_DT019X_MIC_DEV 0x6a +#define SB_DT019X_SPKR_DEV 0x6a +#define SB_DT019X_LINE_DEV 0x6e +#define SB_DT019X_OUTPUT_SW2 0x4c +#define SB_DT019X_CAPTURE_SW 0x6c + +#define SB_DT019X_CAP_CD 0x02 +#define SB_DT019X_CAP_MIC 0x04 +#define SB_DT019X_CAP_LINE 0x06 +#define SB_DT019X_CAP_SYNTH 0x07 +#define SB_DT019X_CAP_MAIN 0x07 + +#define SB_ALS4000_MONO_IO_CTRL 0x4b +#define SB_ALS4000_OUT_MIXER_CTRL_2 0x4c +#define SB_ALS4000_MIC_IN_GAIN 0x4d +#define SB_ALS4000_ANALOG_REFRNC_VOLT_CTRL 0x4e +#define SB_ALS4000_FMDAC 0x4f +#define SB_ALS4000_3D_SND_FX 0x50 +#define SB_ALS4000_3D_TIME_DELAY 0x51 +#define SB_ALS4000_3D_AUTO_MUTE 0x52 +#define SB_ALS4000_ANALOG_BLOCK_CTRL 0x53 +#define SB_ALS4000_3D_DELAYLINE_PATTERN 0x54 +#define SB_ALS4000_CR3_CONFIGURATION 0xc3 /* bit 7 is Digital Loop Enable */ +#define SB_ALS4000_QSOUND 0xdb + +/* IRQ setting bitmap */ +#define SB_IRQSETUP_IRQ9 0x01 +#define SB_IRQSETUP_IRQ5 0x02 +#define SB_IRQSETUP_IRQ7 0x04 +#define SB_IRQSETUP_IRQ10 0x08 + +/* IRQ types */ +#define SB_IRQTYPE_8BIT 0x01 +#define SB_IRQTYPE_16BIT 0x02 +#define SB_IRQTYPE_MPUIN 0x04 +#define ALS4K_IRQTYPE_CR1E_DMA 0x20 + +/* DMA setting bitmap */ +#define SB_DMASETUP_DMA0 0x01 +#define SB_DMASETUP_DMA1 0x02 +#define SB_DMASETUP_DMA3 0x08 +#define SB_DMASETUP_DMA5 0x20 +#define SB_DMASETUP_DMA6 0x40 +#define SB_DMASETUP_DMA7 0x80 + +/* + * + */ + +static inline void snd_sb_ack_8bit(struct snd_sb *chip) +{ + inb(SBP(chip, DATA_AVAIL)); +} + +static inline void snd_sb_ack_16bit(struct snd_sb *chip) +{ + inb(SBP(chip, DATA_AVAIL_16)); +} + +/* sb_common.c */ +int snd_sbdsp_command(struct snd_sb *chip, unsigned char val); +int snd_sbdsp_get_byte(struct snd_sb *chip); +int snd_sbdsp_reset(struct snd_sb *chip); +int snd_sbdsp_create(struct snd_card *card, + unsigned long port, + int irq, + irq_handler_t irq_handler, + int dma8, int dma16, + unsigned short hardware, + struct snd_sb **r_chip); +/* sb_mixer.c */ +void snd_sbmixer_write(struct snd_sb *chip, unsigned char reg, unsigned char data); +unsigned char snd_sbmixer_read(struct snd_sb *chip, unsigned char reg); +int snd_sbmixer_new(struct snd_sb *chip); +#ifdef CONFIG_PM +void snd_sbmixer_suspend(struct snd_sb *chip); +void snd_sbmixer_resume(struct snd_sb *chip); +#endif + +/* sb8_init.c */ +int snd_sb8dsp_pcm(struct snd_sb *chip, int device); +/* sb8.c */ +irqreturn_t snd_sb8dsp_interrupt(struct snd_sb *chip); +int snd_sb8_playback_open(struct snd_pcm_substream *substream); +int snd_sb8_capture_open(struct snd_pcm_substream *substream); +int snd_sb8_playback_close(struct snd_pcm_substream *substream); +int snd_sb8_capture_close(struct snd_pcm_substream *substream); +/* midi8.c */ +irqreturn_t snd_sb8dsp_midi_interrupt(struct snd_sb *chip); +int snd_sb8dsp_midi(struct snd_sb *chip, int device); + +/* sb16_init.c */ +int snd_sb16dsp_pcm(struct snd_sb *chip, int device); +const struct snd_pcm_ops *snd_sb16dsp_get_pcm_ops(int direction); +int snd_sb16dsp_configure(struct snd_sb *chip); +/* sb16.c */ +irqreturn_t snd_sb16dsp_interrupt(int irq, void *dev_id); + +/* exported mixer stuffs */ +enum { + SB_MIX_SINGLE, + SB_MIX_DOUBLE, + SB_MIX_INPUT_SW, + SB_MIX_CAPTURE_PRO, + SB_MIX_CAPTURE_DT019X, + SB_MIX_MONO_CAPTURE_ALS4K +}; + +#define SB_MIXVAL_DOUBLE(left_reg, right_reg, left_shift, right_shift, mask) \ + ((left_reg) | ((right_reg) << 8) | ((left_shift) << 16) | ((right_shift) << 19) | ((mask) << 24)) +#define SB_MIXVAL_SINGLE(reg, shift, mask) \ + ((reg) | ((shift) << 16) | ((mask) << 24)) +#define SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) \ + ((reg1) | ((reg2) << 8) | ((left_shift) << 16) | ((right_shift) << 24)) + +int snd_sbmixer_add_ctl(struct snd_sb *chip, const char *name, int index, int type, unsigned long value); + +/* for ease of use */ +struct sbmix_elem { + const char *name; + int type; + unsigned long private_value; +}; + +#define SB_SINGLE(xname, reg, shift, mask) \ +{ .name = xname, \ + .type = SB_MIX_SINGLE, \ + .private_value = SB_MIXVAL_SINGLE(reg, shift, mask) } + +#define SB_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask) \ +{ .name = xname, \ + .type = SB_MIX_DOUBLE, \ + .private_value = SB_MIXVAL_DOUBLE(left_reg, right_reg, left_shift, right_shift, mask) } + +#define SB16_INPUT_SW(xname, reg1, reg2, left_shift, right_shift) \ +{ .name = xname, \ + .type = SB_MIX_INPUT_SW, \ + .private_value = SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) } + +static inline int snd_sbmixer_add_ctl_elem(struct snd_sb *chip, const struct sbmix_elem *c) +{ + return snd_sbmixer_add_ctl(chip, c->name, 0, c->type, c->private_value); +} + +#endif /* __SOUND_SB_H */ diff --git a/include/sound/sb16_csp.h b/include/sound/sb16_csp.h new file mode 100644 index 000000000..cafd415e2 --- /dev/null +++ b/include/sound/sb16_csp.h @@ -0,0 +1,76 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (c) 1999 by Uros Bizjak <uros@kss-loka.si> + * Takashi Iwai <tiwai@suse.de> + * + * SB16ASP/AWE32 CSP control + */ +#ifndef __SOUND_SB16_CSP_H +#define __SOUND_SB16_CSP_H + +#include <sound/sb.h> +#include <sound/hwdep.h> +#include <linux/firmware.h> +#include <uapi/sound/sb16_csp.h> + +struct snd_sb_csp; + +/* indices for the known CSP programs */ +enum { + CSP_PROGRAM_MULAW, + CSP_PROGRAM_ALAW, + CSP_PROGRAM_ADPCM_INIT, + CSP_PROGRAM_ADPCM_PLAYBACK, + CSP_PROGRAM_ADPCM_CAPTURE, + + CSP_PROGRAM_COUNT +}; + +/* + * CSP operators + */ +struct snd_sb_csp_ops { + int (*csp_use) (struct snd_sb_csp * p); + int (*csp_unuse) (struct snd_sb_csp * p); + int (*csp_autoload) (struct snd_sb_csp * p, snd_pcm_format_t pcm_sfmt, int play_rec_mode); + int (*csp_start) (struct snd_sb_csp * p, int sample_width, int channels); + int (*csp_stop) (struct snd_sb_csp * p); + int (*csp_qsound_transfer) (struct snd_sb_csp * p); +}; + +/* + * CSP private data + */ +struct snd_sb_csp { + struct snd_sb *chip; /* SB16 DSP */ + int used; /* usage flag - exclusive */ + char codec_name[16]; /* name of codec */ + unsigned short func_nr; /* function number */ + unsigned int acc_format; /* accepted PCM formats */ + int acc_channels; /* accepted channels */ + int acc_width; /* accepted sample width */ + int acc_rates; /* accepted sample rates */ + int mode; /* MODE */ + int run_channels; /* current CSP channels */ + int run_width; /* current sample width */ + int version; /* CSP version (0x10 - 0x1f) */ + int running; /* running state */ + + struct snd_sb_csp_ops ops; /* operators */ + + spinlock_t q_lock; /* locking */ + int q_enabled; /* enabled flag */ + int qpos_left; /* left position */ + int qpos_right; /* right position */ + int qpos_changed; /* position changed flag */ + + struct snd_kcontrol *qsound_switch; + struct snd_kcontrol *qsound_space; + + struct mutex access_mutex; /* locking */ + + const struct firmware *csp_programs[CSP_PROGRAM_COUNT]; +}; + +int snd_sb_csp_new(struct snd_sb *chip, int device, struct snd_hwdep ** rhwdep); +#endif /* __SOUND_SB16_CSP */ diff --git a/include/sound/seq_device.h b/include/sound/seq_device.h new file mode 100644 index 000000000..8899affe9 --- /dev/null +++ b/include/sound/seq_device.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SEQ_DEVICE_H +#define __SOUND_SEQ_DEVICE_H + +/* + * ALSA sequencer device management + * Copyright (c) 1999 by Takashi Iwai <tiwai@suse.de> + */ + +/* + * registered device information + */ + +struct snd_seq_device { + /* device info */ + struct snd_card *card; /* sound card */ + int device; /* device number */ + const char *id; /* driver id */ + char name[80]; /* device name */ + int argsize; /* size of the argument */ + void *driver_data; /* private data for driver */ + void *private_data; /* private data for the caller */ + void (*private_free)(struct snd_seq_device *device); + struct device dev; +}; + +#define to_seq_dev(_dev) \ + container_of(_dev, struct snd_seq_device, dev) + +/* sequencer driver */ + +/* driver operators + * probe: + * Initialize the device with given parameters. + * Typically, + * 1. call snd_hwdep_new + * 2. allocate private data and initialize it + * 3. call snd_hwdep_register + * 4. store the instance to dev->driver_data pointer. + * + * remove: + * Release the private data. + * Typically, call snd_device_free(dev->card, dev->driver_data) + */ +struct snd_seq_driver { + struct device_driver driver; + char *id; + int argsize; +}; + +#define to_seq_drv(_drv) \ + container_of(_drv, struct snd_seq_driver, driver) + +/* + * prototypes + */ +#ifdef CONFIG_MODULES +void snd_seq_device_load_drivers(void); +#else +#define snd_seq_device_load_drivers() +#endif +int snd_seq_device_new(struct snd_card *card, int device, const char *id, + int argsize, struct snd_seq_device **result); + +#define SNDRV_SEQ_DEVICE_ARGPTR(dev) (void *)((char *)(dev) + sizeof(struct snd_seq_device)) + +int __must_check __snd_seq_driver_register(struct snd_seq_driver *drv, + struct module *mod); +#define snd_seq_driver_register(drv) \ + __snd_seq_driver_register(drv, THIS_MODULE) +void snd_seq_driver_unregister(struct snd_seq_driver *drv); + +#define module_snd_seq_driver(drv) \ + module_driver(drv, snd_seq_driver_register, snd_seq_driver_unregister) + +/* + * id strings for generic devices + */ +#define SNDRV_SEQ_DEV_ID_MIDISYNTH "seq-midi" +#define SNDRV_SEQ_DEV_ID_OPL3 "opl3-synth" + +#endif /* __SOUND_SEQ_DEVICE_H */ diff --git a/include/sound/seq_kernel.h b/include/sound/seq_kernel.h new file mode 100644 index 000000000..658911926 --- /dev/null +++ b/include/sound/seq_kernel.h @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SEQ_KERNEL_H +#define __SOUND_SEQ_KERNEL_H + +/* + * Main kernel header file for the ALSA sequencer + * Copyright (c) 1998 by Frank van de Pol <fvdpol@coil.demon.nl> + */ +#include <linux/time.h> +#include <sound/asequencer.h> + +typedef struct snd_seq_real_time snd_seq_real_time_t; +typedef union snd_seq_timestamp snd_seq_timestamp_t; + +/* maximum number of queues */ +#define SNDRV_SEQ_MAX_QUEUES 32 + +/* max number of concurrent clients */ +#define SNDRV_SEQ_MAX_CLIENTS 192 + +/* max number of concurrent ports */ +#define SNDRV_SEQ_MAX_PORTS 254 + +/* max number of events in memory pool */ +#define SNDRV_SEQ_MAX_EVENTS 2000 + +/* default number of events in memory pool */ +#define SNDRV_SEQ_DEFAULT_EVENTS 500 + +/* max number of events in memory pool for one client (outqueue) */ +#define SNDRV_SEQ_MAX_CLIENT_EVENTS 2000 + +/* default number of events in memory pool for one client (outqueue) */ +#define SNDRV_SEQ_DEFAULT_CLIENT_EVENTS 200 + +/* max delivery path length */ +/* NOTE: this shouldn't be greater than MAX_LOCKDEP_SUBCLASSES */ +#define SNDRV_SEQ_MAX_HOPS 8 + +/* max size of event size */ +#define SNDRV_SEQ_MAX_EVENT_LEN 0x3fffffff + +/* call-backs for kernel port */ +struct snd_seq_port_callback { + struct module *owner; + void *private_data; + int (*subscribe)(void *private_data, struct snd_seq_port_subscribe *info); + int (*unsubscribe)(void *private_data, struct snd_seq_port_subscribe *info); + int (*use)(void *private_data, struct snd_seq_port_subscribe *info); + int (*unuse)(void *private_data, struct snd_seq_port_subscribe *info); + int (*event_input)(struct snd_seq_event *ev, int direct, void *private_data, int atomic, int hop); + void (*private_free)(void *private_data); + /*...*/ +}; + +/* interface for kernel client */ +__printf(3, 4) +int snd_seq_create_kernel_client(struct snd_card *card, int client_index, + const char *name_fmt, ...); +int snd_seq_delete_kernel_client(int client); +int snd_seq_kernel_client_enqueue(int client, struct snd_seq_event *ev, + struct file *file, bool blocking); +int snd_seq_kernel_client_dispatch(int client, struct snd_seq_event *ev, int atomic, int hop); +int snd_seq_kernel_client_ctl(int client, unsigned int cmd, void *arg); + +#define SNDRV_SEQ_EXT_MASK 0xc0000000 +#define SNDRV_SEQ_EXT_USRPTR 0x80000000 +#define SNDRV_SEQ_EXT_CHAINED 0x40000000 + +typedef int (*snd_seq_dump_func_t)(void *ptr, void *buf, int count); +int snd_seq_expand_var_event(const struct snd_seq_event *event, int count, char *buf, + int in_kernel, int size_aligned); +int snd_seq_dump_var_event(const struct snd_seq_event *event, + snd_seq_dump_func_t func, void *private_data); + +/* interface for OSS emulation */ +int snd_seq_set_queue_tempo(int client, struct snd_seq_queue_tempo *tempo); + +/* port callback routines */ +void snd_port_init_callback(struct snd_seq_port_callback *p); +struct snd_seq_port_callback *snd_port_alloc_callback(void); + +/* port attach/detach */ +int snd_seq_event_port_attach(int client, struct snd_seq_port_callback *pcbp, + int cap, int type, int midi_channels, int midi_voices, char *portname); +int snd_seq_event_port_detach(int client, int port); + +#ifdef CONFIG_MODULES +void snd_seq_autoload_init(void); +void snd_seq_autoload_exit(void); +#else +#define snd_seq_autoload_init() +#define snd_seq_autoload_exit() +#endif + +#endif /* __SOUND_SEQ_KERNEL_H */ diff --git a/include/sound/seq_midi_emul.h b/include/sound/seq_midi_emul.h new file mode 100644 index 000000000..88799d1e1 --- /dev/null +++ b/include/sound/seq_midi_emul.h @@ -0,0 +1,184 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SEQ_MIDI_EMUL_H +#define __SOUND_SEQ_MIDI_EMUL_H + +/* + * Midi channel definition for optional channel management. + * + * Copyright (C) 1999 Steve Ratcliffe + */ + +#include <sound/seq_kernel.h> + +/* + * This structure is used to keep track of the current state on each + * channel. All drivers for hardware that does not understand midi + * directly will probably need to use this structure. + */ +struct snd_midi_channel { + void *private; /* A back pointer to driver data */ + int number; /* The channel number */ + int client; /* The client associated with this channel */ + int port; /* The port associated with this channel */ + + unsigned char midi_mode; /* GM, GS, XG etc */ + unsigned int + drum_channel:1, /* Drum channel */ + param_type:1 /* RPN/NRPN */ + ; + + unsigned char midi_aftertouch; /* Aftertouch (key pressure) */ + unsigned char midi_pressure; /* Channel pressure */ + unsigned char midi_program; /* Instrument number */ + short midi_pitchbend; /* Pitch bend amount */ + + unsigned char control[128]; /* Current value of all controls */ + unsigned char note[128]; /* Current status for all notes */ + + short gm_rpn_pitch_bend_range; /* Pitch bend range */ + short gm_rpn_fine_tuning; /* Master fine tuning */ + short gm_rpn_coarse_tuning; /* Master coarse tuning */ + +}; + +/* + * A structure that represets a set of channels bound to a port. There + * would usually be 16 channels per port. But fewer could be used for + * particular cases. + * The channel set consists of information describing the client and + * port for this midi synth and an array of snd_midi_channel structures. + * A driver that had no need for snd_midi_channel could still use the + * channel set type if it wished with the channel array null. + */ +struct snd_midi_channel_set { + void *private_data; /* Driver data */ + int client; /* Client for this port */ + int port; /* The port number */ + + int max_channels; /* Size of the channels array */ + struct snd_midi_channel *channels; + + unsigned char midi_mode; /* MIDI operating mode */ + unsigned char gs_master_volume; /* SYSEX master volume: 0-127 */ + unsigned char gs_chorus_mode; + unsigned char gs_reverb_mode; + +}; + +struct snd_midi_op { + void (*note_on)(void *private_data, int note, int vel, struct snd_midi_channel *chan); + void (*note_off)(void *private_data,int note, int vel, struct snd_midi_channel *chan); /* release note */ + void (*key_press)(void *private_data, int note, int vel, struct snd_midi_channel *chan); + void (*note_terminate)(void *private_data, int note, struct snd_midi_channel *chan); /* terminate note immediately */ + void (*control)(void *private_data, int type, struct snd_midi_channel *chan); + void (*nrpn)(void *private_data, struct snd_midi_channel *chan, + struct snd_midi_channel_set *chset); + void (*sysex)(void *private_data, unsigned char *buf, int len, int parsed, + struct snd_midi_channel_set *chset); +}; + +/* + * These defines are used so that pitchbend, aftertouch etc, can be + * distinguished from controller values. + */ +/* 0-127 controller values */ +#define MIDI_CTL_PITCHBEND 0x80 +#define MIDI_CTL_AFTERTOUCH 0x81 +#define MIDI_CTL_CHAN_PRESSURE 0x82 + +/* + * These names exist to allow symbolic access to the controls array. + * The usage is eg: chan->gm_bank_select. Another implementation would + * be really have these members in the struct, and not the array. + */ +#define gm_bank_select control[0] +#define gm_modulation control[1] +#define gm_breath control[2] +#define gm_foot_pedal control[4] +#define gm_portamento_time control[5] +#define gm_data_entry control[6] +#define gm_volume control[7] +#define gm_balance control[8] +#define gm_pan control[10] +#define gm_expression control[11] +#define gm_effect_control1 control[12] +#define gm_effect_control2 control[13] +#define gm_slider1 control[16] +#define gm_slider2 control[17] +#define gm_slider3 control[18] +#define gm_slider4 control[19] + +#define gm_bank_select_lsb control[32] +#define gm_modulation_wheel_lsb control[33] +#define gm_breath_lsb control[34] +#define gm_foot_pedal_lsb control[36] +#define gm_portamento_time_lsb control[37] +#define gm_data_entry_lsb control[38] +#define gm_volume_lsb control[39] +#define gm_balance_lsb control[40] +#define gm_pan_lsb control[42] +#define gm_expression_lsb control[43] +#define gm_effect_control1_lsb control[44] +#define gm_effect_control2_lsb control[45] + +#define gm_sustain control[MIDI_CTL_SUSTAIN] +#define gm_hold gm_sustain +#define gm_portamento control[MIDI_CTL_PORTAMENTO] +#define gm_sostenuto control[MIDI_CTL_SOSTENUTO] + +/* + * These macros give the complete value of the controls that consist + * of coarse and fine pairs. Of course the fine controls are seldom used + * but there is no harm in being complete. + */ +#define SNDRV_GM_BANK_SELECT(cp) (((cp)->control[0]<<7)|((cp)->control[32])) +#define SNDRV_GM_MODULATION_WHEEL(cp) (((cp)->control[1]<<7)|((cp)->control[33])) +#define SNDRV_GM_BREATH(cp) (((cp)->control[2]<<7)|((cp)->control[34])) +#define SNDRV_GM_FOOT_PEDAL(cp) (((cp)->control[4]<<7)|((cp)->control[36])) +#define SNDRV_GM_PORTAMENTO_TIME(cp) (((cp)->control[5]<<7)|((cp)->control[37])) +#define SNDRV_GM_DATA_ENTRY(cp) (((cp)->control[6]<<7)|((cp)->control[38])) +#define SNDRV_GM_VOLUME(cp) (((cp)->control[7]<<7)|((cp)->control[39])) +#define SNDRV_GM_BALANCE(cp) (((cp)->control[8]<<7)|((cp)->control[40])) +#define SNDRV_GM_PAN(cp) (((cp)->control[10]<<7)|((cp)->control[42])) +#define SNDRV_GM_EXPRESSION(cp) (((cp)->control[11]<<7)|((cp)->control[43])) + + +/* MIDI mode */ +#define SNDRV_MIDI_MODE_NONE 0 /* Generic midi */ +#define SNDRV_MIDI_MODE_GM 1 +#define SNDRV_MIDI_MODE_GS 2 +#define SNDRV_MIDI_MODE_XG 3 +#define SNDRV_MIDI_MODE_MT32 4 + +/* MIDI note state */ +#define SNDRV_MIDI_NOTE_OFF 0x00 +#define SNDRV_MIDI_NOTE_ON 0x01 +#define SNDRV_MIDI_NOTE_RELEASED 0x02 +#define SNDRV_MIDI_NOTE_SOSTENUTO 0x04 + +#define SNDRV_MIDI_PARAM_TYPE_REGISTERED 0 +#define SNDRV_MIDI_PARAM_TYPE_NONREGISTERED 1 + +/* SYSEX parse flag */ +enum { + SNDRV_MIDI_SYSEX_NOT_PARSED = 0, + SNDRV_MIDI_SYSEX_GM_ON, + SNDRV_MIDI_SYSEX_GS_ON, + SNDRV_MIDI_SYSEX_GS_RESET, + SNDRV_MIDI_SYSEX_GS_CHORUS_MODE, + SNDRV_MIDI_SYSEX_GS_REVERB_MODE, + SNDRV_MIDI_SYSEX_GS_MASTER_VOLUME, + SNDRV_MIDI_SYSEX_GS_PROGRAM, + SNDRV_MIDI_SYSEX_GS_DRUM_CHANNEL, + SNDRV_MIDI_SYSEX_XG_ON, +}; + +/* Prototypes for midi_process.c */ +void snd_midi_process_event(const struct snd_midi_op *ops, + struct snd_seq_event *ev, + struct snd_midi_channel_set *chanset); +void snd_midi_channel_set_clear(struct snd_midi_channel_set *chset); +struct snd_midi_channel_set *snd_midi_channel_alloc_set(int n); +void snd_midi_channel_free_set(struct snd_midi_channel_set *chset); + +#endif /* __SOUND_SEQ_MIDI_EMUL_H */ diff --git a/include/sound/seq_midi_event.h b/include/sound/seq_midi_event.h new file mode 100644 index 000000000..3b5d0d7e4 --- /dev/null +++ b/include/sound/seq_midi_event.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SEQ_MIDI_EVENT_H +#define __SOUND_SEQ_MIDI_EVENT_H + +/* + * MIDI byte <-> sequencer event coder + * + * Copyright (C) 1998,99 Takashi Iwai <tiwai@suse.de>, + * Jaroslav Kysela <perex@perex.cz> + */ + +#include <sound/asequencer.h> + +#define MAX_MIDI_EVENT_BUF 256 + +/* midi status */ +struct snd_midi_event { + int qlen; /* queue length */ + int read; /* chars read */ + int type; /* current event type */ + unsigned char lastcmd; /* last command (for MIDI state handling) */ + unsigned char nostat; /* no state flag */ + int bufsize; /* allocated buffer size */ + unsigned char *buf; /* input buffer */ + spinlock_t lock; +}; + +int snd_midi_event_new(int bufsize, struct snd_midi_event **rdev); +void snd_midi_event_free(struct snd_midi_event *dev); +void snd_midi_event_reset_encode(struct snd_midi_event *dev); +void snd_midi_event_reset_decode(struct snd_midi_event *dev); +void snd_midi_event_no_status(struct snd_midi_event *dev, int on); +bool snd_midi_event_encode_byte(struct snd_midi_event *dev, unsigned char c, + struct snd_seq_event *ev); +/* decode from event to bytes - return number of written bytes if success */ +long snd_midi_event_decode(struct snd_midi_event *dev, unsigned char *buf, long count, + struct snd_seq_event *ev); + +#endif /* __SOUND_SEQ_MIDI_EVENT_H */ diff --git a/include/sound/seq_oss.h b/include/sound/seq_oss.h new file mode 100644 index 000000000..7bf10a0fa --- /dev/null +++ b/include/sound/seq_oss.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SEQ_OSS_H +#define __SOUND_SEQ_OSS_H + +/* + * OSS compatible sequencer driver + * + * Copyright (C) 1998,99 Takashi Iwai + */ + +#include <sound/asequencer.h> +#include <sound/seq_kernel.h> + +/* + * argument structure for synthesizer operations + */ +struct snd_seq_oss_arg { + /* given by OSS sequencer */ + int app_index; /* application unique index */ + int file_mode; /* file mode - see below */ + int seq_mode; /* sequencer mode - see below */ + + /* following must be initialized in open callback */ + struct snd_seq_addr addr; /* opened port address */ + void *private_data; /* private data for lowlevel drivers */ + + /* note-on event passing mode: initially given by OSS seq, + * but configurable by drivers - see below + */ + int event_passing; +}; + + +/* + * synthesizer operation callbacks + */ +struct snd_seq_oss_callback { + struct module *owner; + int (*open)(struct snd_seq_oss_arg *p, void *closure); + int (*close)(struct snd_seq_oss_arg *p); + int (*ioctl)(struct snd_seq_oss_arg *p, unsigned int cmd, unsigned long arg); + int (*load_patch)(struct snd_seq_oss_arg *p, int format, const char __user *buf, int offs, int count); + int (*reset)(struct snd_seq_oss_arg *p); + int (*raw_event)(struct snd_seq_oss_arg *p, unsigned char *data); +}; + +/* flag: file_mode */ +#define SNDRV_SEQ_OSS_FILE_ACMODE 3 +#define SNDRV_SEQ_OSS_FILE_READ 1 +#define SNDRV_SEQ_OSS_FILE_WRITE 2 +#define SNDRV_SEQ_OSS_FILE_NONBLOCK 4 + +/* flag: seq_mode */ +#define SNDRV_SEQ_OSS_MODE_SYNTH 0 +#define SNDRV_SEQ_OSS_MODE_MUSIC 1 + +/* flag: event_passing */ +#define SNDRV_SEQ_OSS_PROCESS_EVENTS 0 /* key == 255 is processed as velocity change */ +#define SNDRV_SEQ_OSS_PASS_EVENTS 1 /* pass all events to callback */ +#define SNDRV_SEQ_OSS_PROCESS_KEYPRESS 2 /* key >= 128 will be processed as key-pressure */ + +/* default control rate: fixed */ +#define SNDRV_SEQ_OSS_CTRLRATE 100 + +/* default max queue length: configurable by module option */ +#define SNDRV_SEQ_OSS_MAX_QLEN 1024 + + +/* + * data pointer to snd_seq_register_device + */ +struct snd_seq_oss_reg { + int type; + int subtype; + int nvoices; + struct snd_seq_oss_callback oper; + void *private_data; +}; + +/* device id */ +#define SNDRV_SEQ_DEV_ID_OSS "seq-oss" + +#endif /* __SOUND_SEQ_OSS_H */ diff --git a/include/sound/seq_oss_legacy.h b/include/sound/seq_oss_legacy.h new file mode 100644 index 000000000..6cf2d7c0f --- /dev/null +++ b/include/sound/seq_oss_legacy.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SEQ_OSS_LEGACY_H +#define __SOUND_SEQ_OSS_LEGACY_H + +/* + * OSS compatible macro definitions + * + * Copyright (C) 2000 Abramo Bagnara <abramo@alsa-project.org> + */ + +#include <linux/soundcard.h> + +#ifndef SAMPLE_TYPE_AWE32 +#define SAMPLE_TYPE_AWE32 0x20 +#endif + +#endif /* __SOUND_SEQ_OSS_LEGACY_H */ + diff --git a/include/sound/seq_virmidi.h b/include/sound/seq_virmidi.h new file mode 100644 index 000000000..56a3f38df --- /dev/null +++ b/include/sound/seq_virmidi.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SEQ_VIRMIDI_H +#define __SOUND_SEQ_VIRMIDI_H + +/* + * Virtual Raw MIDI client on Sequencer + * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>, + * Jaroslav Kysela <perex@perex.cz> + */ + +#include <sound/rawmidi.h> +#include <sound/seq_midi_event.h> + +/* + * device file instance: + * This instance is created at each time the midi device file is + * opened. Each instance has its own input buffer and MIDI parser + * (buffer), and is associated with the device instance. + */ +struct snd_virmidi { + struct list_head list; + int seq_mode; + int client; + int port; + bool trigger; + struct snd_midi_event *parser; + struct snd_seq_event event; + struct snd_virmidi_dev *rdev; + struct snd_rawmidi_substream *substream; + struct work_struct output_work; +}; + +#define SNDRV_VIRMIDI_SUBSCRIBE (1<<0) +#define SNDRV_VIRMIDI_USE (1<<1) + +/* + * device record: + * Each virtual midi device has one device instance. It contains + * common information and the linked-list of opened files, + */ +struct snd_virmidi_dev { + struct snd_card *card; /* associated card */ + struct snd_rawmidi *rmidi; /* rawmidi device */ + int seq_mode; /* SNDRV_VIRMIDI_XXX */ + int device; /* sequencer device */ + int client; /* created/attached client */ + int port; /* created/attached port */ + unsigned int flags; /* SNDRV_VIRMIDI_* */ + rwlock_t filelist_lock; + struct rw_semaphore filelist_sem; + struct list_head filelist; +}; + +/* sequencer mode: + * ATTACH = input/output events from midi device are routed to the + * attached sequencer port. sequencer port is not created + * by virmidi itself. + * the input to rawmidi must be processed by passing the + * incoming events via snd_virmidi_receive() + * DISPATCH = input/output events are routed to subscribers. + * sequencer port is created in virmidi. + */ +#define SNDRV_VIRMIDI_SEQ_NONE 0 +#define SNDRV_VIRMIDI_SEQ_ATTACH 1 +#define SNDRV_VIRMIDI_SEQ_DISPATCH 2 + +int snd_virmidi_new(struct snd_card *card, int device, struct snd_rawmidi **rrmidi); + +#endif /* __SOUND_SEQ_VIRMIDI */ diff --git a/include/sound/sh_dac_audio.h b/include/sound/sh_dac_audio.h new file mode 100644 index 000000000..54f373e2a --- /dev/null +++ b/include/sound/sh_dac_audio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * SH_DAC specific configuration, for the dac_audio platform_device + * + * Copyright (C) 2009 Rafael Ignacio Zurita <rizurita@yahoo.com> + */ + +#ifndef __INCLUDE_SH_DAC_AUDIO_H +#define __INCLUDE_SH_DAC_AUDIO_H + +struct dac_audio_pdata { + int buffer_size; + int channel; + void (*start)(struct dac_audio_pdata *pd); + void (*stop)(struct dac_audio_pdata *pd); +}; + +#endif /* __INCLUDE_SH_DAC_AUDIO_H */ diff --git a/include/sound/sh_fsi.h b/include/sound/sh_fsi.h new file mode 100644 index 000000000..89eafe23e --- /dev/null +++ b/include/sound/sh_fsi.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Fifo-attached Serial Interface (FSI) support for SH7724 + * + * Copyright (C) 2009 Renesas Solutions Corp. + * Kuninori Morimoto <morimoto.kuninori@renesas.com> + */ +#ifndef __SOUND_FSI_H +#define __SOUND_FSI_H + +#include <linux/clk.h> +#include <sound/soc.h> + +/* + * flags + */ +#define SH_FSI_FMT_SPDIF (1 << 0) /* spdif for HDMI */ +#define SH_FSI_ENABLE_STREAM_MODE (1 << 1) /* for 16bit data */ +#define SH_FSI_CLK_CPG (1 << 2) /* FSIxCK + FSI-DIV */ + +struct sh_fsi_port_info { + unsigned long flags; + int tx_id; + int rx_id; +}; + +struct sh_fsi_platform_info { + struct sh_fsi_port_info port_a; + struct sh_fsi_port_info port_b; +}; + +#endif /* __SOUND_FSI_H */ diff --git a/include/sound/simple_card.h b/include/sound/simple_card.h new file mode 100644 index 000000000..d264e5463 --- /dev/null +++ b/include/sound/simple_card.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * ASoC simple sound card support + * + * Copyright (C) 2012 Renesas Solutions Corp. + * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + */ + +#ifndef __SIMPLE_CARD_H +#define __SIMPLE_CARD_H + +#include <sound/soc.h> +#include <sound/simple_card_utils.h> + +struct asoc_simple_card_info { + const char *name; + const char *card; + const char *codec; + const char *platform; + + unsigned int daifmt; + struct asoc_simple_dai cpu_dai; + struct asoc_simple_dai codec_dai; +}; + +#endif /* __SIMPLE_CARD_H */ diff --git a/include/sound/simple_card_utils.h b/include/sound/simple_card_utils.h new file mode 100644 index 000000000..25e049f44 --- /dev/null +++ b/include/sound/simple_card_utils.h @@ -0,0 +1,277 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * simple_card_utils.h + * + * Copyright (c) 2016 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + */ + +#ifndef __SIMPLE_CARD_UTILS_H +#define __SIMPLE_CARD_UTILS_H + +#include <linux/clk.h> +#include <sound/soc.h> + +#define asoc_simple_init_hp(card, sjack, prefix) \ + asoc_simple_init_jack(card, sjack, 1, prefix, NULL) +#define asoc_simple_init_mic(card, sjack, prefix) \ + asoc_simple_init_jack(card, sjack, 0, prefix, NULL) + +struct asoc_simple_tdm_width_map { + u8 sample_bits; + u8 slot_count; + u16 slot_width; +}; + +struct asoc_simple_dai { + const char *name; + unsigned int sysclk; + int clk_direction; + int slots; + int slot_width; + unsigned int tx_slot_mask; + unsigned int rx_slot_mask; + struct clk *clk; + bool clk_fixed; + struct asoc_simple_tdm_width_map *tdm_width_map; + int n_tdm_widths; +}; + +struct asoc_simple_data { + u32 convert_rate; + u32 convert_channels; + const char *convert_sample_format; +}; + +struct asoc_simple_jack { + struct snd_soc_jack jack; + struct snd_soc_jack_pin pin; + struct snd_soc_jack_gpio gpio; +}; + +struct prop_nums { + int cpus; + int codecs; + int platforms; +}; + +struct asoc_simple_priv { + struct snd_soc_card snd_card; + struct simple_dai_props { + struct asoc_simple_dai *cpu_dai; + struct asoc_simple_dai *codec_dai; + struct snd_soc_dai_link_component *cpus; + struct snd_soc_dai_link_component *codecs; + struct snd_soc_dai_link_component *platforms; + struct asoc_simple_data adata; + struct snd_soc_codec_conf *codec_conf; + struct prop_nums num; + unsigned int mclk_fs; + } *dai_props; + struct asoc_simple_jack hp_jack; + struct asoc_simple_jack mic_jack; + struct snd_soc_dai_link *dai_link; + struct asoc_simple_dai *dais; + struct snd_soc_dai_link_component *dlcs; + struct snd_soc_dai_link_component dummy; + struct snd_soc_codec_conf *codec_conf; + struct gpio_desc *pa_gpio; + const struct snd_soc_ops *ops; + unsigned int dpcm_selectable:1; + unsigned int force_dpcm:1; +}; +#define simple_priv_to_card(priv) (&(priv)->snd_card) +#define simple_priv_to_props(priv, i) ((priv)->dai_props + (i)) +#define simple_priv_to_dev(priv) (simple_priv_to_card(priv)->dev) +#define simple_priv_to_link(priv, i) (simple_priv_to_card(priv)->dai_link + (i)) + +#define simple_props_to_dlc_cpu(props, i) ((props)->cpus + i) +#define simple_props_to_dlc_codec(props, i) ((props)->codecs + i) +#define simple_props_to_dlc_platform(props, i) ((props)->platforms + i) + +#define simple_props_to_dai_cpu(props, i) ((props)->cpu_dai + i) +#define simple_props_to_dai_codec(props, i) ((props)->codec_dai + i) +#define simple_props_to_codec_conf(props, i) ((props)->codec_conf + i) + +#define for_each_prop_dlc_cpus(props, i, cpu) \ + for ((i) = 0; \ + ((i) < (props)->num.cpus) && \ + ((cpu) = simple_props_to_dlc_cpu(props, i)); \ + (i)++) +#define for_each_prop_dlc_codecs(props, i, codec) \ + for ((i) = 0; \ + ((i) < (props)->num.codecs) && \ + ((codec) = simple_props_to_dlc_codec(props, i)); \ + (i)++) +#define for_each_prop_dlc_platforms(props, i, platform) \ + for ((i) = 0; \ + ((i) < (props)->num.platforms) && \ + ((platform) = simple_props_to_dlc_platform(props, i)); \ + (i)++) +#define for_each_prop_codec_conf(props, i, conf) \ + for ((i) = 0; \ + ((i) < (props)->num.codecs) && \ + (props)->codec_conf && \ + ((conf) = simple_props_to_codec_conf(props, i)); \ + (i)++) + +#define for_each_prop_dai_cpu(props, i, cpu) \ + for ((i) = 0; \ + ((i) < (props)->num.cpus) && \ + ((cpu) = simple_props_to_dai_cpu(props, i)); \ + (i)++) +#define for_each_prop_dai_codec(props, i, codec) \ + for ((i) = 0; \ + ((i) < (props)->num.codecs) && \ + ((codec) = simple_props_to_dai_codec(props, i)); \ + (i)++) + +#define SNDRV_MAX_LINKS 512 + +struct link_info { + int link; /* number of link */ + int cpu; /* turn for CPU / Codec */ + struct prop_nums num[SNDRV_MAX_LINKS]; +}; + +int asoc_simple_parse_daifmt(struct device *dev, + struct device_node *node, + struct device_node *codec, + char *prefix, + unsigned int *retfmt); +int asoc_simple_parse_tdm_width_map(struct device *dev, struct device_node *np, + struct asoc_simple_dai *dai); + +__printf(3, 4) +int asoc_simple_set_dailink_name(struct device *dev, + struct snd_soc_dai_link *dai_link, + const char *fmt, ...); +int asoc_simple_parse_card_name(struct snd_soc_card *card, + char *prefix); + +int asoc_simple_parse_clk(struct device *dev, + struct device_node *node, + struct asoc_simple_dai *simple_dai, + struct snd_soc_dai_link_component *dlc); +int asoc_simple_startup(struct snd_pcm_substream *substream); +void asoc_simple_shutdown(struct snd_pcm_substream *substream); +int asoc_simple_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +int asoc_simple_dai_init(struct snd_soc_pcm_runtime *rtd); +int asoc_simple_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); + +#define asoc_simple_parse_tdm(np, dai) \ + snd_soc_of_parse_tdm_slot(np, &(dai)->tx_slot_mask, \ + &(dai)->rx_slot_mask, \ + &(dai)->slots, \ + &(dai)->slot_width); + +void asoc_simple_canonicalize_platform(struct snd_soc_dai_link_component *platforms, + struct snd_soc_dai_link_component *cpus); +void asoc_simple_canonicalize_cpu(struct snd_soc_dai_link_component *cpus, + int is_single_links); + +void asoc_simple_clean_reference(struct snd_soc_card *card); + +void asoc_simple_convert_fixup(struct asoc_simple_data *data, + struct snd_pcm_hw_params *params); +void asoc_simple_parse_convert(struct device_node *np, char *prefix, + struct asoc_simple_data *data); +bool asoc_simple_is_convert_required(const struct asoc_simple_data *data); + +int asoc_simple_parse_routing(struct snd_soc_card *card, + char *prefix); +int asoc_simple_parse_widgets(struct snd_soc_card *card, + char *prefix); +int asoc_simple_parse_pin_switches(struct snd_soc_card *card, + char *prefix); + +int asoc_simple_init_jack(struct snd_soc_card *card, + struct asoc_simple_jack *sjack, + int is_hp, char *prefix, char *pin); +int asoc_simple_init_priv(struct asoc_simple_priv *priv, + struct link_info *li); +int asoc_simple_remove(struct platform_device *pdev); + +int asoc_graph_card_probe(struct snd_soc_card *card); +int asoc_graph_is_ports0(struct device_node *port); + +#ifdef DEBUG +static inline void asoc_simple_debug_dai(struct asoc_simple_priv *priv, + char *name, + struct asoc_simple_dai *dai) +{ + struct device *dev = simple_priv_to_dev(priv); + + /* dai might be NULL */ + if (!dai) + return; + + if (dai->name) + dev_dbg(dev, "%s dai name = %s\n", + name, dai->name); + + if (dai->slots) + dev_dbg(dev, "%s slots = %d\n", name, dai->slots); + if (dai->slot_width) + dev_dbg(dev, "%s slot width = %d\n", name, dai->slot_width); + if (dai->tx_slot_mask) + dev_dbg(dev, "%s tx slot mask = %d\n", name, dai->tx_slot_mask); + if (dai->rx_slot_mask) + dev_dbg(dev, "%s rx slot mask = %d\n", name, dai->rx_slot_mask); + if (dai->clk) + dev_dbg(dev, "%s clk %luHz\n", name, clk_get_rate(dai->clk)); + if (dai->sysclk) + dev_dbg(dev, "%s sysclk = %dHz\n", + name, dai->sysclk); + if (dai->clk || dai->sysclk) + dev_dbg(dev, "%s direction = %s\n", + name, dai->clk_direction ? "OUT" : "IN"); +} + +static inline void asoc_simple_debug_info(struct asoc_simple_priv *priv) +{ + struct snd_soc_card *card = simple_priv_to_card(priv); + struct device *dev = simple_priv_to_dev(priv); + + int i; + + if (card->name) + dev_dbg(dev, "Card Name: %s\n", card->name); + + for (i = 0; i < card->num_links; i++) { + struct simple_dai_props *props = simple_priv_to_props(priv, i); + struct snd_soc_dai_link *link = simple_priv_to_link(priv, i); + struct asoc_simple_dai *dai; + struct snd_soc_codec_conf *cnf; + int j; + + dev_dbg(dev, "DAI%d\n", i); + + dev_dbg(dev, "cpu num = %d\n", link->num_cpus); + for_each_prop_dai_cpu(props, j, dai) + asoc_simple_debug_dai(priv, "cpu", dai); + dev_dbg(dev, "codec num = %d\n", link->num_codecs); + for_each_prop_dai_codec(props, j, dai) + asoc_simple_debug_dai(priv, "codec", dai); + + if (link->name) + dev_dbg(dev, "dai name = %s\n", link->name); + if (link->dai_fmt) + dev_dbg(dev, "dai format = %04x\n", link->dai_fmt); + if (props->adata.convert_rate) + dev_dbg(dev, "convert_rate = %d\n", props->adata.convert_rate); + if (props->adata.convert_channels) + dev_dbg(dev, "convert_channels = %d\n", props->adata.convert_channels); + for_each_prop_codec_conf(props, j, cnf) + if (cnf->name_prefix) + dev_dbg(dev, "name prefix = %s\n", cnf->name_prefix); + if (props->mclk_fs) + dev_dbg(dev, "mclk-fs = %d\n", props->mclk_fs); + } +} +#else +#define asoc_simple_debug_info(priv) +#endif /* DEBUG */ + +#endif /* __SIMPLE_CARD_UTILS_H */ diff --git a/include/sound/snd_wavefront.h b/include/sound/snd_wavefront.h new file mode 100644 index 000000000..55053557c --- /dev/null +++ b/include/sound/snd_wavefront.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __SOUND_SND_WAVEFRONT_H__ +#define __SOUND_SND_WAVEFRONT_H__ + +#include <sound/mpu401.h> +#include <sound/hwdep.h> +#include <sound/rawmidi.h> +#include <sound/wavefront.h> /* generic OSS/ALSA/user-level wavefront header */ + +/* MIDI interface */ + +struct _snd_wavefront_midi; +struct _snd_wavefront_card; +struct _snd_wavefront; + +typedef struct _snd_wavefront_midi snd_wavefront_midi_t; +typedef struct _snd_wavefront_card snd_wavefront_card_t; +typedef struct _snd_wavefront snd_wavefront_t; + +typedef enum { internal_mpu = 0, external_mpu = 1 } snd_wavefront_mpu_id; + +struct _snd_wavefront_midi { + unsigned long base; /* I/O port address */ + char isvirtual; /* doing virtual MIDI stuff ? */ + char istimer; /* timer is used */ + snd_wavefront_mpu_id output_mpu; /* most-recently-used */ + snd_wavefront_mpu_id input_mpu; /* most-recently-used */ + unsigned int mode[2]; /* MPU401_MODE_XXX */ + struct snd_rawmidi_substream *substream_output[2]; + struct snd_rawmidi_substream *substream_input[2]; + struct timer_list timer; + snd_wavefront_card_t *timer_card; + spinlock_t open; + spinlock_t virtual; /* protects isvirtual */ +}; + +#define OUTPUT_READY 0x40 +#define INPUT_AVAIL 0x80 +#define MPU_ACK 0xFE +#define UART_MODE_ON 0x3F + +extern const struct snd_rawmidi_ops snd_wavefront_midi_output; +extern const struct snd_rawmidi_ops snd_wavefront_midi_input; + +extern void snd_wavefront_midi_enable_virtual (snd_wavefront_card_t *); +extern void snd_wavefront_midi_disable_virtual (snd_wavefront_card_t *); +extern void snd_wavefront_midi_interrupt (snd_wavefront_card_t *); +extern int snd_wavefront_midi_start (snd_wavefront_card_t *); + +struct _snd_wavefront { + unsigned long irq; /* "you were one, one of the few ..." */ + unsigned long base; /* low i/o port address */ + struct resource *res_base; /* i/o port resource allocation */ + +#define mpu_data_port base +#define mpu_command_port base + 1 /* write semantics */ +#define mpu_status_port base + 1 /* read semantics */ +#define data_port base + 2 +#define status_port base + 3 /* read semantics */ +#define control_port base + 3 /* write semantics */ +#define block_port base + 4 /* 16 bit, writeonly */ +#define last_block_port base + 6 /* 16 bit, writeonly */ + + /* FX ports. These are mapped through the ICS2115 to the YS225. + The ICS2115 takes care of flipping the relevant pins on the + YS225 so that access to each of these ports does the right + thing. Note: these are NOT documented by Turtle Beach. + */ + +#define fx_status base + 8 +#define fx_op base + 8 +#define fx_lcr base + 9 +#define fx_dsp_addr base + 0xa +#define fx_dsp_page base + 0xb +#define fx_dsp_lsb base + 0xc +#define fx_dsp_msb base + 0xd +#define fx_mod_addr base + 0xe +#define fx_mod_data base + 0xf + + volatile int irq_ok; /* set by interrupt handler */ + volatile int irq_cnt; /* ditto */ + char debug; /* debugging flags */ + int freemem; /* installed RAM, in bytes */ + + char fw_version[2]; /* major = [0], minor = [1] */ + char hw_version[2]; /* major = [0], minor = [1] */ + char israw; /* needs Motorola microcode */ + char has_fx; /* has FX processor (Tropez+) */ + char fx_initialized; /* FX's register pages initialized */ + char prog_status[WF_MAX_PROGRAM]; /* WF_SLOT_* */ + char patch_status[WF_MAX_PATCH]; /* WF_SLOT_* */ + char sample_status[WF_MAX_SAMPLE]; /* WF_ST_* | WF_SLOT_* */ + int samples_used; /* how many */ + char interrupts_are_midi; /* h/w MPU interrupts enabled ? */ + char rom_samples_rdonly; /* can we write on ROM samples */ + spinlock_t irq_lock; + wait_queue_head_t interrupt_sleeper; + snd_wavefront_midi_t midi; /* ICS2115 MIDI interface */ + struct snd_card *card; +}; + +struct _snd_wavefront_card { + snd_wavefront_t wavefront; +#ifdef CONFIG_PNP + struct pnp_dev *wss; + struct pnp_dev *ctrl; + struct pnp_dev *mpu; + struct pnp_dev *synth; +#endif /* CONFIG_PNP */ +}; + +extern void snd_wavefront_internal_interrupt (snd_wavefront_card_t *card); +extern int snd_wavefront_detect_irq (snd_wavefront_t *dev) ; +extern int snd_wavefront_check_irq (snd_wavefront_t *dev, int irq); +extern int snd_wavefront_restart (snd_wavefront_t *dev); +extern int snd_wavefront_start (snd_wavefront_t *dev); +extern int snd_wavefront_detect (snd_wavefront_card_t *card); +extern int snd_wavefront_config_midi (snd_wavefront_t *dev) ; +extern int snd_wavefront_cmd (snd_wavefront_t *, int, unsigned char *, + unsigned char *); + +extern int snd_wavefront_synth_ioctl (struct snd_hwdep *, + struct file *, + unsigned int cmd, + unsigned long arg); +extern int snd_wavefront_synth_open (struct snd_hwdep *, struct file *); +extern int snd_wavefront_synth_release (struct snd_hwdep *, struct file *); + +/* FX processor - see also yss225.[ch] */ + +extern int snd_wavefront_fx_start (snd_wavefront_t *); +extern int snd_wavefront_fx_detect (snd_wavefront_t *); +extern int snd_wavefront_fx_ioctl (struct snd_hwdep *, + struct file *, + unsigned int cmd, + unsigned long arg); +extern int snd_wavefront_fx_open (struct snd_hwdep *, struct file *); +extern int snd_wavefront_fx_release (struct snd_hwdep *, struct file *); + +/* prefix in all snd_printk() delivered messages */ + +#define LOGNAME "WaveFront: " + +#endif /* __SOUND_SND_WAVEFRONT_H__ */ diff --git a/include/sound/soc-acpi-intel-match.h b/include/sound/soc-acpi-intel-match.h new file mode 100644 index 000000000..82a7db23d --- /dev/null +++ b/include/sound/soc-acpi-intel-match.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2017, Intel Corporation. All rights reserved. + */ + +#ifndef __LINUX_SND_SOC_ACPI_INTEL_MATCH_H +#define __LINUX_SND_SOC_ACPI_INTEL_MATCH_H + +#include <linux/module.h> +#include <linux/stddef.h> +#include <linux/acpi.h> + +/* + * these tables are not constants, some fields can be used for + * pdata or machine ops + */ +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_broadwell_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_baytrail_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cherrytrail_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_skl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_kbl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_bxt_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_glk_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cnl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cfl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cml_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_icl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_tgl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_ehl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_jsl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_adl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_rpl_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_mtl_machines[]; + +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cnl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cfl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_cml_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_icl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_tgl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_adl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_rpl_sdw_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_mtl_sdw_machines[]; + +/* + * generic table used for HDA codec-based platforms, possibly with + * additional ACPI-enumerated codecs + */ +extern struct snd_soc_acpi_mach snd_soc_acpi_intel_hda_machines[]; + +#endif diff --git a/include/sound/soc-acpi.h b/include/sound/soc-acpi.h new file mode 100644 index 000000000..1a5f90b0a --- /dev/null +++ b/include/sound/soc-acpi.h @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only + * + * Copyright (C) 2013-15, Intel Corporation. All rights reserved. + */ + +#ifndef __LINUX_SND_SOC_ACPI_H +#define __LINUX_SND_SOC_ACPI_H + +#include <linux/stddef.h> +#include <linux/acpi.h> +#include <linux/mod_devicetable.h> + +struct snd_soc_acpi_package_context { + char *name; /* package name */ + int length; /* number of elements */ + struct acpi_buffer *format; + struct acpi_buffer *state; + bool data_valid; +}; + +/* codec name is used in DAIs is i2c-<HID>:00 with HID being 8 chars */ +#define SND_ACPI_I2C_ID_LEN (4 + ACPI_ID_LEN + 3 + 1) + +#if IS_ENABLED(CONFIG_ACPI) +/* acpi match */ +struct snd_soc_acpi_mach * +snd_soc_acpi_find_machine(struct snd_soc_acpi_mach *machines); + +bool snd_soc_acpi_find_package_from_hid(const u8 hid[ACPI_ID_LEN], + struct snd_soc_acpi_package_context *ctx); + +/* check all codecs */ +struct snd_soc_acpi_mach *snd_soc_acpi_codec_list(void *arg); + +#else +/* acpi match */ +static inline struct snd_soc_acpi_mach * +snd_soc_acpi_find_machine(struct snd_soc_acpi_mach *machines) +{ + return NULL; +} + +static inline bool +snd_soc_acpi_find_package_from_hid(const u8 hid[ACPI_ID_LEN], + struct snd_soc_acpi_package_context *ctx) +{ + return false; +} + +/* check all codecs */ +static inline struct snd_soc_acpi_mach *snd_soc_acpi_codec_list(void *arg) +{ + return NULL; +} +#endif + +/** + * snd_soc_acpi_mach_params: interface for machine driver configuration + * + * @acpi_ipc_irq_index: used for BYT-CR detection + * @platform: string used for HDAudio codec support + * @codec_mask: used for HDAudio support + * @dmic_num: number of SoC- or chipset-attached PDM digital microphones + * @common_hdmi_codec_drv: use commom HDAudio HDMI codec driver + * @link_mask: SoundWire links enabled on the board + * @links: array of SoundWire link _ADR descriptors, null terminated + * @i2s_link_mask: I2S/TDM links enabled on the board + * @num_dai_drivers: number of elements in @dai_drivers + * @dai_drivers: pointer to dai_drivers, used e.g. in nocodec mode + * @subsystem_vendor: optional PCI SSID vendor value + * @subsystem_device: optional PCI SSID device value + * @subsystem_id_set: true if a value has been written to + * subsystem_vendor and subsystem_device. + */ +struct snd_soc_acpi_mach_params { + u32 acpi_ipc_irq_index; + const char *platform; + u32 codec_mask; + u32 dmic_num; + bool common_hdmi_codec_drv; + u32 link_mask; + const struct snd_soc_acpi_link_adr *links; + u32 i2s_link_mask; + u32 num_dai_drivers; + struct snd_soc_dai_driver *dai_drivers; + unsigned short subsystem_vendor; + unsigned short subsystem_device; + bool subsystem_id_set; +}; + +/** + * snd_soc_acpi_endpoint - endpoint descriptor + * @num: endpoint number (mandatory, unique per device) + * @aggregated: 0 (independent) or 1 (logically grouped) + * @group_position: zero-based order (only when @aggregated is 1) + * @group_id: platform-unique group identifier (only when @aggregrated is 1) + */ +struct snd_soc_acpi_endpoint { + u8 num; + u8 aggregated; + u8 group_position; + u8 group_id; +}; + +/** + * snd_soc_acpi_adr_device - descriptor for _ADR-enumerated device + * @adr: 64 bit ACPI _ADR value + * @num_endpoints: number of endpoints for this device + * @endpoints: array of endpoints + * @name_prefix: string used for codec controls + */ +struct snd_soc_acpi_adr_device { + const u64 adr; + const u8 num_endpoints; + const struct snd_soc_acpi_endpoint *endpoints; + const char *name_prefix; +}; + +/** + * snd_soc_acpi_link_adr - ACPI-based list of _ADR enumerated devices + * @mask: one bit set indicates the link this list applies to + * @num_adr: ARRAY_SIZE of devices + * @adr_d: array of devices + * + * The number of devices per link can be more than 1, e.g. in SoundWire + * multi-drop configurations. + */ + +struct snd_soc_acpi_link_adr { + const u32 mask; + const u32 num_adr; + const struct snd_soc_acpi_adr_device *adr_d; +}; + +/* + * when set the topology uses the -ssp<N> suffix, where N is determined based on + * BIOS or DMI information + */ +#define SND_SOC_ACPI_TPLG_INTEL_SSP_NUMBER BIT(0) + +/* + * when more than one SSP is reported in the link mask, use the most significant. + * This choice was found to be valid on platforms with ES8336 codecs. + */ +#define SND_SOC_ACPI_TPLG_INTEL_SSP_MSB BIT(1) + +/* + * when set the topology uses the -dmic<N>ch suffix, where N is determined based on + * BIOS or DMI information + */ +#define SND_SOC_ACPI_TPLG_INTEL_DMIC_NUMBER BIT(2) + +/** + * snd_soc_acpi_mach: ACPI-based machine descriptor. Most of the fields are + * related to the hardware, except for the firmware and topology file names. + * A platform supported by legacy and Sound Open Firmware (SOF) would expose + * all firmware/topology related fields. + * + * @id: ACPI ID (usually the codec's) used to find a matching machine driver. + * @comp_ids: list of compatible audio codecs using the same machine driver, + * firmware and topology + * @link_mask: describes required board layout, e.g. for SoundWire. + * @links: array of link _ADR descriptors, null terminated. + * @drv_name: machine driver name + * @fw_filename: firmware file name. Used when SOF is not enabled. + * @tplg_filename: topology file name. Used when SOF is not enabled. + * @board: board name + * @machine_quirk: pointer to quirk, usually based on DMI information when + * ACPI ID alone is not sufficient, wrong or misleading + * @quirk_data: data used to uniquely identify a machine, usually a list of + * audio codecs whose presence if checked with ACPI + * @pdata: intended for platform data or machine specific-ops. This structure + * is not constant since this field may be updated at run-time + * @sof_tplg_filename: Sound Open Firmware topology file name, if enabled + * @tplg_quirk_mask: quirks to select different topology files dynamically + */ +/* Descriptor for SST ASoC machine driver */ +struct snd_soc_acpi_mach { + u8 id[ACPI_ID_LEN]; + const char *uid; + const struct snd_soc_acpi_codecs *comp_ids; + const u32 link_mask; + const struct snd_soc_acpi_link_adr *links; + const char *drv_name; + const char *fw_filename; + const char *tplg_filename; + const char *board; + struct snd_soc_acpi_mach * (*machine_quirk)(void *arg); + const void *quirk_data; + void *pdata; + struct snd_soc_acpi_mach_params mach_params; + const char *sof_tplg_filename; + const u32 tplg_quirk_mask; +}; + +#define SND_SOC_ACPI_MAX_CODECS 3 + +/** + * struct snd_soc_acpi_codecs: Structure to hold secondary codec information + * apart from the matched one, this data will be passed to the quirk function + * to match with the ACPI detected devices + * + * @num_codecs: number of secondary codecs used in the platform + * @codecs: holds the codec IDs + * + */ +struct snd_soc_acpi_codecs { + int num_codecs; + u8 codecs[SND_SOC_ACPI_MAX_CODECS][ACPI_ID_LEN]; +}; + +static inline bool snd_soc_acpi_sof_parent(struct device *dev) +{ + return dev->parent && dev->parent->driver && dev->parent->driver->name && + !strncmp(dev->parent->driver->name, "sof-audio-acpi", strlen("sof-audio-acpi")); +} + +#endif diff --git a/include/sound/soc-card.h b/include/sound/soc-card.h new file mode 100644 index 000000000..40d3023cf --- /dev/null +++ b/include/sound/soc-card.h @@ -0,0 +1,110 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * soc-card.h + * + * Copyright (C) 2019 Renesas Electronics Corp. + * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + */ +#ifndef __SOC_CARD_H +#define __SOC_CARD_H + +enum snd_soc_card_subclass { + SND_SOC_CARD_CLASS_INIT = 0, + SND_SOC_CARD_CLASS_RUNTIME = 1, +}; + +struct snd_kcontrol *snd_soc_card_get_kcontrol(struct snd_soc_card *soc_card, + const char *name); +int snd_soc_card_jack_new(struct snd_soc_card *card, const char *id, int type, + struct snd_soc_jack *jack); +int snd_soc_card_jack_new_pins(struct snd_soc_card *card, const char *id, + int type, struct snd_soc_jack *jack, + struct snd_soc_jack_pin *pins, + unsigned int num_pins); + +int snd_soc_card_suspend_pre(struct snd_soc_card *card); +int snd_soc_card_suspend_post(struct snd_soc_card *card); +int snd_soc_card_resume_pre(struct snd_soc_card *card); +int snd_soc_card_resume_post(struct snd_soc_card *card); + +int snd_soc_card_probe(struct snd_soc_card *card); +int snd_soc_card_late_probe(struct snd_soc_card *card); +void snd_soc_card_fixup_controls(struct snd_soc_card *card); +int snd_soc_card_remove(struct snd_soc_card *card); + +int snd_soc_card_set_bias_level(struct snd_soc_card *card, + struct snd_soc_dapm_context *dapm, + enum snd_soc_bias_level level); +int snd_soc_card_set_bias_level_post(struct snd_soc_card *card, + struct snd_soc_dapm_context *dapm, + enum snd_soc_bias_level level); + +int snd_soc_card_add_dai_link(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_link); +void snd_soc_card_remove_dai_link(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_link); + +#ifdef CONFIG_PCI +static inline void snd_soc_card_set_pci_ssid(struct snd_soc_card *card, + unsigned short vendor, + unsigned short device) +{ + card->pci_subsystem_vendor = vendor; + card->pci_subsystem_device = device; + card->pci_subsystem_set = true; +} + +static inline int snd_soc_card_get_pci_ssid(struct snd_soc_card *card, + unsigned short *vendor, + unsigned short *device) +{ + if (!card->pci_subsystem_set) + return -ENOENT; + + *vendor = card->pci_subsystem_vendor; + *device = card->pci_subsystem_device; + + return 0; +} +#else /* !CONFIG_PCI */ +static inline void snd_soc_card_set_pci_ssid(struct snd_soc_card *card, + unsigned short vendor, + unsigned short device) +{ +} + +static inline int snd_soc_card_get_pci_ssid(struct snd_soc_card *card, + unsigned short *vendor, + unsigned short *device) +{ + return -ENOENT; +} +#endif /* CONFIG_PCI */ + +/* device driver data */ +static inline void snd_soc_card_set_drvdata(struct snd_soc_card *card, + void *data) +{ + card->drvdata = data; +} + +static inline void *snd_soc_card_get_drvdata(struct snd_soc_card *card) +{ + return card->drvdata; +} + +static inline +struct snd_soc_dai *snd_soc_card_get_codec_dai(struct snd_soc_card *card, + const char *dai_name) +{ + struct snd_soc_pcm_runtime *rtd; + + for_each_card_rtds(card, rtd) { + if (!strcmp(asoc_rtd_to_codec(rtd, 0)->name, dai_name)) + return asoc_rtd_to_codec(rtd, 0); + } + + return NULL; +} + +#endif /* __SOC_CARD_H */ diff --git a/include/sound/soc-component.h b/include/sound/soc-component.h new file mode 100644 index 000000000..c26ffb033 --- /dev/null +++ b/include/sound/soc-component.h @@ -0,0 +1,521 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * soc-component.h + * + * Copyright (C) 2019 Renesas Electronics Corp. + * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + */ +#ifndef __SOC_COMPONENT_H +#define __SOC_COMPONENT_H + +#include <sound/soc.h> + +/* + * Component probe and remove ordering levels for components with runtime + * dependencies. + */ +#define SND_SOC_COMP_ORDER_FIRST -2 +#define SND_SOC_COMP_ORDER_EARLY -1 +#define SND_SOC_COMP_ORDER_NORMAL 0 +#define SND_SOC_COMP_ORDER_LATE 1 +#define SND_SOC_COMP_ORDER_LAST 2 + +#define for_each_comp_order(order) \ + for (order = SND_SOC_COMP_ORDER_FIRST; \ + order <= SND_SOC_COMP_ORDER_LAST; \ + order++) + +/* component interface */ +struct snd_compress_ops { + int (*open)(struct snd_soc_component *component, + struct snd_compr_stream *stream); + int (*free)(struct snd_soc_component *component, + struct snd_compr_stream *stream); + int (*set_params)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct snd_compr_params *params); + int (*get_params)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct snd_codec *params); + int (*set_metadata)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct snd_compr_metadata *metadata); + int (*get_metadata)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct snd_compr_metadata *metadata); + int (*trigger)(struct snd_soc_component *component, + struct snd_compr_stream *stream, int cmd); + int (*pointer)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct snd_compr_tstamp *tstamp); + int (*copy)(struct snd_soc_component *component, + struct snd_compr_stream *stream, char __user *buf, + size_t count); + int (*mmap)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct vm_area_struct *vma); + int (*ack)(struct snd_soc_component *component, + struct snd_compr_stream *stream, size_t bytes); + int (*get_caps)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct snd_compr_caps *caps); + int (*get_codec_caps)(struct snd_soc_component *component, + struct snd_compr_stream *stream, + struct snd_compr_codec_caps *codec); +}; + +struct snd_soc_component_driver { + const char *name; + + /* Default control and setup, added after probe() is run */ + const struct snd_kcontrol_new *controls; + unsigned int num_controls; + const struct snd_soc_dapm_widget *dapm_widgets; + unsigned int num_dapm_widgets; + const struct snd_soc_dapm_route *dapm_routes; + unsigned int num_dapm_routes; + + int (*probe)(struct snd_soc_component *component); + void (*remove)(struct snd_soc_component *component); + int (*suspend)(struct snd_soc_component *component); + int (*resume)(struct snd_soc_component *component); + + unsigned int (*read)(struct snd_soc_component *component, + unsigned int reg); + int (*write)(struct snd_soc_component *component, + unsigned int reg, unsigned int val); + + /* pcm creation and destruction */ + int (*pcm_construct)(struct snd_soc_component *component, + struct snd_soc_pcm_runtime *rtd); + void (*pcm_destruct)(struct snd_soc_component *component, + struct snd_pcm *pcm); + + /* component wide operations */ + int (*set_sysclk)(struct snd_soc_component *component, + int clk_id, int source, unsigned int freq, int dir); + int (*set_pll)(struct snd_soc_component *component, int pll_id, + int source, unsigned int freq_in, unsigned int freq_out); + int (*set_jack)(struct snd_soc_component *component, + struct snd_soc_jack *jack, void *data); + + /* DT */ + int (*of_xlate_dai_name)(struct snd_soc_component *component, + const struct of_phandle_args *args, + const char **dai_name); + int (*of_xlate_dai_id)(struct snd_soc_component *comment, + struct device_node *endpoint); + void (*seq_notifier)(struct snd_soc_component *component, + enum snd_soc_dapm_type type, int subseq); + int (*stream_event)(struct snd_soc_component *component, int event); + int (*set_bias_level)(struct snd_soc_component *component, + enum snd_soc_bias_level level); + + int (*open)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + int (*close)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + int (*ioctl)(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + unsigned int cmd, void *arg); + int (*hw_params)(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); + int (*hw_free)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + int (*prepare)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + int (*trigger)(struct snd_soc_component *component, + struct snd_pcm_substream *substream, int cmd); + int (*sync_stop)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + snd_pcm_uframes_t (*pointer)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + int (*get_time_info)(struct snd_soc_component *component, + struct snd_pcm_substream *substream, struct timespec64 *system_ts, + struct timespec64 *audio_ts, + struct snd_pcm_audio_tstamp_config *audio_tstamp_config, + struct snd_pcm_audio_tstamp_report *audio_tstamp_report); + int (*copy_user)(struct snd_soc_component *component, + struct snd_pcm_substream *substream, int channel, + unsigned long pos, void __user *buf, + unsigned long bytes); + struct page *(*page)(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + unsigned long offset); + int (*mmap)(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + struct vm_area_struct *vma); + int (*ack)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + snd_pcm_sframes_t (*delay)(struct snd_soc_component *component, + struct snd_pcm_substream *substream); + + const struct snd_compress_ops *compress_ops; + + /* probe ordering - for components with runtime dependencies */ + int probe_order; + int remove_order; + + /* + * signal if the module handling the component should not be removed + * if a pcm is open. Setting this would prevent the module + * refcount being incremented in probe() but allow it be incremented + * when a pcm is opened and decremented when it is closed. + */ + unsigned int module_get_upon_open:1; + + /* bits */ + unsigned int idle_bias_on:1; + unsigned int suspend_bias_off:1; + unsigned int use_pmdown_time:1; /* care pmdown_time at stop */ + /* + * Indicates that the component does not care about the endianness of + * PCM audio data and the core will ensure that both LE and BE variants + * of each used format are present. Typically this is because the + * component sits behind a bus that abstracts away the endian of the + * original data, ie. one for which the transmission endian is defined + * (I2S/SLIMbus/SoundWire), or the concept of endian doesn't exist (PDM, + * analogue). + */ + unsigned int endianness:1; + unsigned int legacy_dai_naming:1; + + /* this component uses topology and ignore machine driver FEs */ + const char *ignore_machine; + const char *topology_name_prefix; + int (*be_hw_params_fixup)(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); + bool use_dai_pcm_id; /* use DAI link PCM ID as PCM device number */ + int be_pcm_base; /* base device ID for all BE PCMs */ + +#ifdef CONFIG_DEBUG_FS + const char *debugfs_prefix; +#endif +}; + +struct snd_soc_component { + const char *name; + int id; + const char *name_prefix; + struct device *dev; + struct snd_soc_card *card; + + unsigned int active; + + unsigned int suspended:1; /* is in suspend PM state */ + + struct list_head list; + struct list_head card_aux_list; /* for auxiliary bound components */ + struct list_head card_list; + + const struct snd_soc_component_driver *driver; + + struct list_head dai_list; + int num_dai; + + struct regmap *regmap; + int val_bytes; + + struct mutex io_mutex; + + /* attached dynamic objects */ + struct list_head dobj_list; + + /* + * DO NOT use any of the fields below in drivers, they are temporary and + * are going to be removed again soon. If you use them in driver code + * the driver will be marked as BROKEN when these fields are removed. + */ + + /* Don't use these, use snd_soc_component_get_dapm() */ + struct snd_soc_dapm_context dapm; + + /* machine specific init */ + int (*init)(struct snd_soc_component *component); + + /* function mark */ + void *mark_module; + struct snd_pcm_substream *mark_open; + struct snd_pcm_substream *mark_hw_params; + struct snd_pcm_substream *mark_trigger; + struct snd_compr_stream *mark_compr_open; + void *mark_pm; + + struct dentry *debugfs_root; + const char *debugfs_prefix; +}; + +#define for_each_component_dais(component, dai)\ + list_for_each_entry(dai, &(component)->dai_list, list) +#define for_each_component_dais_safe(component, dai, _dai)\ + list_for_each_entry_safe(dai, _dai, &(component)->dai_list, list) + +/** + * snd_soc_dapm_to_component() - Casts a DAPM context to the component it is + * embedded in + * @dapm: The DAPM context to cast to the component + * + * This function must only be used on DAPM contexts that are known to be part of + * a component (e.g. in a component driver). Otherwise the behavior is + * undefined. + */ +static inline struct snd_soc_component *snd_soc_dapm_to_component( + struct snd_soc_dapm_context *dapm) +{ + return container_of(dapm, struct snd_soc_component, dapm); +} + +/** + * snd_soc_component_get_dapm() - Returns the DAPM context associated with a + * component + * @component: The component for which to get the DAPM context + */ +static inline struct snd_soc_dapm_context *snd_soc_component_get_dapm( + struct snd_soc_component *component) +{ + return &component->dapm; +} + +/** + * snd_soc_component_init_bias_level() - Initialize COMPONENT DAPM bias level + * @component: The COMPONENT for which to initialize the DAPM bias level + * @level: The DAPM level to initialize to + * + * Initializes the COMPONENT DAPM bias level. See snd_soc_dapm_init_bias_level() + */ +static inline void +snd_soc_component_init_bias_level(struct snd_soc_component *component, + enum snd_soc_bias_level level) +{ + snd_soc_dapm_init_bias_level( + snd_soc_component_get_dapm(component), level); +} + +/** + * snd_soc_component_get_bias_level() - Get current COMPONENT DAPM bias level + * @component: The COMPONENT for which to get the DAPM bias level + * + * Returns: The current DAPM bias level of the COMPONENT. + */ +static inline enum snd_soc_bias_level +snd_soc_component_get_bias_level(struct snd_soc_component *component) +{ + return snd_soc_dapm_get_bias_level( + snd_soc_component_get_dapm(component)); +} + +/** + * snd_soc_component_force_bias_level() - Set the COMPONENT DAPM bias level + * @component: The COMPONENT for which to set the level + * @level: The level to set to + * + * Forces the COMPONENT bias level to a specific state. See + * snd_soc_dapm_force_bias_level(). + */ +static inline int +snd_soc_component_force_bias_level(struct snd_soc_component *component, + enum snd_soc_bias_level level) +{ + return snd_soc_dapm_force_bias_level( + snd_soc_component_get_dapm(component), + level); +} + +/** + * snd_soc_dapm_kcontrol_component() - Returns the component associated to a + * kcontrol + * @kcontrol: The kcontrol + * + * This function must only be used on DAPM contexts that are known to be part of + * a COMPONENT (e.g. in a COMPONENT driver). Otherwise the behavior is undefined + */ +static inline struct snd_soc_component *snd_soc_dapm_kcontrol_component( + struct snd_kcontrol *kcontrol) +{ + return snd_soc_dapm_to_component(snd_soc_dapm_kcontrol_dapm(kcontrol)); +} + +/** + * snd_soc_component_cache_sync() - Sync the register cache with the hardware + * @component: COMPONENT to sync + * + * Note: This function will call regcache_sync() + */ +static inline int snd_soc_component_cache_sync( + struct snd_soc_component *component) +{ + return regcache_sync(component->regmap); +} + +void snd_soc_component_set_aux(struct snd_soc_component *component, + struct snd_soc_aux_dev *aux); +int snd_soc_component_init(struct snd_soc_component *component); +int snd_soc_component_is_dummy(struct snd_soc_component *component); + +/* component IO */ +unsigned int snd_soc_component_read(struct snd_soc_component *component, + unsigned int reg); +int snd_soc_component_write(struct snd_soc_component *component, + unsigned int reg, unsigned int val); +int snd_soc_component_update_bits(struct snd_soc_component *component, + unsigned int reg, unsigned int mask, + unsigned int val); +int snd_soc_component_update_bits_async(struct snd_soc_component *component, + unsigned int reg, unsigned int mask, + unsigned int val); +void snd_soc_component_async_complete(struct snd_soc_component *component); +int snd_soc_component_test_bits(struct snd_soc_component *component, + unsigned int reg, unsigned int mask, + unsigned int value); + +unsigned int snd_soc_component_read_field(struct snd_soc_component *component, + unsigned int reg, unsigned int mask); +int snd_soc_component_write_field(struct snd_soc_component *component, + unsigned int reg, unsigned int mask, + unsigned int val); + +/* component wide operations */ +int snd_soc_component_set_sysclk(struct snd_soc_component *component, + int clk_id, int source, + unsigned int freq, int dir); +int snd_soc_component_set_pll(struct snd_soc_component *component, int pll_id, + int source, unsigned int freq_in, + unsigned int freq_out); +int snd_soc_component_set_jack(struct snd_soc_component *component, + struct snd_soc_jack *jack, void *data); + +void snd_soc_component_seq_notifier(struct snd_soc_component *component, + enum snd_soc_dapm_type type, int subseq); +int snd_soc_component_stream_event(struct snd_soc_component *component, + int event); +int snd_soc_component_set_bias_level(struct snd_soc_component *component, + enum snd_soc_bias_level level); + +void snd_soc_component_setup_regmap(struct snd_soc_component *component); +#ifdef CONFIG_REGMAP +void snd_soc_component_init_regmap(struct snd_soc_component *component, + struct regmap *regmap); +void snd_soc_component_exit_regmap(struct snd_soc_component *component); +#endif + +#define snd_soc_component_module_get_when_probe(component)\ + snd_soc_component_module_get(component, NULL, 0) +#define snd_soc_component_module_get_when_open(component, substream) \ + snd_soc_component_module_get(component, substream, 1) +int snd_soc_component_module_get(struct snd_soc_component *component, + void *mark, int upon_open); +#define snd_soc_component_module_put_when_remove(component) \ + snd_soc_component_module_put(component, NULL, 0, 0) +#define snd_soc_component_module_put_when_close(component, substream, rollback) \ + snd_soc_component_module_put(component, substream, 1, rollback) +void snd_soc_component_module_put(struct snd_soc_component *component, + void *mark, int upon_open, int rollback); + +static inline void snd_soc_component_set_drvdata(struct snd_soc_component *c, + void *data) +{ + dev_set_drvdata(c->dev, data); +} + +static inline void *snd_soc_component_get_drvdata(struct snd_soc_component *c) +{ + return dev_get_drvdata(c->dev); +} + +static inline unsigned int +snd_soc_component_active(struct snd_soc_component *component) +{ + return component->active; +} + +/* component pin */ +int snd_soc_component_enable_pin(struct snd_soc_component *component, + const char *pin); +int snd_soc_component_enable_pin_unlocked(struct snd_soc_component *component, + const char *pin); +int snd_soc_component_disable_pin(struct snd_soc_component *component, + const char *pin); +int snd_soc_component_disable_pin_unlocked(struct snd_soc_component *component, + const char *pin); +int snd_soc_component_nc_pin(struct snd_soc_component *component, + const char *pin); +int snd_soc_component_nc_pin_unlocked(struct snd_soc_component *component, + const char *pin); +int snd_soc_component_get_pin_status(struct snd_soc_component *component, + const char *pin); +int snd_soc_component_force_enable_pin(struct snd_soc_component *component, + const char *pin); +int snd_soc_component_force_enable_pin_unlocked( + struct snd_soc_component *component, + const char *pin); + +/* component driver ops */ +int snd_soc_component_open(struct snd_soc_component *component, + struct snd_pcm_substream *substream); +int snd_soc_component_close(struct snd_soc_component *component, + struct snd_pcm_substream *substream, + int rollback); +void snd_soc_component_suspend(struct snd_soc_component *component); +void snd_soc_component_resume(struct snd_soc_component *component); +int snd_soc_component_is_suspended(struct snd_soc_component *component); +int snd_soc_component_probe(struct snd_soc_component *component); +void snd_soc_component_remove(struct snd_soc_component *component); +int snd_soc_component_of_xlate_dai_id(struct snd_soc_component *component, + struct device_node *ep); +int snd_soc_component_of_xlate_dai_name(struct snd_soc_component *component, + const struct of_phandle_args *args, + const char **dai_name); +int snd_soc_component_compr_open(struct snd_soc_component *component, + struct snd_compr_stream *cstream); +void snd_soc_component_compr_free(struct snd_soc_component *component, + struct snd_compr_stream *cstream, + int rollback); +int snd_soc_component_compr_trigger(struct snd_compr_stream *cstream, int cmd); +int snd_soc_component_compr_set_params(struct snd_compr_stream *cstream, + struct snd_compr_params *params); +int snd_soc_component_compr_get_params(struct snd_compr_stream *cstream, + struct snd_codec *params); +int snd_soc_component_compr_get_caps(struct snd_compr_stream *cstream, + struct snd_compr_caps *caps); +int snd_soc_component_compr_get_codec_caps(struct snd_compr_stream *cstream, + struct snd_compr_codec_caps *codec); +int snd_soc_component_compr_ack(struct snd_compr_stream *cstream, size_t bytes); +int snd_soc_component_compr_pointer(struct snd_compr_stream *cstream, + struct snd_compr_tstamp *tstamp); +int snd_soc_component_compr_copy(struct snd_compr_stream *cstream, + char __user *buf, size_t count); +int snd_soc_component_compr_set_metadata(struct snd_compr_stream *cstream, + struct snd_compr_metadata *metadata); +int snd_soc_component_compr_get_metadata(struct snd_compr_stream *cstream, + struct snd_compr_metadata *metadata); + +int snd_soc_pcm_component_pointer(struct snd_pcm_substream *substream); +int snd_soc_pcm_component_ioctl(struct snd_pcm_substream *substream, + unsigned int cmd, void *arg); +int snd_soc_pcm_component_sync_stop(struct snd_pcm_substream *substream); +int snd_soc_pcm_component_copy_user(struct snd_pcm_substream *substream, + int channel, unsigned long pos, + void __user *buf, unsigned long bytes); +struct page *snd_soc_pcm_component_page(struct snd_pcm_substream *substream, + unsigned long offset); +int snd_soc_pcm_component_mmap(struct snd_pcm_substream *substream, + struct vm_area_struct *vma); +int snd_soc_pcm_component_new(struct snd_soc_pcm_runtime *rtd); +void snd_soc_pcm_component_free(struct snd_soc_pcm_runtime *rtd); +int snd_soc_pcm_component_prepare(struct snd_pcm_substream *substream); +int snd_soc_pcm_component_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +void snd_soc_pcm_component_hw_free(struct snd_pcm_substream *substream, + int rollback); +int snd_soc_pcm_component_trigger(struct snd_pcm_substream *substream, + int cmd, int rollback); +int snd_soc_pcm_component_pm_runtime_get(struct snd_soc_pcm_runtime *rtd, + void *stream); +void snd_soc_pcm_component_pm_runtime_put(struct snd_soc_pcm_runtime *rtd, + void *stream, int rollback); +int snd_soc_pcm_component_ack(struct snd_pcm_substream *substream); +void snd_soc_pcm_component_delay(struct snd_pcm_substream *substream, + snd_pcm_sframes_t *cpu_delay, snd_pcm_sframes_t *codec_delay); + +#endif /* __SOC_COMPONENT_H */ diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h new file mode 100644 index 000000000..ea7509672 --- /dev/null +++ b/include/sound/soc-dai.h @@ -0,0 +1,570 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * linux/sound/soc-dai.h -- ALSA SoC Layer + * + * Copyright: 2005-2008 Wolfson Microelectronics. PLC. + * + * Digital Audio Interface (DAI) API. + */ + +#ifndef __LINUX_SND_SOC_DAI_H +#define __LINUX_SND_SOC_DAI_H + + +#include <linux/list.h> +#include <sound/asoc.h> + +struct snd_pcm_substream; +struct snd_soc_dapm_widget; +struct snd_compr_stream; + +/* + * DAI hardware audio formats. + * + * Describes the physical PCM data formating and clocking. Add new formats + * to the end. + */ +#define SND_SOC_DAIFMT_I2S SND_SOC_DAI_FORMAT_I2S +#define SND_SOC_DAIFMT_RIGHT_J SND_SOC_DAI_FORMAT_RIGHT_J +#define SND_SOC_DAIFMT_LEFT_J SND_SOC_DAI_FORMAT_LEFT_J +#define SND_SOC_DAIFMT_DSP_A SND_SOC_DAI_FORMAT_DSP_A +#define SND_SOC_DAIFMT_DSP_B SND_SOC_DAI_FORMAT_DSP_B +#define SND_SOC_DAIFMT_AC97 SND_SOC_DAI_FORMAT_AC97 +#define SND_SOC_DAIFMT_PDM SND_SOC_DAI_FORMAT_PDM + +/* left and right justified also known as MSB and LSB respectively */ +#define SND_SOC_DAIFMT_MSB SND_SOC_DAIFMT_LEFT_J +#define SND_SOC_DAIFMT_LSB SND_SOC_DAIFMT_RIGHT_J + +/* Describes the possible PCM format */ +/* + * use SND_SOC_DAI_FORMAT_xx as eash shift. + * see + * snd_soc_runtime_get_dai_fmt() + */ +#define SND_SOC_POSSIBLE_DAIFMT_FORMAT_SHIFT 0 +#define SND_SOC_POSSIBLE_DAIFMT_FORMAT_MASK (0xFFFF << SND_SOC_POSSIBLE_DAIFMT_FORMAT_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_I2S (1 << SND_SOC_DAI_FORMAT_I2S) +#define SND_SOC_POSSIBLE_DAIFMT_RIGHT_J (1 << SND_SOC_DAI_FORMAT_RIGHT_J) +#define SND_SOC_POSSIBLE_DAIFMT_LEFT_J (1 << SND_SOC_DAI_FORMAT_LEFT_J) +#define SND_SOC_POSSIBLE_DAIFMT_DSP_A (1 << SND_SOC_DAI_FORMAT_DSP_A) +#define SND_SOC_POSSIBLE_DAIFMT_DSP_B (1 << SND_SOC_DAI_FORMAT_DSP_B) +#define SND_SOC_POSSIBLE_DAIFMT_AC97 (1 << SND_SOC_DAI_FORMAT_AC97) +#define SND_SOC_POSSIBLE_DAIFMT_PDM (1 << SND_SOC_DAI_FORMAT_PDM) + +/* + * DAI Clock gating. + * + * DAI bit clocks can be gated (disabled) when the DAI is not + * sending or receiving PCM data in a frame. This can be used to save power. + */ +#define SND_SOC_DAIFMT_CONT (1 << 4) /* continuous clock */ +#define SND_SOC_DAIFMT_GATED (0 << 4) /* clock is gated */ + +/* Describes the possible PCM format */ +/* + * define GATED -> CONT. GATED will be selected if both are selected. + * see + * snd_soc_runtime_get_dai_fmt() + */ +#define SND_SOC_POSSIBLE_DAIFMT_CLOCK_SHIFT 16 +#define SND_SOC_POSSIBLE_DAIFMT_CLOCK_MASK (0xFFFF << SND_SOC_POSSIBLE_DAIFMT_CLOCK_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_GATED (0x1ULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_CONT (0x2ULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_SHIFT) + +/* + * DAI hardware signal polarity. + * + * Specifies whether the DAI can also support inverted clocks for the specified + * format. + * + * BCLK: + * - "normal" polarity means signal is available at rising edge of BCLK + * - "inverted" polarity means signal is available at falling edge of BCLK + * + * FSYNC "normal" polarity depends on the frame format: + * - I2S: frame consists of left then right channel data. Left channel starts + * with falling FSYNC edge, right channel starts with rising FSYNC edge. + * - Left/Right Justified: frame consists of left then right channel data. + * Left channel starts with rising FSYNC edge, right channel starts with + * falling FSYNC edge. + * - DSP A/B: Frame starts with rising FSYNC edge. + * - AC97: Frame starts with rising FSYNC edge. + * + * "Negative" FSYNC polarity is the one opposite of "normal" polarity. + */ +#define SND_SOC_DAIFMT_NB_NF (0 << 8) /* normal bit clock + frame */ +#define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */ +#define SND_SOC_DAIFMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */ +#define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */ + +/* Describes the possible PCM format */ +#define SND_SOC_POSSIBLE_DAIFMT_INV_SHIFT 32 +#define SND_SOC_POSSIBLE_DAIFMT_INV_MASK (0xFFFFULL << SND_SOC_POSSIBLE_DAIFMT_INV_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_NB_NF (0x1ULL << SND_SOC_POSSIBLE_DAIFMT_INV_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_NB_IF (0x2ULL << SND_SOC_POSSIBLE_DAIFMT_INV_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_IB_NF (0x4ULL << SND_SOC_POSSIBLE_DAIFMT_INV_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_IB_IF (0x8ULL << SND_SOC_POSSIBLE_DAIFMT_INV_SHIFT) + +/* + * DAI hardware clock providers/consumers + * + * This is wrt the codec, the inverse is true for the interface + * i.e. if the codec is clk and FRM provider then the interface is + * clk and frame consumer. + */ +#define SND_SOC_DAIFMT_CBP_CFP (1 << 12) /* codec clk provider & frame provider */ +#define SND_SOC_DAIFMT_CBC_CFP (2 << 12) /* codec clk consumer & frame provider */ +#define SND_SOC_DAIFMT_CBP_CFC (3 << 12) /* codec clk provider & frame consumer */ +#define SND_SOC_DAIFMT_CBC_CFC (4 << 12) /* codec clk consumer & frame consumer */ + +/* previous definitions kept for backwards-compatibility, do not use in new contributions */ +#define SND_SOC_DAIFMT_CBM_CFM SND_SOC_DAIFMT_CBP_CFP +#define SND_SOC_DAIFMT_CBS_CFM SND_SOC_DAIFMT_CBC_CFP +#define SND_SOC_DAIFMT_CBM_CFS SND_SOC_DAIFMT_CBP_CFC +#define SND_SOC_DAIFMT_CBS_CFS SND_SOC_DAIFMT_CBC_CFC + +/* when passed to set_fmt directly indicate if the device is provider or consumer */ +#define SND_SOC_DAIFMT_BP_FP SND_SOC_DAIFMT_CBP_CFP +#define SND_SOC_DAIFMT_BC_FP SND_SOC_DAIFMT_CBC_CFP +#define SND_SOC_DAIFMT_BP_FC SND_SOC_DAIFMT_CBP_CFC +#define SND_SOC_DAIFMT_BC_FC SND_SOC_DAIFMT_CBC_CFC + +/* Describes the possible PCM format */ +#define SND_SOC_POSSIBLE_DAIFMT_CLOCK_PROVIDER_SHIFT 48 +#define SND_SOC_POSSIBLE_DAIFMT_CLOCK_PROVIDER_MASK (0xFFFFULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_PROVIDER_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_CBP_CFP (0x1ULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_PROVIDER_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_CBC_CFP (0x2ULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_PROVIDER_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_CBP_CFC (0x4ULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_PROVIDER_SHIFT) +#define SND_SOC_POSSIBLE_DAIFMT_CBC_CFC (0x8ULL << SND_SOC_POSSIBLE_DAIFMT_CLOCK_PROVIDER_SHIFT) + +#define SND_SOC_DAIFMT_FORMAT_MASK 0x000f +#define SND_SOC_DAIFMT_CLOCK_MASK 0x00f0 +#define SND_SOC_DAIFMT_INV_MASK 0x0f00 +#define SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK 0xf000 + +#define SND_SOC_DAIFMT_MASTER_MASK SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK + +/* + * Master Clock Directions + */ +#define SND_SOC_CLOCK_IN 0 +#define SND_SOC_CLOCK_OUT 1 + +#define SND_SOC_STD_AC97_FMTS (SNDRV_PCM_FMTBIT_S8 |\ + SNDRV_PCM_FMTBIT_S16_LE |\ + SNDRV_PCM_FMTBIT_S16_BE |\ + SNDRV_PCM_FMTBIT_S20_3LE |\ + SNDRV_PCM_FMTBIT_S20_3BE |\ + SNDRV_PCM_FMTBIT_S20_LE |\ + SNDRV_PCM_FMTBIT_S20_BE |\ + SNDRV_PCM_FMTBIT_S24_3LE |\ + SNDRV_PCM_FMTBIT_S24_3BE |\ + SNDRV_PCM_FMTBIT_S32_LE |\ + SNDRV_PCM_FMTBIT_S32_BE) + +struct snd_soc_dai_driver; +struct snd_soc_dai; +struct snd_ac97_bus_ops; + +/* Digital Audio Interface clocking API.*/ +int snd_soc_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id, + unsigned int freq, int dir); + +int snd_soc_dai_set_clkdiv(struct snd_soc_dai *dai, + int div_id, int div); + +int snd_soc_dai_set_pll(struct snd_soc_dai *dai, + int pll_id, int source, unsigned int freq_in, unsigned int freq_out); + +int snd_soc_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio); + +/* Digital Audio interface formatting */ +int snd_soc_dai_get_fmt_max_priority(struct snd_soc_pcm_runtime *rtd); +u64 snd_soc_dai_get_fmt(struct snd_soc_dai *dai, int priority); +int snd_soc_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt); + +int snd_soc_dai_set_tdm_slot(struct snd_soc_dai *dai, + unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width); + +int snd_soc_dai_set_channel_map(struct snd_soc_dai *dai, + unsigned int tx_num, unsigned int *tx_slot, + unsigned int rx_num, unsigned int *rx_slot); + +int snd_soc_dai_set_tristate(struct snd_soc_dai *dai, int tristate); + +/* Digital Audio Interface mute */ +int snd_soc_dai_digital_mute(struct snd_soc_dai *dai, int mute, + int direction); + + +int snd_soc_dai_get_channel_map(struct snd_soc_dai *dai, + unsigned int *tx_num, unsigned int *tx_slot, + unsigned int *rx_num, unsigned int *rx_slot); + +int snd_soc_dai_is_dummy(struct snd_soc_dai *dai); + +int snd_soc_dai_hw_params(struct snd_soc_dai *dai, + struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +void snd_soc_dai_hw_free(struct snd_soc_dai *dai, + struct snd_pcm_substream *substream, + int rollback); +int snd_soc_dai_startup(struct snd_soc_dai *dai, + struct snd_pcm_substream *substream); +void snd_soc_dai_shutdown(struct snd_soc_dai *dai, + struct snd_pcm_substream *substream, int rollback); +void snd_soc_dai_suspend(struct snd_soc_dai *dai); +void snd_soc_dai_resume(struct snd_soc_dai *dai); +int snd_soc_dai_compress_new(struct snd_soc_dai *dai, + struct snd_soc_pcm_runtime *rtd, int num); +bool snd_soc_dai_stream_valid(struct snd_soc_dai *dai, int stream); +void snd_soc_dai_link_set_capabilities(struct snd_soc_dai_link *dai_link); +void snd_soc_dai_action(struct snd_soc_dai *dai, + int stream, int action); +static inline void snd_soc_dai_activate(struct snd_soc_dai *dai, + int stream) +{ + snd_soc_dai_action(dai, stream, 1); +} +static inline void snd_soc_dai_deactivate(struct snd_soc_dai *dai, + int stream) +{ + snd_soc_dai_action(dai, stream, -1); +} +int snd_soc_dai_active(struct snd_soc_dai *dai); + +int snd_soc_pcm_dai_probe(struct snd_soc_pcm_runtime *rtd, int order); +int snd_soc_pcm_dai_remove(struct snd_soc_pcm_runtime *rtd, int order); +int snd_soc_pcm_dai_new(struct snd_soc_pcm_runtime *rtd); +int snd_soc_pcm_dai_prepare(struct snd_pcm_substream *substream); +int snd_soc_pcm_dai_trigger(struct snd_pcm_substream *substream, int cmd, + int rollback); +int snd_soc_pcm_dai_bespoke_trigger(struct snd_pcm_substream *substream, + int cmd); +void snd_soc_pcm_dai_delay(struct snd_pcm_substream *substream, + snd_pcm_sframes_t *cpu_delay, snd_pcm_sframes_t *codec_delay); + +int snd_soc_dai_compr_startup(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream); +void snd_soc_dai_compr_shutdown(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, + int rollback); +int snd_soc_dai_compr_trigger(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, int cmd); +int snd_soc_dai_compr_set_params(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, + struct snd_compr_params *params); +int snd_soc_dai_compr_get_params(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, + struct snd_codec *params); +int snd_soc_dai_compr_ack(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, + size_t bytes); +int snd_soc_dai_compr_pointer(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, + struct snd_compr_tstamp *tstamp); +int snd_soc_dai_compr_set_metadata(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, + struct snd_compr_metadata *metadata); +int snd_soc_dai_compr_get_metadata(struct snd_soc_dai *dai, + struct snd_compr_stream *cstream, + struct snd_compr_metadata *metadata); + +struct snd_soc_dai_ops { + /* + * DAI clocking configuration, all optional. + * Called by soc_card drivers, normally in their hw_params. + */ + int (*set_sysclk)(struct snd_soc_dai *dai, + int clk_id, unsigned int freq, int dir); + int (*set_pll)(struct snd_soc_dai *dai, int pll_id, int source, + unsigned int freq_in, unsigned int freq_out); + int (*set_clkdiv)(struct snd_soc_dai *dai, int div_id, int div); + int (*set_bclk_ratio)(struct snd_soc_dai *dai, unsigned int ratio); + + /* + * DAI format configuration + * Called by soc_card drivers, normally in their hw_params. + */ + int (*set_fmt)(struct snd_soc_dai *dai, unsigned int fmt); + int (*xlate_tdm_slot_mask)(unsigned int slots, + unsigned int *tx_mask, unsigned int *rx_mask); + int (*set_tdm_slot)(struct snd_soc_dai *dai, + unsigned int tx_mask, unsigned int rx_mask, + int slots, int slot_width); + int (*set_channel_map)(struct snd_soc_dai *dai, + unsigned int tx_num, unsigned int *tx_slot, + unsigned int rx_num, unsigned int *rx_slot); + int (*get_channel_map)(struct snd_soc_dai *dai, + unsigned int *tx_num, unsigned int *tx_slot, + unsigned int *rx_num, unsigned int *rx_slot); + int (*set_tristate)(struct snd_soc_dai *dai, int tristate); + + int (*set_stream)(struct snd_soc_dai *dai, + void *stream, int direction); + void *(*get_stream)(struct snd_soc_dai *dai, int direction); + + /* + * DAI digital mute - optional. + * Called by soc-core to minimise any pops. + */ + int (*mute_stream)(struct snd_soc_dai *dai, int mute, int stream); + + /* + * ALSA PCM audio operations - all optional. + * Called by soc-core during audio PCM operations. + */ + int (*startup)(struct snd_pcm_substream *, + struct snd_soc_dai *); + void (*shutdown)(struct snd_pcm_substream *, + struct snd_soc_dai *); + int (*hw_params)(struct snd_pcm_substream *, + struct snd_pcm_hw_params *, struct snd_soc_dai *); + int (*hw_free)(struct snd_pcm_substream *, + struct snd_soc_dai *); + int (*prepare)(struct snd_pcm_substream *, + struct snd_soc_dai *); + /* + * NOTE: Commands passed to the trigger function are not necessarily + * compatible with the current state of the dai. For example this + * sequence of commands is possible: START STOP STOP. + * So do not unconditionally use refcounting functions in the trigger + * function, e.g. clk_enable/disable. + */ + int (*trigger)(struct snd_pcm_substream *, int, + struct snd_soc_dai *); + int (*bespoke_trigger)(struct snd_pcm_substream *, int, + struct snd_soc_dai *); + /* + * For hardware based FIFO caused delay reporting. + * Optional. + */ + snd_pcm_sframes_t (*delay)(struct snd_pcm_substream *, + struct snd_soc_dai *); + + /* + * Format list for auto selection. + * Format will be increased if priority format was + * not selected. + * see + * snd_soc_dai_get_fmt() + */ + u64 *auto_selectable_formats; + int num_auto_selectable_formats; + + /* bit field */ + unsigned int no_capture_mute:1; +}; + +struct snd_soc_cdai_ops { + /* + * for compress ops + */ + int (*startup)(struct snd_compr_stream *, + struct snd_soc_dai *); + int (*shutdown)(struct snd_compr_stream *, + struct snd_soc_dai *); + int (*set_params)(struct snd_compr_stream *, + struct snd_compr_params *, struct snd_soc_dai *); + int (*get_params)(struct snd_compr_stream *, + struct snd_codec *, struct snd_soc_dai *); + int (*set_metadata)(struct snd_compr_stream *, + struct snd_compr_metadata *, struct snd_soc_dai *); + int (*get_metadata)(struct snd_compr_stream *, + struct snd_compr_metadata *, struct snd_soc_dai *); + int (*trigger)(struct snd_compr_stream *, int, + struct snd_soc_dai *); + int (*pointer)(struct snd_compr_stream *, + struct snd_compr_tstamp *, struct snd_soc_dai *); + int (*ack)(struct snd_compr_stream *, size_t, + struct snd_soc_dai *); +}; + +/* + * Digital Audio Interface Driver. + * + * Describes the Digital Audio Interface in terms of its ALSA, DAI and AC97 + * operations and capabilities. Codec and platform drivers will register this + * structure for every DAI they have. + * + * This structure covers the clocking, formating and ALSA operations for each + * interface. + */ +struct snd_soc_dai_driver { + /* DAI description */ + const char *name; + unsigned int id; + unsigned int base; + struct snd_soc_dobj dobj; + + /* DAI driver callbacks */ + int (*probe)(struct snd_soc_dai *dai); + int (*remove)(struct snd_soc_dai *dai); + /* compress dai */ + int (*compress_new)(struct snd_soc_pcm_runtime *rtd, int num); + /* Optional Callback used at pcm creation*/ + int (*pcm_new)(struct snd_soc_pcm_runtime *rtd, + struct snd_soc_dai *dai); + + /* ops */ + const struct snd_soc_dai_ops *ops; + const struct snd_soc_cdai_ops *cops; + + /* DAI capabilities */ + struct snd_soc_pcm_stream capture; + struct snd_soc_pcm_stream playback; + unsigned int symmetric_rate:1; + unsigned int symmetric_channels:1; + unsigned int symmetric_sample_bits:1; + + /* probe ordering - for components with runtime dependencies */ + int probe_order; + int remove_order; +}; + +/* + * Digital Audio Interface runtime data. + * + * Holds runtime data for a DAI. + */ +struct snd_soc_dai { + const char *name; + int id; + struct device *dev; + + /* driver ops */ + struct snd_soc_dai_driver *driver; + + /* DAI runtime info */ + unsigned int stream_active[SNDRV_PCM_STREAM_LAST + 1]; /* usage count */ + + struct snd_soc_dapm_widget *playback_widget; + struct snd_soc_dapm_widget *capture_widget; + + /* DAI DMA data */ + void *playback_dma_data; + void *capture_dma_data; + + /* Symmetry data - only valid if symmetry is being enforced */ + unsigned int rate; + unsigned int channels; + unsigned int sample_bits; + + /* parent platform/codec */ + struct snd_soc_component *component; + + /* CODEC TDM slot masks and params (for fixup) */ + unsigned int tx_mask; + unsigned int rx_mask; + + struct list_head list; + + /* function mark */ + struct snd_pcm_substream *mark_startup; + struct snd_pcm_substream *mark_hw_params; + struct snd_pcm_substream *mark_trigger; + struct snd_compr_stream *mark_compr_startup; + + /* bit field */ + unsigned int probed:1; +}; + +static inline struct snd_soc_pcm_stream * +snd_soc_dai_get_pcm_stream(const struct snd_soc_dai *dai, int stream) +{ + return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? + &dai->driver->playback : &dai->driver->capture; +} + +static inline +struct snd_soc_dapm_widget *snd_soc_dai_get_widget( + struct snd_soc_dai *dai, int stream) +{ + return (stream == SNDRV_PCM_STREAM_PLAYBACK) ? + dai->playback_widget : dai->capture_widget; +} + +static inline void *snd_soc_dai_get_dma_data(const struct snd_soc_dai *dai, + const struct snd_pcm_substream *ss) +{ + return (ss->stream == SNDRV_PCM_STREAM_PLAYBACK) ? + dai->playback_dma_data : dai->capture_dma_data; +} + +static inline void snd_soc_dai_set_dma_data(struct snd_soc_dai *dai, + const struct snd_pcm_substream *ss, + void *data) +{ + if (ss->stream == SNDRV_PCM_STREAM_PLAYBACK) + dai->playback_dma_data = data; + else + dai->capture_dma_data = data; +} + +static inline void snd_soc_dai_init_dma_data(struct snd_soc_dai *dai, + void *playback, void *capture) +{ + dai->playback_dma_data = playback; + dai->capture_dma_data = capture; +} + +static inline void snd_soc_dai_set_drvdata(struct snd_soc_dai *dai, + void *data) +{ + dev_set_drvdata(dai->dev, data); +} + +static inline void *snd_soc_dai_get_drvdata(struct snd_soc_dai *dai) +{ + return dev_get_drvdata(dai->dev); +} + +/** + * snd_soc_dai_set_stream() - Configures a DAI for stream operation + * @dai: DAI + * @stream: STREAM (opaque structure depending on DAI type) + * @direction: Stream direction(Playback/Capture) + * Some subsystems, such as SoundWire, don't have a notion of direction and we reuse + * the ASoC stream direction to configure sink/source ports. + * Playback maps to source ports and Capture for sink ports. + * + * This should be invoked with NULL to clear the stream set previously. + * Returns 0 on success, a negative error code otherwise. + */ +static inline int snd_soc_dai_set_stream(struct snd_soc_dai *dai, + void *stream, int direction) +{ + if (dai->driver->ops->set_stream) + return dai->driver->ops->set_stream(dai, stream, direction); + else + return -ENOTSUPP; +} + +/** + * snd_soc_dai_get_stream() - Retrieves stream from DAI + * @dai: DAI + * @direction: Stream direction(Playback/Capture) + * + * This routine only retrieves that was previously configured + * with snd_soc_dai_get_stream() + * + * Returns pointer to stream or an ERR_PTR value, e.g. + * ERR_PTR(-ENOTSUPP) if callback is not supported; + */ +static inline void *snd_soc_dai_get_stream(struct snd_soc_dai *dai, + int direction) +{ + if (dai->driver->ops->get_stream) + return dai->driver->ops->get_stream(dai, direction); + else + return ERR_PTR(-ENOTSUPP); +} + +static inline unsigned int +snd_soc_dai_stream_active(struct snd_soc_dai *dai, int stream) +{ + return dai->stream_active[stream]; +} + +#endif diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h new file mode 100644 index 000000000..9f2b1e6d8 --- /dev/null +++ b/include/sound/soc-dapm.h @@ -0,0 +1,818 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * linux/sound/soc-dapm.h -- ALSA SoC Dynamic Audio Power Management + * + * Author: Liam Girdwood + * Created: Aug 11th 2005 + * Copyright: Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_SOC_DAPM_H +#define __LINUX_SND_SOC_DAPM_H + +#include <linux/types.h> +#include <sound/control.h> +#include <sound/soc-topology.h> +#include <sound/asoc.h> + +struct device; +struct snd_pcm_substream; +struct snd_soc_pcm_runtime; +struct soc_enum; + +/* widget has no PM register bit */ +#define SND_SOC_NOPM -1 + +/* + * SoC dynamic audio power management + * + * We can have up to 4 power domains + * 1. Codec domain - VREF, VMID + * Usually controlled at codec probe/remove, although can be set + * at stream time if power is not needed for sidetone, etc. + * 2. Platform/Machine domain - physically connected inputs and outputs + * Is platform/machine and user action specific, is set in the machine + * driver and by userspace e.g when HP are inserted + * 3. Path domain - Internal codec path mixers + * Are automatically set when mixer and mux settings are + * changed by the user. + * 4. Stream domain - DAC's and ADC's. + * Enabled when stream playback/capture is started. + */ + +/* codec domain */ +#define SND_SOC_DAPM_VMID(wname) \ +{ .id = snd_soc_dapm_vmid, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0} + +/* platform domain */ +#define SND_SOC_DAPM_SIGGEN(wname) \ +{ .id = snd_soc_dapm_siggen, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM } +#define SND_SOC_DAPM_SINK(wname) \ +{ .id = snd_soc_dapm_sink, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM } +#define SND_SOC_DAPM_INPUT(wname) \ +{ .id = snd_soc_dapm_input, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM } +#define SND_SOC_DAPM_OUTPUT(wname) \ +{ .id = snd_soc_dapm_output, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM } +#define SND_SOC_DAPM_MIC(wname, wevent) \ +{ .id = snd_soc_dapm_mic, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD} +#define SND_SOC_DAPM_HP(wname, wevent) \ +{ .id = snd_soc_dapm_hp, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ + .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD} +#define SND_SOC_DAPM_SPK(wname, wevent) \ +{ .id = snd_soc_dapm_spk, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ + .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD} +#define SND_SOC_DAPM_LINE(wname, wevent) \ +{ .id = snd_soc_dapm_line, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ + .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD} + +#define SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert) \ + .reg = wreg, .mask = 1, .shift = wshift, \ + .on_val = winvert ? 0 : 1, .off_val = winvert ? 1 : 0 + +/* path domain */ +#define SND_SOC_DAPM_PGA(wname, wreg, wshift, winvert,\ + wcontrols, wncontrols) \ +{ .id = snd_soc_dapm_pga, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = wncontrols} +#define SND_SOC_DAPM_OUT_DRV(wname, wreg, wshift, winvert,\ + wcontrols, wncontrols) \ +{ .id = snd_soc_dapm_out_drv, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = wncontrols} +#define SND_SOC_DAPM_MIXER(wname, wreg, wshift, winvert, \ + wcontrols, wncontrols)\ +{ .id = snd_soc_dapm_mixer, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = wncontrols} +#define SND_SOC_DAPM_MIXER_NAMED_CTL(wname, wreg, wshift, winvert, \ + wcontrols, wncontrols)\ +{ .id = snd_soc_dapm_mixer_named_ctl, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = wncontrols} +/* DEPRECATED: use SND_SOC_DAPM_SUPPLY */ +#define SND_SOC_DAPM_MICBIAS(wname, wreg, wshift, winvert) \ +{ .id = snd_soc_dapm_micbias, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = NULL, .num_kcontrols = 0} +#define SND_SOC_DAPM_SWITCH(wname, wreg, wshift, winvert, wcontrols) \ +{ .id = snd_soc_dapm_switch, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = 1} +#define SND_SOC_DAPM_MUX(wname, wreg, wshift, winvert, wcontrols) \ +{ .id = snd_soc_dapm_mux, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = 1} +#define SND_SOC_DAPM_DEMUX(wname, wreg, wshift, winvert, wcontrols) \ +{ .id = snd_soc_dapm_demux, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = 1} + +/* Simplified versions of above macros, assuming wncontrols = ARRAY_SIZE(wcontrols) */ +#define SOC_PGA_ARRAY(wname, wreg, wshift, winvert,\ + wcontrols) \ +{ .id = snd_soc_dapm_pga, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols)} +#define SOC_MIXER_ARRAY(wname, wreg, wshift, winvert, \ + wcontrols)\ +{ .id = snd_soc_dapm_mixer, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols)} +#define SOC_MIXER_NAMED_CTL_ARRAY(wname, wreg, wshift, winvert, \ + wcontrols)\ +{ .id = snd_soc_dapm_mixer_named_ctl, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols)} + +/* path domain with event - event handler must return 0 for success */ +#define SND_SOC_DAPM_PGA_E(wname, wreg, wshift, winvert, wcontrols, \ + wncontrols, wevent, wflags) \ +{ .id = snd_soc_dapm_pga, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = wncontrols, \ + .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_OUT_DRV_E(wname, wreg, wshift, winvert, wcontrols, \ + wncontrols, wevent, wflags) \ +{ .id = snd_soc_dapm_out_drv, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = wncontrols, \ + .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_MIXER_E(wname, wreg, wshift, winvert, wcontrols, \ + wncontrols, wevent, wflags) \ +{ .id = snd_soc_dapm_mixer, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = wncontrols, \ + .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_MIXER_NAMED_CTL_E(wname, wreg, wshift, winvert, \ + wcontrols, wncontrols, wevent, wflags) \ +{ .id = snd_soc_dapm_mixer, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, \ + .num_kcontrols = wncontrols, .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_SWITCH_E(wname, wreg, wshift, winvert, wcontrols, \ + wevent, wflags) \ +{ .id = snd_soc_dapm_switch, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = 1, \ + .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_MUX_E(wname, wreg, wshift, winvert, wcontrols, \ + wevent, wflags) \ +{ .id = snd_soc_dapm_mux, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = 1, \ + .event = wevent, .event_flags = wflags} + +/* additional sequencing control within an event type */ +#define SND_SOC_DAPM_PGA_S(wname, wsubseq, wreg, wshift, winvert, \ + wevent, wflags) \ +{ .id = snd_soc_dapm_pga, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .event = wevent, .event_flags = wflags, \ + .subseq = wsubseq} +#define SND_SOC_DAPM_SUPPLY_S(wname, wsubseq, wreg, wshift, winvert, wevent, \ + wflags) \ +{ .id = snd_soc_dapm_supply, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .event = wevent, .event_flags = wflags, .subseq = wsubseq} + +/* Simplified versions of above macros, assuming wncontrols = ARRAY_SIZE(wcontrols) */ +#define SOC_PGA_E_ARRAY(wname, wreg, wshift, winvert, wcontrols, \ + wevent, wflags) \ +{ .id = snd_soc_dapm_pga, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols), \ + .event = wevent, .event_flags = wflags} +#define SOC_MIXER_E_ARRAY(wname, wreg, wshift, winvert, wcontrols, \ + wevent, wflags) \ +{ .id = snd_soc_dapm_mixer, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols), \ + .event = wevent, .event_flags = wflags} +#define SOC_MIXER_NAMED_CTL_E_ARRAY(wname, wreg, wshift, winvert, \ + wcontrols, wevent, wflags) \ +{ .id = snd_soc_dapm_mixer, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .kcontrol_news = wcontrols, .num_kcontrols = ARRAY_SIZE(wcontrols), \ + .event = wevent, .event_flags = wflags} + +/* events that are pre and post DAPM */ +#define SND_SOC_DAPM_PRE(wname, wevent) \ +{ .id = snd_soc_dapm_pre, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD} +#define SND_SOC_DAPM_POST(wname, wevent) \ +{ .id = snd_soc_dapm_post, .name = wname, .kcontrol_news = NULL, \ + .num_kcontrols = 0, .reg = SND_SOC_NOPM, .event = wevent, \ + .event_flags = SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD} + +/* stream domain */ +#define SND_SOC_DAPM_AIF_IN(wname, stname, wchan, wreg, wshift, winvert) \ +{ .id = snd_soc_dapm_aif_in, .name = wname, .sname = stname, \ + .channel = wchan, SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), } +#define SND_SOC_DAPM_AIF_IN_E(wname, stname, wchan, wreg, wshift, winvert, \ + wevent, wflags) \ +{ .id = snd_soc_dapm_aif_in, .name = wname, .sname = stname, \ + .channel = wchan, SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .event = wevent, .event_flags = wflags } +#define SND_SOC_DAPM_AIF_OUT(wname, stname, wchan, wreg, wshift, winvert) \ +{ .id = snd_soc_dapm_aif_out, .name = wname, .sname = stname, \ + .channel = wchan, SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), } +#define SND_SOC_DAPM_AIF_OUT_E(wname, stname, wchan, wreg, wshift, winvert, \ + wevent, wflags) \ +{ .id = snd_soc_dapm_aif_out, .name = wname, .sname = stname, \ + .channel = wchan, SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .event = wevent, .event_flags = wflags } +#define SND_SOC_DAPM_DAC(wname, stname, wreg, wshift, winvert) \ +{ .id = snd_soc_dapm_dac, .name = wname, .sname = stname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert) } +#define SND_SOC_DAPM_DAC_E(wname, stname, wreg, wshift, winvert, \ + wevent, wflags) \ +{ .id = snd_soc_dapm_dac, .name = wname, .sname = stname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .event = wevent, .event_flags = wflags} + +#define SND_SOC_DAPM_ADC(wname, stname, wreg, wshift, winvert) \ +{ .id = snd_soc_dapm_adc, .name = wname, .sname = stname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), } +#define SND_SOC_DAPM_ADC_E(wname, stname, wreg, wshift, winvert, \ + wevent, wflags) \ +{ .id = snd_soc_dapm_adc, .name = wname, .sname = stname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_CLOCK_SUPPLY(wname) \ +{ .id = snd_soc_dapm_clock_supply, .name = wname, \ + .reg = SND_SOC_NOPM, .event = dapm_clock_event, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD } + +/* generic widgets */ +#define SND_SOC_DAPM_REG(wid, wname, wreg, wshift, wmask, won_val, woff_val) \ +{ .id = wid, .name = wname, .kcontrol_news = NULL, .num_kcontrols = 0, \ + .reg = wreg, .shift = wshift, .mask = wmask, \ + .on_val = won_val, .off_val = woff_val, } +#define SND_SOC_DAPM_SUPPLY(wname, wreg, wshift, winvert, wevent, wflags) \ +{ .id = snd_soc_dapm_supply, .name = wname, \ + SND_SOC_DAPM_INIT_REG_VAL(wreg, wshift, winvert), \ + .event = wevent, .event_flags = wflags} +#define SND_SOC_DAPM_REGULATOR_SUPPLY(wname, wdelay, wflags) \ +{ .id = snd_soc_dapm_regulator_supply, .name = wname, \ + .reg = SND_SOC_NOPM, .shift = wdelay, .event = dapm_regulator_event, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD, \ + .on_val = wflags} +#define SND_SOC_DAPM_PINCTRL(wname, active, sleep) \ +{ .id = snd_soc_dapm_pinctrl, .name = wname, \ + .priv = (&(struct snd_soc_dapm_pinctrl_priv) \ + { .active_state = active, .sleep_state = sleep,}), \ + .reg = SND_SOC_NOPM, .event = dapm_pinctrl_event, \ + .event_flags = SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD } + + + +/* dapm kcontrol types */ +#define SOC_DAPM_DOUBLE(xname, reg, lshift, rshift, max, invert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \ + .private_value = SOC_DOUBLE_VALUE(reg, lshift, rshift, max, invert, 0) } +#define SOC_DAPM_DOUBLE_R(xname, lreg, rreg, shift, max, invert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \ + .private_value = SOC_DOUBLE_R_VALUE(lreg, rreg, shift, max, invert) } +#define SOC_DAPM_SINGLE(xname, reg, shift, max, invert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \ + .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } +#define SOC_DAPM_SINGLE_AUTODISABLE(xname, reg, shift, max, invert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \ + .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 1) } +#define SOC_DAPM_SINGLE_VIRT(xname, max) \ + SOC_DAPM_SINGLE(xname, SND_SOC_NOPM, 0, max, 0) +#define SOC_DAPM_SINGLE_TLV(xname, reg, shift, max, invert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_volsw, \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \ + .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } +#define SOC_DAPM_SINGLE_TLV_AUTODISABLE(xname, reg, shift, max, invert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_volsw, \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .get = snd_soc_dapm_get_volsw, .put = snd_soc_dapm_put_volsw, \ + .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 1) } +#define SOC_DAPM_SINGLE_TLV_VIRT(xname, max, tlv_array) \ + SOC_DAPM_SINGLE(xname, SND_SOC_NOPM, 0, max, 0, tlv_array) +#define SOC_DAPM_ENUM(xname, xenum) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_enum_double, \ + .get = snd_soc_dapm_get_enum_double, \ + .put = snd_soc_dapm_put_enum_double, \ + .private_value = (unsigned long)&xenum } +#define SOC_DAPM_ENUM_EXT(xname, xenum, xget, xput) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_enum_double, \ + .get = xget, \ + .put = xput, \ + .private_value = (unsigned long)&xenum } +#define SOC_DAPM_PIN_SWITCH(xname) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname " Switch", \ + .info = snd_soc_dapm_info_pin_switch, \ + .get = snd_soc_dapm_get_pin_switch, \ + .put = snd_soc_dapm_put_pin_switch, \ + .private_value = (unsigned long)xname } + +/* dapm stream operations */ +#define SND_SOC_DAPM_STREAM_NOP 0x0 +#define SND_SOC_DAPM_STREAM_START 0x1 +#define SND_SOC_DAPM_STREAM_STOP 0x2 +#define SND_SOC_DAPM_STREAM_SUSPEND 0x4 +#define SND_SOC_DAPM_STREAM_RESUME 0x8 +#define SND_SOC_DAPM_STREAM_PAUSE_PUSH 0x10 +#define SND_SOC_DAPM_STREAM_PAUSE_RELEASE 0x20 + +/* dapm event types */ +#define SND_SOC_DAPM_PRE_PMU 0x1 /* before widget power up */ +#define SND_SOC_DAPM_POST_PMU 0x2 /* after widget power up */ +#define SND_SOC_DAPM_PRE_PMD 0x4 /* before widget power down */ +#define SND_SOC_DAPM_POST_PMD 0x8 /* after widget power down */ +#define SND_SOC_DAPM_PRE_REG 0x10 /* before audio path setup */ +#define SND_SOC_DAPM_POST_REG 0x20 /* after audio path setup */ +#define SND_SOC_DAPM_WILL_PMU 0x40 /* called at start of sequence */ +#define SND_SOC_DAPM_WILL_PMD 0x80 /* called at start of sequence */ +#define SND_SOC_DAPM_PRE_POST_PMD \ + (SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD) +#define SND_SOC_DAPM_PRE_POST_PMU \ + (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU) + +/* convenience event type detection */ +#define SND_SOC_DAPM_EVENT_ON(e) \ + (e & (SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU)) +#define SND_SOC_DAPM_EVENT_OFF(e) \ + (e & (SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD)) + +/* regulator widget flags */ +#define SND_SOC_DAPM_REGULATOR_BYPASS 0x1 /* bypass when disabled */ + +struct snd_soc_dapm_widget; +enum snd_soc_dapm_type; +struct snd_soc_dapm_path; +struct snd_soc_dapm_pin; +struct snd_soc_dapm_route; +struct snd_soc_dapm_context; +struct regulator; +struct snd_soc_dapm_widget_list; +struct snd_soc_dapm_update; +enum snd_soc_dapm_direction; + +/* + * Bias levels + * + * @ON: Bias is fully on for audio playback and capture operations. + * @PREPARE: Prepare for audio operations. Called before DAPM switching for + * stream start and stop operations. + * @STANDBY: Low power standby state when no playback/capture operations are + * in progress. NOTE: The transition time between STANDBY and ON + * should be as fast as possible and no longer than 10ms. + * @OFF: Power Off. No restrictions on transition times. + */ +enum snd_soc_bias_level { + SND_SOC_BIAS_OFF = 0, + SND_SOC_BIAS_STANDBY = 1, + SND_SOC_BIAS_PREPARE = 2, + SND_SOC_BIAS_ON = 3, +}; + +int dapm_regulator_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +int dapm_clock_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); +int dapm_pinctrl_event(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *kcontrol, int event); + +/* dapm controls */ +int snd_soc_dapm_put_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_dapm_get_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_dapm_get_enum_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_dapm_put_enum_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_dapm_info_pin_switch(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_soc_dapm_get_pin_switch(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uncontrol); +int snd_soc_dapm_put_pin_switch(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *uncontrol); +int snd_soc_dapm_new_controls(struct snd_soc_dapm_context *dapm, + const struct snd_soc_dapm_widget *widget, + int num); +struct snd_soc_dapm_widget *snd_soc_dapm_new_control( + struct snd_soc_dapm_context *dapm, + const struct snd_soc_dapm_widget *widget); +struct snd_soc_dapm_widget *snd_soc_dapm_new_control_unlocked( + struct snd_soc_dapm_context *dapm, + const struct snd_soc_dapm_widget *widget); +int snd_soc_dapm_new_dai_widgets(struct snd_soc_dapm_context *dapm, + struct snd_soc_dai *dai); +void snd_soc_dapm_free_widget(struct snd_soc_dapm_widget *w); +int snd_soc_dapm_link_dai_widgets(struct snd_soc_card *card); +void snd_soc_dapm_connect_dai_link_widgets(struct snd_soc_card *card); + +int snd_soc_dapm_update_dai(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai); + +/* dapm path setup */ +int snd_soc_dapm_new_widgets(struct snd_soc_card *card); +void snd_soc_dapm_free(struct snd_soc_dapm_context *dapm); +void snd_soc_dapm_init(struct snd_soc_dapm_context *dapm, + struct snd_soc_card *card, + struct snd_soc_component *component); +int snd_soc_dapm_add_routes(struct snd_soc_dapm_context *dapm, + const struct snd_soc_dapm_route *route, int num); +int snd_soc_dapm_del_routes(struct snd_soc_dapm_context *dapm, + const struct snd_soc_dapm_route *route, int num); +int snd_soc_dapm_weak_routes(struct snd_soc_dapm_context *dapm, + const struct snd_soc_dapm_route *route, int num); +void snd_soc_dapm_free_widget(struct snd_soc_dapm_widget *w); +void snd_soc_dapm_reset_cache(struct snd_soc_dapm_context *dapm); + +/* dapm events */ +void snd_soc_dapm_stream_event(struct snd_soc_pcm_runtime *rtd, int stream, + int event); +void snd_soc_dapm_stream_stop(struct snd_soc_pcm_runtime *rtd, int stream); +void snd_soc_dapm_shutdown(struct snd_soc_card *card); + +/* external DAPM widget events */ +int snd_soc_dapm_mixer_update_power(struct snd_soc_dapm_context *dapm, + struct snd_kcontrol *kcontrol, int connect, + struct snd_soc_dapm_update *update); +int snd_soc_dapm_mux_update_power(struct snd_soc_dapm_context *dapm, + struct snd_kcontrol *kcontrol, int mux, struct soc_enum *e, + struct snd_soc_dapm_update *update); + +/* dapm sys fs - used by the core */ +extern struct attribute *soc_dapm_dev_attrs[]; +void snd_soc_dapm_debugfs_init(struct snd_soc_dapm_context *dapm, + struct dentry *parent); + +/* dapm audio pin control and status */ +int snd_soc_dapm_enable_pin(struct snd_soc_dapm_context *dapm, + const char *pin); +int snd_soc_dapm_enable_pin_unlocked(struct snd_soc_dapm_context *dapm, + const char *pin); +int snd_soc_dapm_disable_pin(struct snd_soc_dapm_context *dapm, + const char *pin); +int snd_soc_dapm_disable_pin_unlocked(struct snd_soc_dapm_context *dapm, + const char *pin); +int snd_soc_dapm_nc_pin(struct snd_soc_dapm_context *dapm, const char *pin); +int snd_soc_dapm_nc_pin_unlocked(struct snd_soc_dapm_context *dapm, + const char *pin); +int snd_soc_dapm_get_pin_status(struct snd_soc_dapm_context *dapm, + const char *pin); +int snd_soc_dapm_sync(struct snd_soc_dapm_context *dapm); +int snd_soc_dapm_sync_unlocked(struct snd_soc_dapm_context *dapm); +int snd_soc_dapm_force_enable_pin(struct snd_soc_dapm_context *dapm, + const char *pin); +int snd_soc_dapm_force_enable_pin_unlocked(struct snd_soc_dapm_context *dapm, + const char *pin); +int snd_soc_dapm_ignore_suspend(struct snd_soc_dapm_context *dapm, + const char *pin); +unsigned int dapm_kcontrol_get_value(const struct snd_kcontrol *kcontrol); + +/* Mostly internal - should not normally be used */ +void dapm_mark_endpoints_dirty(struct snd_soc_card *card); + +/* dapm path query */ +int snd_soc_dapm_dai_get_connected_widgets(struct snd_soc_dai *dai, int stream, + struct snd_soc_dapm_widget_list **list, + bool (*custom_stop_condition)(struct snd_soc_dapm_widget *, + enum snd_soc_dapm_direction)); +void snd_soc_dapm_dai_free_widgets(struct snd_soc_dapm_widget_list **list); + +struct snd_soc_dapm_context *snd_soc_dapm_kcontrol_dapm( + struct snd_kcontrol *kcontrol); + +struct snd_soc_dapm_widget *snd_soc_dapm_kcontrol_widget( + struct snd_kcontrol *kcontrol); + +int snd_soc_dapm_force_bias_level(struct snd_soc_dapm_context *dapm, + enum snd_soc_bias_level level); + +/* dapm widget types */ +enum snd_soc_dapm_type { + snd_soc_dapm_input = 0, /* input pin */ + snd_soc_dapm_output, /* output pin */ + snd_soc_dapm_mux, /* selects 1 analog signal from many inputs */ + snd_soc_dapm_demux, /* connects the input to one of multiple outputs */ + snd_soc_dapm_mixer, /* mixes several analog signals together */ + snd_soc_dapm_mixer_named_ctl, /* mixer with named controls */ + snd_soc_dapm_pga, /* programmable gain/attenuation (volume) */ + snd_soc_dapm_out_drv, /* output driver */ + snd_soc_dapm_adc, /* analog to digital converter */ + snd_soc_dapm_dac, /* digital to analog converter */ + snd_soc_dapm_micbias, /* microphone bias (power) - DEPRECATED: use snd_soc_dapm_supply */ + snd_soc_dapm_mic, /* microphone */ + snd_soc_dapm_hp, /* headphones */ + snd_soc_dapm_spk, /* speaker */ + snd_soc_dapm_line, /* line input/output */ + snd_soc_dapm_switch, /* analog switch */ + snd_soc_dapm_vmid, /* codec bias/vmid - to minimise pops */ + snd_soc_dapm_pre, /* machine specific pre widget - exec first */ + snd_soc_dapm_post, /* machine specific post widget - exec last */ + snd_soc_dapm_supply, /* power/clock supply */ + snd_soc_dapm_pinctrl, /* pinctrl */ + snd_soc_dapm_regulator_supply, /* external regulator */ + snd_soc_dapm_clock_supply, /* external clock */ + snd_soc_dapm_aif_in, /* audio interface input */ + snd_soc_dapm_aif_out, /* audio interface output */ + snd_soc_dapm_siggen, /* signal generator */ + snd_soc_dapm_sink, + snd_soc_dapm_dai_in, /* link to DAI structure */ + snd_soc_dapm_dai_out, + snd_soc_dapm_dai_link, /* link between two DAI structures */ + snd_soc_dapm_kcontrol, /* Auto-disabled kcontrol */ + snd_soc_dapm_buffer, /* DSP/CODEC internal buffer */ + snd_soc_dapm_scheduler, /* DSP/CODEC internal scheduler */ + snd_soc_dapm_effect, /* DSP/CODEC effect component */ + snd_soc_dapm_src, /* DSP/CODEC SRC component */ + snd_soc_dapm_asrc, /* DSP/CODEC ASRC component */ + snd_soc_dapm_encoder, /* FW/SW audio encoder component */ + snd_soc_dapm_decoder, /* FW/SW audio decoder component */ + + /* Don't edit below this line */ + SND_SOC_DAPM_TYPE_COUNT +}; + +enum snd_soc_dapm_subclass { + SND_SOC_DAPM_CLASS_INIT = 0, + SND_SOC_DAPM_CLASS_RUNTIME = 1, +}; + +/* + * DAPM audio route definition. + * + * Defines an audio route originating at source via control and finishing + * at sink. + */ +struct snd_soc_dapm_route { + const char *sink; + const char *control; + const char *source; + + /* Note: currently only supported for links where source is a supply */ + int (*connected)(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink); + + struct snd_soc_dobj dobj; +}; + +/* dapm audio path between two widgets */ +struct snd_soc_dapm_path { + const char *name; + + /* + * source (input) and sink (output) widgets + * The union is for convience, since it is a lot nicer to type + * p->source, rather than p->node[SND_SOC_DAPM_DIR_IN] + */ + union { + struct { + struct snd_soc_dapm_widget *source; + struct snd_soc_dapm_widget *sink; + }; + struct snd_soc_dapm_widget *node[2]; + }; + + /* status */ + u32 connect:1; /* source and sink widgets are connected */ + u32 walking:1; /* path is in the process of being walked */ + u32 weak:1; /* path ignored for power management */ + u32 is_supply:1; /* At least one of the connected widgets is a supply */ + + int (*connected)(struct snd_soc_dapm_widget *source, + struct snd_soc_dapm_widget *sink); + + struct list_head list_node[2]; + struct list_head list_kcontrol; + struct list_head list; +}; + +/* dapm widget */ +struct snd_soc_dapm_widget { + enum snd_soc_dapm_type id; + const char *name; /* widget name */ + const char *sname; /* stream name */ + struct list_head list; + struct snd_soc_dapm_context *dapm; + + void *priv; /* widget specific data */ + struct regulator *regulator; /* attached regulator */ + struct pinctrl *pinctrl; /* attached pinctrl */ + + /* dapm control */ + int reg; /* negative reg = no direct dapm */ + unsigned char shift; /* bits to shift */ + unsigned int mask; /* non-shifted mask */ + unsigned int on_val; /* on state value */ + unsigned int off_val; /* off state value */ + unsigned char power:1; /* block power status */ + unsigned char active:1; /* active stream on DAC, ADC's */ + unsigned char connected:1; /* connected codec pin */ + unsigned char new:1; /* cnew complete */ + unsigned char force:1; /* force state */ + unsigned char ignore_suspend:1; /* kept enabled over suspend */ + unsigned char new_power:1; /* power from this run */ + unsigned char power_checked:1; /* power checked this run */ + unsigned char is_supply:1; /* Widget is a supply type widget */ + unsigned char is_ep:2; /* Widget is a endpoint type widget */ + int subseq; /* sort within widget type */ + + int (*power_check)(struct snd_soc_dapm_widget *w); + + /* external events */ + unsigned short event_flags; /* flags to specify event types */ + int (*event)(struct snd_soc_dapm_widget*, struct snd_kcontrol *, int); + + /* kcontrols that relate to this widget */ + int num_kcontrols; + const struct snd_kcontrol_new *kcontrol_news; + struct snd_kcontrol **kcontrols; + struct snd_soc_dobj dobj; + + /* widget input and output edges */ + struct list_head edges[2]; + + /* used during DAPM updates */ + struct list_head work_list; + struct list_head power_list; + struct list_head dirty; + int endpoints[2]; + + struct clk *clk; + + int channel; +}; + +struct snd_soc_dapm_update { + struct snd_kcontrol *kcontrol; + int reg; + int mask; + int val; + int reg2; + int mask2; + int val2; + bool has_second_set; +}; + +struct snd_soc_dapm_wcache { + struct snd_soc_dapm_widget *widget; +}; + +/* DAPM context */ +struct snd_soc_dapm_context { + enum snd_soc_bias_level bias_level; + unsigned int idle_bias_off:1; /* Use BIAS_OFF instead of STANDBY */ + /* Go to BIAS_OFF in suspend if the DAPM context is idle */ + unsigned int suspend_bias_off:1; + + struct device *dev; /* from parent - for debug */ + struct snd_soc_component *component; /* parent component */ + struct snd_soc_card *card; /* parent card */ + + /* used during DAPM updates */ + enum snd_soc_bias_level target_bias_level; + struct list_head list; + + struct snd_soc_dapm_wcache path_sink_cache; + struct snd_soc_dapm_wcache path_source_cache; + +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_dapm; +#endif +}; + +/* A list of widgets associated with an object, typically a snd_kcontrol */ +struct snd_soc_dapm_widget_list { + int num_widgets; + struct snd_soc_dapm_widget *widgets[]; +}; + +#define for_each_dapm_widgets(list, i, widget) \ + for ((i) = 0; \ + (i) < list->num_widgets && (widget = list->widgets[i]); \ + (i)++) + +struct snd_soc_dapm_stats { + int power_checks; + int path_checks; + int neighbour_checks; +}; + +struct snd_soc_dapm_pinctrl_priv { + const char *active_state; + const char *sleep_state; +}; + +/** + * snd_soc_dapm_init_bias_level() - Initialize DAPM bias level + * @dapm: The DAPM context to initialize + * @level: The DAPM level to initialize to + * + * This function only sets the driver internal state of the DAPM level and will + * not modify the state of the device. Hence it should not be used during normal + * operation, but only to synchronize the internal state to the device state. + * E.g. during driver probe to set the DAPM level to the one corresponding with + * the power-on reset state of the device. + * + * To change the DAPM state of the device use snd_soc_dapm_set_bias_level(). + */ +static inline void snd_soc_dapm_init_bias_level( + struct snd_soc_dapm_context *dapm, enum snd_soc_bias_level level) +{ + dapm->bias_level = level; +} + +/** + * snd_soc_dapm_get_bias_level() - Get current DAPM bias level + * @dapm: The context for which to get the bias level + * + * Returns: The current bias level of the passed DAPM context. + */ +static inline enum snd_soc_bias_level snd_soc_dapm_get_bias_level( + struct snd_soc_dapm_context *dapm) +{ + return dapm->bias_level; +} + +enum snd_soc_dapm_direction { + SND_SOC_DAPM_DIR_IN, + SND_SOC_DAPM_DIR_OUT +}; + +#define SND_SOC_DAPM_DIR_TO_EP(x) BIT(x) + +#define SND_SOC_DAPM_EP_SOURCE SND_SOC_DAPM_DIR_TO_EP(SND_SOC_DAPM_DIR_IN) +#define SND_SOC_DAPM_EP_SINK SND_SOC_DAPM_DIR_TO_EP(SND_SOC_DAPM_DIR_OUT) + +/** + * snd_soc_dapm_widget_for_each_sink_path - Iterates over all paths in the + * specified direction of a widget + * @w: The widget + * @dir: Whether to iterate over the paths where the specified widget is the + * incoming or outgoing widgets + * @p: The path iterator variable + */ +#define snd_soc_dapm_widget_for_each_path(w, dir, p) \ + list_for_each_entry(p, &w->edges[dir], list_node[dir]) + +/** + * snd_soc_dapm_widget_for_each_sink_path_safe - Iterates over all paths in the + * specified direction of a widget + * @w: The widget + * @dir: Whether to iterate over the paths where the specified widget is the + * incoming or outgoing widgets + * @p: The path iterator variable + * @next_p: Temporary storage for the next path + * + * This function works like snd_soc_dapm_widget_for_each_sink_path, expect that + * it is safe to remove the current path from the list while iterating + */ +#define snd_soc_dapm_widget_for_each_path_safe(w, dir, p, next_p) \ + list_for_each_entry_safe(p, next_p, &w->edges[dir], list_node[dir]) + +/** + * snd_soc_dapm_widget_for_each_sink_path - Iterates over all paths leaving a + * widget + * @w: The widget + * @p: The path iterator variable + */ +#define snd_soc_dapm_widget_for_each_sink_path(w, p) \ + snd_soc_dapm_widget_for_each_path(w, SND_SOC_DAPM_DIR_IN, p) + +/** + * snd_soc_dapm_widget_for_each_source_path - Iterates over all paths leading to + * a widget + * @w: The widget + * @p: The path iterator variable + */ +#define snd_soc_dapm_widget_for_each_source_path(w, p) \ + snd_soc_dapm_widget_for_each_path(w, SND_SOC_DAPM_DIR_OUT, p) + +#endif diff --git a/include/sound/soc-dpcm.h b/include/sound/soc-dpcm.h new file mode 100644 index 000000000..27a5642f0 --- /dev/null +++ b/include/sound/soc-dpcm.h @@ -0,0 +1,177 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * linux/sound/soc-dpcm.h -- ALSA SoC Dynamic PCM Support + * + * Author: Liam Girdwood <lrg@ti.com> + */ + +#ifndef __LINUX_SND_SOC_DPCM_H +#define __LINUX_SND_SOC_DPCM_H + +#include <linux/slab.h> +#include <linux/list.h> +#include <sound/pcm.h> + +struct snd_soc_pcm_runtime; + +/* + * Types of runtime_update to perform. e.g. originated from FE PCM ops + * or audio route changes triggered by muxes/mixers. + */ +enum snd_soc_dpcm_update { + SND_SOC_DPCM_UPDATE_NO = 0, + SND_SOC_DPCM_UPDATE_BE, + SND_SOC_DPCM_UPDATE_FE, +}; + +/* + * Dynamic PCM Frontend -> Backend link management states. + */ +enum snd_soc_dpcm_link_state { + SND_SOC_DPCM_LINK_STATE_NEW = 0, /* newly created link */ + SND_SOC_DPCM_LINK_STATE_FREE, /* link to be dismantled */ +}; + +/* + * Dynamic PCM Frontend -> Backend link PCM states. + */ +enum snd_soc_dpcm_state { + SND_SOC_DPCM_STATE_NEW = 0, + SND_SOC_DPCM_STATE_OPEN, + SND_SOC_DPCM_STATE_HW_PARAMS, + SND_SOC_DPCM_STATE_PREPARE, + SND_SOC_DPCM_STATE_START, + SND_SOC_DPCM_STATE_STOP, + SND_SOC_DPCM_STATE_PAUSED, + SND_SOC_DPCM_STATE_SUSPEND, + SND_SOC_DPCM_STATE_HW_FREE, + SND_SOC_DPCM_STATE_CLOSE, +}; + +/* + * Dynamic PCM trigger ordering. Triggering flexibility is required as some + * DSPs require triggering before/after their CPU platform and DAIs. + * + * i.e. some clients may want to manually order this call in their PCM + * trigger() whilst others will just use the regular core ordering. + */ +enum snd_soc_dpcm_trigger { + SND_SOC_DPCM_TRIGGER_PRE = 0, + SND_SOC_DPCM_TRIGGER_POST, + SND_SOC_DPCM_TRIGGER_BESPOKE, +}; + +/* + * Dynamic PCM link + * This links together a FE and BE DAI at runtime and stores the link + * state information and the hw_params configuration. + */ +struct snd_soc_dpcm { + /* FE and BE DAIs*/ + struct snd_soc_pcm_runtime *be; + struct snd_soc_pcm_runtime *fe; + + /* link state */ + enum snd_soc_dpcm_link_state state; + + /* list of BE and FE for this DPCM link */ + struct list_head list_be; + struct list_head list_fe; + + /* hw params for this link - may be different for each link */ + struct snd_pcm_hw_params hw_params; +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_state; +#endif +}; + +/* + * Dynamic PCM runtime data. + */ +struct snd_soc_dpcm_runtime { + struct list_head be_clients; + struct list_head fe_clients; + + int users; + struct snd_pcm_runtime *runtime; + struct snd_pcm_hw_params hw_params; + + /* state and update */ + enum snd_soc_dpcm_update runtime_update; + enum snd_soc_dpcm_state state; + + int trigger_pending; /* trigger cmd + 1 if pending, 0 if not */ + + int be_start; /* refcount protected by BE stream pcm lock */ + int be_pause; /* refcount protected by BE stream pcm lock */ + bool fe_pause; /* used to track STOP after PAUSE */ +}; + +#define for_each_dpcm_fe(be, stream, _dpcm) \ + list_for_each_entry(_dpcm, &(be)->dpcm[stream].fe_clients, list_fe) + +#define for_each_dpcm_be(fe, stream, _dpcm) \ + list_for_each_entry(_dpcm, &(fe)->dpcm[stream].be_clients, list_be) +#define for_each_dpcm_be_safe(fe, stream, _dpcm, __dpcm) \ + list_for_each_entry_safe(_dpcm, __dpcm, &(fe)->dpcm[stream].be_clients, list_be) +#define for_each_dpcm_be_rollback(fe, stream, _dpcm) \ + list_for_each_entry_continue_reverse(_dpcm, &(fe)->dpcm[stream].be_clients, list_be) + +/* can this BE stop and free */ +int snd_soc_dpcm_can_be_free_stop(struct snd_soc_pcm_runtime *fe, + struct snd_soc_pcm_runtime *be, int stream); + +/* can this BE perform a hw_params() */ +int snd_soc_dpcm_can_be_params(struct snd_soc_pcm_runtime *fe, + struct snd_soc_pcm_runtime *be, int stream); + +/* can this BE perform prepare */ +int snd_soc_dpcm_can_be_prepared(struct snd_soc_pcm_runtime *fe, + struct snd_soc_pcm_runtime *be, int stream); + +/* is the current PCM operation for this FE ? */ +int snd_soc_dpcm_fe_can_update(struct snd_soc_pcm_runtime *fe, int stream); + +/* is the current PCM operation for this BE ? */ +int snd_soc_dpcm_be_can_update(struct snd_soc_pcm_runtime *fe, + struct snd_soc_pcm_runtime *be, int stream); + +/* get the substream for this BE */ +struct snd_pcm_substream * + snd_soc_dpcm_get_substream(struct snd_soc_pcm_runtime *be, int stream); + +/* update audio routing between PCMs and any DAI links */ +int snd_soc_dpcm_runtime_update(struct snd_soc_card *card); + +#ifdef CONFIG_DEBUG_FS +void soc_dpcm_debugfs_add(struct snd_soc_pcm_runtime *rtd); +#else +static inline void soc_dpcm_debugfs_add(struct snd_soc_pcm_runtime *rtd) +{ +} +#endif + +int dpcm_path_get(struct snd_soc_pcm_runtime *fe, + int stream, struct snd_soc_dapm_widget_list **list_); +void dpcm_path_put(struct snd_soc_dapm_widget_list **list); +int dpcm_process_paths(struct snd_soc_pcm_runtime *fe, + int stream, struct snd_soc_dapm_widget_list **list, int new); +int dpcm_be_dai_startup(struct snd_soc_pcm_runtime *fe, int stream); +void dpcm_be_dai_stop(struct snd_soc_pcm_runtime *fe, int stream, + int do_hw_free, struct snd_soc_dpcm *last); +void dpcm_be_disconnect(struct snd_soc_pcm_runtime *fe, int stream); +void dpcm_clear_pending_state(struct snd_soc_pcm_runtime *fe, int stream); +void dpcm_be_dai_hw_free(struct snd_soc_pcm_runtime *fe, int stream); +int dpcm_be_dai_hw_params(struct snd_soc_pcm_runtime *fe, int tream); +int dpcm_be_dai_trigger(struct snd_soc_pcm_runtime *fe, int stream, int cmd); +int dpcm_be_dai_prepare(struct snd_soc_pcm_runtime *fe, int stream); +int dpcm_dapm_stream_event(struct snd_soc_pcm_runtime *fe, int dir, + int event); +bool dpcm_end_walk_at_be(struct snd_soc_dapm_widget *widget, enum snd_soc_dapm_direction dir); + +#define dpcm_be_dai_startup_rollback(fe, stream, last) \ + dpcm_be_dai_stop(fe, stream, 0, last) +#define dpcm_be_dai_startup_unwind(fe, stream) dpcm_be_dai_stop(fe, stream, 0, NULL) +#define dpcm_be_dai_shutdown(fe, stream) dpcm_be_dai_stop(fe, stream, 1, NULL) + +#endif diff --git a/include/sound/soc-jack.h b/include/sound/soc-jack.h new file mode 100644 index 000000000..a0abb1ee5 --- /dev/null +++ b/include/sound/soc-jack.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * soc-jack.h + * + * Copyright (C) 2019 Renesas Electronics Corp. + * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + */ +#ifndef __SOC_JACK_H +#define __SOC_JACK_H + +/** + * struct snd_soc_jack_pin - Describes a pin to update based on jack detection + * + * @pin: name of the pin to update + * @mask: bits to check for in reported jack status + * @invert: if non-zero then pin is enabled when status is not reported + * @list: internal list entry + */ +struct snd_soc_jack_pin { + struct list_head list; + const char *pin; + int mask; + bool invert; +}; + +/** + * struct snd_soc_jack_zone - Describes voltage zones of jack detection + * + * @min_mv: start voltage in mv + * @max_mv: end voltage in mv + * @jack_type: type of jack that is expected for this voltage + * @debounce_time: debounce_time for jack, codec driver should wait for this + * duration before reading the adc for voltages + * @list: internal list entry + */ +struct snd_soc_jack_zone { + unsigned int min_mv; + unsigned int max_mv; + unsigned int jack_type; + unsigned int debounce_time; + struct list_head list; +}; + +/** + * struct snd_soc_jack_gpio - Describes a gpio pin for jack detection + * + * @gpio: legacy gpio number + * @idx: gpio descriptor index within the function of the GPIO + * consumer device + * @gpiod_dev: GPIO consumer device + * @name: gpio name. Also as connection ID for the GPIO consumer + * device function name lookup + * @report: value to report when jack detected + * @invert: report presence in low state + * @debounce_time: debounce time in ms + * @wake: enable as wake source + * @jack_status_check: callback function which overrides the detection + * to provide more complex checks (eg, reading an + * ADC). + */ +struct snd_soc_jack_gpio { + unsigned int gpio; + unsigned int idx; + struct device *gpiod_dev; + const char *name; + int report; + int invert; + int debounce_time; + bool wake; + + /* private: */ + struct snd_soc_jack *jack; + struct delayed_work work; + struct notifier_block pm_notifier; + struct gpio_desc *desc; + + void *data; + /* public: */ + int (*jack_status_check)(void *data); +}; + +struct snd_soc_jack { + struct mutex mutex; + struct snd_jack *jack; + struct snd_soc_card *card; + struct list_head pins; + int status; + struct blocking_notifier_head notifier; + struct list_head jack_zones; +}; + +/* Jack reporting */ +void snd_soc_jack_report(struct snd_soc_jack *jack, int status, int mask); +int snd_soc_jack_add_pins(struct snd_soc_jack *jack, int count, + struct snd_soc_jack_pin *pins); +void snd_soc_jack_notifier_register(struct snd_soc_jack *jack, + struct notifier_block *nb); +void snd_soc_jack_notifier_unregister(struct snd_soc_jack *jack, + struct notifier_block *nb); +int snd_soc_jack_add_zones(struct snd_soc_jack *jack, int count, + struct snd_soc_jack_zone *zones); +int snd_soc_jack_get_type(struct snd_soc_jack *jack, int micbias_voltage); +#ifdef CONFIG_GPIOLIB +int snd_soc_jack_add_gpios(struct snd_soc_jack *jack, int count, + struct snd_soc_jack_gpio *gpios); +int snd_soc_jack_add_gpiods(struct device *gpiod_dev, + struct snd_soc_jack *jack, + int count, struct snd_soc_jack_gpio *gpios); +void snd_soc_jack_free_gpios(struct snd_soc_jack *jack, int count, + struct snd_soc_jack_gpio *gpios); +#else +static inline int snd_soc_jack_add_gpios(struct snd_soc_jack *jack, int count, + struct snd_soc_jack_gpio *gpios) +{ + return 0; +} + +static inline int snd_soc_jack_add_gpiods(struct device *gpiod_dev, + struct snd_soc_jack *jack, + int count, + struct snd_soc_jack_gpio *gpios) +{ + return 0; +} + +static inline void snd_soc_jack_free_gpios(struct snd_soc_jack *jack, int count, + struct snd_soc_jack_gpio *gpios) +{ +} +#endif + +#endif /* __SOC_JACK_H */ diff --git a/include/sound/soc-link.h b/include/sound/soc-link.h new file mode 100644 index 000000000..9314cde17 --- /dev/null +++ b/include/sound/soc-link.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * soc-link.h + * + * Copyright (C) 2019 Renesas Electronics Corp. + * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> + */ +#ifndef __SOC_LINK_H +#define __SOC_LINK_H + +int snd_soc_link_init(struct snd_soc_pcm_runtime *rtd); +void snd_soc_link_exit(struct snd_soc_pcm_runtime *rtd); +int snd_soc_link_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); + +int snd_soc_link_startup(struct snd_pcm_substream *substream); +void snd_soc_link_shutdown(struct snd_pcm_substream *substream, + int rollback); +int snd_soc_link_prepare(struct snd_pcm_substream *substream); +int snd_soc_link_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params); +void snd_soc_link_hw_free(struct snd_pcm_substream *substream, + int rollback); + +int snd_soc_link_trigger(struct snd_pcm_substream *substream, int cmd, + int rollback); +int snd_soc_link_compr_startup(struct snd_compr_stream *cstream); +void snd_soc_link_compr_shutdown(struct snd_compr_stream *cstream, + int rollback); +int snd_soc_link_compr_set_params(struct snd_compr_stream *cstream); + +#endif /* __SOC_LINK_H */ diff --git a/include/sound/soc-topology.h b/include/sound/soc-topology.h new file mode 100644 index 000000000..b4b896f83 --- /dev/null +++ b/include/sound/soc-topology.h @@ -0,0 +1,198 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * linux/sound/soc-topology.h -- ALSA SoC Firmware Controls and DAPM + * + * Copyright (C) 2012 Texas Instruments Inc. + * Copyright (C) 2015 Intel Corporation. + * + * Simple file API to load FW that includes mixers, coefficients, DAPM graphs, + * algorithms, equalisers, DAIs, widgets, FE caps, BE caps, codec link caps etc. + */ + +#ifndef __LINUX_SND_SOC_TPLG_H +#define __LINUX_SND_SOC_TPLG_H + +#include <sound/asoc.h> +#include <linux/list.h> + +struct firmware; +struct snd_kcontrol; +struct snd_soc_tplg_pcm_be; +struct snd_ctl_elem_value; +struct snd_ctl_elem_info; +struct snd_soc_dapm_widget; +struct snd_soc_component; +struct snd_soc_tplg_pcm_fe; +struct snd_soc_dapm_context; +struct snd_soc_card; +struct snd_kcontrol_new; +struct snd_soc_dai_link; +struct snd_soc_dai_driver; +struct snd_soc_dai; +struct snd_soc_dapm_route; + +/* dynamic object type */ +enum snd_soc_dobj_type { + SND_SOC_DOBJ_NONE = 0, /* object is not dynamic */ + SND_SOC_DOBJ_MIXER, + SND_SOC_DOBJ_BYTES, + SND_SOC_DOBJ_ENUM, + SND_SOC_DOBJ_GRAPH, + SND_SOC_DOBJ_WIDGET, + SND_SOC_DOBJ_DAI_LINK, + SND_SOC_DOBJ_PCM, + SND_SOC_DOBJ_CODEC_LINK, + SND_SOC_DOBJ_BACKEND_LINK, +}; + +/* dynamic control object */ +struct snd_soc_dobj_control { + struct snd_kcontrol *kcontrol; + char **dtexts; + unsigned long *dvalues; +}; + +/* dynamic widget object */ +struct snd_soc_dobj_widget { + unsigned int *kcontrol_type; /* kcontrol type: mixer, enum, bytes */ +}; + +/* generic dynamic object - all dynamic objects belong to this struct */ +struct snd_soc_dobj { + enum snd_soc_dobj_type type; + unsigned int index; /* objects can belong in different groups */ + struct list_head list; + struct snd_soc_tplg_ops *ops; + union { + struct snd_soc_dobj_control control; + struct snd_soc_dobj_widget widget; + }; + void *private; /* core does not touch this */ +}; + +/* + * Kcontrol operations - used to map handlers onto firmware based controls. + */ +struct snd_soc_tplg_kcontrol_ops { + u32 id; + int (*get)(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + int (*put)(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + int (*info)(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +}; + +/* Bytes ext operations, for TLV byte controls */ +struct snd_soc_tplg_bytes_ext_ops { + u32 id; + int (*get)(struct snd_kcontrol *kcontrol, unsigned int __user *bytes, + unsigned int size); + int (*put)(struct snd_kcontrol *kcontrol, + const unsigned int __user *bytes, unsigned int size); +}; + +/* + * DAPM widget event handlers - used to map handlers onto widgets. + */ +struct snd_soc_tplg_widget_events { + u16 type; + int (*event_handler)(struct snd_soc_dapm_widget *w, + struct snd_kcontrol *k, int event); +}; + +/* + * Public API - Used by component drivers to load and unload dynamic objects + * and their resources. + */ +struct snd_soc_tplg_ops { + + /* external kcontrol init - used for any driver specific init */ + int (*control_load)(struct snd_soc_component *, int index, + struct snd_kcontrol_new *, struct snd_soc_tplg_ctl_hdr *); + int (*control_unload)(struct snd_soc_component *, + struct snd_soc_dobj *); + + /* DAPM graph route element loading and unloading */ + int (*dapm_route_load)(struct snd_soc_component *, int index, + struct snd_soc_dapm_route *route); + int (*dapm_route_unload)(struct snd_soc_component *, + struct snd_soc_dobj *); + + /* external widget init - used for any driver specific init */ + int (*widget_load)(struct snd_soc_component *, int index, + struct snd_soc_dapm_widget *, + struct snd_soc_tplg_dapm_widget *); + int (*widget_ready)(struct snd_soc_component *, int index, + struct snd_soc_dapm_widget *, + struct snd_soc_tplg_dapm_widget *); + int (*widget_unload)(struct snd_soc_component *, + struct snd_soc_dobj *); + + /* FE DAI - used for any driver specific init */ + int (*dai_load)(struct snd_soc_component *, int index, + struct snd_soc_dai_driver *dai_drv, + struct snd_soc_tplg_pcm *pcm, struct snd_soc_dai *dai); + + int (*dai_unload)(struct snd_soc_component *, + struct snd_soc_dobj *); + + /* DAI link - used for any driver specific init */ + int (*link_load)(struct snd_soc_component *, int index, + struct snd_soc_dai_link *link, + struct snd_soc_tplg_link_config *cfg); + int (*link_unload)(struct snd_soc_component *, + struct snd_soc_dobj *); + + /* callback to handle vendor bespoke data */ + int (*vendor_load)(struct snd_soc_component *, int index, + struct snd_soc_tplg_hdr *); + int (*vendor_unload)(struct snd_soc_component *, + struct snd_soc_tplg_hdr *); + + /* completion - called at completion of firmware loading */ + int (*complete)(struct snd_soc_component *comp); + + /* manifest - optional to inform component of manifest */ + int (*manifest)(struct snd_soc_component *, int index, + struct snd_soc_tplg_manifest *); + + /* vendor specific kcontrol handlers available for binding */ + const struct snd_soc_tplg_kcontrol_ops *io_ops; + int io_ops_count; + + /* vendor specific bytes ext handlers available for binding */ + const struct snd_soc_tplg_bytes_ext_ops *bytes_ext_ops; + int bytes_ext_ops_count; +}; + +#ifdef CONFIG_SND_SOC_TOPOLOGY + +/* gets a pointer to data from the firmware block header */ +static inline const void *snd_soc_tplg_get_data(struct snd_soc_tplg_hdr *hdr) +{ + const void *ptr = hdr; + + return ptr + sizeof(*hdr); +} + +/* Dynamic Object loading and removal for component drivers */ +int snd_soc_tplg_component_load(struct snd_soc_component *comp, + struct snd_soc_tplg_ops *ops, const struct firmware *fw); +int snd_soc_tplg_component_remove(struct snd_soc_component *comp); + +/* Binds event handlers to dynamic widgets */ +int snd_soc_tplg_widget_bind_event(struct snd_soc_dapm_widget *w, + const struct snd_soc_tplg_widget_events *events, int num_events, + u16 event_type); + +#else + +static inline int snd_soc_tplg_component_remove(struct snd_soc_component *comp) +{ + return 0; +} + +#endif + +#endif diff --git a/include/sound/soc.h b/include/sound/soc.h new file mode 100644 index 000000000..108617cea --- /dev/null +++ b/include/sound/soc.h @@ -0,0 +1,1383 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * linux/sound/soc.h -- ALSA SoC Layer + * + * Author: Liam Girdwood + * Created: Aug 11th 2005 + * Copyright: Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_SOC_H +#define __LINUX_SND_SOC_H + +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/types.h> +#include <linux/notifier.h> +#include <linux/workqueue.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/regmap.h> +#include <linux/log2.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/compress_driver.h> +#include <sound/control.h> +#include <sound/ac97_codec.h> + +/* + * Convenience kcontrol builders + */ +#define SOC_DOUBLE_VALUE(xreg, shift_left, shift_right, xmax, xinvert, xautodisable) \ + ((unsigned long)&(struct soc_mixer_control) \ + {.reg = xreg, .rreg = xreg, .shift = shift_left, \ + .rshift = shift_right, .max = xmax, \ + .invert = xinvert, .autodisable = xautodisable}) +#define SOC_DOUBLE_S_VALUE(xreg, shift_left, shift_right, xmin, xmax, xsign_bit, xinvert, xautodisable) \ + ((unsigned long)&(struct soc_mixer_control) \ + {.reg = xreg, .rreg = xreg, .shift = shift_left, \ + .rshift = shift_right, .min = xmin, .max = xmax, \ + .sign_bit = xsign_bit, .invert = xinvert, .autodisable = xautodisable}) +#define SOC_SINGLE_VALUE(xreg, xshift, xmax, xinvert, xautodisable) \ + SOC_DOUBLE_VALUE(xreg, xshift, xshift, xmax, xinvert, xautodisable) +#define SOC_SINGLE_VALUE_EXT(xreg, xmax, xinvert) \ + ((unsigned long)&(struct soc_mixer_control) \ + {.reg = xreg, .max = xmax, .invert = xinvert}) +#define SOC_DOUBLE_R_VALUE(xlreg, xrreg, xshift, xmax, xinvert) \ + ((unsigned long)&(struct soc_mixer_control) \ + {.reg = xlreg, .rreg = xrreg, .shift = xshift, .rshift = xshift, \ + .max = xmax, .invert = xinvert}) +#define SOC_DOUBLE_R_S_VALUE(xlreg, xrreg, xshift, xmin, xmax, xsign_bit, xinvert) \ + ((unsigned long)&(struct soc_mixer_control) \ + {.reg = xlreg, .rreg = xrreg, .shift = xshift, .rshift = xshift, \ + .max = xmax, .min = xmin, .sign_bit = xsign_bit, \ + .invert = xinvert}) +#define SOC_DOUBLE_R_RANGE_VALUE(xlreg, xrreg, xshift, xmin, xmax, xinvert) \ + ((unsigned long)&(struct soc_mixer_control) \ + {.reg = xlreg, .rreg = xrreg, .shift = xshift, .rshift = xshift, \ + .min = xmin, .max = xmax, .invert = xinvert}) +#define SOC_SINGLE(xname, reg, shift, max, invert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ + .put = snd_soc_put_volsw, \ + .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } +#define SOC_SINGLE_RANGE(xname, xreg, xshift, xmin, xmax, xinvert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .info = snd_soc_info_volsw_range, .get = snd_soc_get_volsw_range, \ + .put = snd_soc_put_volsw_range, \ + .private_value = (unsigned long)&(struct soc_mixer_control) \ + {.reg = xreg, .rreg = xreg, .shift = xshift, \ + .rshift = xshift, .min = xmin, .max = xmax, \ + .invert = xinvert} } +#define SOC_SINGLE_TLV(xname, reg, shift, max, invert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ + .put = snd_soc_put_volsw, \ + .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) } +#define SOC_SINGLE_SX_TLV(xname, xreg, xshift, xmin, xmax, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array),\ + .info = snd_soc_info_volsw_sx, \ + .get = snd_soc_get_volsw_sx,\ + .put = snd_soc_put_volsw_sx, \ + .private_value = (unsigned long)&(struct soc_mixer_control) \ + {.reg = xreg, .rreg = xreg, \ + .shift = xshift, .rshift = xshift, \ + .max = xmax, .min = xmin} } +#define SOC_SINGLE_RANGE_TLV(xname, xreg, xshift, xmin, xmax, xinvert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw_range, \ + .get = snd_soc_get_volsw_range, .put = snd_soc_put_volsw_range, \ + .private_value = (unsigned long)&(struct soc_mixer_control) \ + {.reg = xreg, .rreg = xreg, .shift = xshift, \ + .rshift = xshift, .min = xmin, .max = xmax, \ + .invert = xinvert} } +#define SOC_DOUBLE(xname, reg, shift_left, shift_right, max, invert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .info = snd_soc_info_volsw, .get = snd_soc_get_volsw, \ + .put = snd_soc_put_volsw, \ + .private_value = SOC_DOUBLE_VALUE(reg, shift_left, shift_right, \ + max, invert, 0) } +#define SOC_DOUBLE_STS(xname, reg, shift_left, shift_right, max, invert) \ +{ \ + .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .info = snd_soc_info_volsw, .get = snd_soc_get_volsw, \ + .access = SNDRV_CTL_ELEM_ACCESS_READ | \ + SNDRV_CTL_ELEM_ACCESS_VOLATILE, \ + .private_value = SOC_DOUBLE_VALUE(reg, shift_left, shift_right, \ + max, invert, 0) } +#define SOC_DOUBLE_R(xname, reg_left, reg_right, xshift, xmax, xinvert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_get_volsw, .put = snd_soc_put_volsw, \ + .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \ + xmax, xinvert) } +#define SOC_DOUBLE_R_RANGE(xname, reg_left, reg_right, xshift, xmin, \ + xmax, xinvert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .info = snd_soc_info_volsw_range, \ + .get = snd_soc_get_volsw_range, .put = snd_soc_put_volsw_range, \ + .private_value = SOC_DOUBLE_R_RANGE_VALUE(reg_left, reg_right, \ + xshift, xmin, xmax, xinvert) } +#define SOC_DOUBLE_TLV(xname, reg, shift_left, shift_right, max, invert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, .get = snd_soc_get_volsw, \ + .put = snd_soc_put_volsw, \ + .private_value = SOC_DOUBLE_VALUE(reg, shift_left, shift_right, \ + max, invert, 0) } +#define SOC_DOUBLE_SX_TLV(xname, xreg, shift_left, shift_right, xmin, xmax, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw_sx, \ + .get = snd_soc_get_volsw_sx, \ + .put = snd_soc_put_volsw_sx, \ + .private_value = (unsigned long)&(struct soc_mixer_control) \ + {.reg = xreg, .rreg = xreg, \ + .shift = shift_left, .rshift = shift_right, \ + .max = xmax, .min = xmin} } +#define SOC_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, xinvert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_get_volsw, .put = snd_soc_put_volsw, \ + .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \ + xmax, xinvert) } +#define SOC_DOUBLE_R_RANGE_TLV(xname, reg_left, reg_right, xshift, xmin, \ + xmax, xinvert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw_range, \ + .get = snd_soc_get_volsw_range, .put = snd_soc_put_volsw_range, \ + .private_value = SOC_DOUBLE_R_RANGE_VALUE(reg_left, reg_right, \ + xshift, xmin, xmax, xinvert) } +#define SOC_DOUBLE_R_SX_TLV(xname, xreg, xrreg, xshift, xmin, xmax, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw_sx, \ + .get = snd_soc_get_volsw_sx, \ + .put = snd_soc_put_volsw_sx, \ + .private_value = (unsigned long)&(struct soc_mixer_control) \ + {.reg = xreg, .rreg = xrreg, \ + .shift = xshift, .rshift = xshift, \ + .max = xmax, .min = xmin} } +#define SOC_DOUBLE_R_S_TLV(xname, reg_left, reg_right, xshift, xmin, xmax, xsign_bit, xinvert, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = snd_soc_get_volsw, .put = snd_soc_put_volsw, \ + .private_value = SOC_DOUBLE_R_S_VALUE(reg_left, reg_right, xshift, \ + xmin, xmax, xsign_bit, xinvert) } +#define SOC_SINGLE_S_TLV(xname, xreg, xshift, xmin, xmax, xsign_bit, xinvert, tlv_array) \ + SOC_DOUBLE_R_S_TLV(xname, xreg, xreg, xshift, xmin, xmax, xsign_bit, xinvert, tlv_array) +#define SOC_SINGLE_S8_TLV(xname, xreg, xmin, xmax, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ + .put = snd_soc_put_volsw, \ + .private_value = (unsigned long)&(struct soc_mixer_control) \ + {.reg = xreg, .rreg = xreg, \ + .min = xmin, .max = xmax, \ + .sign_bit = 7,} } +#define SOC_DOUBLE_S8_TLV(xname, xreg, xmin, xmax, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\ + .put = snd_soc_put_volsw, \ + .private_value = SOC_DOUBLE_S_VALUE(xreg, 0, 8, xmin, xmax, 7, 0, 0) } +#define SOC_ENUM_DOUBLE(xreg, xshift_l, xshift_r, xitems, xtexts) \ +{ .reg = xreg, .shift_l = xshift_l, .shift_r = xshift_r, \ + .items = xitems, .texts = xtexts, \ + .mask = xitems ? roundup_pow_of_two(xitems) - 1 : 0} +#define SOC_ENUM_SINGLE(xreg, xshift, xitems, xtexts) \ + SOC_ENUM_DOUBLE(xreg, xshift, xshift, xitems, xtexts) +#define SOC_ENUM_SINGLE_EXT(xitems, xtexts) \ +{ .items = xitems, .texts = xtexts } +#define SOC_VALUE_ENUM_DOUBLE(xreg, xshift_l, xshift_r, xmask, xitems, xtexts, xvalues) \ +{ .reg = xreg, .shift_l = xshift_l, .shift_r = xshift_r, \ + .mask = xmask, .items = xitems, .texts = xtexts, .values = xvalues} +#define SOC_VALUE_ENUM_SINGLE(xreg, xshift, xmask, xitems, xtexts, xvalues) \ + SOC_VALUE_ENUM_DOUBLE(xreg, xshift, xshift, xmask, xitems, xtexts, xvalues) +#define SOC_VALUE_ENUM_SINGLE_AUTODISABLE(xreg, xshift, xmask, xitems, xtexts, xvalues) \ +{ .reg = xreg, .shift_l = xshift, .shift_r = xshift, \ + .mask = xmask, .items = xitems, .texts = xtexts, \ + .values = xvalues, .autodisable = 1} +#define SOC_ENUM_SINGLE_VIRT(xitems, xtexts) \ + SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, xitems, xtexts) +#define SOC_ENUM(xname, xenum) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname,\ + .info = snd_soc_info_enum_double, \ + .get = snd_soc_get_enum_double, .put = snd_soc_put_enum_double, \ + .private_value = (unsigned long)&xenum } +#define SOC_SINGLE_EXT(xname, xreg, xshift, xmax, xinvert,\ + xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmax, xinvert, 0) } +#define SOC_DOUBLE_EXT(xname, reg, shift_left, shift_right, max, invert,\ + xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = \ + SOC_DOUBLE_VALUE(reg, shift_left, shift_right, max, invert, 0) } +#define SOC_DOUBLE_R_EXT(xname, reg_left, reg_right, xshift, xmax, xinvert,\ + xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \ + xmax, xinvert) } +#define SOC_SINGLE_EXT_TLV(xname, xreg, xshift, xmax, xinvert,\ + xhandler_get, xhandler_put, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmax, xinvert, 0) } +#define SOC_SINGLE_RANGE_EXT_TLV(xname, xreg, xshift, xmin, xmax, xinvert, \ + xhandler_get, xhandler_put, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\ + SNDRV_CTL_ELEM_ACCESS_READWRITE,\ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw_range, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = (unsigned long)&(struct soc_mixer_control) \ + {.reg = xreg, .rreg = xreg, .shift = xshift, \ + .rshift = xshift, .min = xmin, .max = xmax, \ + .invert = xinvert} } +#define SOC_DOUBLE_EXT_TLV(xname, xreg, shift_left, shift_right, xmax, xinvert,\ + xhandler_get, xhandler_put, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = SOC_DOUBLE_VALUE(xreg, shift_left, shift_right, \ + xmax, xinvert, 0) } +#define SOC_DOUBLE_R_EXT_TLV(xname, reg_left, reg_right, xshift, xmax, xinvert,\ + xhandler_get, xhandler_put, tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = SOC_DOUBLE_R_VALUE(reg_left, reg_right, xshift, \ + xmax, xinvert) } +#define SOC_DOUBLE_R_S_EXT_TLV(xname, reg_left, reg_right, xshift, xmin, xmax, \ + xsign_bit, xinvert, xhandler_get, xhandler_put, \ + tlv_array) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \ + SNDRV_CTL_ELEM_ACCESS_READWRITE, \ + .tlv.p = (tlv_array), \ + .info = snd_soc_info_volsw, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = SOC_DOUBLE_R_S_VALUE(reg_left, reg_right, xshift, \ + xmin, xmax, xsign_bit, xinvert) } +#define SOC_SINGLE_S_EXT_TLV(xname, xreg, xshift, xmin, xmax, \ + xsign_bit, xinvert, xhandler_get, xhandler_put, \ + tlv_array) \ + SOC_DOUBLE_R_S_EXT_TLV(xname, xreg, xreg, xshift, xmin, xmax, \ + xsign_bit, xinvert, xhandler_get, xhandler_put, \ + tlv_array) +#define SOC_SINGLE_BOOL_EXT(xname, xdata, xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_bool_ext, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = xdata } +#define SOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_info_enum_double, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = (unsigned long)&xenum } +#define SOC_VALUE_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put) \ + SOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put) + +#define SND_SOC_BYTES(xname, xbase, xregs) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info, .get = snd_soc_bytes_get, \ + .put = snd_soc_bytes_put, .private_value = \ + ((unsigned long)&(struct soc_bytes) \ + {.base = xbase, .num_regs = xregs }) } +#define SND_SOC_BYTES_E(xname, xbase, xregs, xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info, .get = xhandler_get, \ + .put = xhandler_put, .private_value = \ + ((unsigned long)&(struct soc_bytes) \ + {.base = xbase, .num_regs = xregs }) } + +#define SND_SOC_BYTES_MASK(xname, xbase, xregs, xmask) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info, .get = snd_soc_bytes_get, \ + .put = snd_soc_bytes_put, .private_value = \ + ((unsigned long)&(struct soc_bytes) \ + {.base = xbase, .num_regs = xregs, \ + .mask = xmask }) } + +/* + * SND_SOC_BYTES_EXT is deprecated, please USE SND_SOC_BYTES_TLV instead + */ +#define SND_SOC_BYTES_EXT(xname, xcount, xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .info = snd_soc_bytes_info_ext, \ + .get = xhandler_get, .put = xhandler_put, \ + .private_value = (unsigned long)&(struct soc_bytes_ext) \ + {.max = xcount} } +#define SND_SOC_BYTES_TLV(xname, xcount, xhandler_get, xhandler_put) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ + .access = SNDRV_CTL_ELEM_ACCESS_TLV_READWRITE | \ + SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \ + .tlv.c = (snd_soc_bytes_tlv_callback), \ + .info = snd_soc_bytes_info_ext, \ + .private_value = (unsigned long)&(struct soc_bytes_ext) \ + {.max = xcount, .get = xhandler_get, .put = xhandler_put, } } +#define SOC_SINGLE_XR_SX(xname, xregbase, xregcount, xnbits, \ + xmin, xmax, xinvert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \ + .info = snd_soc_info_xr_sx, .get = snd_soc_get_xr_sx, \ + .put = snd_soc_put_xr_sx, \ + .private_value = (unsigned long)&(struct soc_mreg_control) \ + {.regbase = xregbase, .regcount = xregcount, .nbits = xnbits, \ + .invert = xinvert, .min = xmin, .max = xmax} } + +#define SOC_SINGLE_STROBE(xname, xreg, xshift, xinvert) \ + SOC_SINGLE_EXT(xname, xreg, xshift, 1, xinvert, \ + snd_soc_get_strobe, snd_soc_put_strobe) + +/* + * Simplified versions of above macros, declaring a struct and calculating + * ARRAY_SIZE internally + */ +#define SOC_ENUM_DOUBLE_DECL(name, xreg, xshift_l, xshift_r, xtexts) \ + const struct soc_enum name = SOC_ENUM_DOUBLE(xreg, xshift_l, xshift_r, \ + ARRAY_SIZE(xtexts), xtexts) +#define SOC_ENUM_SINGLE_DECL(name, xreg, xshift, xtexts) \ + SOC_ENUM_DOUBLE_DECL(name, xreg, xshift, xshift, xtexts) +#define SOC_ENUM_SINGLE_EXT_DECL(name, xtexts) \ + const struct soc_enum name = SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(xtexts), xtexts) +#define SOC_VALUE_ENUM_DOUBLE_DECL(name, xreg, xshift_l, xshift_r, xmask, xtexts, xvalues) \ + const struct soc_enum name = SOC_VALUE_ENUM_DOUBLE(xreg, xshift_l, xshift_r, xmask, \ + ARRAY_SIZE(xtexts), xtexts, xvalues) +#define SOC_VALUE_ENUM_SINGLE_DECL(name, xreg, xshift, xmask, xtexts, xvalues) \ + SOC_VALUE_ENUM_DOUBLE_DECL(name, xreg, xshift, xshift, xmask, xtexts, xvalues) + +#define SOC_VALUE_ENUM_SINGLE_AUTODISABLE_DECL(name, xreg, xshift, xmask, xtexts, xvalues) \ + const struct soc_enum name = SOC_VALUE_ENUM_SINGLE_AUTODISABLE(xreg, \ + xshift, xmask, ARRAY_SIZE(xtexts), xtexts, xvalues) + +#define SOC_ENUM_SINGLE_VIRT_DECL(name, xtexts) \ + const struct soc_enum name = SOC_ENUM_SINGLE_VIRT(ARRAY_SIZE(xtexts), xtexts) + +struct device_node; +struct snd_jack; +struct snd_soc_card; +struct snd_soc_pcm_stream; +struct snd_soc_ops; +struct snd_soc_pcm_runtime; +struct snd_soc_dai; +struct snd_soc_dai_driver; +struct snd_soc_dai_link; +struct snd_soc_component; +struct snd_soc_component_driver; +struct soc_enum; +struct snd_soc_jack; +struct snd_soc_jack_zone; +struct snd_soc_jack_pin; +#include <sound/soc-dapm.h> +#include <sound/soc-dpcm.h> +#include <sound/soc-topology.h> + +struct snd_soc_jack_gpio; + +enum snd_soc_pcm_subclass { + SND_SOC_PCM_CLASS_PCM = 0, + SND_SOC_PCM_CLASS_BE = 1, +}; + +int snd_soc_register_card(struct snd_soc_card *card); +void snd_soc_unregister_card(struct snd_soc_card *card); +int devm_snd_soc_register_card(struct device *dev, struct snd_soc_card *card); +#ifdef CONFIG_PM_SLEEP +int snd_soc_suspend(struct device *dev); +int snd_soc_resume(struct device *dev); +#else +static inline int snd_soc_suspend(struct device *dev) +{ + return 0; +} + +static inline int snd_soc_resume(struct device *dev) +{ + return 0; +} +#endif +int snd_soc_poweroff(struct device *dev); +int snd_soc_component_initialize(struct snd_soc_component *component, + const struct snd_soc_component_driver *driver, + struct device *dev); +int snd_soc_add_component(struct snd_soc_component *component, + struct snd_soc_dai_driver *dai_drv, + int num_dai); +int snd_soc_register_component(struct device *dev, + const struct snd_soc_component_driver *component_driver, + struct snd_soc_dai_driver *dai_drv, int num_dai); +int devm_snd_soc_register_component(struct device *dev, + const struct snd_soc_component_driver *component_driver, + struct snd_soc_dai_driver *dai_drv, int num_dai); +void snd_soc_unregister_component(struct device *dev); +void snd_soc_unregister_component_by_driver(struct device *dev, + const struct snd_soc_component_driver *component_driver); +struct snd_soc_component *snd_soc_lookup_component_nolocked(struct device *dev, + const char *driver_name); +struct snd_soc_component *snd_soc_lookup_component(struct device *dev, + const char *driver_name); + +int soc_new_pcm(struct snd_soc_pcm_runtime *rtd, int num); +#ifdef CONFIG_SND_SOC_COMPRESS +int snd_soc_new_compress(struct snd_soc_pcm_runtime *rtd, int num); +#else +static inline int snd_soc_new_compress(struct snd_soc_pcm_runtime *rtd, int num) +{ + return 0; +} +#endif + +void snd_soc_disconnect_sync(struct device *dev); + +struct snd_soc_pcm_runtime *snd_soc_get_pcm_runtime(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_link); + +bool snd_soc_runtime_ignore_pmdown_time(struct snd_soc_pcm_runtime *rtd); + +void snd_soc_runtime_action(struct snd_soc_pcm_runtime *rtd, + int stream, int action); +static inline void snd_soc_runtime_activate(struct snd_soc_pcm_runtime *rtd, + int stream) +{ + snd_soc_runtime_action(rtd, stream, 1); +} +static inline void snd_soc_runtime_deactivate(struct snd_soc_pcm_runtime *rtd, + int stream) +{ + snd_soc_runtime_action(rtd, stream, -1); +} + +int snd_soc_runtime_calc_hw(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hardware *hw, int stream); + +int snd_soc_runtime_set_dai_fmt(struct snd_soc_pcm_runtime *rtd, + unsigned int dai_fmt); + +#ifdef CONFIG_DMI +int snd_soc_set_dmi_name(struct snd_soc_card *card, const char *flavour); +#else +static inline int snd_soc_set_dmi_name(struct snd_soc_card *card, + const char *flavour) +{ + return 0; +} +#endif + +/* Utility functions to get clock rates from various things */ +int snd_soc_calc_frame_size(int sample_size, int channels, int tdm_slots); +int snd_soc_params_to_frame_size(struct snd_pcm_hw_params *params); +int snd_soc_calc_bclk(int fs, int sample_size, int channels, int tdm_slots); +int snd_soc_params_to_bclk(struct snd_pcm_hw_params *parms); +int snd_soc_tdm_params_to_bclk(struct snd_pcm_hw_params *params, + int tdm_width, int tdm_slots, int slot_multiple); + +/* set runtime hw params */ +int snd_soc_set_runtime_hwparams(struct snd_pcm_substream *substream, + const struct snd_pcm_hardware *hw); + +struct snd_ac97 *snd_soc_alloc_ac97_component(struct snd_soc_component *component); +struct snd_ac97 *snd_soc_new_ac97_component(struct snd_soc_component *component, + unsigned int id, unsigned int id_mask); +void snd_soc_free_ac97_component(struct snd_ac97 *ac97); + +#ifdef CONFIG_SND_SOC_AC97_BUS +int snd_soc_set_ac97_ops(struct snd_ac97_bus_ops *ops); +int snd_soc_set_ac97_ops_of_reset(struct snd_ac97_bus_ops *ops, + struct platform_device *pdev); + +extern struct snd_ac97_bus_ops *soc_ac97_ops; +#else +static inline int snd_soc_set_ac97_ops_of_reset(struct snd_ac97_bus_ops *ops, + struct platform_device *pdev) +{ + return 0; +} + +static inline int snd_soc_set_ac97_ops(struct snd_ac97_bus_ops *ops) +{ + return 0; +} +#endif + +/* + *Controls + */ +struct snd_kcontrol *snd_soc_cnew(const struct snd_kcontrol_new *_template, + void *data, const char *long_name, + const char *prefix); +int snd_soc_add_component_controls(struct snd_soc_component *component, + const struct snd_kcontrol_new *controls, unsigned int num_controls); +int snd_soc_add_card_controls(struct snd_soc_card *soc_card, + const struct snd_kcontrol_new *controls, int num_controls); +int snd_soc_add_dai_controls(struct snd_soc_dai *dai, + const struct snd_kcontrol_new *controls, int num_controls); +int snd_soc_info_enum_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_soc_get_enum_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_put_enum_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_info_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_soc_info_volsw_sx(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +#define snd_soc_info_bool_ext snd_ctl_boolean_mono_info +int snd_soc_get_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_put_volsw(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +#define snd_soc_get_volsw_2r snd_soc_get_volsw +#define snd_soc_put_volsw_2r snd_soc_put_volsw +int snd_soc_get_volsw_sx(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_put_volsw_sx(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_info_volsw_range(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_soc_put_volsw_range(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_get_volsw_range(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_limit_volume(struct snd_soc_card *card, + const char *name, int max); +int snd_soc_bytes_info(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_soc_bytes_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_bytes_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_bytes_info_ext(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *ucontrol); +int snd_soc_bytes_tlv_callback(struct snd_kcontrol *kcontrol, int op_flag, + unsigned int size, unsigned int __user *tlv); +int snd_soc_info_xr_sx(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_soc_get_xr_sx(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_put_xr_sx(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_get_strobe(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_soc_put_strobe(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +/* SoC PCM stream information */ +struct snd_soc_pcm_stream { + const char *stream_name; + u64 formats; /* SNDRV_PCM_FMTBIT_* */ + unsigned int rates; /* SNDRV_PCM_RATE_* */ + unsigned int rate_min; /* min rate */ + unsigned int rate_max; /* max rate */ + unsigned int channels_min; /* min channels */ + unsigned int channels_max; /* max channels */ + unsigned int sig_bits; /* number of bits of content */ +}; + +/* SoC audio ops */ +struct snd_soc_ops { + int (*startup)(struct snd_pcm_substream *); + void (*shutdown)(struct snd_pcm_substream *); + int (*hw_params)(struct snd_pcm_substream *, struct snd_pcm_hw_params *); + int (*hw_free)(struct snd_pcm_substream *); + int (*prepare)(struct snd_pcm_substream *); + int (*trigger)(struct snd_pcm_substream *, int); +}; + +struct snd_soc_compr_ops { + int (*startup)(struct snd_compr_stream *); + void (*shutdown)(struct snd_compr_stream *); + int (*set_params)(struct snd_compr_stream *); + int (*trigger)(struct snd_compr_stream *); +}; + +struct snd_soc_component* +snd_soc_rtdcom_lookup(struct snd_soc_pcm_runtime *rtd, + const char *driver_name); + +struct snd_soc_dai_link_component { + const char *name; + struct device_node *of_node; + const char *dai_name; +}; + +struct snd_soc_dai_link { + /* config - must be set by machine driver */ + const char *name; /* Codec name */ + const char *stream_name; /* Stream name */ + + /* + * You MAY specify the link's CPU-side device, either by device name, + * or by DT/OF node, but not both. If this information is omitted, + * the CPU-side DAI is matched using .cpu_dai_name only, which hence + * must be globally unique. These fields are currently typically used + * only for codec to codec links, or systems using device tree. + */ + /* + * You MAY specify the DAI name of the CPU DAI. If this information is + * omitted, the CPU-side DAI is matched using .cpu_name/.cpu_of_node + * only, which only works well when that device exposes a single DAI. + */ + struct snd_soc_dai_link_component *cpus; + unsigned int num_cpus; + + /* + * You MUST specify the link's codec, either by device name, or by + * DT/OF node, but not both. + */ + /* You MUST specify the DAI name within the codec */ + struct snd_soc_dai_link_component *codecs; + unsigned int num_codecs; + + /* + * You MAY specify the link's platform/PCM/DMA driver, either by + * device name, or by DT/OF node, but not both. Some forms of link + * do not need a platform. In such case, platforms are not mandatory. + */ + struct snd_soc_dai_link_component *platforms; + unsigned int num_platforms; + + int id; /* optional ID for machine driver link identification */ + + const struct snd_soc_pcm_stream *params; + unsigned int num_params; + + unsigned int dai_fmt; /* format to set on init */ + + enum snd_soc_dpcm_trigger trigger[2]; /* trigger type for DPCM */ + + /* codec/machine specific init - e.g. add machine controls */ + int (*init)(struct snd_soc_pcm_runtime *rtd); + + /* codec/machine specific exit - dual of init() */ + void (*exit)(struct snd_soc_pcm_runtime *rtd); + + /* optional hw_params re-writing for BE and FE sync */ + int (*be_hw_params_fixup)(struct snd_soc_pcm_runtime *rtd, + struct snd_pcm_hw_params *params); + + /* machine stream operations */ + const struct snd_soc_ops *ops; + const struct snd_soc_compr_ops *compr_ops; + + /* Mark this pcm with non atomic ops */ + unsigned int nonatomic:1; + + /* For unidirectional dai links */ + unsigned int playback_only:1; + unsigned int capture_only:1; + + /* Keep DAI active over suspend */ + unsigned int ignore_suspend:1; + + /* Symmetry requirements */ + unsigned int symmetric_rate:1; + unsigned int symmetric_channels:1; + unsigned int symmetric_sample_bits:1; + + /* Do not create a PCM for this DAI link (Backend link) */ + unsigned int no_pcm:1; + + /* This DAI link can route to other DAI links at runtime (Frontend)*/ + unsigned int dynamic:1; + + /* DPCM capture and Playback support */ + unsigned int dpcm_capture:1; + unsigned int dpcm_playback:1; + + /* DPCM used FE & BE merged format */ + unsigned int dpcm_merged_format:1; + /* DPCM used FE & BE merged channel */ + unsigned int dpcm_merged_chan:1; + /* DPCM used FE & BE merged rate */ + unsigned int dpcm_merged_rate:1; + + /* pmdown_time is ignored at stop */ + unsigned int ignore_pmdown_time:1; + + /* Do not create a PCM for this DAI link (Backend link) */ + unsigned int ignore:1; + + /* This flag will reorder stop sequence. By enabling this flag + * DMA controller stop sequence will be invoked first followed by + * CPU DAI driver stop sequence + */ + unsigned int stop_dma_first:1; + +#ifdef CONFIG_SND_SOC_TOPOLOGY + struct snd_soc_dobj dobj; /* For topology */ +#endif +}; + +static inline struct snd_soc_dai_link_component* +asoc_link_to_cpu(struct snd_soc_dai_link *link, int n) { + return &(link)->cpus[n]; +} + +static inline struct snd_soc_dai_link_component* +asoc_link_to_codec(struct snd_soc_dai_link *link, int n) { + return &(link)->codecs[n]; +} + +static inline struct snd_soc_dai_link_component* +asoc_link_to_platform(struct snd_soc_dai_link *link, int n) { + return &(link)->platforms[n]; +} + +#define for_each_link_codecs(link, i, codec) \ + for ((i) = 0; \ + ((i) < link->num_codecs) && \ + ((codec) = asoc_link_to_codec(link, i)); \ + (i)++) + +#define for_each_link_platforms(link, i, platform) \ + for ((i) = 0; \ + ((i) < link->num_platforms) && \ + ((platform) = asoc_link_to_platform(link, i)); \ + (i)++) + +#define for_each_link_cpus(link, i, cpu) \ + for ((i) = 0; \ + ((i) < link->num_cpus) && \ + ((cpu) = asoc_link_to_cpu(link, i)); \ + (i)++) + +/* + * Sample 1 : Single CPU/Codec/Platform + * + * SND_SOC_DAILINK_DEFS(test, + * DAILINK_COMP_ARRAY(COMP_CPU("cpu_dai")), + * DAILINK_COMP_ARRAY(COMP_CODEC("codec", "codec_dai")), + * DAILINK_COMP_ARRAY(COMP_PLATFORM("platform"))); + * + * struct snd_soc_dai_link link = { + * ... + * SND_SOC_DAILINK_REG(test), + * }; + * + * Sample 2 : Multi CPU/Codec, no Platform + * + * SND_SOC_DAILINK_DEFS(test, + * DAILINK_COMP_ARRAY(COMP_CPU("cpu_dai1"), + * COMP_CPU("cpu_dai2")), + * DAILINK_COMP_ARRAY(COMP_CODEC("codec1", "codec_dai1"), + * COMP_CODEC("codec2", "codec_dai2"))); + * + * struct snd_soc_dai_link link = { + * ... + * SND_SOC_DAILINK_REG(test), + * }; + * + * Sample 3 : Define each CPU/Codec/Platform manually + * + * SND_SOC_DAILINK_DEF(test_cpu, + * DAILINK_COMP_ARRAY(COMP_CPU("cpu_dai1"), + * COMP_CPU("cpu_dai2"))); + * SND_SOC_DAILINK_DEF(test_codec, + * DAILINK_COMP_ARRAY(COMP_CODEC("codec1", "codec_dai1"), + * COMP_CODEC("codec2", "codec_dai2"))); + * SND_SOC_DAILINK_DEF(test_platform, + * DAILINK_COMP_ARRAY(COMP_PLATFORM("platform"))); + * + * struct snd_soc_dai_link link = { + * ... + * SND_SOC_DAILINK_REG(test_cpu, + * test_codec, + * test_platform), + * }; + * + * Sample 4 : Sample3 without platform + * + * struct snd_soc_dai_link link = { + * ... + * SND_SOC_DAILINK_REG(test_cpu, + * test_codec); + * }; + */ + +#define SND_SOC_DAILINK_REG1(name) SND_SOC_DAILINK_REG3(name##_cpus, name##_codecs, name##_platforms) +#define SND_SOC_DAILINK_REG2(cpu, codec) SND_SOC_DAILINK_REG3(cpu, codec, null_dailink_component) +#define SND_SOC_DAILINK_REG3(cpu, codec, platform) \ + .cpus = cpu, \ + .num_cpus = ARRAY_SIZE(cpu), \ + .codecs = codec, \ + .num_codecs = ARRAY_SIZE(codec), \ + .platforms = platform, \ + .num_platforms = ARRAY_SIZE(platform) + +#define SND_SOC_DAILINK_REGx(_1, _2, _3, func, ...) func +#define SND_SOC_DAILINK_REG(...) \ + SND_SOC_DAILINK_REGx(__VA_ARGS__, \ + SND_SOC_DAILINK_REG3, \ + SND_SOC_DAILINK_REG2, \ + SND_SOC_DAILINK_REG1)(__VA_ARGS__) + +#define SND_SOC_DAILINK_DEF(name, def...) \ + static struct snd_soc_dai_link_component name[] = { def } + +#define SND_SOC_DAILINK_DEFS(name, cpu, codec, platform...) \ + SND_SOC_DAILINK_DEF(name##_cpus, cpu); \ + SND_SOC_DAILINK_DEF(name##_codecs, codec); \ + SND_SOC_DAILINK_DEF(name##_platforms, platform) + +#define DAILINK_COMP_ARRAY(param...) param +#define COMP_EMPTY() { } +#define COMP_CPU(_dai) { .dai_name = _dai, } +#define COMP_CODEC(_name, _dai) { .name = _name, .dai_name = _dai, } +#define COMP_PLATFORM(_name) { .name = _name } +#define COMP_AUX(_name) { .name = _name } +#define COMP_CODEC_CONF(_name) { .name = _name } +#define COMP_DUMMY() { .name = "snd-soc-dummy", .dai_name = "snd-soc-dummy-dai", } + +extern struct snd_soc_dai_link_component null_dailink_component[0]; + + +struct snd_soc_codec_conf { + /* + * specify device either by device name, or by + * DT/OF node, but not both. + */ + struct snd_soc_dai_link_component dlc; + + /* + * optional map of kcontrol, widget and path name prefixes that are + * associated per device + */ + const char *name_prefix; +}; + +struct snd_soc_aux_dev { + /* + * specify multi-codec either by device name, or by + * DT/OF node, but not both. + */ + struct snd_soc_dai_link_component dlc; + + /* codec/machine specific init - e.g. add machine controls */ + int (*init)(struct snd_soc_component *component); +}; + +/* SoC card */ +struct snd_soc_card { + const char *name; + const char *long_name; + const char *driver_name; + const char *components; +#ifdef CONFIG_DMI + char dmi_longname[80]; +#endif /* CONFIG_DMI */ + +#ifdef CONFIG_PCI + /* + * PCI does not define 0 as invalid, so pci_subsystem_set indicates + * whether a value has been written to these fields. + */ + unsigned short pci_subsystem_vendor; + unsigned short pci_subsystem_device; + bool pci_subsystem_set; +#endif /* CONFIG_PCI */ + + char topology_shortname[32]; + + struct device *dev; + struct snd_card *snd_card; + struct module *owner; + + struct mutex mutex; + struct mutex dapm_mutex; + + /* Mutex for PCM operations */ + struct mutex pcm_mutex; + enum snd_soc_pcm_subclass pcm_subclass; + + int (*probe)(struct snd_soc_card *card); + int (*late_probe)(struct snd_soc_card *card); + void (*fixup_controls)(struct snd_soc_card *card); + int (*remove)(struct snd_soc_card *card); + + /* the pre and post PM functions are used to do any PM work before and + * after the codec and DAI's do any PM work. */ + int (*suspend_pre)(struct snd_soc_card *card); + int (*suspend_post)(struct snd_soc_card *card); + int (*resume_pre)(struct snd_soc_card *card); + int (*resume_post)(struct snd_soc_card *card); + + /* callbacks */ + int (*set_bias_level)(struct snd_soc_card *, + struct snd_soc_dapm_context *dapm, + enum snd_soc_bias_level level); + int (*set_bias_level_post)(struct snd_soc_card *, + struct snd_soc_dapm_context *dapm, + enum snd_soc_bias_level level); + + int (*add_dai_link)(struct snd_soc_card *, + struct snd_soc_dai_link *link); + void (*remove_dai_link)(struct snd_soc_card *, + struct snd_soc_dai_link *link); + + long pmdown_time; + + /* CPU <--> Codec DAI links */ + struct snd_soc_dai_link *dai_link; /* predefined links only */ + int num_links; /* predefined links only */ + + struct list_head rtd_list; + int num_rtd; + + /* optional codec specific configuration */ + struct snd_soc_codec_conf *codec_conf; + int num_configs; + + /* + * optional auxiliary devices such as amplifiers or codecs with DAI + * link unused + */ + struct snd_soc_aux_dev *aux_dev; + int num_aux_devs; + struct list_head aux_comp_list; + + const struct snd_kcontrol_new *controls; + int num_controls; + + /* + * Card-specific routes and widgets. + * Note: of_dapm_xxx for Device Tree; Otherwise for driver build-in. + */ + const struct snd_soc_dapm_widget *dapm_widgets; + int num_dapm_widgets; + const struct snd_soc_dapm_route *dapm_routes; + int num_dapm_routes; + const struct snd_soc_dapm_widget *of_dapm_widgets; + int num_of_dapm_widgets; + const struct snd_soc_dapm_route *of_dapm_routes; + int num_of_dapm_routes; + + /* lists of probed devices belonging to this card */ + struct list_head component_dev_list; + struct list_head list; + + struct list_head widgets; + struct list_head paths; + struct list_head dapm_list; + struct list_head dapm_dirty; + + /* attached dynamic objects */ + struct list_head dobj_list; + + /* Generic DAPM context for the card */ + struct snd_soc_dapm_context dapm; + struct snd_soc_dapm_stats dapm_stats; + struct snd_soc_dapm_update *update; + +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_card_root; +#endif +#ifdef CONFIG_PM_SLEEP + struct work_struct deferred_resume_work; +#endif + u32 pop_time; + + /* bit field */ + unsigned int instantiated:1; + unsigned int topology_shortname_created:1; + unsigned int fully_routed:1; + unsigned int disable_route_checks:1; + unsigned int probed:1; + unsigned int component_chaining:1; + + void *drvdata; +}; +#define for_each_card_prelinks(card, i, link) \ + for ((i) = 0; \ + ((i) < (card)->num_links) && ((link) = &(card)->dai_link[i]); \ + (i)++) +#define for_each_card_pre_auxs(card, i, aux) \ + for ((i) = 0; \ + ((i) < (card)->num_aux_devs) && ((aux) = &(card)->aux_dev[i]); \ + (i)++) + +#define for_each_card_rtds(card, rtd) \ + list_for_each_entry(rtd, &(card)->rtd_list, list) +#define for_each_card_rtds_safe(card, rtd, _rtd) \ + list_for_each_entry_safe(rtd, _rtd, &(card)->rtd_list, list) + +#define for_each_card_auxs(card, component) \ + list_for_each_entry(component, &card->aux_comp_list, card_aux_list) +#define for_each_card_auxs_safe(card, component, _comp) \ + list_for_each_entry_safe(component, _comp, \ + &card->aux_comp_list, card_aux_list) + +#define for_each_card_components(card, component) \ + list_for_each_entry(component, &(card)->component_dev_list, card_list) + +#define for_each_card_dapms(card, dapm) \ + list_for_each_entry(dapm, &card->dapm_list, list) + +#define for_each_card_widgets(card, w)\ + list_for_each_entry(w, &card->widgets, list) +#define for_each_card_widgets_safe(card, w, _w) \ + list_for_each_entry_safe(w, _w, &card->widgets, list) + +/* SoC machine DAI configuration, glues a codec and cpu DAI together */ +struct snd_soc_pcm_runtime { + struct device *dev; + struct snd_soc_card *card; + struct snd_soc_dai_link *dai_link; + struct snd_pcm_ops ops; + + unsigned int params_select; /* currently selected param for dai link */ + + /* Dynamic PCM BE runtime data */ + struct snd_soc_dpcm_runtime dpcm[SNDRV_PCM_STREAM_LAST + 1]; + struct snd_soc_dapm_widget *c2c_widget[SNDRV_PCM_STREAM_LAST + 1]; + + long pmdown_time; + + /* runtime devices */ + struct snd_pcm *pcm; + struct snd_compr *compr; + + /* + * dais = cpu_dai + codec_dai + * see + * soc_new_pcm_runtime() + * asoc_rtd_to_cpu() + * asoc_rtd_to_codec() + */ + struct snd_soc_dai **dais; + + struct delayed_work delayed_work; + void (*close_delayed_work_func)(struct snd_soc_pcm_runtime *rtd); +#ifdef CONFIG_DEBUG_FS + struct dentry *debugfs_dpcm_root; +#endif + + unsigned int num; /* 0-based and monotonic increasing */ + struct list_head list; /* rtd list of the soc card */ + + /* function mark */ + struct snd_pcm_substream *mark_startup; + struct snd_pcm_substream *mark_hw_params; + struct snd_pcm_substream *mark_trigger; + struct snd_compr_stream *mark_compr_startup; + + /* bit field */ + unsigned int pop_wait:1; + unsigned int fe_compr:1; /* for Dynamic PCM */ + + int num_components; + struct snd_soc_component *components[]; /* CPU/Codec/Platform */ +}; +/* see soc_new_pcm_runtime() */ +#define asoc_rtd_to_cpu(rtd, n) (rtd)->dais[n] +#define asoc_rtd_to_codec(rtd, n) (rtd)->dais[n + (rtd)->dai_link->num_cpus] +#define asoc_substream_to_rtd(substream) \ + (struct snd_soc_pcm_runtime *)snd_pcm_substream_chip(substream) + +#define for_each_rtd_components(rtd, i, component) \ + for ((i) = 0, component = NULL; \ + ((i) < rtd->num_components) && ((component) = rtd->components[i]);\ + (i)++) +#define for_each_rtd_cpu_dais(rtd, i, dai) \ + for ((i) = 0; \ + ((i) < rtd->dai_link->num_cpus) && ((dai) = asoc_rtd_to_cpu(rtd, i)); \ + (i)++) +#define for_each_rtd_codec_dais(rtd, i, dai) \ + for ((i) = 0; \ + ((i) < rtd->dai_link->num_codecs) && ((dai) = asoc_rtd_to_codec(rtd, i)); \ + (i)++) +#define for_each_rtd_dais(rtd, i, dai) \ + for ((i) = 0; \ + ((i) < (rtd)->dai_link->num_cpus + (rtd)->dai_link->num_codecs) && \ + ((dai) = (rtd)->dais[i]); \ + (i)++) + +void snd_soc_close_delayed_work(struct snd_soc_pcm_runtime *rtd); + +/* mixer control */ +struct soc_mixer_control { + int min, max, platform_max; + int reg, rreg; + unsigned int shift, rshift; + unsigned int sign_bit; + unsigned int invert:1; + unsigned int autodisable:1; +#ifdef CONFIG_SND_SOC_TOPOLOGY + struct snd_soc_dobj dobj; +#endif +}; + +struct soc_bytes { + int base; + int num_regs; + u32 mask; +}; + +struct soc_bytes_ext { + int max; +#ifdef CONFIG_SND_SOC_TOPOLOGY + struct snd_soc_dobj dobj; +#endif + /* used for TLV byte control */ + int (*get)(struct snd_kcontrol *kcontrol, unsigned int __user *bytes, + unsigned int size); + int (*put)(struct snd_kcontrol *kcontrol, const unsigned int __user *bytes, + unsigned int size); +}; + +/* multi register control */ +struct soc_mreg_control { + long min, max; + unsigned int regbase, regcount, nbits, invert; +}; + +/* enumerated kcontrol */ +struct soc_enum { + int reg; + unsigned char shift_l; + unsigned char shift_r; + unsigned int items; + unsigned int mask; + const char * const *texts; + const unsigned int *values; + unsigned int autodisable:1; +#ifdef CONFIG_SND_SOC_TOPOLOGY + struct snd_soc_dobj dobj; +#endif +}; + +static inline bool snd_soc_volsw_is_stereo(struct soc_mixer_control *mc) +{ + if (mc->reg == mc->rreg && mc->shift == mc->rshift) + return false; + /* + * mc->reg == mc->rreg && mc->shift != mc->rshift, or + * mc->reg != mc->rreg means that the control is + * stereo (bits in one register or in two registers) + */ + return true; +} + +static inline unsigned int snd_soc_enum_val_to_item(struct soc_enum *e, + unsigned int val) +{ + unsigned int i; + + if (!e->values) + return val; + + for (i = 0; i < e->items; i++) + if (val == e->values[i]) + return i; + + return 0; +} + +static inline unsigned int snd_soc_enum_item_to_val(struct soc_enum *e, + unsigned int item) +{ + if (!e->values) + return item; + + return e->values[item]; +} + +/** + * snd_soc_kcontrol_component() - Returns the component that registered the + * control + * @kcontrol: The control for which to get the component + * + * Note: This function will work correctly if the control has been registered + * for a component. With snd_soc_add_codec_controls() or via table based + * setup for either a CODEC or component driver. Otherwise the behavior is + * undefined. + */ +static inline struct snd_soc_component *snd_soc_kcontrol_component( + struct snd_kcontrol *kcontrol) +{ + return snd_kcontrol_chip(kcontrol); +} + +int snd_soc_util_init(void); +void snd_soc_util_exit(void); + +int snd_soc_of_parse_card_name(struct snd_soc_card *card, + const char *propname); +int snd_soc_of_parse_audio_simple_widgets(struct snd_soc_card *card, + const char *propname); +int snd_soc_of_parse_pin_switches(struct snd_soc_card *card, const char *prop); +int snd_soc_of_get_slot_mask(struct device_node *np, + const char *prop_name, + unsigned int *mask); +int snd_soc_of_parse_tdm_slot(struct device_node *np, + unsigned int *tx_mask, + unsigned int *rx_mask, + unsigned int *slots, + unsigned int *slot_width); +void snd_soc_of_parse_node_prefix(struct device_node *np, + struct snd_soc_codec_conf *codec_conf, + struct device_node *of_node, + const char *propname); +static inline +void snd_soc_of_parse_audio_prefix(struct snd_soc_card *card, + struct snd_soc_codec_conf *codec_conf, + struct device_node *of_node, + const char *propname) +{ + snd_soc_of_parse_node_prefix(card->dev->of_node, + codec_conf, of_node, propname); +} + +int snd_soc_of_parse_audio_routing(struct snd_soc_card *card, + const char *propname); +int snd_soc_of_parse_aux_devs(struct snd_soc_card *card, const char *propname); + +unsigned int snd_soc_daifmt_clock_provider_flipped(unsigned int dai_fmt); +unsigned int snd_soc_daifmt_clock_provider_from_bitmap(unsigned int bit_frame); + +unsigned int snd_soc_daifmt_parse_format(struct device_node *np, const char *prefix); +unsigned int snd_soc_daifmt_parse_clock_provider_raw(struct device_node *np, + const char *prefix, + struct device_node **bitclkmaster, + struct device_node **framemaster); +#define snd_soc_daifmt_parse_clock_provider_as_bitmap(np, prefix) \ + snd_soc_daifmt_parse_clock_provider_raw(np, prefix, NULL, NULL) +#define snd_soc_daifmt_parse_clock_provider_as_phandle \ + snd_soc_daifmt_parse_clock_provider_raw +#define snd_soc_daifmt_parse_clock_provider_as_flag(np, prefix) \ + snd_soc_daifmt_clock_provider_from_bitmap( \ + snd_soc_daifmt_parse_clock_provider_as_bitmap(np, prefix)) + +int snd_soc_get_dai_id(struct device_node *ep); +int snd_soc_get_dai_name(const struct of_phandle_args *args, + const char **dai_name); +int snd_soc_of_get_dai_name(struct device_node *of_node, + const char **dai_name); +int snd_soc_of_get_dai_link_codecs(struct device *dev, + struct device_node *of_node, + struct snd_soc_dai_link *dai_link); +void snd_soc_of_put_dai_link_codecs(struct snd_soc_dai_link *dai_link); +int snd_soc_of_get_dai_link_cpus(struct device *dev, + struct device_node *of_node, + struct snd_soc_dai_link *dai_link); +void snd_soc_of_put_dai_link_cpus(struct snd_soc_dai_link *dai_link); + +int snd_soc_add_pcm_runtime(struct snd_soc_card *card, + struct snd_soc_dai_link *dai_link); +void snd_soc_remove_pcm_runtime(struct snd_soc_card *card, + struct snd_soc_pcm_runtime *rtd); + +struct snd_soc_dai *snd_soc_register_dai(struct snd_soc_component *component, + struct snd_soc_dai_driver *dai_drv, + bool legacy_dai_naming); +struct snd_soc_dai *devm_snd_soc_register_dai(struct device *dev, + struct snd_soc_component *component, + struct snd_soc_dai_driver *dai_drv, + bool legacy_dai_naming); +void snd_soc_unregister_dai(struct snd_soc_dai *dai); + +struct snd_soc_dai *snd_soc_find_dai( + const struct snd_soc_dai_link_component *dlc); +struct snd_soc_dai *snd_soc_find_dai_with_mutex( + const struct snd_soc_dai_link_component *dlc); + +#include <sound/soc-dai.h> + +static inline +int snd_soc_fixup_dai_links_platform_name(struct snd_soc_card *card, + const char *platform_name) +{ + struct snd_soc_dai_link *dai_link; + const char *name; + int i; + + if (!platform_name) /* nothing to do */ + return 0; + + /* set platform name for each dailink */ + for_each_card_prelinks(card, i, dai_link) { + /* only single platform is supported for now */ + if (dai_link->num_platforms != 1) + return -EINVAL; + + if (!dai_link->platforms) + return -EINVAL; + + name = devm_kstrdup(card->dev, platform_name, GFP_KERNEL); + if (!name) + return -ENOMEM; + + /* only single platform is supported for now */ + dai_link->platforms->name = name; + } + + return 0; +} + +#ifdef CONFIG_DEBUG_FS +extern struct dentry *snd_soc_debugfs_root; +#endif + +extern const struct dev_pm_ops snd_soc_pm_ops; + +/* Helper functions */ +static inline void snd_soc_dapm_mutex_lock(struct snd_soc_dapm_context *dapm) +{ + mutex_lock_nested(&dapm->card->dapm_mutex, SND_SOC_DAPM_CLASS_RUNTIME); +} + +static inline void snd_soc_dapm_mutex_unlock(struct snd_soc_dapm_context *dapm) +{ + mutex_unlock(&dapm->card->dapm_mutex); +} + +#include <sound/soc-component.h> +#include <sound/soc-card.h> +#include <sound/soc-jack.h> + +#endif diff --git a/include/sound/sof.h b/include/sound/sof.h new file mode 100644 index 000000000..1caeb7bf1 --- /dev/null +++ b/include/sound/sof.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation. All rights reserved. + * + * Author: Liam Girdwood <liam.r.girdwood@linux.intel.com> + */ + +#ifndef __INCLUDE_SOUND_SOF_H +#define __INCLUDE_SOUND_SOF_H + +#include <linux/pci.h> +#include <sound/soc.h> +#include <sound/soc-acpi.h> + +struct snd_sof_dsp_ops; +struct snd_sof_dev; + +/** + * enum sof_fw_state - DSP firmware state definitions + * @SOF_FW_BOOT_NOT_STARTED: firmware boot is not yet started + * @SOF_FW_BOOT_PREPARE: preparing for boot (firmware loading for exaqmple) + * @SOF_FW_BOOT_IN_PROGRESS: firmware boot is in progress + * @SOF_FW_BOOT_FAILED: firmware boot failed + * @SOF_FW_BOOT_READY_FAILED: firmware booted but fw_ready op failed + * @SOF_FW_BOOT_READY_OK: firmware booted and fw_ready op passed + * @SOF_FW_BOOT_COMPLETE: firmware is booted up and functional + * @SOF_FW_CRASHED: firmware crashed after successful boot + */ +enum sof_fw_state { + SOF_FW_BOOT_NOT_STARTED = 0, + SOF_FW_BOOT_PREPARE, + SOF_FW_BOOT_IN_PROGRESS, + SOF_FW_BOOT_FAILED, + SOF_FW_BOOT_READY_FAILED, + SOF_FW_BOOT_READY_OK, + SOF_FW_BOOT_COMPLETE, + SOF_FW_CRASHED, +}; + +/* DSP power states */ +enum sof_dsp_power_states { + SOF_DSP_PM_D0, + SOF_DSP_PM_D1, + SOF_DSP_PM_D2, + SOF_DSP_PM_D3, +}; + +/* Definitions for multiple IPCs */ +enum sof_ipc_type { + SOF_IPC, + SOF_INTEL_IPC4, + SOF_IPC_TYPE_COUNT +}; + +/* + * SOF Platform data. + */ +struct snd_sof_pdata { + const struct firmware *fw; + const char *name; + const char *platform; + + /* + * PCI SSID. As PCI does not define 0 as invalid, the subsystem_id_set + * flag indicates that a value has been written to these members. + */ + unsigned short subsystem_vendor; + unsigned short subsystem_device; + bool subsystem_id_set; + + struct device *dev; + + /* indicate how many first bytes shouldn't be loaded into DSP memory. */ + size_t fw_offset; + + /* + * notification callback used if the hardware initialization + * can take time or is handled in a workqueue. This callback + * can be used by the caller to e.g. enable runtime_pm + * or limit functionality until all low-level inits are + * complete. + */ + void (*sof_probe_complete)(struct device *dev); + + /* descriptor */ + const struct sof_dev_desc *desc; + + /* firmware and topology filenames */ + const char *fw_filename_prefix; + const char *fw_filename; + const char *tplg_filename_prefix; + const char *tplg_filename; + + /* machine */ + struct platform_device *pdev_mach; + const struct snd_soc_acpi_mach *machine; + const struct snd_sof_of_mach *of_machine; + + void *hw_pdata; + + enum sof_ipc_type ipc_type; +}; + +/* + * Descriptor used for setting up SOF platform data. This is used when + * ACPI/PCI data is missing or mapped differently. + */ +struct sof_dev_desc { + /* list of machines using this configuration */ + struct snd_soc_acpi_mach *machines; + struct snd_sof_of_mach *of_machines; + + /* alternate list of machines using this configuration */ + struct snd_soc_acpi_mach *alt_machines; + + bool use_acpi_target_states; + + /* Platform resource indexes in BAR / ACPI resources. */ + /* Must set to -1 if not used - add new items to end */ + int resindex_lpe_base; + int resindex_pcicfg_base; + int resindex_imr_base; + int irqindex_host_ipc; + + /* IPC timeouts in ms */ + int ipc_timeout; + int boot_timeout; + + /* chip information for dsp */ + const void *chip_info; + + /* defaults for no codec mode */ + const char *nocodec_tplg_filename; + + /* information on supported IPCs */ + unsigned int ipc_supported_mask; + enum sof_ipc_type ipc_default; + + /* defaults paths for firmware and topology files */ + const char *default_fw_path[SOF_IPC_TYPE_COUNT]; + const char *default_tplg_path[SOF_IPC_TYPE_COUNT]; + + /* default firmware name */ + const char *default_fw_filename[SOF_IPC_TYPE_COUNT]; + + struct snd_sof_dsp_ops *ops; + int (*ops_init)(struct snd_sof_dev *sdev); + void (*ops_free)(struct snd_sof_dev *sdev); +}; + +int sof_dai_get_mclk(struct snd_soc_pcm_runtime *rtd); +int sof_dai_get_bclk(struct snd_soc_pcm_runtime *rtd); + +#endif diff --git a/include/sound/sof/channel_map.h b/include/sound/sof/channel_map.h new file mode 100644 index 000000000..d363f0ca6 --- /dev/null +++ b/include/sound/sof/channel_map.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2019 Intel Corporation. All rights reserved. + */ + +#ifndef __IPC_CHANNEL_MAP_H__ +#define __IPC_CHANNEL_MAP_H__ + +#include <uapi/sound/sof/header.h> +#include <sound/sof/header.h> + +/** + * \brief Channel map, specifies transformation of one-to-many or many-to-one. + * + * In case of one-to-many specifies how the output channels are computed out of + * a single source channel, + * in case of many-to-one specifies how a single target channel is computed + * from a multichannel input stream. + * + * Channel index specifies position of the channel in the stream on the 'one' + * side. + * + * Ext ID is the identifier of external part of the transformation. Depending + * on the context, it may be pipeline ID, dai ID, ... + * + * Channel mask describes which channels are taken into account on the "many" + * side. Bit[i] set to 1 means that i-th channel is used for computation + * (either as source or as a target). + * + * Channel mask is followed by array of coefficients in Q2.30 format, + * one per each channel set in the mask (left to right, LS bit set in the + * mask corresponds to ch_coeffs[0]). + */ +struct sof_ipc_channel_map { + uint32_t ch_index; + uint32_t ext_id; + uint32_t ch_mask; + uint32_t reserved; + int32_t ch_coeffs[]; +} __packed; + +/** + * \brief Complete map for each channel of a multichannel stream. + * + * num_ch_map Specifies number of items in the ch_map. + * More than one transformation per a single channel is allowed (in case + * multiple external entities are transformed). + * A channel may be skipped in the transformation list, then it is filled + * with 0's by the transformation function. + */ +struct sof_ipc_stream_map { + struct sof_ipc_cmd_hdr hdr; + uint32_t num_ch_map; + uint32_t reserved[3]; + struct sof_ipc_channel_map ch_map[]; +} __packed; + +#endif /* __IPC_CHANNEL_MAP_H__ */ diff --git a/include/sound/sof/control.h b/include/sound/sof/control.h new file mode 100644 index 000000000..983d374fe --- /dev/null +++ b/include/sound/sof/control.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation. All rights reserved. + */ + +#ifndef __INCLUDE_SOUND_SOF_CONTROL_H__ +#define __INCLUDE_SOUND_SOF_CONTROL_H__ + +#include <uapi/sound/sof/header.h> +#include <sound/sof/header.h> + +/* + * Component Mixers and Controls + */ + +/* channel positions - uses same values as ALSA */ +enum sof_ipc_chmap { + SOF_CHMAP_UNKNOWN = 0, + SOF_CHMAP_NA, /**< N/A, silent */ + SOF_CHMAP_MONO, /**< mono stream */ + SOF_CHMAP_FL, /**< front left */ + SOF_CHMAP_FR, /**< front right */ + SOF_CHMAP_RL, /**< rear left */ + SOF_CHMAP_RR, /**< rear right */ + SOF_CHMAP_FC, /**< front centre */ + SOF_CHMAP_LFE, /**< LFE */ + SOF_CHMAP_SL, /**< side left */ + SOF_CHMAP_SR, /**< side right */ + SOF_CHMAP_RC, /**< rear centre */ + SOF_CHMAP_FLC, /**< front left centre */ + SOF_CHMAP_FRC, /**< front right centre */ + SOF_CHMAP_RLC, /**< rear left centre */ + SOF_CHMAP_RRC, /**< rear right centre */ + SOF_CHMAP_FLW, /**< front left wide */ + SOF_CHMAP_FRW, /**< front right wide */ + SOF_CHMAP_FLH, /**< front left high */ + SOF_CHMAP_FCH, /**< front centre high */ + SOF_CHMAP_FRH, /**< front right high */ + SOF_CHMAP_TC, /**< top centre */ + SOF_CHMAP_TFL, /**< top front left */ + SOF_CHMAP_TFR, /**< top front right */ + SOF_CHMAP_TFC, /**< top front centre */ + SOF_CHMAP_TRL, /**< top rear left */ + SOF_CHMAP_TRR, /**< top rear right */ + SOF_CHMAP_TRC, /**< top rear centre */ + SOF_CHMAP_TFLC, /**< top front left centre */ + SOF_CHMAP_TFRC, /**< top front right centre */ + SOF_CHMAP_TSL, /**< top side left */ + SOF_CHMAP_TSR, /**< top side right */ + SOF_CHMAP_LLFE, /**< left LFE */ + SOF_CHMAP_RLFE, /**< right LFE */ + SOF_CHMAP_BC, /**< bottom centre */ + SOF_CHMAP_BLC, /**< bottom left centre */ + SOF_CHMAP_BRC, /**< bottom right centre */ + SOF_CHMAP_LAST = SOF_CHMAP_BRC, +}; + +/* control data type and direction */ +enum sof_ipc_ctrl_type { + /* per channel data - uses struct sof_ipc_ctrl_value_chan */ + SOF_CTRL_TYPE_VALUE_CHAN_GET = 0, + SOF_CTRL_TYPE_VALUE_CHAN_SET, + /* component data - uses struct sof_ipc_ctrl_value_comp */ + SOF_CTRL_TYPE_VALUE_COMP_GET, + SOF_CTRL_TYPE_VALUE_COMP_SET, + /* bespoke data - uses struct sof_abi_hdr */ + SOF_CTRL_TYPE_DATA_GET, + SOF_CTRL_TYPE_DATA_SET, +}; + +/* control command type */ +enum sof_ipc_ctrl_cmd { + SOF_CTRL_CMD_VOLUME = 0, /**< maps to ALSA volume style controls */ + SOF_CTRL_CMD_ENUM, /**< maps to ALSA enum style controls */ + SOF_CTRL_CMD_SWITCH, /**< maps to ALSA switch style controls */ + SOF_CTRL_CMD_BINARY, /**< maps to ALSA binary style controls */ +}; + +/* generic channel mapped value data */ +struct sof_ipc_ctrl_value_chan { + uint32_t channel; /**< channel map - enum sof_ipc_chmap */ + uint32_t value; +} __packed; + +/* generic component mapped value data */ +struct sof_ipc_ctrl_value_comp { + uint32_t index; /**< component source/sink/control index in control */ + union { + uint32_t uvalue; + int32_t svalue; + }; +} __packed; + +/* generic control data */ +struct sof_ipc_ctrl_data { + struct sof_ipc_reply rhdr; + uint32_t comp_id; + + /* control access and data type */ + uint32_t type; /**< enum sof_ipc_ctrl_type */ + uint32_t cmd; /**< enum sof_ipc_ctrl_cmd */ + uint32_t index; /**< control index for comps > 1 control */ + + /* control data - can either be appended or DMAed from host */ + struct sof_ipc_host_buffer buffer; + uint32_t num_elems; /**< in array elems or bytes for data type */ + uint32_t elems_remaining; /**< elems remaining if sent in parts */ + + uint32_t msg_index; /**< for large messages sent in parts */ + + /* reserved for future use */ + uint32_t reserved[6]; + + /* control data - add new types if needed */ + union { + /* channel values can be used by volume type controls */ + DECLARE_FLEX_ARRAY(struct sof_ipc_ctrl_value_chan, chanv); + /* component values used by routing controls like mux, mixer */ + DECLARE_FLEX_ARRAY(struct sof_ipc_ctrl_value_comp, compv); + /* data can be used by binary controls */ + DECLARE_FLEX_ARRAY(struct sof_abi_hdr, data); + }; +} __packed; + +/** Event type */ +enum sof_ipc_ctrl_event_type { + SOF_CTRL_EVENT_GENERIC = 0, /**< generic event */ + SOF_CTRL_EVENT_GENERIC_METADATA, /**< generic event with metadata */ + SOF_CTRL_EVENT_KD, /**< keyword detection event */ + SOF_CTRL_EVENT_VAD, /**< voice activity detection event */ +}; + +/** + * Generic notification data. + */ +struct sof_ipc_comp_event { + struct sof_ipc_reply rhdr; + uint16_t src_comp_type; /**< COMP_TYPE_ */ + uint32_t src_comp_id; /**< source component id */ + uint32_t event_type; /**< event type - SOF_CTRL_EVENT_* */ + uint32_t num_elems; /**< in array elems or bytes for data type */ + + /* reserved for future use */ + uint32_t reserved[8]; + + /* control data - add new types if needed */ + union { + /* data can be used by binary controls */ + struct sof_abi_hdr data[0]; + /* event specific values */ + uint32_t event_value; + }; +} __packed; + +#endif diff --git a/include/sound/sof/dai-amd.h b/include/sound/sof/dai-amd.h new file mode 100644 index 000000000..92f45c180 --- /dev/null +++ b/include/sound/sof/dai-amd.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2021 Advanced Micro Devices, Inc.. All rights reserved. + */ + +#ifndef __INCLUDE_SOUND_SOF_DAI_AMD_H__ +#define __INCLUDE_SOUND_SOF_DAI_AMD_H__ + +#include <sound/sof/header.h> + +/* ACP Configuration Request - SOF_IPC_DAI_AMD_CONFIG */ +struct sof_ipc_dai_acp_params { + struct sof_ipc_hdr hdr; + + uint32_t fsync_rate; /* FSYNC frequency in Hz */ + uint32_t tdm_slots; +} __packed; + +/* ACPDMIC Configuration Request - SOF_IPC_DAI_AMD_CONFIG */ +struct sof_ipc_dai_acpdmic_params { + uint32_t pdm_rate; + uint32_t pdm_ch; +} __packed; + +#endif diff --git a/include/sound/sof/dai-imx.h b/include/sound/sof/dai-imx.h new file mode 100644 index 000000000..ca8325353 --- /dev/null +++ b/include/sound/sof/dai-imx.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Copyright 2019 NXP + * + * Author: Daniel Baluta <daniel.baluta@nxp.com> + */ + +#ifndef __INCLUDE_SOUND_SOF_DAI_IMX_H__ +#define __INCLUDE_SOUND_SOF_DAI_IMX_H__ + +#include <sound/sof/header.h> + +/* ESAI Configuration Request - SOF_IPC_DAI_ESAI_CONFIG */ +struct sof_ipc_dai_esai_params { + struct sof_ipc_hdr hdr; + + /* MCLK */ + uint16_t reserved1; + uint16_t mclk_id; + uint32_t mclk_direction; + + uint32_t mclk_rate; /* MCLK frequency in Hz */ + uint32_t fsync_rate; /* FSYNC frequency in Hz */ + uint32_t bclk_rate; /* BCLK frequency in Hz */ + + /* TDM */ + uint32_t tdm_slots; + uint32_t rx_slots; + uint32_t tx_slots; + uint16_t tdm_slot_width; + uint16_t reserved2; /* alignment */ +} __packed; + +/* SAI Configuration Request - SOF_IPC_DAI_SAI_CONFIG */ +struct sof_ipc_dai_sai_params { + struct sof_ipc_hdr hdr; + + /* MCLK */ + uint16_t reserved1; + uint16_t mclk_id; + uint32_t mclk_direction; + + uint32_t mclk_rate; /* MCLK frequency in Hz */ + uint32_t fsync_rate; /* FSYNC frequency in Hz */ + uint32_t bclk_rate; /* BCLK frequency in Hz */ + + /* TDM */ + uint32_t tdm_slots; + uint32_t rx_slots; + uint32_t tx_slots; + uint16_t tdm_slot_width; + uint16_t reserved2; /* alignment */ +} __packed; +#endif diff --git a/include/sound/sof/dai-intel.h b/include/sound/sof/dai-intel.h new file mode 100644 index 000000000..5b93b7292 --- /dev/null +++ b/include/sound/sof/dai-intel.h @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation. All rights reserved. + */ + +#ifndef __INCLUDE_SOUND_SOF_DAI_INTEL_H__ +#define __INCLUDE_SOUND_SOF_DAI_INTEL_H__ + +#include <sound/sof/header.h> + + /* ssc1: TINTE */ +#define SOF_DAI_INTEL_SSP_QUIRK_TINTE (1 << 0) + /* ssc1: PINTE */ +#define SOF_DAI_INTEL_SSP_QUIRK_PINTE (1 << 1) + /* ssc2: SMTATF */ +#define SOF_DAI_INTEL_SSP_QUIRK_SMTATF (1 << 2) + /* ssc2: MMRATF */ +#define SOF_DAI_INTEL_SSP_QUIRK_MMRATF (1 << 3) + /* ssc2: PSPSTWFDFD */ +#define SOF_DAI_INTEL_SSP_QUIRK_PSPSTWFDFD (1 << 4) + /* ssc2: PSPSRWFDFD */ +#define SOF_DAI_INTEL_SSP_QUIRK_PSPSRWFDFD (1 << 5) +/* ssc1: LBM */ +#define SOF_DAI_INTEL_SSP_QUIRK_LBM (1 << 6) + + /* here is the possibility to define others aux macros */ + +#define SOF_DAI_INTEL_SSP_FRAME_PULSE_WIDTH_MAX 38 +#define SOF_DAI_INTEL_SSP_SLOT_PADDING_MAX 31 + +/* SSP clocks control settings + * + * Macros for clks_control field in sof_ipc_dai_ssp_params struct. + */ + +/* mclk 0 disable */ +#define SOF_DAI_INTEL_SSP_MCLK_0_DISABLE BIT(0) +/* mclk 1 disable */ +#define SOF_DAI_INTEL_SSP_MCLK_1_DISABLE BIT(1) +/* mclk keep active */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_KA BIT(2) +/* bclk keep active */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_KA BIT(3) +/* fs keep active */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_FS_KA BIT(4) +/* bclk idle */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_IDLE_HIGH BIT(5) +/* mclk early start */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_ES BIT(6) +/* bclk early start */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_BCLK_ES BIT(7) +/* mclk always on */ +#define SOF_DAI_INTEL_SSP_CLKCTRL_MCLK_AON BIT(8) + +/* DMIC max. four controllers for eight microphone channels */ +#define SOF_DAI_INTEL_DMIC_NUM_CTRL 4 + +/* SSP Configuration Request - SOF_IPC_DAI_SSP_CONFIG */ +struct sof_ipc_dai_ssp_params { + struct sof_ipc_hdr hdr; + uint16_t reserved1; + uint16_t mclk_id; + + uint32_t mclk_rate; /* mclk frequency in Hz */ + uint32_t fsync_rate; /* fsync frequency in Hz */ + uint32_t bclk_rate; /* bclk frequency in Hz */ + + /* TDM */ + uint32_t tdm_slots; + uint32_t rx_slots; + uint32_t tx_slots; + + /* data */ + uint32_t sample_valid_bits; + uint16_t tdm_slot_width; + uint16_t reserved2; /* alignment */ + + /* MCLK */ + uint32_t mclk_direction; + + uint16_t frame_pulse_width; + uint16_t tdm_per_slot_padding_flag; + uint32_t clks_control; + uint32_t quirks; + uint32_t bclk_delay; /* guaranteed time (ms) for which BCLK + * will be driven, before sending data + */ +} __packed; + +/* HDA Configuration Request - SOF_IPC_DAI_HDA_CONFIG */ +struct sof_ipc_dai_hda_params { + struct sof_ipc_hdr hdr; + uint32_t link_dma_ch; + uint32_t rate; + uint32_t channels; +} __packed; + +/* ALH Configuration Request - SOF_IPC_DAI_ALH_CONFIG */ +struct sof_ipc_dai_alh_params { + struct sof_ipc_hdr hdr; + uint32_t stream_id; + uint32_t rate; + uint32_t channels; + + /* reserved for future use */ + uint32_t reserved[13]; +} __packed; + +/* DMIC Configuration Request - SOF_IPC_DAI_DMIC_CONFIG */ + +/* This struct is defined per 2ch PDM controller available in the platform. + * Normally it is sufficient to set the used microphone specific enables to 1 + * and keep other parameters as zero. The customizations are: + * + * 1. If a device mixes different microphones types with different polarity + * and/or the absolute polarity matters the PCM signal from a microphone + * can be inverted with the controls. + * + * 2. If the microphones in a stereo pair do not appear in captured stream + * in desired order due to board schematics choises they can be swapped with + * the clk_edge parameter. + * + * 3. If PDM bit errors are seen in capture (poor quality) the skew parameter + * that delays the sampling time of data by half cycles of DMIC source clock + * can be tried for improvement. However there is no guarantee for this to fix + * data integrity problems. + */ +struct sof_ipc_dai_dmic_pdm_ctrl { + struct sof_ipc_hdr hdr; + uint16_t id; /**< PDM controller ID */ + + uint16_t enable_mic_a; /**< Use A (left) channel mic (0 or 1)*/ + uint16_t enable_mic_b; /**< Use B (right) channel mic (0 or 1)*/ + + uint16_t polarity_mic_a; /**< Optionally invert mic A signal (0 or 1) */ + uint16_t polarity_mic_b; /**< Optionally invert mic B signal (0 or 1) */ + + uint16_t clk_edge; /**< Optionally swap data clock edge (0 or 1) */ + uint16_t skew; /**< Adjust PDM data sampling vs. clock (0..15) */ + + uint16_t reserved[3]; /**< Make sure the total size is 4 bytes aligned */ +} __packed; + +/* This struct contains the global settings for all 2ch PDM controllers. The + * version number used in configuration data is checked vs. version used by + * device driver src/drivers/dmic.c need to match. It is incremented from + * initial value 1 if updates done for the to driver would alter the operation + * of the microphone. + * + * Note: The microphone clock (pdmclk_min, pdmclk_max, duty_min, duty_max) + * parameters need to be set as defined in microphone data sheet. E.g. clock + * range 1.0 - 3.2 MHz is usually supported microphones. Some microphones are + * multi-mode capable and there may be denied mic clock frequencies between + * the modes. In such case set the clock range limits of the desired mode to + * avoid the driver to set clock to an illegal rate. + * + * The duty cycle could be set to 48-52% if not known. Generally these + * parameters can be altered within data sheet specified limits to match + * required audio application performance power. + * + * The microphone clock needs to be usually about 50-80 times the used audio + * sample rate. With highest sample rates above 48 kHz this can relaxed + * somewhat. + * + * The parameter wake_up_time describes how long time the microphone needs + * for the data line to produce valid output from mic clock start. The driver + * will mute the captured audio for the given time. The min_clock_on_time + * parameter is used to prevent too short clock bursts to happen. The driver + * will keep the clock active after capture stop if this time is not yet + * met. The unit for both is microseconds (us). Exceed of 100 ms will be + * treated as an error. + */ +struct sof_ipc_dai_dmic_params { + struct sof_ipc_hdr hdr; + uint32_t driver_ipc_version; /**< Version (1..N) */ + + uint32_t pdmclk_min; /**< Minimum microphone clock in Hz (100000..N) */ + uint32_t pdmclk_max; /**< Maximum microphone clock in Hz (min...N) */ + + uint32_t fifo_fs; /**< FIFO sample rate in Hz (8000..96000) */ + uint32_t reserved_1; /**< Reserved */ + uint16_t fifo_bits; /**< FIFO word length (16 or 32) */ + uint16_t fifo_bits_b; /**< Deprecated since firmware ABI 3.0.1 */ + + uint16_t duty_min; /**< Min. mic clock duty cycle in % (20..80) */ + uint16_t duty_max; /**< Max. mic clock duty cycle in % (min..80) */ + + uint32_t num_pdm_active; /**< Number of active pdm controllers. */ + /**< Range is 1..SOF_DAI_INTEL_DMIC_NUM_CTRL */ + + uint32_t wake_up_time; /**< Time from clock start to data (us) */ + uint32_t min_clock_on_time; /**< Min. time that clk is kept on (us) */ + uint32_t unmute_ramp_time; /**< Length of logarithmic gain ramp (ms) */ + + /* reserved for future use */ + uint32_t reserved[5]; + + /**< PDM controllers configuration */ + struct sof_ipc_dai_dmic_pdm_ctrl pdm[SOF_DAI_INTEL_DMIC_NUM_CTRL]; +} __packed; + +#endif diff --git a/include/sound/sof/dai-mediatek.h b/include/sound/sof/dai-mediatek.h new file mode 100644 index 000000000..62dd47205 --- /dev/null +++ b/include/sound/sof/dai-mediatek.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * Copyright(c) 2021 Mediatek Corporation. All rights reserved. + * + * Author: Bo Pan <bo.pan@mediatek.com> + */ + +#ifndef __INCLUDE_SOUND_SOF_DAI_MEDIATEK_H__ +#define __INCLUDE_SOUND_SOF_DAI_MEDIATEK_H__ + +#include <sound/sof/header.h> + +struct sof_ipc_dai_mtk_afe_params { + struct sof_ipc_hdr hdr; + u32 channels; + u32 rate; + u32 format; + u32 stream_id; + u32 reserved[4]; /* reserve for future */ +} __packed; + +#endif + diff --git a/include/sound/sof/dai.h b/include/sound/sof/dai.h new file mode 100644 index 000000000..9fbd3832b --- /dev/null +++ b/include/sound/sof/dai.h @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation. All rights reserved. + */ + +#ifndef __INCLUDE_SOUND_SOF_DAI_H__ +#define __INCLUDE_SOUND_SOF_DAI_H__ + +#include <sound/sof/header.h> +#include <sound/sof/dai-intel.h> +#include <sound/sof/dai-imx.h> +#include <sound/sof/dai-amd.h> +#include <sound/sof/dai-mediatek.h> + +/* + * DAI Configuration. + * + * Each different DAI type will have it's own structure and IPC cmd. + */ + +#define SOF_DAI_FMT_I2S 1 /**< I2S mode */ +#define SOF_DAI_FMT_RIGHT_J 2 /**< Right Justified mode */ +#define SOF_DAI_FMT_LEFT_J 3 /**< Left Justified mode */ +#define SOF_DAI_FMT_DSP_A 4 /**< L data MSB after FRM LRC */ +#define SOF_DAI_FMT_DSP_B 5 /**< L data MSB during FRM LRC */ +#define SOF_DAI_FMT_PDM 6 /**< Pulse density modulation */ + +#define SOF_DAI_FMT_CONT (1 << 4) /**< continuous clock */ +#define SOF_DAI_FMT_GATED (0 << 4) /**< clock is gated */ + +#define SOF_DAI_FMT_NB_NF (0 << 8) /**< normal bit clock + frame */ +#define SOF_DAI_FMT_NB_IF (2 << 8) /**< normal BCLK + inv FRM */ +#define SOF_DAI_FMT_IB_NF (3 << 8) /**< invert BCLK + nor FRM */ +#define SOF_DAI_FMT_IB_IF (4 << 8) /**< invert BCLK + FRM */ + +#define SOF_DAI_FMT_CBP_CFP (0 << 12) /**< codec bclk provider & frame provider */ +#define SOF_DAI_FMT_CBC_CFP (2 << 12) /**< codec bclk consumer & frame provider */ +#define SOF_DAI_FMT_CBP_CFC (3 << 12) /**< codec bclk provider & frame consumer */ +#define SOF_DAI_FMT_CBC_CFC (4 << 12) /**< codec bclk consumer & frame consumer */ + +/* keep old definitions for backwards compatibility */ +#define SOF_DAI_FMT_CBM_CFM SOF_DAI_FMT_CBP_CFP +#define SOF_DAI_FMT_CBS_CFM SOF_DAI_FMT_CBC_CFP +#define SOF_DAI_FMT_CBM_CFS SOF_DAI_FMT_CBP_CFC +#define SOF_DAI_FMT_CBS_CFS SOF_DAI_FMT_CBC_CFC + +#define SOF_DAI_FMT_FORMAT_MASK 0x000f +#define SOF_DAI_FMT_CLOCK_MASK 0x00f0 +#define SOF_DAI_FMT_INV_MASK 0x0f00 +#define SOF_DAI_FMT_CLOCK_PROVIDER_MASK 0xf000 + +/* + * DAI_CONFIG flags. The 4 LSB bits are used for the commands, HW_PARAMS, HW_FREE and PAUSE + * representing when the IPC is sent. The 4 MSB bits are used to add quirks along with the above + * commands. + */ +#define SOF_DAI_CONFIG_FLAGS_CMD_MASK 0xF +#define SOF_DAI_CONFIG_FLAGS_NONE 0 /**< DAI_CONFIG sent without stage information */ +#define SOF_DAI_CONFIG_FLAGS_HW_PARAMS BIT(0) /**< DAI_CONFIG sent during hw_params stage */ +#define SOF_DAI_CONFIG_FLAGS_HW_FREE BIT(1) /**< DAI_CONFIG sent during hw_free stage */ +/**< DAI_CONFIG sent during pause trigger. Only available ABI 3.20 onwards */ +#define SOF_DAI_CONFIG_FLAGS_PAUSE BIT(2) +#define SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT 4 +#define SOF_DAI_CONFIG_FLAGS_QUIRK_MASK (0xF << SOF_DAI_CONFIG_FLAGS_QUIRK_SHIFT) +/* + * This should be used along with the SOF_DAI_CONFIG_FLAGS_HW_PARAMS to indicate that pipeline + * stop/pause and DAI DMA stop/pause should happen in two steps. This change is only available + * ABI 3.20 onwards. + */ +#define SOF_DAI_CONFIG_FLAGS_2_STEP_STOP BIT(0) + +/** \brief Types of DAI */ +enum sof_ipc_dai_type { + SOF_DAI_INTEL_NONE = 0, /**< None */ + SOF_DAI_INTEL_SSP, /**< Intel SSP */ + SOF_DAI_INTEL_DMIC, /**< Intel DMIC */ + SOF_DAI_INTEL_HDA, /**< Intel HD/A */ + SOF_DAI_INTEL_ALH, /**< Intel ALH */ + SOF_DAI_IMX_SAI, /**< i.MX SAI */ + SOF_DAI_IMX_ESAI, /**< i.MX ESAI */ + SOF_DAI_AMD_BT, /**< AMD ACP BT*/ + SOF_DAI_AMD_SP, /**< AMD ACP SP */ + SOF_DAI_AMD_DMIC, /**< AMD ACP DMIC */ + SOF_DAI_MEDIATEK_AFE, /**< Mediatek AFE */ + SOF_DAI_AMD_HS, /**< Amd HS */ +}; + +/* general purpose DAI configuration */ +struct sof_ipc_dai_config { + struct sof_ipc_cmd_hdr hdr; + uint32_t type; /**< DAI type - enum sof_ipc_dai_type */ + uint32_t dai_index; /**< index of this type dai */ + + /* physical protocol and clocking */ + uint16_t format; /**< SOF_DAI_FMT_ */ + uint8_t group_id; /**< group ID, 0 means no group (ABI 3.17) */ + uint8_t flags; /**< SOF_DAI_CONFIG_FLAGS_ (ABI 3.19) */ + + /* reserved for future use */ + uint32_t reserved[8]; + + /* HW specific data */ + union { + struct sof_ipc_dai_ssp_params ssp; + struct sof_ipc_dai_dmic_params dmic; + struct sof_ipc_dai_hda_params hda; + struct sof_ipc_dai_alh_params alh; + struct sof_ipc_dai_esai_params esai; + struct sof_ipc_dai_sai_params sai; + struct sof_ipc_dai_acp_params acpbt; + struct sof_ipc_dai_acp_params acpsp; + struct sof_ipc_dai_acpdmic_params acpdmic; + struct sof_ipc_dai_acp_params acphs; + struct sof_ipc_dai_mtk_afe_params afe; + }; +} __packed; + +struct sof_dai_private_data { + struct sof_ipc_comp_dai *comp_dai; + struct sof_ipc_dai_config *dai_config; +}; + +#endif diff --git a/include/sound/sof/debug.h b/include/sound/sof/debug.h new file mode 100644 index 000000000..38693e3fb --- /dev/null +++ b/include/sound/sof/debug.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2020 Intel Corporation. All rights reserved. + * + * Author: Karol Trzcinski <karolx.trzcinski@linux.intel.com> + */ + +#ifndef __INCLUDE_SOUND_SOF_DEBUG_H__ +#define __INCLUDE_SOUND_SOF_DEBUG_H__ + +#include <sound/sof/header.h> + +/** ABI3.18 */ +enum sof_ipc_dbg_mem_zone { + SOF_IPC_MEM_ZONE_SYS = 0, /**< System zone */ + SOF_IPC_MEM_ZONE_SYS_RUNTIME = 1, /**< System-runtime zone */ + SOF_IPC_MEM_ZONE_RUNTIME = 2, /**< Runtime zone */ + SOF_IPC_MEM_ZONE_BUFFER = 3, /**< Buffer zone */ + SOF_IPC_MEM_ZONE_RUNTIME_SHARED = 4, /**< System runtime zone */ + SOF_IPC_MEM_ZONE_SYS_SHARED = 5, /**< System shared zone */ +}; + +/** ABI3.18 */ +struct sof_ipc_dbg_mem_usage_elem { + uint32_t zone; /**< see sof_ipc_dbg_mem_zone */ + uint32_t id; /**< heap index within zone */ + uint32_t used; /**< number of bytes used in zone */ + uint32_t free; /**< number of bytes free to use within zone */ + uint32_t reserved; /**< for future use */ +} __packed; + +/** ABI3.18 */ +struct sof_ipc_dbg_mem_usage { + struct sof_ipc_reply rhdr; /**< generic IPC reply header */ + uint32_t reserved[4]; /**< reserved for future use */ + uint32_t num_elems; /**< elems[] counter */ + struct sof_ipc_dbg_mem_usage_elem elems[]; /**< memory usage information */ +} __packed; + +#endif diff --git a/include/sound/sof/ext_manifest.h b/include/sound/sof/ext_manifest.h new file mode 100644 index 000000000..2a7e05558 --- /dev/null +++ b/include/sound/sof/ext_manifest.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2020 Intel Corporation. All rights reserved. + */ + +/* + * Extended manifest is a place to store metadata about firmware, known during + * compilation time - for example firmware version or used compiler. + * Given information are read on host side before firmware startup. + * This part of output binary is not signed. + */ + +#ifndef __SOF_FIRMWARE_EXT_MANIFEST_H__ +#define __SOF_FIRMWARE_EXT_MANIFEST_H__ + +#include <linux/bits.h> +#include <linux/compiler.h> +#include <linux/types.h> +#include <sound/sof/info.h> + +/* In ASCII `XMan` */ +#define SOF_EXT_MAN_MAGIC_NUMBER 0x6e614d58 + +/* Build u32 number in format MMmmmppp */ +#define SOF_EXT_MAN_BUILD_VERSION(MAJOR, MINOR, PATH) ((uint32_t)( \ + ((MAJOR) << 24) | \ + ((MINOR) << 12) | \ + (PATH))) + +/* check extended manifest version consistency */ +#define SOF_EXT_MAN_VERSION_INCOMPATIBLE(host_ver, cli_ver) ( \ + ((host_ver) & GENMASK(31, 24)) != \ + ((cli_ver) & GENMASK(31, 24))) + +/* used extended manifest header version */ +#define SOF_EXT_MAN_VERSION SOF_EXT_MAN_BUILD_VERSION(1, 0, 0) + +/* extended manifest header, deleting any field breaks backward compatibility */ +struct sof_ext_man_header { + uint32_t magic; /*< identification number, */ + /*< EXT_MAN_MAGIC_NUMBER */ + uint32_t full_size; /*< [bytes] full size of ext_man, */ + /*< (header + content + padding) */ + uint32_t header_size; /*< [bytes] makes header extensionable, */ + /*< after append new field to ext_man header */ + /*< then backward compatible won't be lost */ + uint32_t header_version; /*< value of EXT_MAN_VERSION */ + /*< not related with following content */ + + /* just after this header should be list of ext_man_elem_* elements */ +} __packed; + +/* Now define extended manifest elements */ + +/* Extended manifest elements types */ +enum sof_ext_man_elem_type { + SOF_EXT_MAN_ELEM_FW_VERSION = 0, + SOF_EXT_MAN_ELEM_WINDOW = 1, + SOF_EXT_MAN_ELEM_CC_VERSION = 2, + SOF_EXT_MAN_ELEM_DBG_ABI = 4, + SOF_EXT_MAN_ELEM_CONFIG_DATA = 5, /**< ABI3.17 */ + SOF_EXT_MAN_ELEM_PLATFORM_CONFIG_DATA = 6, +}; + +/* extended manifest element header */ +struct sof_ext_man_elem_header { + uint32_t type; /*< SOF_EXT_MAN_ELEM_ */ + uint32_t size; /*< in bytes, including header size */ + + /* just after this header should be type dependent content */ +} __packed; + +/* FW version */ +struct sof_ext_man_fw_version { + struct sof_ext_man_elem_header hdr; + /* use sof_ipc struct because of code re-use */ + struct sof_ipc_fw_version version; + uint32_t flags; +} __packed; + +/* extended data memory windows for IPC, trace and debug */ +struct sof_ext_man_window { + struct sof_ext_man_elem_header hdr; + /* use sof_ipc struct because of code re-use */ + struct sof_ipc_window ipc_window; +} __packed; + +/* Used C compiler description */ +struct sof_ext_man_cc_version { + struct sof_ext_man_elem_header hdr; + /* use sof_ipc struct because of code re-use */ + struct sof_ipc_cc_version cc_version; +} __packed; + +struct ext_man_dbg_abi { + struct sof_ext_man_elem_header hdr; + /* use sof_ipc struct because of code re-use */ + struct sof_ipc_user_abi_version dbg_abi; +} __packed; + +/* EXT_MAN_ELEM_CONFIG_DATA elements identificators, ABI3.17 */ +enum config_elem_type { + SOF_EXT_MAN_CONFIG_EMPTY = 0, + SOF_EXT_MAN_CONFIG_IPC_MSG_SIZE = 1, + SOF_EXT_MAN_CONFIG_MEMORY_USAGE_SCAN = 2, /**< ABI 3.18 */ +}; + +struct sof_config_elem { + uint32_t token; + uint32_t value; +} __packed; + +/* firmware configuration information */ +struct sof_ext_man_config_data { + struct sof_ext_man_elem_header hdr; + + struct sof_config_elem elems[]; +} __packed; + +#endif /* __SOF_FIRMWARE_EXT_MANIFEST_H__ */ diff --git a/include/sound/sof/ext_manifest4.h b/include/sound/sof/ext_manifest4.h new file mode 100644 index 000000000..ec97edcbb --- /dev/null +++ b/include/sound/sof/ext_manifest4.h @@ -0,0 +1,119 @@ +/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + */ + +/* + * Extended manifest is a place to store metadata about firmware, known during + * compilation time - for example firmware version or used compiler. + * Given information are read on host side before firmware startup. + * This part of output binary is not signed. + */ + +#ifndef __SOF_FIRMWARE_EXT_MANIFEST4_H__ +#define __SOF_FIRMWARE_EXT_MANIFEST4_H__ + +#include <linux/uuid.h> + +/* In ASCII $AE1 */ +#define SOF_EXT_MAN4_MAGIC_NUMBER 0x31454124 + +#define MAX_MODULE_NAME_LEN 8 +#define MAX_FW_BINARY_NAME 8 +#define DEFAULT_HASH_SHA256_LEN 32 +#define SOF_MAN4_FW_HDR_OFFSET 0x2000 +#define SOF_MAN4_FW_HDR_OFFSET_CAVS_1_5 0x284 + +/********************************************************************* + * extended manifest (struct sof_ext_manifest4_hdr) + *------------------- + * css_manifest hdr + *------------------- + * offset reserved for future + *------------------- + * fw_hdr (struct sof_man4_fw_binary_header) + *------------------- + * module_entry[0] (struct sof_man4_module) + *------------------- + * module_entry[1] + *------------------- + * ... + *------------------- + * module_entry[n] + *------------------- + * module_config[0] (struct sof_man4_module_config) + *------------------- + * module_config[1] + *------------------- + * ... + *------------------- + * module_config[m] + *------------------- + * FW content + *------------------- + *********************************************************************/ + +struct sof_ext_manifest4_hdr { + uint32_t id; + uint32_t len; /* length of extension manifest */ + uint16_t version_major; /* header version */ + uint16_t version_minor; + uint32_t num_module_entries; +} __packed; + +struct sof_man4_fw_binary_header { + /* This part must be unchanged to be backward compatible with SPT-LP ROM */ + uint32_t id; + uint32_t len; /* sizeof(sof_man4_fw_binary_header) in bytes */ + uint8_t name[MAX_FW_BINARY_NAME]; + uint32_t preload_page_count; /* number of pages of preloaded image */ + uint32_t fw_image_flags; + uint32_t feature_mask; + uint16_t major_version; /* Firmware version */ + uint16_t minor_version; + uint16_t hotfix_version; + uint16_t build_version; + uint32_t num_module_entries; + + /* This part may change to contain any additional data for BaseFw that is skipped by ROM */ + uint32_t hw_buf_base_addr; + uint32_t hw_buf_length; + uint32_t load_offset; /* This value is used by ROM */ +} __packed; + +struct sof_man4_segment_desc { + uint32_t flags; + uint32_t v_base_addr; + uint32_t file_offset; +} __packed; + +struct sof_man4_module { + uint32_t id; + uint8_t name[MAX_MODULE_NAME_LEN]; + guid_t uuid; + uint32_t type; + uint8_t hash[DEFAULT_HASH_SHA256_LEN]; + uint32_t entry_point; + uint16_t cfg_offset; + uint16_t cfg_count; + uint32_t affinity_mask; + uint16_t instance_max_count; + uint16_t instance_stack_size; + struct sof_man4_segment_desc segments[3]; +} __packed; + +struct sof_man4_module_config { + uint32_t par[4]; /* module parameters */ + uint32_t is_bytes; /* actual size of instance .bss (bytes) */ + uint32_t cps; /* cycles per second */ + uint32_t ibs; /* input buffer size (bytes) */ + uint32_t obs; /* output buffer size (bytes) */ + uint32_t module_flags; /* flags, reserved for future use */ + uint32_t cpc; /* cycles per single run */ + uint32_t obls; /* output block size, reserved for future use */ +} __packed; + +#endif /* __SOF_FIRMWARE_EXT_MANIFEST4_H__ */ diff --git a/include/sound/sof/header.h b/include/sound/sof/header.h new file mode 100644 index 000000000..b22e925c7 --- /dev/null +++ b/include/sound/sof/header.h @@ -0,0 +1,205 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation. All rights reserved. + */ + +#ifndef __INCLUDE_SOUND_SOF_HEADER_H__ +#define __INCLUDE_SOUND_SOF_HEADER_H__ + +#include <linux/types.h> +#include <uapi/sound/sof/abi.h> + +/** \addtogroup sof_uapi uAPI + * SOF uAPI specification. + * @{ + */ + +/* + * IPC messages have a prefixed 32 bit identifier made up as follows :- + * + * 0xGCCCNNNN where + * G is global cmd type (4 bits) + * C is command type (12 bits) + * I is the ID number (16 bits) - monotonic and overflows + * + * This is sent at the start of the IPM message in the mailbox. Messages should + * not be sent in the doorbell (special exceptions for firmware . + */ + +/* Global Message - Generic */ +#define SOF_GLB_TYPE_SHIFT 28 +#define SOF_GLB_TYPE_MASK (0xfUL << SOF_GLB_TYPE_SHIFT) +#define SOF_GLB_TYPE(x) ((x) << SOF_GLB_TYPE_SHIFT) + +/* Command Message - Generic */ +#define SOF_CMD_TYPE_SHIFT 16 +#define SOF_CMD_TYPE_MASK (0xfffL << SOF_CMD_TYPE_SHIFT) +#define SOF_CMD_TYPE(x) ((x) << SOF_CMD_TYPE_SHIFT) + +/* Global Message Types */ +#define SOF_IPC_GLB_REPLY SOF_GLB_TYPE(0x1U) +#define SOF_IPC_GLB_COMPOUND SOF_GLB_TYPE(0x2U) +#define SOF_IPC_GLB_TPLG_MSG SOF_GLB_TYPE(0x3U) +#define SOF_IPC_GLB_PM_MSG SOF_GLB_TYPE(0x4U) +#define SOF_IPC_GLB_COMP_MSG SOF_GLB_TYPE(0x5U) +#define SOF_IPC_GLB_STREAM_MSG SOF_GLB_TYPE(0x6U) +#define SOF_IPC_FW_READY SOF_GLB_TYPE(0x7U) +#define SOF_IPC_GLB_DAI_MSG SOF_GLB_TYPE(0x8U) +#define SOF_IPC_GLB_TRACE_MSG SOF_GLB_TYPE(0x9U) +#define SOF_IPC_GLB_GDB_DEBUG SOF_GLB_TYPE(0xAU) +#define SOF_IPC_GLB_TEST_MSG SOF_GLB_TYPE(0xBU) +#define SOF_IPC_GLB_PROBE SOF_GLB_TYPE(0xCU) +#define SOF_IPC_GLB_DEBUG SOF_GLB_TYPE(0xDU) + +/* + * DSP Command Message Types + */ + +/* topology */ +#define SOF_IPC_TPLG_COMP_NEW SOF_CMD_TYPE(0x001) +#define SOF_IPC_TPLG_COMP_FREE SOF_CMD_TYPE(0x002) +#define SOF_IPC_TPLG_COMP_CONNECT SOF_CMD_TYPE(0x003) +#define SOF_IPC_TPLG_PIPE_NEW SOF_CMD_TYPE(0x010) +#define SOF_IPC_TPLG_PIPE_FREE SOF_CMD_TYPE(0x011) +#define SOF_IPC_TPLG_PIPE_CONNECT SOF_CMD_TYPE(0x012) +#define SOF_IPC_TPLG_PIPE_COMPLETE SOF_CMD_TYPE(0x013) +#define SOF_IPC_TPLG_BUFFER_NEW SOF_CMD_TYPE(0x020) +#define SOF_IPC_TPLG_BUFFER_FREE SOF_CMD_TYPE(0x021) + +/* PM */ +#define SOF_IPC_PM_CTX_SAVE SOF_CMD_TYPE(0x001) +#define SOF_IPC_PM_CTX_RESTORE SOF_CMD_TYPE(0x002) +#define SOF_IPC_PM_CTX_SIZE SOF_CMD_TYPE(0x003) +#define SOF_IPC_PM_CLK_SET SOF_CMD_TYPE(0x004) +#define SOF_IPC_PM_CLK_GET SOF_CMD_TYPE(0x005) +#define SOF_IPC_PM_CLK_REQ SOF_CMD_TYPE(0x006) +#define SOF_IPC_PM_CORE_ENABLE SOF_CMD_TYPE(0x007) +#define SOF_IPC_PM_GATE SOF_CMD_TYPE(0x008) + +/* component runtime config - multiple different types */ +#define SOF_IPC_COMP_SET_VALUE SOF_CMD_TYPE(0x001) +#define SOF_IPC_COMP_GET_VALUE SOF_CMD_TYPE(0x002) +#define SOF_IPC_COMP_SET_DATA SOF_CMD_TYPE(0x003) +#define SOF_IPC_COMP_GET_DATA SOF_CMD_TYPE(0x004) +#define SOF_IPC_COMP_NOTIFICATION SOF_CMD_TYPE(0x005) + +/* DAI messages */ +#define SOF_IPC_DAI_CONFIG SOF_CMD_TYPE(0x001) +#define SOF_IPC_DAI_LOOPBACK SOF_CMD_TYPE(0x002) + +/* stream */ +#define SOF_IPC_STREAM_PCM_PARAMS SOF_CMD_TYPE(0x001) +#define SOF_IPC_STREAM_PCM_PARAMS_REPLY SOF_CMD_TYPE(0x002) +#define SOF_IPC_STREAM_PCM_FREE SOF_CMD_TYPE(0x003) +#define SOF_IPC_STREAM_TRIG_START SOF_CMD_TYPE(0x004) +#define SOF_IPC_STREAM_TRIG_STOP SOF_CMD_TYPE(0x005) +#define SOF_IPC_STREAM_TRIG_PAUSE SOF_CMD_TYPE(0x006) +#define SOF_IPC_STREAM_TRIG_RELEASE SOF_CMD_TYPE(0x007) +#define SOF_IPC_STREAM_TRIG_DRAIN SOF_CMD_TYPE(0x008) +#define SOF_IPC_STREAM_TRIG_XRUN SOF_CMD_TYPE(0x009) +#define SOF_IPC_STREAM_POSITION SOF_CMD_TYPE(0x00a) +#define SOF_IPC_STREAM_VORBIS_PARAMS SOF_CMD_TYPE(0x010) +#define SOF_IPC_STREAM_VORBIS_FREE SOF_CMD_TYPE(0x011) + +/* probe */ +#define SOF_IPC_PROBE_INIT SOF_CMD_TYPE(0x001) +#define SOF_IPC_PROBE_DEINIT SOF_CMD_TYPE(0x002) +#define SOF_IPC_PROBE_DMA_ADD SOF_CMD_TYPE(0x003) +#define SOF_IPC_PROBE_DMA_INFO SOF_CMD_TYPE(0x004) +#define SOF_IPC_PROBE_DMA_REMOVE SOF_CMD_TYPE(0x005) +#define SOF_IPC_PROBE_POINT_ADD SOF_CMD_TYPE(0x006) +#define SOF_IPC_PROBE_POINT_INFO SOF_CMD_TYPE(0x007) +#define SOF_IPC_PROBE_POINT_REMOVE SOF_CMD_TYPE(0x008) + +/* trace */ +#define SOF_IPC_TRACE_DMA_PARAMS SOF_CMD_TYPE(0x001) +#define SOF_IPC_TRACE_DMA_POSITION SOF_CMD_TYPE(0x002) +#define SOF_IPC_TRACE_DMA_PARAMS_EXT SOF_CMD_TYPE(0x003) +#define SOF_IPC_TRACE_FILTER_UPDATE SOF_CMD_TYPE(0x004) /**< ABI3.17 */ +#define SOF_IPC_TRACE_DMA_FREE SOF_CMD_TYPE(0x005) /**< ABI3.20 */ + +/* debug */ +#define SOF_IPC_DEBUG_MEM_USAGE SOF_CMD_TYPE(0x001) + +/* test */ +#define SOF_IPC_TEST_IPC_FLOOD SOF_CMD_TYPE(0x001) + +/* Get message component id */ +#define SOF_IPC_MESSAGE_ID(x) ((x) & 0xffff) + +/* maximum message size for mailbox Tx/Rx */ +#define SOF_IPC_MSG_MAX_SIZE 384 + +/* + * Structure Header - Header for all IPC structures except command structs. + * The size can be greater than the structure size and that means there is + * extended bespoke data beyond the end of the structure including variable + * arrays. + */ + +struct sof_ipc_hdr { + uint32_t size; /**< size of structure */ +} __packed; + +/* + * Command Header - Header for all IPC commands. Identifies IPC message. + * The size can be greater than the structure size and that means there is + * extended bespoke data beyond the end of the structure including variable + * arrays. + */ + +struct sof_ipc_cmd_hdr { + uint32_t size; /**< size of structure */ + uint32_t cmd; /**< SOF_IPC_GLB_ + cmd */ +} __packed; + +/* + * Generic reply message. Some commands override this with their own reply + * types that must include this at start. + */ +struct sof_ipc_reply { + struct sof_ipc_cmd_hdr hdr; + int32_t error; /**< negative error numbers */ +} __packed; + +/* + * Compound commands - SOF_IPC_GLB_COMPOUND. + * + * Compound commands are sent to the DSP as a single IPC operation. The + * commands are split into blocks and each block has a header. This header + * identifies the command type and the number of commands before the next + * header. + */ + +struct sof_ipc_compound_hdr { + struct sof_ipc_cmd_hdr hdr; + uint32_t count; /**< count of 0 means end of compound sequence */ +} __packed; + +/** + * OOPS header architecture specific data. + */ +struct sof_ipc_dsp_oops_arch_hdr { + uint32_t arch; /* Identifier of architecture */ + uint32_t totalsize; /* Total size of oops message */ +} __packed; + +/** + * OOPS header platform specific data. + */ +struct sof_ipc_dsp_oops_plat_hdr { + uint32_t configidhi; /* ConfigID hi 32bits */ + uint32_t configidlo; /* ConfigID lo 32bits */ + uint32_t numaregs; /* Special regs num */ + uint32_t stackoffset; /* Offset to stack pointer from beginning of + * oops message + */ + uint32_t stackptr; /* Stack ptr */ +} __packed; + +/** @}*/ + +#endif diff --git a/include/sound/sof/info.h b/include/sound/sof/info.h new file mode 100644 index 000000000..75193850e --- /dev/null +++ b/include/sound/sof/info.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation. All rights reserved. + */ + +#ifndef __INCLUDE_SOUND_SOF_INFO_H__ +#define __INCLUDE_SOUND_SOF_INFO_H__ + +#include <sound/sof/header.h> +#include <sound/sof/stream.h> + +/* + * Firmware boot and version + */ + +#define SOF_IPC_MAX_ELEMS 16 + +/* + * Firmware boot info flag bits (64-bit) + */ +#define SOF_IPC_INFO_BUILD BIT(0) +#define SOF_IPC_INFO_LOCKS BIT(1) +#define SOF_IPC_INFO_LOCKSV BIT(2) +#define SOF_IPC_INFO_GDB BIT(3) +#define SOF_IPC_INFO_D3_PERSISTENT BIT(4) + +/* extended data types that can be appended onto end of sof_ipc_fw_ready */ +enum sof_ipc_ext_data { + SOF_IPC_EXT_UNUSED = 0, + SOF_IPC_EXT_WINDOW = 1, + SOF_IPC_EXT_CC_INFO = 2, + SOF_IPC_EXT_PROBE_INFO = 3, + SOF_IPC_EXT_USER_ABI_INFO = 4, +}; + +/* Build u32 number in format MMmmmppp */ +#define SOF_FW_VER(MAJOR, MINOR, PATCH) ((uint32_t)( \ + ((MAJOR) << 24) | ((MINOR) << 12) | (PATCH))) + +/* FW version - SOF_IPC_GLB_VERSION */ +struct sof_ipc_fw_version { + struct sof_ipc_hdr hdr; + uint16_t major; + uint16_t minor; + uint16_t micro; + uint16_t build; + uint8_t date[12]; + uint8_t time[10]; + uint8_t tag[6]; + uint32_t abi_version; + /* used to check FW and ldc file compatibility, reproducible value */ + uint32_t src_hash; + + /* reserved for future use */ + uint32_t reserved[3]; +} __packed; + +/* FW ready Message - sent by firmware when boot has completed */ +struct sof_ipc_fw_ready { + struct sof_ipc_cmd_hdr hdr; + uint32_t dspbox_offset; /* dsp initiated IPC mailbox */ + uint32_t hostbox_offset; /* host initiated IPC mailbox */ + uint32_t dspbox_size; + uint32_t hostbox_size; + struct sof_ipc_fw_version version; + + /* Miscellaneous flags */ + uint64_t flags; + + /* reserved for future use */ + uint32_t reserved[4]; +} __packed; + +/* + * Extended Firmware data. All optional, depends on platform/arch. + */ +enum sof_ipc_region { + SOF_IPC_REGION_DOWNBOX = 0, + SOF_IPC_REGION_UPBOX, + SOF_IPC_REGION_TRACE, + SOF_IPC_REGION_DEBUG, + SOF_IPC_REGION_STREAM, + SOF_IPC_REGION_REGS, + SOF_IPC_REGION_EXCEPTION, +}; + +struct sof_ipc_ext_data_hdr { + struct sof_ipc_cmd_hdr hdr; + uint32_t type; /**< SOF_IPC_EXT_ */ +} __packed; + +struct sof_ipc_window_elem { + struct sof_ipc_hdr hdr; + uint32_t type; /**< SOF_IPC_REGION_ */ + uint32_t id; /**< platform specific - used to map to host memory */ + uint32_t flags; /**< R, W, RW, etc - to define */ + uint32_t size; /**< size of region in bytes */ + /* offset in window region as windows can be partitioned */ + uint32_t offset; +} __packed; + +/* extended data memory windows for IPC, trace and debug */ +struct sof_ipc_window { + struct sof_ipc_ext_data_hdr ext_hdr; + uint32_t num_windows; + struct sof_ipc_window_elem window[SOF_IPC_MAX_ELEMS]; +} __packed; + +struct sof_ipc_cc_version { + struct sof_ipc_ext_data_hdr ext_hdr; + uint32_t major; + uint32_t minor; + uint32_t micro; + + /* reserved for future use */ + uint32_t reserved[4]; + + uint8_t name[16]; /* null terminated compiler name */ + uint8_t optim[4]; /* null terminated compiler -O flag value */ + uint8_t desc[32]; /* null terminated compiler description */ +} __packed; + +/* extended data: Probe setup */ +struct sof_ipc_probe_support { + struct sof_ipc_ext_data_hdr ext_hdr; + + uint32_t probe_points_max; + uint32_t injection_dmas_max; + + /* reserved for future use */ + uint32_t reserved[2]; +} __packed; + +/* extended data: user abi version(s) */ +struct sof_ipc_user_abi_version { + struct sof_ipc_ext_data_hdr ext_hdr; + + uint32_t abi_dbg_version; +} __packed; + +#endif diff --git a/include/sound/sof/ipc4/header.h b/include/sound/sof/ipc4/header.h new file mode 100644 index 000000000..99efe0ef1 --- /dev/null +++ b/include/sound/sof/ipc4/header.h @@ -0,0 +1,473 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2022 Intel Corporation. All rights reserved. + */ + +#ifndef __INCLUDE_SOUND_SOF_IPC4_HEADER_H__ +#define __INCLUDE_SOUND_SOF_IPC4_HEADER_H__ + +#include <linux/types.h> +#include <uapi/sound/sof/abi.h> + +/* maximum message size for mailbox Tx/Rx */ +#define SOF_IPC4_MSG_MAX_SIZE 4096 + +/** \addtogroup sof_uapi uAPI + * SOF uAPI specification. + * @{ + */ + +/** + * struct sof_ipc4_msg - Placeholder of an IPC4 message + * @header_u64: IPC4 header as single u64 number + * @primary: Primary, mandatory part of the header + * @extension: Extended part of the header, if not used it should be + * set to 0 + * @data_size: Size of data in bytes pointed by @data_ptr + * @data_ptr: Pointer to the optional payload of a message + */ +struct sof_ipc4_msg { + union { + u64 header_u64; + struct { + u32 primary; + u32 extension; + }; + }; + + size_t data_size; + void *data_ptr; +}; + +/** + * struct sof_ipc4_tuple - Generic type/ID and parameter tuple + * @type: type/ID + * @size: size of the @value array in bytes + * @value: value for the given type + */ +struct sof_ipc4_tuple { + uint32_t type; + uint32_t size; + uint32_t value[]; +} __packed; + +/* + * IPC4 messages have two 32 bit identifier made up as follows :- + * + * header - msg type, msg id, msg direction ... + * extension - extra params such as msg data size in mailbox + * + * These are sent at the start of the IPC message in the mailbox. Messages + * should not be sent in the doorbell (special exceptions for firmware). + */ + +/* + * IPC4 primary header bit allocation for messages + * bit 0-23: message type specific + * bit 24-28: type: enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG + * enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG + * bit 29: response - sof_ipc4_msg_dir + * bit 30: target - enum sof_ipc4_msg_target + * bit 31: reserved, unused + */ + +/* Value of target field - must fit into 1 bit */ +enum sof_ipc4_msg_target { + /* Global FW message */ + SOF_IPC4_FW_GEN_MSG, + + /* Module message */ + SOF_IPC4_MODULE_MSG +}; + +/* Value of type field - must fit into 5 bits */ +enum sof_ipc4_global_msg { + SOF_IPC4_GLB_BOOT_CONFIG, + SOF_IPC4_GLB_ROM_CONTROL, + SOF_IPC4_GLB_IPCGATEWAY_CMD, + + /* 3 .. 12: RESERVED - do not use */ + + SOF_IPC4_GLB_PERF_MEASUREMENTS_CMD = 13, + SOF_IPC4_GLB_CHAIN_DMA, + + SOF_IPC4_GLB_LOAD_MULTIPLE_MODULES, + SOF_IPC4_GLB_UNLOAD_MULTIPLE_MODULES, + + /* pipeline settings */ + SOF_IPC4_GLB_CREATE_PIPELINE, + SOF_IPC4_GLB_DELETE_PIPELINE, + SOF_IPC4_GLB_SET_PIPELINE_STATE, + SOF_IPC4_GLB_GET_PIPELINE_STATE, + SOF_IPC4_GLB_GET_PIPELINE_CONTEXT_SIZE, + SOF_IPC4_GLB_SAVE_PIPELINE, + SOF_IPC4_GLB_RESTORE_PIPELINE, + + /* Loads library (using Code Load or HD/A Host Output DMA) */ + SOF_IPC4_GLB_LOAD_LIBRARY, + + /* 25: RESERVED - do not use */ + + SOF_IPC4_GLB_INTERNAL_MESSAGE = 26, + + /* Notification (FW to SW driver) */ + SOF_IPC4_GLB_NOTIFICATION, + + /* 28 .. 31: RESERVED - do not use */ + + SOF_IPC4_GLB_TYPE_LAST, +}; + +/* Value of response field - must fit into 1 bit */ +enum sof_ipc4_msg_dir { + SOF_IPC4_MSG_REQUEST, + SOF_IPC4_MSG_REPLY, +}; + +enum sof_ipc4_pipeline_state { + SOF_IPC4_PIPE_INVALID_STATE, + SOF_IPC4_PIPE_UNINITIALIZED, + SOF_IPC4_PIPE_RESET, + SOF_IPC4_PIPE_PAUSED, + SOF_IPC4_PIPE_RUNNING, + SOF_IPC4_PIPE_EOS +}; + +/* Generic message fields (bit 24-30) */ + +/* encoded to header's msg_tgt field */ +#define SOF_IPC4_MSG_TARGET_SHIFT 30 +#define SOF_IPC4_MSG_TARGET_MASK BIT(30) +#define SOF_IPC4_MSG_TARGET(x) ((x) << SOF_IPC4_MSG_TARGET_SHIFT) +#define SOF_IPC4_MSG_IS_MODULE_MSG(x) ((x) & SOF_IPC4_MSG_TARGET_MASK ? 1 : 0) + +/* encoded to header's rsp field */ +#define SOF_IPC4_MSG_DIR_SHIFT 29 +#define SOF_IPC4_MSG_DIR_MASK BIT(29) +#define SOF_IPC4_MSG_DIR(x) ((x) << SOF_IPC4_MSG_DIR_SHIFT) + +/* encoded to header's type field */ +#define SOF_IPC4_MSG_TYPE_SHIFT 24 +#define SOF_IPC4_MSG_TYPE_MASK GENMASK(28, 24) +#define SOF_IPC4_MSG_TYPE_SET(x) (((x) << SOF_IPC4_MSG_TYPE_SHIFT) & \ + SOF_IPC4_MSG_TYPE_MASK) +#define SOF_IPC4_MSG_TYPE_GET(x) (((x) & SOF_IPC4_MSG_TYPE_MASK) >> \ + SOF_IPC4_MSG_TYPE_SHIFT) + +/* Global message type specific field definitions */ + +/* pipeline creation ipc msg */ +#define SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT 16 +#define SOF_IPC4_GLB_PIPE_INSTANCE_MASK GENMASK(23, 16) +#define SOF_IPC4_GLB_PIPE_INSTANCE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_INSTANCE_SHIFT) + +#define SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT 11 +#define SOF_IPC4_GLB_PIPE_PRIORITY_MASK GENMASK(15, 11) +#define SOF_IPC4_GLB_PIPE_PRIORITY(x) ((x) << SOF_IPC4_GLB_PIPE_PRIORITY_SHIFT) + +#define SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT 0 +#define SOF_IPC4_GLB_PIPE_MEM_SIZE_MASK GENMASK(10, 0) +#define SOF_IPC4_GLB_PIPE_MEM_SIZE(x) ((x) << SOF_IPC4_GLB_PIPE_MEM_SIZE_SHIFT) + +#define SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT 0 +#define SOF_IPC4_GLB_PIPE_EXT_LP_MASK BIT(0) +#define SOF_IPC4_GLB_PIPE_EXT_LP(x) ((x) << SOF_IPC4_GLB_PIPE_EXT_LP_SHIFT) + +/* pipeline set state ipc msg */ +#define SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT 16 +#define SOF_IPC4_GLB_PIPE_STATE_ID_MASK GENMASK(23, 16) +#define SOF_IPC4_GLB_PIPE_STATE_ID(x) ((x) << SOF_IPC4_GLB_PIPE_STATE_ID_SHIFT) + +#define SOF_IPC4_GLB_PIPE_STATE_SHIFT 0 +#define SOF_IPC4_GLB_PIPE_STATE_MASK GENMASK(15, 0) +#define SOF_IPC4_GLB_PIPE_STATE(x) ((x) << SOF_IPC4_GLB_PIPE_STATE_SHIFT) + +enum sof_ipc4_channel_config { + /* one channel only. */ + SOF_IPC4_CHANNEL_CONFIG_MONO, + /* L & R. */ + SOF_IPC4_CHANNEL_CONFIG_STEREO, + /* L, R & LFE; PCM only. */ + SOF_IPC4_CHANNEL_CONFIG_2_POINT_1, + /* L, C & R; MP3 & AAC only. */ + SOF_IPC4_CHANNEL_CONFIG_3_POINT_0, + /* L, C, R & LFE; PCM only. */ + SOF_IPC4_CHANNEL_CONFIG_3_POINT_1, + /* L, R, Ls & Rs; PCM only. */ + SOF_IPC4_CHANNEL_CONFIG_QUATRO, + /* L, C, R & Cs; MP3 & AAC only. */ + SOF_IPC4_CHANNEL_CONFIG_4_POINT_0, + /* L, C, R, Ls & Rs. */ + SOF_IPC4_CHANNEL_CONFIG_5_POINT_0, + /* L, C, R, Ls, Rs & LFE. */ + SOF_IPC4_CHANNEL_CONFIG_5_POINT_1, + /* one channel replicated in two. */ + SOF_IPC4_CHANNEL_CONFIG_DUAL_MONO, + /* Stereo (L,R) in 4 slots, 1st stream: [ L, R, -, - ] */ + SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_0, + /* Stereo (L,R) in 4 slots, 2nd stream: [ -, -, L, R ] */ + SOF_IPC4_CHANNEL_CONFIG_I2S_DUAL_STEREO_1, + /* L, C, R, Ls, Rs & LFE., LS, RS */ + SOF_IPC4_CHANNEL_CONFIG_7_POINT_1, +}; + +enum sof_ipc4_interleaved_style { + SOF_IPC4_CHANNELS_INTERLEAVED, + SOF_IPC4_CHANNELS_NONINTERLEAVED, +}; + +enum sof_ipc4_sample_type { + SOF_IPC4_MSB_INTEGER, /* integer with Most Significant Byte first */ + SOF_IPC4_LSB_INTEGER, /* integer with Least Significant Byte first */ +}; + +struct sof_ipc4_audio_format { + uint32_t sampling_frequency; + uint32_t bit_depth; + uint32_t ch_map; + uint32_t ch_cfg; /* sof_ipc4_channel_config */ + uint32_t interleaving_style; + uint32_t fmt_cfg; /* channels_count valid_bit_depth s_type */ +} __packed __aligned(4); + +#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_SHIFT 0 +#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK GENMASK(7, 0) +#define SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(x) \ + ((x) & SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT_MASK) +#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT 8 +#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK GENMASK(15, 8) +#define SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(x) \ + (((x) & SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_MASK) >> \ + SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH_SHIFT) +#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT 16 +#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK GENMASK(23, 16) +#define SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE(x) \ + (((x) & SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_MASK) >> \ + SOF_IPC4_AUDIO_FORMAT_CFG_SAMPLE_TYPE_SHIFT) + +/* Module message type specific field definitions */ + +enum sof_ipc4_module_type { + SOF_IPC4_MOD_INIT_INSTANCE, + SOF_IPC4_MOD_CONFIG_GET, + SOF_IPC4_MOD_CONFIG_SET, + SOF_IPC4_MOD_LARGE_CONFIG_GET, + SOF_IPC4_MOD_LARGE_CONFIG_SET, + SOF_IPC4_MOD_BIND, + SOF_IPC4_MOD_UNBIND, + SOF_IPC4_MOD_SET_DX, + SOF_IPC4_MOD_SET_D0IX, + SOF_IPC4_MOD_ENTER_MODULE_RESTORE, + SOF_IPC4_MOD_EXIT_MODULE_RESTORE, + SOF_IPC4_MOD_DELETE_INSTANCE, + + SOF_IPC4_MOD_TYPE_LAST, +}; + +struct sof_ipc4_base_module_cfg { + uint32_t cpc; /* the max count of Cycles Per Chunk processing */ + uint32_t ibs; /* input Buffer Size (in bytes) */ + uint32_t obs; /* output Buffer Size (in bytes) */ + uint32_t is_pages; /* number of physical pages used */ + struct sof_ipc4_audio_format audio_fmt; +} __packed __aligned(4); + +/* common module ipc msg */ +#define SOF_IPC4_MOD_INSTANCE_SHIFT 16 +#define SOF_IPC4_MOD_INSTANCE_MASK GENMASK(23, 16) +#define SOF_IPC4_MOD_INSTANCE(x) ((x) << SOF_IPC4_MOD_INSTANCE_SHIFT) + +#define SOF_IPC4_MOD_ID_SHIFT 0 +#define SOF_IPC4_MOD_ID_MASK GENMASK(15, 0) +#define SOF_IPC4_MOD_ID(x) ((x) << SOF_IPC4_MOD_ID_SHIFT) + +/* init module ipc msg */ +#define SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT 0 +#define SOF_IPC4_MOD_EXT_PARAM_SIZE_MASK GENMASK(15, 0) +#define SOF_IPC4_MOD_EXT_PARAM_SIZE(x) ((x) << SOF_IPC4_MOD_EXT_PARAM_SIZE_SHIFT) + +#define SOF_IPC4_MOD_EXT_PPL_ID_SHIFT 16 +#define SOF_IPC4_MOD_EXT_PPL_ID_MASK GENMASK(23, 16) +#define SOF_IPC4_MOD_EXT_PPL_ID(x) ((x) << SOF_IPC4_MOD_EXT_PPL_ID_SHIFT) + +#define SOF_IPC4_MOD_EXT_CORE_ID_SHIFT 24 +#define SOF_IPC4_MOD_EXT_CORE_ID_MASK GENMASK(27, 24) +#define SOF_IPC4_MOD_EXT_CORE_ID(x) ((x) << SOF_IPC4_MOD_EXT_CORE_ID_SHIFT) + +#define SOF_IPC4_MOD_EXT_DOMAIN_SHIFT 28 +#define SOF_IPC4_MOD_EXT_DOMAIN_MASK BIT(28) +#define SOF_IPC4_MOD_EXT_DOMAIN(x) ((x) << SOF_IPC4_MOD_EXT_DOMAIN_SHIFT) + +/* bind/unbind module ipc msg */ +#define SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT 0 +#define SOF_IPC4_MOD_EXT_DST_MOD_ID_MASK GENMASK(15, 0) +#define SOF_IPC4_MOD_EXT_DST_MOD_ID(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_ID_SHIFT) + +#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT 16 +#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_MASK GENMASK(23, 16) +#define SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_INSTANCE_SHIFT) + +#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT 24 +#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_MASK GENMASK(26, 24) +#define SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID(x) ((x) << SOF_IPC4_MOD_EXT_DST_MOD_QUEUE_ID_SHIFT) + +#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT 27 +#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_MASK GENMASK(29, 27) +#define SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID(x) ((x) << SOF_IPC4_MOD_EXT_SRC_MOD_QUEUE_ID_SHIFT) + +#define MOD_ENABLE_LOG 6 +#define MOD_SYSTEM_TIME 20 + +/* set module large config */ +#define SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT 0 +#define SOF_IPC4_MOD_EXT_MSG_SIZE_MASK GENMASK(19, 0) +#define SOF_IPC4_MOD_EXT_MSG_SIZE(x) ((x) << SOF_IPC4_MOD_EXT_MSG_SIZE_SHIFT) + +#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT 20 +#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID_MASK GENMASK(27, 20) +#define SOF_IPC4_MOD_EXT_MSG_PARAM_ID(x) ((x) << SOF_IPC4_MOD_EXT_MSG_PARAM_ID_SHIFT) + +#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT 28 +#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_MASK BIT(28) +#define SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK(x) ((x) << SOF_IPC4_MOD_EXT_MSG_LAST_BLOCK_SHIFT) + +#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT 29 +#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_MASK BIT(29) +#define SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK(x) ((x) << SOF_IPC4_MOD_EXT_MSG_FIRST_BLOCK_SHIFT) + +/* Init instance messagees */ +#define SOF_IPC4_MOD_INIT_BASEFW_MOD_ID 0 +#define SOF_IPC4_MOD_INIT_BASEFW_INSTANCE_ID 0 + +enum sof_ipc4_base_fw_params { + SOF_IPC4_FW_PARAM_ENABLE_LOGS = 6, + SOF_IPC4_FW_PARAM_FW_CONFIG, + SOF_IPC4_FW_PARAM_HW_CONFIG_GET, + SOF_IPC4_FW_PARAM_MODULES_INFO_GET, + SOF_IPC4_FW_PARAM_LIBRARIES_INFO_GET = 16, + SOF_IPC4_FW_PARAM_SYSTEM_TIME = 20, +}; + +enum sof_ipc4_fw_config_params { + SOF_IPC4_FW_CFG_FW_VERSION, + SOF_IPC4_FW_CFG_MEMORY_RECLAIMED, + SOF_IPC4_FW_CFG_SLOW_CLOCK_FREQ_HZ, + SOF_IPC4_FW_CFG_FAST_CLOCK_FREQ_HZ, + SOF_IPC4_FW_CFG_DMA_BUFFER_CONFIG, + SOF_IPC4_FW_CFG_ALH_SUPPORT_LEVEL, + SOF_IPC4_FW_CFG_DL_MAILBOX_BYTES, + SOF_IPC4_FW_CFG_UL_MAILBOX_BYTES, + SOF_IPC4_FW_CFG_TRACE_LOG_BYTES, + SOF_IPC4_FW_CFG_MAX_PPL_COUNT, + SOF_IPC4_FW_CFG_MAX_ASTATE_COUNT, + SOF_IPC4_FW_CFG_MAX_MODULE_PIN_COUNT, + SOF_IPC4_FW_CFG_MODULES_COUNT, + SOF_IPC4_FW_CFG_MAX_MOD_INST_COUNT, + SOF_IPC4_FW_CFG_MAX_LL_TASKS_PER_PRI_COUNT, + SOF_IPC4_FW_CFG_LL_PRI_COUNT, + SOF_IPC4_FW_CFG_MAX_DP_TASKS_COUNT, + SOF_IPC4_FW_CFG_MAX_LIBS_COUNT, + SOF_IPC4_FW_CFG_SCHEDULER_CONFIG, + SOF_IPC4_FW_CFG_XTAL_FREQ_HZ, + SOF_IPC4_FW_CFG_CLOCKS_CONFIG, + SOF_IPC4_FW_CFG_RESERVED, + SOF_IPC4_FW_CFG_POWER_GATING_POLICY, + SOF_IPC4_FW_CFG_ASSERT_MODE, +}; + +struct sof_ipc4_fw_version { + uint16_t major; + uint16_t minor; + uint16_t hotfix; + uint16_t build; +} __packed; + +/* Payload data for SOF_IPC4_MOD_SET_DX */ +struct sof_ipc4_dx_state_info { + /* core(s) to apply the change */ + uint32_t core_mask; + /* core state: 0: put core_id to D3; 1: put core_id to D0 */ + uint32_t dx_mask; +} __packed __aligned(4); + +/* Reply messages */ + +/* + * IPC4 primary header bit allocation for replies + * bit 0-23: status + * bit 24-28: type: enum sof_ipc4_global_msg if target is SOF_IPC4_FW_GEN_MSG + * enum sof_ipc4_module_type if target is SOF_IPC4_MODULE_MSG + * bit 29: response - sof_ipc4_msg_dir + * bit 30: target - enum sof_ipc4_msg_target + * bit 31: reserved, unused + */ + +#define SOF_IPC4_REPLY_STATUS GENMASK(23, 0) + +/* Notification messages */ + +/* + * IPC4 primary header bit allocation for notifications + * bit 0-15: notification type specific + * bit 16-23: enum sof_ipc4_notification_type + * bit 24-28: SOF_IPC4_GLB_NOTIFICATION + * bit 29: response - sof_ipc4_msg_dir + * bit 30: target - enum sof_ipc4_msg_target + * bit 31: reserved, unused + */ + +#define SOF_IPC4_MSG_IS_NOTIFICATION(x) (SOF_IPC4_MSG_TYPE_GET(x) == \ + SOF_IPC4_GLB_NOTIFICATION) + +#define SOF_IPC4_NOTIFICATION_TYPE_SHIFT 16 +#define SOF_IPC4_NOTIFICATION_TYPE_MASK GENMASK(23, 16) +#define SOF_IPC4_NOTIFICATION_TYPE_GET(x) (((x) & SOF_IPC4_NOTIFICATION_TYPE_MASK) >> \ + SOF_IPC4_NOTIFICATION_TYPE_SHIFT) + +#define SOF_IPC4_LOG_CORE_SHIFT 12 +#define SOF_IPC4_LOG_CORE_MASK GENMASK(15, 12) +#define SOF_IPC4_LOG_CORE_GET(x) (((x) & SOF_IPC4_LOG_CORE_MASK) >> \ + SOF_IPC4_LOG_CORE_SHIFT) + +/* Value of notification type field - must fit into 8 bits */ +enum sof_ipc4_notification_type { + /* Phrase detected (notification from WoV module) */ + SOF_IPC4_NOTIFY_PHRASE_DETECTED = 4, + /* Event from a resource (pipeline or module instance) */ + SOF_IPC4_NOTIFY_RESOURCE_EVENT, + /* Debug log buffer status changed */ + SOF_IPC4_NOTIFY_LOG_BUFFER_STATUS, + /* Timestamp captured at the link */ + SOF_IPC4_NOTIFY_TIMESTAMP_CAPTURED, + /* FW complete initialization */ + SOF_IPC4_NOTIFY_FW_READY, + /* Audio classifier result (ACA) */ + SOF_IPC4_NOTIFY_FW_AUD_CLASS_RESULT, + /* Exception caught by DSP FW */ + SOF_IPC4_NOTIFY_EXCEPTION_CAUGHT, + /* 11 is skipped by the existing cavs firmware */ + /* Custom module notification */ + SOF_IPC4_NOTIFY_MODULE_NOTIFICATION = 12, + /* 13 is reserved - do not use */ + /* Probe notify data available */ + SOF_IPC4_NOTIFY_PROBE_DATA_AVAILABLE = 14, + /* AM module notifications */ + SOF_IPC4_NOTIFY_ASYNC_MSG_SRVC_MESSAGE, + + SOF_IPC4_NOTIFY_TYPE_LAST, +}; + +struct sof_ipc4_notify_resource_data { + uint32_t resource_type; + uint32_t resource_id; + uint32_t event_type; + uint32_t reserved; + uint32_t data[6]; +} __packed __aligned(4); + +/** @}*/ + +#endif diff --git a/include/sound/sof/pm.h b/include/sound/sof/pm.h new file mode 100644 index 000000000..366aa6ec4 --- /dev/null +++ b/include/sound/sof/pm.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation. All rights reserved. + */ + +#ifndef __INCLUDE_SOUND_SOF_PM_H__ +#define __INCLUDE_SOUND_SOF_PM_H__ + +#include <sound/sof/header.h> + +/* + * PM + */ + +/* PM context element */ +struct sof_ipc_pm_ctx_elem { + struct sof_ipc_hdr hdr; + uint32_t type; + uint32_t size; + uint64_t addr; +} __packed; + +/* + * PM context - SOF_IPC_PM_CTX_SAVE, SOF_IPC_PM_CTX_RESTORE, + * SOF_IPC_PM_CTX_SIZE + */ +struct sof_ipc_pm_ctx { + struct sof_ipc_cmd_hdr hdr; + struct sof_ipc_host_buffer buffer; + uint32_t num_elems; + uint32_t size; + + /* reserved for future use */ + uint32_t reserved[8]; + + struct sof_ipc_pm_ctx_elem elems[]; +} __packed; + +/* enable or disable cores - SOF_IPC_PM_CORE_ENABLE */ +struct sof_ipc_pm_core_config { + struct sof_ipc_cmd_hdr hdr; + uint32_t enable_mask; +} __packed; + +struct sof_ipc_pm_gate { + struct sof_ipc_cmd_hdr hdr; + uint32_t flags; /* platform specific */ + + /* reserved for future use */ + uint32_t reserved[5]; +} __packed; + +#endif diff --git a/include/sound/sof/stream.h b/include/sound/sof/stream.h new file mode 100644 index 000000000..9377113f1 --- /dev/null +++ b/include/sound/sof/stream.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation. All rights reserved. + */ + +#ifndef __INCLUDE_SOUND_SOF_STREAM_H__ +#define __INCLUDE_SOUND_SOF_STREAM_H__ + +#include <sound/sof/header.h> + +/* + * Stream configuration. + */ + +#define SOF_IPC_MAX_CHANNELS 8 + +/* common sample rates for use in masks */ +#define SOF_RATE_8000 (1 << 0) /**< 8000Hz */ +#define SOF_RATE_11025 (1 << 1) /**< 11025Hz */ +#define SOF_RATE_12000 (1 << 2) /**< 12000Hz */ +#define SOF_RATE_16000 (1 << 3) /**< 16000Hz */ +#define SOF_RATE_22050 (1 << 4) /**< 22050Hz */ +#define SOF_RATE_24000 (1 << 5) /**< 24000Hz */ +#define SOF_RATE_32000 (1 << 6) /**< 32000Hz */ +#define SOF_RATE_44100 (1 << 7) /**< 44100Hz */ +#define SOF_RATE_48000 (1 << 8) /**< 48000Hz */ +#define SOF_RATE_64000 (1 << 9) /**< 64000Hz */ +#define SOF_RATE_88200 (1 << 10) /**< 88200Hz */ +#define SOF_RATE_96000 (1 << 11) /**< 96000Hz */ +#define SOF_RATE_176400 (1 << 12) /**< 176400Hz */ +#define SOF_RATE_192000 (1 << 13) /**< 192000Hz */ + +/* continuous and non-standard rates for flexibility */ +#define SOF_RATE_CONTINUOUS (1 << 30) /**< range */ +#define SOF_RATE_KNOT (1 << 31) /**< non-continuous */ + +/* generic PCM flags for runtime settings */ +#define SOF_PCM_FLAG_XRUN_STOP (1 << 0) /**< Stop on any XRUN */ + +/* stream PCM frame format */ +enum sof_ipc_frame { + SOF_IPC_FRAME_S16_LE = 0, + SOF_IPC_FRAME_S24_4LE, + SOF_IPC_FRAME_S32_LE, + SOF_IPC_FRAME_FLOAT, + /* other formats here */ +}; + +/* stream buffer format */ +enum sof_ipc_buffer_format { + SOF_IPC_BUFFER_INTERLEAVED, + SOF_IPC_BUFFER_NONINTERLEAVED, + /* other formats here */ +}; + +/* stream direction */ +enum sof_ipc_stream_direction { + SOF_IPC_STREAM_PLAYBACK = 0, + SOF_IPC_STREAM_CAPTURE, +}; + +/* stream ring info */ +struct sof_ipc_host_buffer { + struct sof_ipc_hdr hdr; + uint32_t phy_addr; + uint32_t pages; + uint32_t size; + uint32_t reserved[3]; +} __packed; + +struct sof_ipc_stream_params { + struct sof_ipc_hdr hdr; + struct sof_ipc_host_buffer buffer; + uint32_t direction; /**< enum sof_ipc_stream_direction */ + uint32_t frame_fmt; /**< enum sof_ipc_frame */ + uint32_t buffer_fmt; /**< enum sof_ipc_buffer_format */ + uint32_t rate; + uint16_t stream_tag; + uint16_t channels; + uint16_t sample_valid_bytes; + uint16_t sample_container_bytes; + + uint32_t host_period_bytes; + uint16_t no_stream_position; /**< 1 means don't send stream position */ + uint8_t cont_update_posn; /**< 1 means continuous update stream position */ + uint8_t reserved0; + int16_t ext_data_length; /**< 0, means no extended data */ + uint8_t reserved[2]; + uint16_t chmap[SOF_IPC_MAX_CHANNELS]; /**< channel map - SOF_CHMAP_ */ + uint8_t ext_data[]; /**< extended data */ +} __packed; + +/* PCM params info - SOF_IPC_STREAM_PCM_PARAMS */ +struct sof_ipc_pcm_params { + struct sof_ipc_cmd_hdr hdr; + uint32_t comp_id; + uint32_t flags; /**< generic PCM flags - SOF_PCM_FLAG_ */ + uint32_t reserved[2]; + struct sof_ipc_stream_params params; +} __packed; + +/* PCM params info reply - SOF_IPC_STREAM_PCM_PARAMS_REPLY */ +struct sof_ipc_pcm_params_reply { + struct sof_ipc_reply rhdr; + uint32_t comp_id; + uint32_t posn_offset; +} __packed; + +/* free stream - SOF_IPC_STREAM_PCM_PARAMS */ +struct sof_ipc_stream { + struct sof_ipc_cmd_hdr hdr; + uint32_t comp_id; +} __packed; + +/* flags indicating which time stamps are in sync with each other */ +#define SOF_TIME_HOST_SYNC (1 << 0) +#define SOF_TIME_DAI_SYNC (1 << 1) +#define SOF_TIME_WALL_SYNC (1 << 2) +#define SOF_TIME_STAMP_SYNC (1 << 3) + +/* flags indicating which time stamps are valid */ +#define SOF_TIME_HOST_VALID (1 << 8) +#define SOF_TIME_DAI_VALID (1 << 9) +#define SOF_TIME_WALL_VALID (1 << 10) +#define SOF_TIME_STAMP_VALID (1 << 11) + +/* flags indicating time stamps are 64bit else 3use low 32bit */ +#define SOF_TIME_HOST_64 (1 << 16) +#define SOF_TIME_DAI_64 (1 << 17) +#define SOF_TIME_WALL_64 (1 << 18) +#define SOF_TIME_STAMP_64 (1 << 19) + +struct sof_ipc_stream_posn { + struct sof_ipc_reply rhdr; + uint32_t comp_id; /**< host component ID */ + uint32_t flags; /**< SOF_TIME_ */ + uint32_t wallclock_hz; /**< frequency of wallclock in Hz */ + uint32_t timestamp_ns; /**< resolution of timestamp in ns */ + uint64_t host_posn; /**< host DMA position in bytes */ + uint64_t dai_posn; /**< DAI DMA position in bytes */ + uint64_t comp_posn; /**< comp position in bytes */ + uint64_t wallclock; /**< audio wall clock */ + uint64_t timestamp; /**< system time stamp */ + uint32_t xrun_comp_id; /**< comp ID of XRUN component */ + int32_t xrun_size; /**< XRUN size in bytes */ +} __packed; + +#endif diff --git a/include/sound/sof/topology.h b/include/sound/sof/topology.h new file mode 100644 index 000000000..88560281d --- /dev/null +++ b/include/sound/sof/topology.h @@ -0,0 +1,303 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation. All rights reserved. + */ + +#ifndef __INCLUDE_SOUND_SOF_TOPOLOGY_H__ +#define __INCLUDE_SOUND_SOF_TOPOLOGY_H__ + +#include <sound/sof/header.h> + +/* + * Component + */ + +/* types of component */ +enum sof_comp_type { + SOF_COMP_NONE = 0, + SOF_COMP_HOST, + SOF_COMP_DAI, + SOF_COMP_SG_HOST, /**< scatter gather variant */ + SOF_COMP_SG_DAI, /**< scatter gather variant */ + SOF_COMP_VOLUME, + SOF_COMP_MIXER, + SOF_COMP_MUX, + SOF_COMP_SRC, + SOF_COMP_SPLITTER, + SOF_COMP_TONE, + SOF_COMP_SWITCH, + SOF_COMP_BUFFER, + SOF_COMP_EQ_IIR, + SOF_COMP_EQ_FIR, + SOF_COMP_KEYWORD_DETECT, + SOF_COMP_KPB, /* A key phrase buffer component */ + SOF_COMP_SELECTOR, /**< channel selector component */ + SOF_COMP_DEMUX, + SOF_COMP_ASRC, /**< Asynchronous sample rate converter */ + SOF_COMP_DCBLOCK, + SOF_COMP_SMART_AMP, /**< smart amplifier component */ + /* keep FILEREAD/FILEWRITE as the last ones */ + SOF_COMP_FILEREAD = 10000, /**< host test based file IO */ + SOF_COMP_FILEWRITE = 10001, /**< host test based file IO */ +}; + +/* XRUN action for component */ +#define SOF_XRUN_STOP 1 /**< stop stream */ +#define SOF_XRUN_UNDER_ZERO 2 /**< send 0s to sink */ +#define SOF_XRUN_OVER_NULL 4 /**< send data to NULL */ + +/* create new generic component - SOF_IPC_TPLG_COMP_NEW */ +struct sof_ipc_comp { + struct sof_ipc_cmd_hdr hdr; + uint32_t id; + enum sof_comp_type type; + uint32_t pipeline_id; + uint32_t core; + + /* extended data length, 0 if no extended data */ + uint32_t ext_data_length; +} __packed; + +/* + * Component Buffers + */ + +/* + * SOF memory capabilities, add new ones at the end + */ +#define SOF_MEM_CAPS_RAM (1 << 0) +#define SOF_MEM_CAPS_ROM (1 << 1) +#define SOF_MEM_CAPS_EXT (1 << 2) /**< external */ +#define SOF_MEM_CAPS_LP (1 << 3) /**< low power */ +#define SOF_MEM_CAPS_HP (1 << 4) /**< high performance */ +#define SOF_MEM_CAPS_DMA (1 << 5) /**< DMA'able */ +#define SOF_MEM_CAPS_CACHE (1 << 6) /**< cacheable */ +#define SOF_MEM_CAPS_EXEC (1 << 7) /**< executable */ + +/* + * overrun will cause ring buffer overwrite, instead of XRUN. + */ +#define SOF_BUF_OVERRUN_PERMITTED BIT(0) + +/* + * underrun will cause readback of 0s, instead of XRUN. + */ +#define SOF_BUF_UNDERRUN_PERMITTED BIT(1) + +/* create new component buffer - SOF_IPC_TPLG_BUFFER_NEW */ +struct sof_ipc_buffer { + struct sof_ipc_comp comp; + uint32_t size; /**< buffer size in bytes */ + uint32_t caps; /**< SOF_MEM_CAPS_ */ + uint32_t flags; /**< SOF_BUF_ flags defined above */ + uint32_t reserved; /**< reserved for future use */ +} __packed; + +/* generic component config data - must always be after struct sof_ipc_comp */ +struct sof_ipc_comp_config { + struct sof_ipc_cmd_hdr hdr; + uint32_t periods_sink; /**< 0 means variable */ + uint32_t periods_source;/**< 0 means variable */ + uint32_t reserved1; /**< reserved */ + uint32_t frame_fmt; /**< SOF_IPC_FRAME_ */ + uint32_t xrun_action; + + /* reserved for future use */ + uint32_t reserved[2]; +} __packed; + +/* generic host component */ +struct sof_ipc_comp_host { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; + uint32_t direction; /**< SOF_IPC_STREAM_ */ + uint32_t no_irq; /**< don't send periodic IRQ to host/DSP */ + uint32_t dmac_config; /**< DMA engine specific */ +} __packed; + +/* generic DAI component */ +struct sof_ipc_comp_dai { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; + uint32_t direction; /**< SOF_IPC_STREAM_ */ + uint32_t dai_index; /**< index of this type dai */ + uint32_t type; /**< DAI type - SOF_DAI_ */ + uint32_t reserved; /**< reserved */ +} __packed; + +/* generic mixer component */ +struct sof_ipc_comp_mixer { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; +} __packed; + +/* volume ramping types */ +enum sof_volume_ramp { + SOF_VOLUME_LINEAR = 0, + SOF_VOLUME_LOG, + SOF_VOLUME_LINEAR_ZC, + SOF_VOLUME_LOG_ZC, +}; + +/* generic volume component */ +struct sof_ipc_comp_volume { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; + uint32_t channels; + uint32_t min_value; + uint32_t max_value; + uint32_t ramp; /**< SOF_VOLUME_ */ + uint32_t initial_ramp; /**< ramp space in ms */ +} __packed; + +/* generic SRC component */ +struct sof_ipc_comp_src { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; + /* either source or sink rate must be non zero */ + uint32_t source_rate; /**< source rate or 0 for variable */ + uint32_t sink_rate; /**< sink rate or 0 for variable */ + uint32_t rate_mask; /**< SOF_RATE_ supported rates */ +} __packed; + +/* generic ASRC component */ +struct sof_ipc_comp_asrc { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; + /* either source or sink rate must be non zero */ + uint32_t source_rate; /**< Define fixed source rate or */ + /**< use 0 to indicate need to get */ + /**< the rate from stream */ + uint32_t sink_rate; /**< Define fixed sink rate or */ + /**< use 0 to indicate need to get */ + /**< the rate from stream */ + uint32_t asynchronous_mode; /**< synchronous 0, asynchronous 1 */ + /**< When 1 the ASRC tracks and */ + /**< compensates for drift. */ + uint32_t operation_mode; /**< push 0, pull 1, In push mode the */ + /**< ASRC consumes a defined number */ + /**< of frames at input, with varying */ + /**< number of frames at output. */ + /**< In pull mode the ASRC outputs */ + /**< a defined number of frames while */ + /**< number of input frames varies. */ + + /* reserved for future use */ + uint32_t reserved[4]; +} __attribute__((packed)); + +/* generic MUX component */ +struct sof_ipc_comp_mux { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; +} __packed; + +/* generic tone generator component */ +struct sof_ipc_comp_tone { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; + int32_t sample_rate; + int32_t frequency; + int32_t amplitude; + int32_t freq_mult; + int32_t ampl_mult; + int32_t length; + int32_t period; + int32_t repeats; + int32_t ramp_step; +} __packed; + +/** \brief Types of processing components */ +enum sof_ipc_process_type { + SOF_PROCESS_NONE = 0, /**< None */ + SOF_PROCESS_EQFIR, /**< Intel FIR */ + SOF_PROCESS_EQIIR, /**< Intel IIR */ + SOF_PROCESS_KEYWORD_DETECT, /**< Keyword Detection */ + SOF_PROCESS_KPB, /**< KeyPhrase Buffer Manager */ + SOF_PROCESS_CHAN_SELECTOR, /**< Channel Selector */ + SOF_PROCESS_MUX, + SOF_PROCESS_DEMUX, + SOF_PROCESS_DCBLOCK, + SOF_PROCESS_SMART_AMP, /**< Smart Amplifier */ +}; + +/* generic "effect", "codec" or proprietary processing component */ +struct sof_ipc_comp_process { + struct sof_ipc_comp comp; + struct sof_ipc_comp_config config; + uint32_t size; /**< size of bespoke data section in bytes */ + uint32_t type; /**< sof_ipc_process_type */ + + /* reserved for future use */ + uint32_t reserved[7]; + + uint8_t data[]; +} __packed; + +/* frees components, buffers and pipelines + * SOF_IPC_TPLG_COMP_FREE, SOF_IPC_TPLG_PIPE_FREE, SOF_IPC_TPLG_BUFFER_FREE + */ +struct sof_ipc_free { + struct sof_ipc_cmd_hdr hdr; + uint32_t id; +} __packed; + +struct sof_ipc_comp_reply { + struct sof_ipc_reply rhdr; + uint32_t id; + uint32_t offset; +} __packed; + +/* + * Pipeline + */ + +/** \brief Types of pipeline scheduling time domains */ +enum sof_ipc_pipe_sched_time_domain { + SOF_TIME_DOMAIN_DMA = 0, /**< DMA interrupt */ + SOF_TIME_DOMAIN_TIMER, /**< Timer interrupt */ +}; + +/* new pipeline - SOF_IPC_TPLG_PIPE_NEW */ +struct sof_ipc_pipe_new { + struct sof_ipc_cmd_hdr hdr; + uint32_t comp_id; /**< component id for pipeline */ + uint32_t pipeline_id; /**< pipeline id */ + uint32_t sched_id; /**< Scheduling component id */ + uint32_t core; /**< core we run on */ + uint32_t period; /**< execution period in us*/ + uint32_t priority; /**< priority level 0 (low) to 10 (max) */ + uint32_t period_mips; /**< worst case instruction count per period */ + uint32_t frames_per_sched;/**< output frames of pipeline, 0 is variable */ + uint32_t xrun_limit_usecs; /**< report xruns greater than limit */ + uint32_t time_domain; /**< scheduling time domain */ +} __packed; + +/* pipeline construction complete - SOF_IPC_TPLG_PIPE_COMPLETE */ +struct sof_ipc_pipe_ready { + struct sof_ipc_cmd_hdr hdr; + uint32_t comp_id; +} __packed; + +struct sof_ipc_pipe_free { + struct sof_ipc_cmd_hdr hdr; + uint32_t comp_id; +} __packed; + +/* connect two components in pipeline - SOF_IPC_TPLG_COMP_CONNECT */ +struct sof_ipc_pipe_comp_connect { + struct sof_ipc_cmd_hdr hdr; + uint32_t source_id; + uint32_t sink_id; +} __packed; + +/* external events */ +enum sof_event_types { + SOF_EVENT_NONE = 0, + SOF_KEYWORD_DETECT_DAPM_EVENT, +}; + +#endif diff --git a/include/sound/sof/trace.h b/include/sound/sof/trace.h new file mode 100644 index 000000000..25ea99f62 --- /dev/null +++ b/include/sound/sof/trace.h @@ -0,0 +1,107 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation. All rights reserved. + */ + +#ifndef __INCLUDE_SOUND_SOF_TRACE_H__ +#define __INCLUDE_SOUND_SOF_TRACE_H__ + +#include <sound/sof/header.h> +#include <sound/sof/stream.h> + +/* + * DMA for Trace + */ + +#define SOF_TRACE_FILENAME_SIZE 32 + +/* DMA for Trace params info - SOF_IPC_DEBUG_DMA_PARAMS */ +/* Deprecated - use sof_ipc_dma_trace_params_ext */ +struct sof_ipc_dma_trace_params { + struct sof_ipc_cmd_hdr hdr; + struct sof_ipc_host_buffer buffer; + uint32_t stream_tag; +} __packed; + +/* DMA for Trace params info - SOF_IPC_DEBUG_DMA_PARAMS_EXT */ +struct sof_ipc_dma_trace_params_ext { + struct sof_ipc_cmd_hdr hdr; + struct sof_ipc_host_buffer buffer; + uint32_t stream_tag; + uint64_t timestamp_ns; /* in nanosecond */ + uint32_t reserved[8]; +} __packed; + +/* DMA for Trace params info - SOF_IPC_DEBUG_DMA_PARAMS */ +struct sof_ipc_dma_trace_posn { + struct sof_ipc_reply rhdr; + uint32_t host_offset; /* Offset of DMA host buffer */ + uint32_t overflow; /* overflow bytes if any */ + uint32_t messages; /* total trace messages */ +} __packed; + +/* Values used in sof_ipc_trace_filter_elem: */ + +/* bits 6..0 */ +#define SOF_IPC_TRACE_FILTER_ELEM_SET_LEVEL 0x01 /**< trace level for selected components */ +#define SOF_IPC_TRACE_FILTER_ELEM_BY_UUID 0x02 /**< filter by uuid key */ +#define SOF_IPC_TRACE_FILTER_ELEM_BY_PIPE 0x03 /**< filter by pipeline */ +#define SOF_IPC_TRACE_FILTER_ELEM_BY_COMP 0x04 /**< filter by component id */ + +/* bit 7 */ +#define SOF_IPC_TRACE_FILTER_ELEM_FIN 0x80 /**< mark last filter in set */ + +/* bits 31..8: Unused */ + +/** part of sof_ipc_trace_filter, ABI3.17 */ +struct sof_ipc_trace_filter_elem { + uint32_t key; /**< SOF_IPC_TRACE_FILTER_ELEM_ {LEVEL, UUID, COMP, PIPE} */ + uint32_t value; /**< element value */ +} __packed; + +/** Runtime tracing filtration data - SOF_IPC_TRACE_FILTER_UPDATE, ABI3.17 */ +struct sof_ipc_trace_filter { + struct sof_ipc_cmd_hdr hdr; /**< IPC command header */ + uint32_t elem_cnt; /**< number of entries in elems[] array */ + uint32_t reserved[8]; /**< reserved for future usage */ + /** variable size array with new filtering settings */ + struct sof_ipc_trace_filter_elem elems[]; +} __packed; + +/* + * Commom debug + */ + +/* + * SOF panic codes + */ +#define SOF_IPC_PANIC_MAGIC 0x0dead000 +#define SOF_IPC_PANIC_MAGIC_MASK 0x0ffff000 +#define SOF_IPC_PANIC_CODE_MASK 0x00000fff +#define SOF_IPC_PANIC_MEM (SOF_IPC_PANIC_MAGIC | 0x0) +#define SOF_IPC_PANIC_WORK (SOF_IPC_PANIC_MAGIC | 0x1) +#define SOF_IPC_PANIC_IPC (SOF_IPC_PANIC_MAGIC | 0x2) +#define SOF_IPC_PANIC_ARCH (SOF_IPC_PANIC_MAGIC | 0x3) +#define SOF_IPC_PANIC_PLATFORM (SOF_IPC_PANIC_MAGIC | 0x4) +#define SOF_IPC_PANIC_TASK (SOF_IPC_PANIC_MAGIC | 0x5) +#define SOF_IPC_PANIC_EXCEPTION (SOF_IPC_PANIC_MAGIC | 0x6) +#define SOF_IPC_PANIC_DEADLOCK (SOF_IPC_PANIC_MAGIC | 0x7) +#define SOF_IPC_PANIC_STACK (SOF_IPC_PANIC_MAGIC | 0x8) +#define SOF_IPC_PANIC_IDLE (SOF_IPC_PANIC_MAGIC | 0x9) +#define SOF_IPC_PANIC_WFI (SOF_IPC_PANIC_MAGIC | 0xa) +#define SOF_IPC_PANIC_ASSERT (SOF_IPC_PANIC_MAGIC | 0xb) + +/* panic info include filename and line number + * filename array will not include null terminator if fully filled + */ +struct sof_ipc_panic_info { + struct sof_ipc_hdr hdr; + uint32_t code; /* SOF_IPC_PANIC_ */ + uint8_t filename[SOF_TRACE_FILENAME_SIZE]; + uint32_t linenum; +} __packed; + +#endif diff --git a/include/sound/sof/xtensa.h b/include/sound/sof/xtensa.h new file mode 100644 index 000000000..87a07e520 --- /dev/null +++ b/include/sound/sof/xtensa.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ +/* + * This file is provided under a dual BSD/GPLv2 license. When using or + * redistributing this file, you may do so under either license. + * + * Copyright(c) 2018 Intel Corporation. All rights reserved. + */ + +#ifndef __INCLUDE_SOUND_SOF_XTENSA_H__ +#define __INCLUDE_SOUND_SOF_XTENSA_H__ + +#include <sound/sof/header.h> + +/* + * Architecture specific debug + */ + +/* Xtensa Firmware Oops data */ +struct sof_ipc_dsp_oops_xtensa { + struct sof_ipc_dsp_oops_arch_hdr arch_hdr; + struct sof_ipc_dsp_oops_plat_hdr plat_hdr; + uint32_t exccause; + uint32_t excvaddr; + uint32_t ps; + uint32_t epc1; + uint32_t epc2; + uint32_t epc3; + uint32_t epc4; + uint32_t epc5; + uint32_t epc6; + uint32_t epc7; + uint32_t eps2; + uint32_t eps3; + uint32_t eps4; + uint32_t eps5; + uint32_t eps6; + uint32_t eps7; + uint32_t depc; + uint32_t intenable; + uint32_t interrupt; + uint32_t sar; + uint32_t debugcause; + uint32_t windowbase; + uint32_t windowstart; + uint32_t excsave1; + uint32_t ar[]; +} __packed; + +#endif diff --git a/include/sound/soundfont.h b/include/sound/soundfont.h new file mode 100644 index 000000000..e445688a4 --- /dev/null +++ b/include/sound/soundfont.h @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_SOUNDFONT_H +#define __SOUND_SOUNDFONT_H + +/* + * Soundfont defines and definitions. + * + * Copyright (C) 1999 Steve Ratcliffe + * Copyright (c) 1999-2000 Takashi iwai <tiwai@suse.de> + */ + +#include <sound/sfnt_info.h> +#include <sound/util_mem.h> + +#define SF_MAX_INSTRUMENTS 128 /* maximum instrument number */ +#define SF_MAX_PRESETS 256 /* drums are mapped from 128 to 256 */ +#define SF_IS_DRUM_BANK(z) ((z) == 128) + +struct snd_sf_zone { + struct snd_sf_zone *next; /* Link to next */ + unsigned char bank; /* Midi bank for this zone */ + unsigned char instr; /* Midi program for this zone */ + unsigned char mapped; /* True if mapped to something else */ + + struct soundfont_voice_info v; /* All the soundfont parameters */ + int counter; + struct snd_sf_sample *sample; /* Link to sample */ + + /* The following deals with preset numbers (programs) */ + struct snd_sf_zone *next_instr; /* Next zone of this instrument */ + struct snd_sf_zone *next_zone; /* Next zone in play list */ +}; + +struct snd_sf_sample { + struct soundfont_sample_info v; + int counter; + struct snd_util_memblk *block; /* allocated data block */ + struct snd_sf_sample *next; +}; + +/* + * This represents all the information relating to a soundfont. + */ +struct snd_soundfont { + struct snd_soundfont *next; /* Link to next */ + /*struct snd_soundfont *prev;*/ /* Link to previous */ + short id; /* file id */ + short type; /* font type */ + unsigned char name[SNDRV_SFNT_PATCH_NAME_LEN]; /* identifier */ + struct snd_sf_zone *zones; /* Font information */ + struct snd_sf_sample *samples; /* The sample headers */ +}; + +/* + * Type of the sample access callback + */ +struct snd_sf_callback { + void *private_data; + int (*sample_new)(void *private_data, struct snd_sf_sample *sp, + struct snd_util_memhdr *hdr, + const void __user *buf, long count); + int (*sample_free)(void *private_data, struct snd_sf_sample *sp, + struct snd_util_memhdr *hdr); + void (*sample_reset)(void *private); +}; + +/* + * List of soundfonts. + */ +struct snd_sf_list { + struct snd_soundfont *currsf; /* The currently open soundfont */ + int open_client; /* client pointer for lock */ + int mem_used; /* used memory size */ + struct snd_sf_zone *presets[SF_MAX_PRESETS]; + struct snd_soundfont *fonts; /* The list of soundfonts */ + int fonts_size; /* number of fonts allocated */ + int zone_counter; /* last allocated time for zone */ + int sample_counter; /* last allocated time for sample */ + int zone_locked; /* locked time for zone */ + int sample_locked; /* locked time for sample */ + struct snd_sf_callback callback; /* callback functions */ + int presets_locked; + struct mutex presets_mutex; + spinlock_t lock; + struct snd_util_memhdr *memhdr; +}; + +/* Prototypes for soundfont.c */ +int snd_soundfont_load(struct snd_sf_list *sflist, const void __user *data, + long count, int client); +int snd_soundfont_load_guspatch(struct snd_sf_list *sflist, const char __user *data, + long count, int client); +int snd_soundfont_close_check(struct snd_sf_list *sflist, int client); + +struct snd_sf_list *snd_sf_new(struct snd_sf_callback *callback, + struct snd_util_memhdr *hdr); +void snd_sf_free(struct snd_sf_list *sflist); + +int snd_soundfont_remove_samples(struct snd_sf_list *sflist); +int snd_soundfont_remove_unlocked(struct snd_sf_list *sflist); + +int snd_soundfont_search_zone(struct snd_sf_list *sflist, int *notep, int vel, + int preset, int bank, + int def_preset, int def_bank, + struct snd_sf_zone **table, int max_layers); + +/* Parameter conversions */ +int snd_sf_calc_parm_hold(int msec); +int snd_sf_calc_parm_attack(int msec); +int snd_sf_calc_parm_decay(int msec); +#define snd_sf_calc_parm_delay(msec) (0x8000 - (msec) * 1000 / 725) +extern int snd_sf_vol_table[128]; +int snd_sf_linear_to_log(unsigned int amount, int offset, int ratio); + + +#endif /* __SOUND_SOUNDFONT_H */ diff --git a/include/sound/spear_dma.h b/include/sound/spear_dma.h new file mode 100644 index 000000000..0269a07b8 --- /dev/null +++ b/include/sound/spear_dma.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* +* linux/spear_dma.h +* +* Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com) +*/ + +#ifndef SPEAR_DMA_H +#define SPEAR_DMA_H + +#include <linux/dmaengine.h> + +struct spear_dma_data { + void *data; + dma_addr_t addr; + u32 max_burst; + enum dma_slave_buswidth addr_width; +}; + +#endif /* SPEAR_DMA_H */ diff --git a/include/sound/spear_spdif.h b/include/sound/spear_spdif.h new file mode 100644 index 000000000..f52f5268c --- /dev/null +++ b/include/sound/spear_spdif.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (ST) 2012 Vipin Kumar (vipin.kumar@st.com) + */ + +#ifndef __SOUND_SPDIF_H +#define __SOUND_SPDIF_H + +struct spear_spdif_platform_data { + /* DMA params */ + void *dma_params; + bool (*filter)(struct dma_chan *chan, void *slave); + void (*reset_perip)(void); +}; + +#endif /* SOUND_SPDIF_H */ diff --git a/include/sound/sta32x.h b/include/sound/sta32x.h new file mode 100644 index 000000000..600494251 --- /dev/null +++ b/include/sound/sta32x.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Platform data for ST STA32x ASoC codec driver. + * + * Copyright: 2011 Raumfeld GmbH + * Author: Johannes Stezenbach <js@sig21.net> + */ +#ifndef __LINUX_SND__STA32X_H +#define __LINUX_SND__STA32X_H + +#define STA32X_OCFG_2CH 0 +#define STA32X_OCFG_2_1CH 1 +#define STA32X_OCFG_1CH 3 + +#define STA32X_OM_CH1 0 +#define STA32X_OM_CH2 1 +#define STA32X_OM_CH3 2 + +#define STA32X_THERMAL_ADJUSTMENT_ENABLE 1 +#define STA32X_THERMAL_RECOVERY_ENABLE 2 + +struct sta32x_platform_data { + u8 output_conf; + u8 ch1_output_mapping; + u8 ch2_output_mapping; + u8 ch3_output_mapping; + int needs_esd_watchdog; + u8 drop_compensation_ns; + unsigned int thermal_warning_recovery:1; + unsigned int thermal_warning_adjustment:1; + unsigned int fault_detect_recovery:1; + unsigned int max_power_use_mpcc:1; + unsigned int max_power_correction:1; + unsigned int am_reduction_mode:1; + unsigned int odd_pwm_speed_mode:1; + unsigned int invalid_input_detect_mute:1; +}; + +#endif /* __LINUX_SND__STA32X_H */ diff --git a/include/sound/sta350.h b/include/sound/sta350.h new file mode 100644 index 000000000..2d9170484 --- /dev/null +++ b/include/sound/sta350.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Platform data for ST STA350 ASoC codec driver. + * + * Copyright: 2014 Raumfeld GmbH + * Author: Sven Brandau <info@brandau.biz> + */ +#ifndef __LINUX_SND__STA350_H +#define __LINUX_SND__STA350_H + +#define STA350_OCFG_2CH 0 +#define STA350_OCFG_2_1CH 1 +#define STA350_OCFG_1CH 3 + +#define STA350_OM_CH1 0 +#define STA350_OM_CH2 1 +#define STA350_OM_CH3 2 + +#define STA350_THERMAL_ADJUSTMENT_ENABLE 1 +#define STA350_THERMAL_RECOVERY_ENABLE 2 +#define STA350_FAULT_DETECT_RECOVERY_BYPASS 1 + +#define STA350_FFX_PM_DROP_COMP 0 +#define STA350_FFX_PM_TAPERED_COMP 1 +#define STA350_FFX_PM_FULL_POWER 2 +#define STA350_FFX_PM_VARIABLE_DROP_COMP 3 + + +struct sta350_platform_data { + u8 output_conf; + u8 ch1_output_mapping; + u8 ch2_output_mapping; + u8 ch3_output_mapping; + u8 ffx_power_output_mode; + u8 drop_compensation_ns; + u8 powerdown_delay_divider; + unsigned int thermal_warning_recovery:1; + unsigned int thermal_warning_adjustment:1; + unsigned int fault_detect_recovery:1; + unsigned int oc_warning_adjustment:1; + unsigned int max_power_use_mpcc:1; + unsigned int max_power_correction:1; + unsigned int am_reduction_mode:1; + unsigned int odd_pwm_speed_mode:1; + unsigned int distortion_compensation:1; + unsigned int invalid_input_detect_mute:1; + unsigned int activate_mute_output:1; + unsigned int bridge_immediate_off:1; + unsigned int noise_shape_dc_cut:1; + unsigned int powerdown_master_vol:1; +}; + +#endif /* __LINUX_SND__STA350_H */ diff --git a/include/sound/tas2552-plat.h b/include/sound/tas2552-plat.h new file mode 100644 index 000000000..6f087b22f --- /dev/null +++ b/include/sound/tas2552-plat.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * TAS2552 driver platform header + * + * Copyright (C) 2014 Texas Instruments Inc. + * + * Author: Dan Murphy <dmurphy@ti.com> + */ + +#ifndef TAS2552_PLAT_H +#define TAS2552_PLAT_H + +struct tas2552_platform_data { + int enable_gpio; +}; + +#endif diff --git a/include/sound/tas5086.h b/include/sound/tas5086.h new file mode 100644 index 000000000..a0a1c380f --- /dev/null +++ b/include/sound/tas5086.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _SND_SOC_CODEC_TAS5086_H_ +#define _SND_SOC_CODEC_TAS5086_H_ + +#define TAS5086_CLK_IDX_MCLK 0 +#define TAS5086_CLK_IDX_SCLK 1 + +#endif /* _SND_SOC_CODEC_TAS5086_H_ */ diff --git a/include/sound/tea6330t.h b/include/sound/tea6330t.h new file mode 100644 index 000000000..1c77b78f6 --- /dev/null +++ b/include/sound/tea6330t.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_TEA6330T_H +#define __SOUND_TEA6330T_H + +/* + * Routines for control of TEA6330T circuit. + * Sound fader control circuit for car radios. + */ + +#include <sound/i2c.h> /* generic i2c support */ + +int snd_tea6330t_detect(struct snd_i2c_bus *bus, int equalizer); +int snd_tea6330t_update_mixer(struct snd_card *card, struct snd_i2c_bus *bus, + int equalizer, int fader); + +#endif /* __SOUND_TEA6330T_H */ diff --git a/include/sound/timer.h b/include/sound/timer.h new file mode 100644 index 000000000..760e132cc --- /dev/null +++ b/include/sound/timer.h @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_TIMER_H +#define __SOUND_TIMER_H + +/* + * Timer abstract layer + * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, + * Abramo Bagnara <abramo@alsa-project.org> + */ + +#include <sound/asound.h> +#include <linux/interrupt.h> + +#define snd_timer_chip(timer) ((timer)->private_data) + +#define SNDRV_TIMER_DEVICES 16 + +#define SNDRV_TIMER_DEV_FLG_PCM 0x10000000 + +#define SNDRV_TIMER_HW_AUTO 0x00000001 /* auto trigger is supported */ +#define SNDRV_TIMER_HW_STOP 0x00000002 /* call stop before start */ +#define SNDRV_TIMER_HW_SLAVE 0x00000004 /* only slave timer (variable resolution) */ +#define SNDRV_TIMER_HW_FIRST 0x00000008 /* first tick can be incomplete */ +#define SNDRV_TIMER_HW_WORK 0x00000010 /* timer is called from work */ + +#define SNDRV_TIMER_IFLG_SLAVE 0x00000001 +#define SNDRV_TIMER_IFLG_RUNNING 0x00000002 +#define SNDRV_TIMER_IFLG_START 0x00000004 +#define SNDRV_TIMER_IFLG_AUTO 0x00000008 /* auto restart */ +#define SNDRV_TIMER_IFLG_FAST 0x00000010 /* fast callback (do not use work) */ +#define SNDRV_TIMER_IFLG_CALLBACK 0x00000020 /* timer callback is active */ +#define SNDRV_TIMER_IFLG_EXCLUSIVE 0x00000040 /* exclusive owner - no more instances */ +#define SNDRV_TIMER_IFLG_EARLY_EVENT 0x00000080 /* write early event to the poll queue */ + +#define SNDRV_TIMER_FLG_CHANGE 0x00000001 +#define SNDRV_TIMER_FLG_RESCHED 0x00000002 /* need reschedule */ + +struct snd_timer; + +struct snd_timer_hardware { + /* -- must be filled with low-level driver */ + unsigned int flags; /* various flags */ + unsigned long resolution; /* average timer resolution for one tick in nsec */ + unsigned long resolution_min; /* minimal resolution */ + unsigned long resolution_max; /* maximal resolution */ + unsigned long ticks; /* max timer ticks per interrupt */ + /* -- low-level functions -- */ + int (*open) (struct snd_timer * timer); + int (*close) (struct snd_timer * timer); + unsigned long (*c_resolution) (struct snd_timer * timer); + int (*start) (struct snd_timer * timer); + int (*stop) (struct snd_timer * timer); + int (*set_period) (struct snd_timer * timer, unsigned long period_num, unsigned long period_den); + int (*precise_resolution) (struct snd_timer * timer, unsigned long *num, unsigned long *den); +}; + +struct snd_timer { + int tmr_class; + struct snd_card *card; + struct module *module; + int tmr_device; + int tmr_subdevice; + char id[64]; + char name[80]; + unsigned int flags; + int running; /* running instances */ + unsigned long sticks; /* schedule ticks */ + void *private_data; + void (*private_free) (struct snd_timer *timer); + struct snd_timer_hardware hw; + spinlock_t lock; + struct list_head device_list; + struct list_head open_list_head; + struct list_head active_list_head; + struct list_head ack_list_head; + struct list_head sack_list_head; /* slow ack list head */ + struct work_struct task_work; + int max_instances; /* upper limit of timer instances */ + int num_instances; /* current number of timer instances */ +}; + +struct snd_timer_instance { + struct snd_timer *timer; + char *owner; + unsigned int flags; + void *private_data; + void (*private_free) (struct snd_timer_instance *ti); + void (*callback) (struct snd_timer_instance *timeri, + unsigned long ticks, unsigned long resolution); + void (*ccallback) (struct snd_timer_instance * timeri, + int event, + struct timespec64 * tstamp, + unsigned long resolution); + void (*disconnect)(struct snd_timer_instance *timeri); + void *callback_data; + unsigned long ticks; /* auto-load ticks when expired */ + unsigned long cticks; /* current ticks */ + unsigned long pticks; /* accumulated ticks for callback */ + unsigned long resolution; /* current resolution for work */ + unsigned long lost; /* lost ticks */ + int slave_class; + unsigned int slave_id; + struct list_head open_list; + struct list_head active_list; + struct list_head ack_list; + struct list_head slave_list_head; + struct list_head slave_active_head; + struct snd_timer_instance *master; +}; + +/* + * Registering + */ + +int snd_timer_new(struct snd_card *card, char *id, struct snd_timer_id *tid, struct snd_timer **rtimer); +void snd_timer_notify(struct snd_timer *timer, int event, struct timespec64 *tstamp); +int snd_timer_global_new(char *id, int device, struct snd_timer **rtimer); +int snd_timer_global_free(struct snd_timer *timer); +int snd_timer_global_register(struct snd_timer *timer); + +struct snd_timer_instance *snd_timer_instance_new(const char *owner); +void snd_timer_instance_free(struct snd_timer_instance *timeri); +int snd_timer_open(struct snd_timer_instance *timeri, struct snd_timer_id *tid, unsigned int slave_id); +void snd_timer_close(struct snd_timer_instance *timeri); +unsigned long snd_timer_resolution(struct snd_timer_instance *timeri); +int snd_timer_start(struct snd_timer_instance *timeri, unsigned int ticks); +int snd_timer_stop(struct snd_timer_instance *timeri); +int snd_timer_continue(struct snd_timer_instance *timeri); +int snd_timer_pause(struct snd_timer_instance *timeri); + +void snd_timer_interrupt(struct snd_timer *timer, unsigned long ticks_left); + +#endif /* __SOUND_TIMER_H */ diff --git a/include/sound/tlv.h b/include/sound/tlv.h new file mode 100644 index 000000000..5cff33a2d --- /dev/null +++ b/include/sound/tlv.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_TLV_H +#define __SOUND_TLV_H + +/* + * Advanced Linux Sound Architecture - ALSA - Driver + * Copyright (c) 2006 by Jaroslav Kysela <perex@perex.cz> + */ + +#include <uapi/sound/tlv.h> + +/* For historical reasons, these macros are aliases to the ones in UAPI. */ +#define TLV_ITEM SNDRV_CTL_TLVD_ITEM +#define TLV_LENGTH SNDRV_CTL_TLVD_LENGTH + +#define TLV_CONTAINER_ITEM SNDRV_CTL_TLVD_CONTAINER_ITEM +#define DECLARE_TLV_CONTAINER SNDRV_CTL_TLVD_DECLARE_CONTAINER + +#define TLV_DB_SCALE_MASK SNDRV_CTL_TLVD_DB_SCALE_MASK +#define TLV_DB_SCALE_MUTE SNDRV_CTL_TLVD_DB_SCALE_MUTE +#define TLV_DB_SCALE_ITEM SNDRV_CTL_TLVD_DB_SCALE_ITEM +#define DECLARE_TLV_DB_SCALE SNDRV_CTL_TLVD_DECLARE_DB_SCALE + +#define TLV_DB_MINMAX_ITEM SNDRV_CTL_TLVD_DB_MINMAX_ITEM +#define TLV_DB_MINMAX_MUTE_ITEM SNDRV_CTL_TLVD_DB_MINMAX_MUTE_ITEM +#define DECLARE_TLV_DB_MINMAX SNDRV_CTL_TLVD_DECLARE_DB_MINMAX +#define DECLARE_TLV_DB_MINMAX_MUTE SNDRV_CTL_TLVD_DECLARE_DB_MINMAX_MUTE + +#define TLV_DB_LINEAR_ITEM SNDRV_CTL_TLVD_DB_LINEAR_ITEM +#define DECLARE_TLV_DB_LINEAR SNDRV_CTL_TLVD_DECLARE_DB_LINEAR + +#define TLV_DB_RANGE_ITEM SNDRV_CTL_TLVD_DB_RANGE_ITEM +#define DECLARE_TLV_DB_RANGE SNDRV_CTL_TLVD_DECLARE_DB_RANGE + +#define TLV_DB_GAIN_MUTE SNDRV_CTL_TLVD_DB_GAIN_MUTE + +/* + * The below assumes that each item TLV is 4 words like DB_SCALE or LINEAR. + * This is an old fasion and obsoleted by commit bf1d1c9b6179("ALSA: tlv: add + * DECLARE_TLV_DB_RANGE()"). + */ +#define TLV_DB_RANGE_HEAD(num) \ + SNDRV_CTL_TLVT_DB_RANGE, 6 * (num) * sizeof(unsigned int) + +#endif /* __SOUND_TLV_H */ diff --git a/include/sound/tlv320aic32x4.h b/include/sound/tlv320aic32x4.h new file mode 100644 index 000000000..0abf74d7e --- /dev/null +++ b/include/sound/tlv320aic32x4.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * tlv320aic32x4.h -- TLV320AIC32X4 Soc Audio driver platform data + * + * Copyright 2011 Vista Silicon S.L. + * + * Author: Javier Martin <javier.martin@vista-silicon.com> + */ + +#ifndef _AIC32X4_PDATA_H +#define _AIC32X4_PDATA_H + +#define AIC32X4_PWR_MICBIAS_2075_LDOIN 0x00000001 +#define AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE 0x00000002 +#define AIC32X4_PWR_AIC32X4_LDO_ENABLE 0x00000004 +#define AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36 0x00000008 +#define AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED 0x00000010 + +#define AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K 0x00000001 +#define AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K 0x00000002 + +/* GPIO API */ +#define AIC32X4_MFPX_DEFAULT_VALUE 0xff + +#define AIC32X4_MFP1_DIN_DISABLED 0 +#define AIC32X4_MFP1_DIN_ENABLED 0x2 +#define AIC32X4_MFP1_GPIO_IN 0x4 + +#define AIC32X4_MFP2_GPIO_OUT_LOW 0x0 +#define AIC32X4_MFP2_GPIO_OUT_HIGH 0x1 + +#define AIC32X4_MFP_GPIO_ENABLED 0x4 + +#define AIC32X4_MFP5_GPIO_DISABLED 0x0 +#define AIC32X4_MFP5_GPIO_INPUT 0x8 +#define AIC32X4_MFP5_GPIO_OUTPUT 0xc +#define AIC32X4_MFP5_GPIO_OUT_LOW 0x0 +#define AIC32X4_MFP5_GPIO_OUT_HIGH 0x1 + +struct aic32x4_setup_data { + unsigned int gpio_func[5]; +}; + +struct aic32x4_pdata { + struct aic32x4_setup_data *setup; + u32 power_cfg; + u32 micpga_routing; + bool swapdacs; + int rstn_gpio; +}; + +#endif diff --git a/include/sound/tlv320aic3x.h b/include/sound/tlv320aic3x.h new file mode 100644 index 000000000..b660a9ed0 --- /dev/null +++ b/include/sound/tlv320aic3x.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Platform data for Texas Instruments TLV320AIC3x codec + * + * Author: Jarkko Nikula <jarkko.nikula@bitmer.com> + */ +#ifndef __TLV320AIC3x_H__ +#define __TLV320AIC3x_H__ + +/* GPIO API */ +enum { + AIC3X_GPIO1_FUNC_DISABLED = 0, + AIC3X_GPIO1_FUNC_AUDIO_WORDCLK_ADC = 1, + AIC3X_GPIO1_FUNC_CLOCK_MUX = 2, + AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV2 = 3, + AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV4 = 4, + AIC3X_GPIO1_FUNC_CLOCK_MUX_DIV8 = 5, + AIC3X_GPIO1_FUNC_SHORT_CIRCUIT_IRQ = 6, + AIC3X_GPIO1_FUNC_AGC_NOISE_IRQ = 7, + AIC3X_GPIO1_FUNC_INPUT = 8, + AIC3X_GPIO1_FUNC_OUTPUT = 9, + AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK = 10, + AIC3X_GPIO1_FUNC_AUDIO_WORDCLK = 11, + AIC3X_GPIO1_FUNC_BUTTON_IRQ = 12, + AIC3X_GPIO1_FUNC_HEADSET_DETECT_IRQ = 13, + AIC3X_GPIO1_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 14, + AIC3X_GPIO1_FUNC_ALL_IRQ = 16 +}; + +enum { + AIC3X_GPIO2_FUNC_DISABLED = 0, + AIC3X_GPIO2_FUNC_HEADSET_DETECT_IRQ = 2, + AIC3X_GPIO2_FUNC_INPUT = 3, + AIC3X_GPIO2_FUNC_OUTPUT = 4, + AIC3X_GPIO2_FUNC_DIGITAL_MIC_INPUT = 5, + AIC3X_GPIO2_FUNC_AUDIO_BITCLK = 8, + AIC3X_GPIO2_FUNC_HEADSET_DETECT_OR_BUTTON_IRQ = 9, + AIC3X_GPIO2_FUNC_ALL_IRQ = 10, + AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_OR_AGC_IRQ = 11, + AIC3X_GPIO2_FUNC_HEADSET_OR_BUTTON_PRESS_OR_SHORT_CIRCUIT_IRQ = 12, + AIC3X_GPIO2_FUNC_SHORT_CIRCUIT_IRQ = 13, + AIC3X_GPIO2_FUNC_AGC_NOISE_IRQ = 14, + AIC3X_GPIO2_FUNC_BUTTON_PRESS_IRQ = 15 +}; + +enum aic3x_micbias_voltage { + AIC3X_MICBIAS_OFF = 0, + AIC3X_MICBIAS_2_0V = 1, + AIC3X_MICBIAS_2_5V = 2, + AIC3X_MICBIAS_AVDDV = 3, +}; + +struct aic3x_setup_data { + unsigned int gpio_func[2]; +}; + +struct aic3x_pdata { + int gpio_reset; /* < 0 if not used */ + struct aic3x_setup_data *setup; + + /* Selects the micbias voltage */ + enum aic3x_micbias_voltage micbias_vg; +}; + +#endif diff --git a/include/sound/tlv320dac33-plat.h b/include/sound/tlv320dac33-plat.h new file mode 100644 index 000000000..7a7249a89 --- /dev/null +++ b/include/sound/tlv320dac33-plat.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Platform header for Texas Instruments TLV320DAC33 codec driver + * + * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> + * + * Copyright: (C) 2009 Nokia Corporation + */ + +#ifndef __TLV320DAC33_PLAT_H +#define __TLV320DAC33_PLAT_H + +struct tlv320dac33_platform_data { + int power_gpio; + int mode1_latency; /* latency caused by the i2c writes in us */ + int auto_fifo_config; /* FIFO config based on the period size */ + int keep_bclk; /* Keep the BCLK running in FIFO modes */ + u8 burst_bclkdiv; +}; + +#endif /* __TLV320DAC33_PLAT_H */ diff --git a/include/sound/tpa6130a2-plat.h b/include/sound/tpa6130a2-plat.h new file mode 100644 index 000000000..a60930e36 --- /dev/null +++ b/include/sound/tpa6130a2-plat.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * TPA6130A2 driver platform header + * + * Copyright (C) Nokia Corporation + * + * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> + */ + +#ifndef TPA6130A2_PLAT_H +#define TPA6130A2_PLAT_H + +struct tpa6130a2_platform_data { + int power_gpio; +}; + +#endif diff --git a/include/sound/uda134x.h b/include/sound/uda134x.h new file mode 100644 index 000000000..db82516da --- /dev/null +++ b/include/sound/uda134x.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * uda134x.h -- UDA134x ALSA SoC Codec driver + * + * Copyright 2007 Dension Audio Systems Ltd. + * Author: Zoltan Devai + */ + +#ifndef _UDA134X_H +#define _UDA134X_H + +#include <sound/l3.h> + +struct uda134x_platform_data { + struct l3_pins l3; + void (*power) (int); + int model; +#define UDA134X_UDA1340 1 +#define UDA134X_UDA1341 2 +#define UDA134X_UDA1344 3 +#define UDA134X_UDA1345 4 +}; + +#endif /* _UDA134X_H */ diff --git a/include/sound/uda1380.h b/include/sound/uda1380.h new file mode 100644 index 000000000..2e42ea2d0 --- /dev/null +++ b/include/sound/uda1380.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * UDA1380 ALSA SoC Codec driver + * + * Copyright 2009 Philipp Zabel + */ + +#ifndef __UDA1380_H +#define __UDA1380_H + +struct uda1380_platform_data { + int gpio_power; + int gpio_reset; + int dac_clk; +#define UDA1380_DAC_CLK_SYSCLK 0 +#define UDA1380_DAC_CLK_WSPLL 1 +}; + +#endif /* __UDA1380_H */ diff --git a/include/sound/util_mem.h b/include/sound/util_mem.h new file mode 100644 index 000000000..01310e089 --- /dev/null +++ b/include/sound/util_mem.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_UTIL_MEM_H +#define __SOUND_UTIL_MEM_H + +#include <linux/mutex.h> +/* + * Copyright (C) 2000 Takashi Iwai <tiwai@suse.de> + * + * Generic memory management routines for soundcard memory allocation + */ + +/* + * memory block + */ +struct snd_util_memblk { + unsigned int size; /* size of this block */ + unsigned int offset; /* zero-offset of this block */ + struct list_head list; /* link */ +}; + +#define snd_util_memblk_argptr(blk) (void*)((char*)(blk) + sizeof(struct snd_util_memblk)) + +/* + * memory management information + */ +struct snd_util_memhdr { + unsigned int size; /* size of whole data */ + struct list_head block; /* block linked-list header */ + int nblocks; /* # of allocated blocks */ + unsigned int used; /* used memory size */ + int block_extra_size; /* extra data size of chunk */ + struct mutex block_mutex; /* lock */ +}; + +/* + * prototypes + */ +struct snd_util_memhdr *snd_util_memhdr_new(int memsize); +void snd_util_memhdr_free(struct snd_util_memhdr *hdr); +struct snd_util_memblk *snd_util_mem_alloc(struct snd_util_memhdr *hdr, int size); +int snd_util_mem_free(struct snd_util_memhdr *hdr, struct snd_util_memblk *blk); +int snd_util_mem_avail(struct snd_util_memhdr *hdr); + +/* functions without mutex */ +struct snd_util_memblk *__snd_util_mem_alloc(struct snd_util_memhdr *hdr, int size); +void __snd_util_mem_free(struct snd_util_memhdr *hdr, struct snd_util_memblk *blk); +struct snd_util_memblk *__snd_util_memblk_new(struct snd_util_memhdr *hdr, + unsigned int units, + struct list_head *prev); + +#endif /* __SOUND_UTIL_MEM_H */ diff --git a/include/sound/vx_core.h b/include/sound/vx_core.h new file mode 100644 index 000000000..1ddd3036b --- /dev/null +++ b/include/sound/vx_core.h @@ -0,0 +1,536 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Driver for Digigram VX soundcards + * + * Hardware core part + * + * Copyright (c) 2002 by Takashi Iwai <tiwai@suse.de> + */ + +#ifndef __SOUND_VX_COMMON_H +#define __SOUND_VX_COMMON_H + +#include <sound/pcm.h> +#include <sound/hwdep.h> +#include <linux/interrupt.h> + +struct firmware; +struct device; + +#define VX_DRIVER_VERSION 0x010000 /* 1.0.0 */ + +/* + */ +#define SIZE_MAX_CMD 0x10 +#define SIZE_MAX_STATUS 0x10 + +struct vx_rmh { + u16 LgCmd; /* length of the command to send (WORDs) */ + u16 LgStat; /* length of the status received (WORDs) */ + u32 Cmd[SIZE_MAX_CMD]; + u32 Stat[SIZE_MAX_STATUS]; + u16 DspStat; /* status type, RMP_SSIZE_XXX */ +}; + +typedef u64 pcx_time_t; + +#define VX_MAX_PIPES 16 +#define VX_MAX_PERIODS 32 +#define VX_MAX_CODECS 2 + +struct vx_ibl_info { + int size; /* the current IBL size (0 = query) in bytes */ + int max_size; /* max. IBL size in bytes */ + int min_size; /* min. IBL size in bytes */ + int granularity; /* granularity */ +}; + +struct vx_pipe { + int number; + unsigned int is_capture: 1; + unsigned int data_mode: 1; + unsigned int running: 1; + unsigned int prepared: 1; + int channels; + unsigned int differed_type; + pcx_time_t pcx_time; + struct snd_pcm_substream *substream; + + int hbuf_size; /* H-buffer size in bytes */ + int buffer_bytes; /* the ALSA pcm buffer size in bytes */ + int period_bytes; /* the ALSA pcm period size in bytes */ + int hw_ptr; /* the current hardware pointer in bytes */ + int position; /* the current position in frames (playback only) */ + int transferred; /* the transferred size (per period) in frames */ + int align; /* size of alignment */ + u64 cur_count; /* current sample position (for playback) */ + + unsigned int references; /* an output pipe may be used for monitoring and/or playback */ + struct vx_pipe *monitoring_pipe; /* pointer to the monitoring pipe (capture pipe only)*/ +}; + +struct vx_core; + +struct snd_vx_ops { + /* low-level i/o */ + unsigned char (*in8)(struct vx_core *chip, int reg); + unsigned int (*in32)(struct vx_core *chip, int reg); + void (*out8)(struct vx_core *chip, int reg, unsigned char val); + void (*out32)(struct vx_core *chip, int reg, unsigned int val); + /* irq */ + int (*test_and_ack)(struct vx_core *chip); + void (*validate_irq)(struct vx_core *chip, int enable); + /* codec */ + void (*write_codec)(struct vx_core *chip, int codec, unsigned int data); + void (*akm_write)(struct vx_core *chip, int reg, unsigned int data); + void (*reset_codec)(struct vx_core *chip); + void (*change_audio_source)(struct vx_core *chip, int src); + void (*set_clock_source)(struct vx_core *chp, int src); + /* chip init */ + int (*load_dsp)(struct vx_core *chip, int idx, const struct firmware *fw); + void (*reset_dsp)(struct vx_core *chip); + void (*reset_board)(struct vx_core *chip, int cold_reset); + int (*add_controls)(struct vx_core *chip); + /* pcm */ + void (*dma_write)(struct vx_core *chip, struct snd_pcm_runtime *runtime, + struct vx_pipe *pipe, int count); + void (*dma_read)(struct vx_core *chip, struct snd_pcm_runtime *runtime, + struct vx_pipe *pipe, int count); +}; + +struct snd_vx_hardware { + const char *name; + int type; /* VX_TYPE_XXX */ + + /* hardware specs */ + unsigned int num_codecs; + unsigned int num_ins; + unsigned int num_outs; + unsigned int output_level_max; + const unsigned int *output_level_db_scale; +}; + +/* hwdep id string */ +#define SND_VX_HWDEP_ID "VX Loader" + +/* hardware type */ +enum { + /* VX222 PCI */ + VX_TYPE_BOARD, /* old VX222 PCI */ + VX_TYPE_V2, /* VX222 V2 PCI */ + VX_TYPE_MIC, /* VX222 Mic PCI */ + /* VX-pocket */ + VX_TYPE_VXPOCKET, /* VXpocket V2 */ + VX_TYPE_VXP440, /* VXpocket 440 */ + VX_TYPE_NUMS +}; + +/* chip status */ +enum { + VX_STAT_XILINX_LOADED = (1 << 0), /* devices are registered */ + VX_STAT_DEVICE_INIT = (1 << 1), /* devices are registered */ + VX_STAT_CHIP_INIT = (1 << 2), /* all operational */ + VX_STAT_IN_SUSPEND = (1 << 10), /* in suspend phase */ + VX_STAT_IS_STALE = (1 << 15) /* device is stale */ +}; + +/* min/max values for analog output for old codecs */ +#define VX_ANALOG_OUT_LEVEL_MAX 0xe3 + +struct vx_core { + /* ALSA stuff */ + struct snd_card *card; + struct snd_pcm *pcm[VX_MAX_CODECS]; + int type; /* VX_TYPE_XXX */ + + int irq; + /* ports are defined externally */ + + /* low-level functions */ + const struct snd_vx_hardware *hw; + const struct snd_vx_ops *ops; + + struct mutex lock; + + unsigned int chip_status; + unsigned int pcm_running; + + struct device *dev; + struct snd_hwdep *hwdep; + + struct vx_rmh irq_rmh; /* RMH used in interrupts */ + + unsigned int audio_info; /* see VX_AUDIO_INFO */ + unsigned int audio_ins; + unsigned int audio_outs; + struct vx_pipe **playback_pipes; + struct vx_pipe **capture_pipes; + + /* clock and audio sources */ + unsigned int audio_source; /* current audio input source */ + unsigned int audio_source_target; + unsigned int clock_mode; /* clock mode (VX_CLOCK_MODE_XXX) */ + unsigned int clock_source; /* current clock source (INTERNAL_QUARTZ or UER_SYNC) */ + unsigned int freq; /* current frequency */ + unsigned int freq_detected; /* detected frequency from digital in */ + unsigned int uer_detected; /* VX_UER_MODE_XXX */ + unsigned int uer_bits; /* IEC958 status bits */ + struct vx_ibl_info ibl; /* IBL information */ + + /* mixer setting */ + int output_level[VX_MAX_CODECS][2]; /* analog output level */ + int audio_gain[2][4]; /* digital audio level (playback/capture) */ + unsigned char audio_active[4]; /* mute/unmute on digital playback */ + int audio_monitor[4]; /* playback hw-monitor level */ + unsigned char audio_monitor_active[4]; /* playback hw-monitor mute/unmute */ + + struct mutex mixer_mutex; + + const struct firmware *firmware[4]; /* loaded firmware data */ +}; + + +/* + * constructor + */ +struct vx_core *snd_vx_create(struct snd_card *card, + const struct snd_vx_hardware *hw, + const struct snd_vx_ops *ops, int extra_size); +int snd_vx_setup_firmware(struct vx_core *chip); +int snd_vx_load_boot_image(struct vx_core *chip, const struct firmware *dsp); +int snd_vx_dsp_boot(struct vx_core *chip, const struct firmware *dsp); +int snd_vx_dsp_load(struct vx_core *chip, const struct firmware *dsp); + +void snd_vx_free_firmware(struct vx_core *chip); + +/* + * interrupt handler; exported for pcmcia + */ +irqreturn_t snd_vx_irq_handler(int irq, void *dev); +irqreturn_t snd_vx_threaded_irq_handler(int irq, void *dev); + +/* + * lowlevel functions + */ +static inline int vx_test_and_ack(struct vx_core *chip) +{ + return chip->ops->test_and_ack(chip); +} + +static inline void vx_validate_irq(struct vx_core *chip, int enable) +{ + chip->ops->validate_irq(chip, enable); +} + +static inline unsigned char snd_vx_inb(struct vx_core *chip, int reg) +{ + return chip->ops->in8(chip, reg); +} + +static inline unsigned int snd_vx_inl(struct vx_core *chip, int reg) +{ + return chip->ops->in32(chip, reg); +} + +static inline void snd_vx_outb(struct vx_core *chip, int reg, unsigned char val) +{ + chip->ops->out8(chip, reg, val); +} + +static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val) +{ + chip->ops->out32(chip, reg, val); +} + +#define vx_inb(chip,reg) snd_vx_inb(chip, VX_##reg) +#define vx_outb(chip,reg,val) snd_vx_outb(chip, VX_##reg,val) +#define vx_inl(chip,reg) snd_vx_inl(chip, VX_##reg) +#define vx_outl(chip,reg,val) snd_vx_outl(chip, VX_##reg,val) + +static inline void vx_reset_dsp(struct vx_core *chip) +{ + chip->ops->reset_dsp(chip); +} + +int vx_send_msg(struct vx_core *chip, struct vx_rmh *rmh); +int vx_send_msg_nolock(struct vx_core *chip, struct vx_rmh *rmh); +int vx_send_rih(struct vx_core *chip, int cmd); +int vx_send_rih_nolock(struct vx_core *chip, int cmd); + +void vx_reset_codec(struct vx_core *chip, int cold_reset); + +/* + * check the bit on the specified register + * returns zero if a bit matches, or a negative error code. + * exported for vxpocket driver + */ +int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int time); +#define vx_check_isr(chip,mask,bit,time) snd_vx_check_reg_bit(chip, VX_ISR, mask, bit, time) +#define vx_wait_isr_bit(chip,bit) vx_check_isr(chip, bit, bit, 200) +#define vx_wait_for_rx_full(chip) vx_wait_isr_bit(chip, ISR_RX_FULL) + + +/* + * pseudo-DMA transfer + */ +static inline void vx_pseudo_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime, + struct vx_pipe *pipe, int count) +{ + chip->ops->dma_write(chip, runtime, pipe, count); +} + +static inline void vx_pseudo_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime, + struct vx_pipe *pipe, int count) +{ + chip->ops->dma_read(chip, runtime, pipe, count); +} + + + +/* error with hardware code, + * the return value is -(VX_ERR_MASK | actual-hw-error-code) + */ +#define VX_ERR_MASK 0x1000000 +#define vx_get_error(err) (-(err) & ~VX_ERR_MASK) + + +/* + * pcm stuff + */ +int snd_vx_pcm_new(struct vx_core *chip); +void vx_pcm_update_intr(struct vx_core *chip, unsigned int events); + +/* + * mixer stuff + */ +int snd_vx_mixer_new(struct vx_core *chip); +void vx_toggle_dac_mute(struct vx_core *chip, int mute); +int vx_sync_audio_source(struct vx_core *chip); +int vx_set_monitor_level(struct vx_core *chip, int audio, int level, int active); + +/* + * IEC958 & clock stuff + */ +void vx_set_iec958_status(struct vx_core *chip, unsigned int bits); +int vx_set_clock(struct vx_core *chip, unsigned int freq); +void vx_set_internal_clock(struct vx_core *chip, unsigned int freq); +int vx_change_frequency(struct vx_core *chip); + + +/* + * PM + */ +int snd_vx_suspend(struct vx_core *card); +int snd_vx_resume(struct vx_core *card); + +/* + * hardware constants + */ + +#define vx_has_new_dsp(chip) ((chip)->type != VX_TYPE_BOARD) +#define vx_is_pcmcia(chip) ((chip)->type >= VX_TYPE_VXPOCKET) + +/* audio input source */ +enum { + VX_AUDIO_SRC_DIGITAL, + VX_AUDIO_SRC_LINE, + VX_AUDIO_SRC_MIC +}; + +/* clock source */ +enum { + INTERNAL_QUARTZ, + UER_SYNC +}; + +/* clock mode */ +enum { + VX_CLOCK_MODE_AUTO, /* depending on the current audio source */ + VX_CLOCK_MODE_INTERNAL, /* fixed to internal quartz */ + VX_CLOCK_MODE_EXTERNAL /* fixed to UER sync */ +}; + +/* SPDIF/UER type */ +enum { + VX_UER_MODE_CONSUMER, + VX_UER_MODE_PROFESSIONAL, + VX_UER_MODE_NOT_PRESENT, +}; + +/* register indices */ +enum { + VX_ICR, + VX_CVR, + VX_ISR, + VX_IVR, + VX_RXH, + VX_TXH = VX_RXH, + VX_RXM, + VX_TXM = VX_RXM, + VX_RXL, + VX_TXL = VX_RXL, + VX_DMA, + VX_CDSP, + VX_RFREQ, + VX_RUER_V2, + VX_GAIN, + VX_DATA = VX_GAIN, + VX_MEMIRQ, + VX_ACQ, + VX_BIT0, + VX_BIT1, + VX_MIC0, + VX_MIC1, + VX_MIC2, + VX_MIC3, + VX_PLX0, + VX_PLX1, + VX_PLX2, + + VX_LOFREQ, // V2: ACQ, VP: RFREQ + VX_HIFREQ, // V2: BIT0, VP: RUER_V2 + VX_CSUER, // V2: BIT1, VP: BIT0 + VX_RUER, // V2: RUER_V2, VP: BIT1 + + VX_REG_MAX, + + /* aliases for VX board */ + VX_RESET_DMA = VX_ISR, + VX_CFG = VX_RFREQ, + VX_STATUS = VX_MEMIRQ, + VX_SELMIC = VX_MIC0, + VX_COMPOT = VX_MIC1, + VX_SCOMPR = VX_MIC2, + VX_GLIMIT = VX_MIC3, + VX_INTCSR = VX_PLX0, + VX_CNTRL = VX_PLX1, + VX_GPIOC = VX_PLX2, + + /* aliases for VXPOCKET board */ + VX_MICRO = VX_MEMIRQ, + VX_CODEC2 = VX_MEMIRQ, + VX_DIALOG = VX_ACQ, + +}; + +/* RMH status type */ +enum { + RMH_SSIZE_FIXED = 0, /* status size given by the driver (in LgStat) */ + RMH_SSIZE_ARG = 1, /* status size given in the LSB byte */ + RMH_SSIZE_MASK = 2, /* status size given in bitmask */ +}; + + +/* bits for ICR register */ +#define ICR_HF1 0x10 +#define ICR_HF0 0x08 +#define ICR_TREQ 0x02 /* Interrupt mode + HREQ set on for transfer (->DSP) request */ +#define ICR_RREQ 0x01 /* Interrupt mode + RREQ set on for transfer (->PC) request */ + +/* bits for CVR register */ +#define CVR_HC 0x80 + +/* bits for ISR register */ +#define ISR_HF3 0x10 +#define ISR_HF2 0x08 +#define ISR_CHK 0x10 +#define ISR_ERR 0x08 +#define ISR_TX_READY 0x04 +#define ISR_TX_EMPTY 0x02 +#define ISR_RX_FULL 0x01 + +/* Constants used to access the DATA register */ +#define VX_DATA_CODEC_MASK 0x80 +#define VX_DATA_XICOR_MASK 0x80 + +/* Constants used to access the CSUER register (both for VX2 and VXP) */ +#define VX_SUER_FREQ_MASK 0x0c +#define VX_SUER_FREQ_32KHz_MASK 0x0c +#define VX_SUER_FREQ_44KHz_MASK 0x00 +#define VX_SUER_FREQ_48KHz_MASK 0x04 +#define VX_SUER_DATA_PRESENT_MASK 0x02 +#define VX_SUER_CLOCK_PRESENT_MASK 0x01 + +#define VX_CUER_HH_BITC_SEL_MASK 0x08 +#define VX_CUER_MH_BITC_SEL_MASK 0x04 +#define VX_CUER_ML_BITC_SEL_MASK 0x02 +#define VX_CUER_LL_BITC_SEL_MASK 0x01 + +#define XX_UER_CBITS_OFFSET_MASK 0x1f + + +/* bits for audio_info */ +#define VX_AUDIO_INFO_REAL_TIME (1<<0) /* real-time processing available */ +#define VX_AUDIO_INFO_OFFLINE (1<<1) /* offline processing available */ +#define VX_AUDIO_INFO_MPEG1 (1<<5) +#define VX_AUDIO_INFO_MPEG2 (1<<6) +#define VX_AUDIO_INFO_LINEAR_8 (1<<7) +#define VX_AUDIO_INFO_LINEAR_16 (1<<8) +#define VX_AUDIO_INFO_LINEAR_24 (1<<9) + +/* DSP Interrupt Request values */ +#define VXP_IRQ_OFFSET 0x40 /* add 0x40 offset for vxpocket and vx222/v2 */ +/* call with vx_send_irq_dsp() */ +#define IRQ_MESS_WRITE_END 0x30 +#define IRQ_MESS_WRITE_NEXT 0x32 +#define IRQ_MESS_READ_NEXT 0x34 +#define IRQ_MESS_READ_END 0x36 +#define IRQ_MESSAGE 0x38 +#define IRQ_RESET_CHK 0x3A +#define IRQ_CONNECT_STREAM_NEXT 0x26 +#define IRQ_CONNECT_STREAM_END 0x28 +#define IRQ_PAUSE_START_CONNECT 0x2A +#define IRQ_END_CONNECTION 0x2C + +/* Is there async. events pending ( IT Source Test ) */ +#define ASYNC_EVENTS_PENDING 0x008000 +#define HBUFFER_EVENTS_PENDING 0x004000 // Not always accurate +#define NOTIF_EVENTS_PENDING 0x002000 +#define TIME_CODE_EVENT_PENDING 0x001000 +#define FREQUENCY_CHANGE_EVENT_PENDING 0x000800 +#define END_OF_BUFFER_EVENTS_PENDING 0x000400 +#define FATAL_DSP_ERROR 0xff0000 + +/* Stream Format Header Defines */ +#define HEADER_FMT_BASE 0xFED00000 +#define HEADER_FMT_MONO 0x000000C0 +#define HEADER_FMT_INTEL 0x00008000 +#define HEADER_FMT_16BITS 0x00002000 +#define HEADER_FMT_24BITS 0x00004000 +#define HEADER_FMT_UPTO11 0x00000200 /* frequency is less or equ. to 11k.*/ +#define HEADER_FMT_UPTO32 0x00000100 /* frequency is over 11k and less then 32k.*/ + +/* Constants used to access the Codec */ +#define XX_CODEC_SELECTOR 0x20 +/* codec commands */ +#define XX_CODEC_ADC_CONTROL_REGISTER 0x01 +#define XX_CODEC_DAC_CONTROL_REGISTER 0x02 +#define XX_CODEC_LEVEL_LEFT_REGISTER 0x03 +#define XX_CODEC_LEVEL_RIGHT_REGISTER 0x04 +#define XX_CODEC_PORT_MODE_REGISTER 0x05 +#define XX_CODEC_STATUS_REPORT_REGISTER 0x06 +#define XX_CODEC_CLOCK_CONTROL_REGISTER 0x07 + +/* + * Audio-level control values + */ +#define CVAL_M110DB 0x000 /* -110dB */ +#define CVAL_M99DB 0x02C +#define CVAL_M21DB 0x163 +#define CVAL_M18DB 0x16F +#define CVAL_M10DB 0x18F +#define CVAL_0DB 0x1B7 +#define CVAL_18DB 0x1FF /* +18dB */ +#define CVAL_MAX 0x1FF + +#define AUDIO_IO_HAS_MUTE_LEVEL 0x400000 +#define AUDIO_IO_HAS_MUTE_MONITORING_1 0x200000 +#define AUDIO_IO_HAS_MUTE_MONITORING_2 0x100000 +#define VALID_AUDIO_IO_DIGITAL_LEVEL 0x01 +#define VALID_AUDIO_IO_MONITORING_LEVEL 0x02 +#define VALID_AUDIO_IO_MUTE_LEVEL 0x04 +#define VALID_AUDIO_IO_MUTE_MONITORING_1 0x08 +#define VALID_AUDIO_IO_MUTE_MONITORING_2 0x10 + + +#endif /* __SOUND_VX_COMMON_H */ diff --git a/include/sound/wavefront.h b/include/sound/wavefront.h new file mode 100644 index 000000000..37ed437e2 --- /dev/null +++ b/include/sound/wavefront.h @@ -0,0 +1,682 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_WAVEFRONT_H__ +#define __SOUND_WAVEFRONT_H__ + +/* + * Driver for Turtle Beach Wavefront cards (Maui,Tropez,Tropez+) + * + * Copyright (c) by Paul Barton-Davis <pbd@op.net> + */ + +#if (!defined(__GNUC__) && !defined(__GNUG__)) + + You will not be able to compile this file correctly without gcc, because + it is necessary to pack the "wavefront_alias" structure to a size + of 22 bytes, corresponding to 16-bit alignment (as would have been + the case on the original platform, MS-DOS). If this is not done, + then WavePatch-format files cannot be read/written correctly. + The method used to do this here ("__attribute__((packed)") is + completely compiler dependent. + + All other wavefront_* types end up aligned to 32 bit values and + still have the same (correct) size. + +#else + + /* However, note that as of G++ 2.7.3.2, g++ was unable to + correctly parse *type* __attribute__ tags. It will do the + right thing if we use the "packed" attribute on each struct + member, which has the same semantics anyway. + */ + +#endif /* __GNUC__ */ + +/***************************** WARNING ******************************** + PLEASE DO NOT MODIFY THIS FILE IN ANY WAY THAT AFFECTS ITS ABILITY TO + BE USED WITH EITHER C *OR* C++. + **********************************************************************/ + +#ifndef NUM_MIDIKEYS +#define NUM_MIDIKEYS 128 +#endif /* NUM_MIDIKEYS */ + +#ifndef NUM_MIDICHANNELS +#define NUM_MIDICHANNELS 16 +#endif /* NUM_MIDICHANNELS */ + +/* These are very useful/important. the original wavefront interface + was developed on a 16 bit system, where sizeof(int) = 2 + bytes. Defining things like this makes the code much more portable, and + easier to understand without having to toggle back and forth + between a 16-bit view of the world and a 32-bit one. + */ + +#ifndef __KERNEL__ +/* keep them for compatibility */ +typedef short s16; +typedef unsigned short u16; +typedef int s32; +typedef unsigned int u32; +typedef char s8; +typedef unsigned char u8; +typedef s16 INT16; +typedef u16 UINT16; +typedef s32 INT32; +typedef u32 UINT32; +typedef s8 CHAR8; +typedef u8 UCHAR8; +#endif + +/* Pseudo-commands not part of the WaveFront command set. + These are used for various driver controls and direct + hardware control. + */ + +#define WFC_DEBUG_DRIVER 0 +#define WFC_FX_IOCTL 1 +#define WFC_PATCH_STATUS 2 +#define WFC_PROGRAM_STATUS 3 +#define WFC_SAMPLE_STATUS 4 +#define WFC_DISABLE_INTERRUPTS 5 +#define WFC_ENABLE_INTERRUPTS 6 +#define WFC_INTERRUPT_STATUS 7 +#define WFC_ROMSAMPLES_RDONLY 8 +#define WFC_IDENTIFY_SLOT_TYPE 9 + +/* Wavefront synth commands + */ + +#define WFC_DOWNLOAD_SAMPLE 0x80 +#define WFC_DOWNLOAD_BLOCK 0x81 +#define WFC_DOWNLOAD_MULTISAMPLE 0x82 +#define WFC_DOWNLOAD_SAMPLE_ALIAS 0x83 +#define WFC_DELETE_SAMPLE 0x84 +#define WFC_REPORT_FREE_MEMORY 0x85 +#define WFC_DOWNLOAD_PATCH 0x86 +#define WFC_DOWNLOAD_PROGRAM 0x87 +#define WFC_SET_SYNTHVOL 0x89 +#define WFC_SET_NVOICES 0x8B +#define WFC_DOWNLOAD_DRUM 0x90 +#define WFC_GET_SYNTHVOL 0x92 +#define WFC_GET_NVOICES 0x94 +#define WFC_DISABLE_CHANNEL 0x9A +#define WFC_ENABLE_CHANNEL 0x9B +#define WFC_MISYNTH_OFF 0x9D +#define WFC_MISYNTH_ON 0x9E +#define WFC_FIRMWARE_VERSION 0x9F +#define WFC_GET_NSAMPLES 0xA0 +#define WFC_DISABLE_DRUM_PROGRAM 0xA2 +#define WFC_UPLOAD_PATCH 0xA3 +#define WFC_UPLOAD_PROGRAM 0xA4 +#define WFC_SET_TUNING 0xA6 +#define WFC_GET_TUNING 0xA7 +#define WFC_VMIDI_ON 0xA8 +#define WFC_VMIDI_OFF 0xA9 +#define WFC_MIDI_STATUS 0xAA +#define WFC_GET_CHANNEL_STATUS 0xAB +#define WFC_DOWNLOAD_SAMPLE_HEADER 0xAC +#define WFC_UPLOAD_SAMPLE_HEADER 0xAD +#define WFC_UPLOAD_MULTISAMPLE 0xAE +#define WFC_UPLOAD_SAMPLE_ALIAS 0xAF +#define WFC_IDENTIFY_SAMPLE_TYPE 0xB0 +#define WFC_DOWNLOAD_EDRUM_PROGRAM 0xB1 +#define WFC_UPLOAD_EDRUM_PROGRAM 0xB2 +#define WFC_SET_EDRUM_CHANNEL 0xB3 +#define WFC_INSTOUT_LEVELS 0xB4 +#define WFC_PEAKOUT_LEVELS 0xB5 +#define WFC_REPORT_CHANNEL_PROGRAMS 0xB6 +#define WFC_HARDWARE_VERSION 0xCF +#define WFC_UPLOAD_SAMPLE_PARAMS 0xD7 +#define WFC_DOWNLOAD_OS 0xF1 +#define WFC_NOOP 0xFF + +#define WF_MAX_SAMPLE 512 +#define WF_MAX_PATCH 256 +#define WF_MAX_PROGRAM 128 + +#define WF_SECTION_MAX 44 /* longest OS section length */ + +/* # of bytes we send to the board when sending it various kinds of + substantive data, such as samples, patches and programs. +*/ + +#define WF_PROGRAM_BYTES 32 +#define WF_PATCH_BYTES 132 +#define WF_SAMPLE_BYTES 27 +#define WF_SAMPLE_HDR_BYTES 25 +#define WF_ALIAS_BYTES 25 +#define WF_DRUM_BYTES 9 +#define WF_MSAMPLE_BYTES 259 /* (MIDI_KEYS * 2) + 3 */ + +#define WF_ACK 0x80 +#define WF_DMA_ACK 0x81 + +/* OR-values for MIDI status bits */ + +#define WF_MIDI_VIRTUAL_ENABLED 0x1 +#define WF_MIDI_VIRTUAL_IS_EXTERNAL 0x2 +#define WF_MIDI_IN_TO_SYNTH_DISABLED 0x4 + +/* slot indexes for struct address_info: makes code a little more mnemonic */ + +#define WF_SYNTH_SLOT 0 +#define WF_INTERNAL_MIDI_SLOT 1 +#define WF_EXTERNAL_MIDI_SLOT 2 + +/* Magic MIDI bytes used to switch I/O streams on the ICS2115 MPU401 + emulation. Note these NEVER show up in output from the device and + should NEVER be used in input unless Virtual MIDI mode has been + disabled. If they do show up as input, the results are unpredictable. +*/ + +#define WF_EXTERNAL_SWITCH 0xFD +#define WF_INTERNAL_SWITCH 0xF9 + +/* Debugging flags */ + +#define WF_DEBUG_CMD 0x1 +#define WF_DEBUG_DATA 0x2 +#define WF_DEBUG_LOAD_PATCH 0x4 +#define WF_DEBUG_IO 0x8 + +/* WavePatch file format stuff */ + +#define WF_WAVEPATCH_VERSION 120; /* Current version number (1.2) */ +#define WF_MAX_COMMENT 64 /* Comment length */ +#define WF_NUM_LAYERS 4 +#define WF_NAME_LENGTH 32 +#define WF_SOURCE_LENGTH 260 + +#define BankFileID "Bank" +#define DrumkitFileID "DrumKit" +#define ProgramFileID "Program" + +struct wf_envelope +{ + u8 attack_time:7; + u8 Unused1:1; + + u8 decay1_time:7; + u8 Unused2:1; + + u8 decay2_time:7; + u8 Unused3:1; + + u8 sustain_time:7; + u8 Unused4:1; + + u8 release_time:7; + u8 Unused5:1; + + u8 release2_time:7; + u8 Unused6:1; + + s8 attack_level; + s8 decay1_level; + s8 decay2_level; + s8 sustain_level; + s8 release_level; + + u8 attack_velocity:7; + u8 Unused7:1; + + u8 volume_velocity:7; + u8 Unused8:1; + + u8 keyboard_scaling:7; + u8 Unused9:1; +}; +typedef struct wf_envelope wavefront_envelope; + +struct wf_lfo +{ + u8 sample_number; + + u8 frequency:7; + u8 Unused1:1; + + u8 am_src:4; + u8 fm_src:4; + + s8 fm_amount; + s8 am_amount; + s8 start_level; + s8 end_level; + + u8 ramp_delay:7; + u8 wave_restart:1; /* for LFO2 only */ + + u8 ramp_time:7; + u8 Unused2:1; +}; +typedef struct wf_lfo wavefront_lfo; + +struct wf_patch +{ + s16 frequency_bias; /* ** THIS IS IN MOTOROLA FORMAT!! ** */ + + u8 amplitude_bias:7; + u8 Unused1:1; + + u8 portamento:7; + u8 Unused2:1; + + u8 sample_number; + + u8 pitch_bend:4; + u8 sample_msb:1; + u8 Unused3:3; + + u8 mono:1; + u8 retrigger:1; + u8 nohold:1; + u8 restart:1; + u8 filterconfig:2; /* SDK says "not used" */ + u8 reuse:1; + u8 reset_lfo:1; + + u8 fm_src2:4; + u8 fm_src1:4; + + s8 fm_amount1; + s8 fm_amount2; + + u8 am_src:4; + u8 Unused4:4; + + s8 am_amount; + + u8 fc1_mode:4; + u8 fc2_mode:4; + + s8 fc1_mod_amount; + s8 fc1_keyboard_scaling; + s8 fc1_bias; + s8 fc2_mod_amount; + s8 fc2_keyboard_scaling; + s8 fc2_bias; + + u8 randomizer:7; + u8 Unused5:1; + + struct wf_envelope envelope1; + struct wf_envelope envelope2; + struct wf_lfo lfo1; + struct wf_lfo lfo2; +}; +typedef struct wf_patch wavefront_patch; + +struct wf_layer +{ + u8 patch_number; + + u8 mix_level:7; + u8 mute:1; + + u8 split_point:7; + u8 play_below:1; + + u8 pan_mod_src:2; + u8 pan_or_mod:1; + u8 pan:4; + u8 split_type:1; +}; +typedef struct wf_layer wavefront_layer; + +struct wf_program +{ + struct wf_layer layer[WF_NUM_LAYERS]; +}; +typedef struct wf_program wavefront_program; + +struct wf_sample_offset +{ + s32 Fraction:4; + s32 Integer:20; + s32 Unused:8; +}; +typedef struct wf_sample_offset wavefront_sample_offset; + +/* Sample slot types */ + +#define WF_ST_SAMPLE 0 +#define WF_ST_MULTISAMPLE 1 +#define WF_ST_ALIAS 2 +#define WF_ST_EMPTY 3 + +/* pseudo's */ + +#define WF_ST_DRUM 4 +#define WF_ST_PROGRAM 5 +#define WF_ST_PATCH 6 +#define WF_ST_SAMPLEHDR 7 + +#define WF_ST_MASK 0xf + +/* Flags for slot status. These occupy the upper bits of the same byte + as a sample type. +*/ + +#define WF_SLOT_USED 0x80 /* XXX don't rely on this being accurate */ +#define WF_SLOT_FILLED 0x40 +#define WF_SLOT_ROM 0x20 + +#define WF_SLOT_MASK 0xf0 + +/* channel constants */ + +#define WF_CH_MONO 0 +#define WF_CH_LEFT 1 +#define WF_CH_RIGHT 2 + +/* Sample formats */ + +#define LINEAR_16BIT 0 +#define WHITE_NOISE 1 +#define LINEAR_8BIT 2 +#define MULAW_8BIT 3 + +#define WF_SAMPLE_IS_8BIT(smpl) ((smpl)->SampleResolution&2) + + +/* + + Because most/all of the sample data we pass in via pointers has + never been copied (just mmap-ed into user space straight from the + disk), it would be nice to allow handling of multi-channel sample + data without forcing user-level extraction of the relevant bytes. + + So, we need a way of specifying which channel to use (the WaveFront + only handles mono samples in a given slot), and the only way to do + this without using some struct other than wavefront_sample as the + interface is the awful hack of using the unused bits in a + wavefront_sample: + + Val Meaning + --- ------- + 0 no channel selection (use channel 1, sample is MONO) + 1 use first channel, and skip one + 2 use second channel, and skip one + 3 use third channel, and skip two + 4 use fourth channel, skip three + 5 use fifth channel, skip four + 6 use six channel, skip five + + + This can handle up to 4 channels, and anyone downloading >4 channels + of sample data just to select one of them needs to find some tools + like sox ... + + NOTE: values 0, 1 and 2 correspond to WF_CH_* above. This is + important. + +*/ + +#define WF_SET_CHANNEL(samp,chn) \ + (samp)->Unused1 = chn & 0x1; \ + (samp)->Unused2 = chn & 0x2; \ + (samp)->Unused3 = chn & 0x4 + +#define WF_GET_CHANNEL(samp) \ + (((samp)->Unused3 << 2)|((samp)->Unused2<<1)|(samp)->Unused1) + +typedef struct wf_sample { + struct wf_sample_offset sampleStartOffset; + struct wf_sample_offset loopStartOffset; + struct wf_sample_offset loopEndOffset; + struct wf_sample_offset sampleEndOffset; + s16 FrequencyBias; + u8 SampleResolution:2; /* sample_format */ + u8 Unused1:1; + u8 Loop:1; + u8 Bidirectional:1; + u8 Unused2:1; + u8 Reverse:1; + u8 Unused3:1; +} wavefront_sample; + +typedef struct wf_multisample { + s16 NumberOfSamples; /* log2 of the number of samples */ + s16 SampleNumber[NUM_MIDIKEYS]; +} wavefront_multisample; + +typedef struct wf_alias { + s16 OriginalSample; + + struct wf_sample_offset sampleStartOffset; + struct wf_sample_offset loopStartOffset; + struct wf_sample_offset sampleEndOffset; + struct wf_sample_offset loopEndOffset; + + s16 FrequencyBias; + + u8 SampleResolution:2; + u8 Unused1:1; + u8 Loop:1; + u8 Bidirectional:1; + u8 Unused2:1; + u8 Reverse:1; + u8 Unused3:1; + + /* This structure is meant to be padded only to 16 bits on their + original. Of course, whoever wrote their documentation didn't + realize that sizeof(struct) can be >= + sum(sizeof(struct-fields)) and so thought that giving a C level + description of the structs used in WavePatch files was + sufficient. I suppose it was, as long as you remember the + standard 16->32 bit issues. + */ + + u8 sixteen_bit_padding; +} __attribute__((packed)) wavefront_alias; + +typedef struct wf_drum { + u8 PatchNumber; + u8 MixLevel:7; + u8 Unmute:1; + u8 Group:4; + u8 Unused1:4; + u8 PanModSource:2; + u8 PanModulated:1; + u8 PanAmount:4; + u8 Unused2:1; +} wavefront_drum; + +typedef struct wf_drumkit { + struct wf_drum drum[NUM_MIDIKEYS]; +} wavefront_drumkit; + +typedef struct wf_channel_programs { + u8 Program[NUM_MIDICHANNELS]; +} wavefront_channel_programs; + +/* How to get MIDI channel status from the data returned by + a WFC_GET_CHANNEL_STATUS command (a struct wf_channel_programs) +*/ + +#define WF_CHANNEL_STATUS(ch,wcp) (wcp)[(ch/7)] & (1<<((ch)%7)) + +typedef union wf_any { + wavefront_sample s; + wavefront_multisample ms; + wavefront_alias a; + wavefront_program pr; + wavefront_patch p; + wavefront_drum d; +} wavefront_any; + +/* Hannu Solvainen hoped that his "patch_info" struct in soundcard.h + might work for other wave-table based patch loading situations. + Alas, his fears were correct. The WaveFront doesn't even come with + just "patches", but several different kind of structures that + control the sound generation process. + */ + +typedef struct wf_patch_info { + + /* the first two fields are used by the OSS "patch loading" interface + only, and are unused by the current user-level library. + */ + + s16 key; /* Use WAVEFRONT_PATCH here */ + u16 devno; /* fill in when sending */ + u8 subkey; /* WF_ST_{SAMPLE,ALIAS,etc.} */ + +#define WAVEFRONT_FIND_FREE_SAMPLE_SLOT 999 + + u16 number; /* patch/sample/prog number */ + + u32 size; /* size of any data included in + one of the fields in `hdrptr', or + as `dataptr'. + + NOTE: for actual samples, this is + the size of the *SELECTED CHANNEL* + even if more data is actually available. + + So, a stereo sample (2 channels) of + 6000 bytes total has `size' = 3000. + + See the macros and comments for + WF_{GET,SET}_CHANNEL above. + + */ + wavefront_any __user *hdrptr; /* user-space ptr to hdr bytes */ + u16 __user *dataptr; /* actual sample data */ + + wavefront_any hdr; /* kernel-space copy of hdr bytes */ +} wavefront_patch_info; + +/* The maximum number of bytes we will ever move to or from user space + in response to a WFC_* command. This obviously doesn't cover + actual sample data. +*/ + +#define WF_MAX_READ sizeof(wavefront_multisample) +#define WF_MAX_WRITE sizeof(wavefront_multisample) + +/* + This allows us to execute any WF command except the download/upload + ones, which are handled differently due to copyin/copyout issues as + well as data-nybbling to/from the card. + */ + +typedef struct wavefront_control { + int cmd; /* WFC_* */ + char status; /* return status to user-space */ + unsigned char rbuf[WF_MAX_READ]; /* bytes read from card */ + unsigned char wbuf[WF_MAX_WRITE]; /* bytes written to card */ +} wavefront_control; + +#define WFCTL_WFCMD 0x1 +#define WFCTL_LOAD_SPP 0x2 + +/* Modulator table */ + +#define WF_MOD_LFO1 0 +#define WF_MOD_LFO2 1 +#define WF_MOD_ENV1 2 +#define WF_MOD_ENV2 3 +#define WF_MOD_KEYBOARD 4 +#define WF_MOD_LOGKEY 5 +#define WF_MOD_VELOCITY 6 +#define WF_MOD_LOGVEL 7 +#define WF_MOD_RANDOM 8 +#define WF_MOD_PRESSURE 9 +#define WF_MOD_MOD_WHEEL 10 +#define WF_MOD_1 WF_MOD_MOD_WHEEL +#define WF_MOD_BREATH 11 +#define WF_MOD_2 WF_MOD_BREATH +#define WF_MOD_FOOT 12 +#define WF_MOD_4 WF_MOD_FOOT +#define WF_MOD_VOLUME 13 +#define WF_MOD_7 WF_MOD_VOLUME +#define WF_MOD_PAN 14 +#define WF_MOD_10 WF_MOD_PAN +#define WF_MOD_EXPR 15 +#define WF_MOD_11 WF_MOD_EXPR + +/* FX-related material */ + +typedef struct wf_fx_info { + int request; /* see list below */ + long data[4]; /* we don't need much */ +} wavefront_fx_info; + +/* support for each of these will be forthcoming once I or someone + else has figured out which of the addresses on page 6 and page 7 of + the YSS225 control each parameter. Incidentally, these come from + the Windows driver interface, but again, Turtle Beach didn't + document the API to use them. +*/ + +#define WFFX_SETOUTGAIN 0 +#define WFFX_SETSTEREOOUTGAIN 1 +#define WFFX_SETREVERBIN1GAIN 2 +#define WFFX_SETREVERBIN2GAIN 3 +#define WFFX_SETREVERBIN3GAIN 4 +#define WFFX_SETCHORUSINPORT 5 +#define WFFX_SETREVERBIN1PORT 6 +#define WFFX_SETREVERBIN2PORT 7 +#define WFFX_SETREVERBIN3PORT 8 +#define WFFX_SETEFFECTPORT 9 +#define WFFX_SETAUXPORT 10 +#define WFFX_SETREVERBTYPE 11 +#define WFFX_SETREVERBDELAY 12 +#define WFFX_SETCHORUSLFO 13 +#define WFFX_SETCHORUSPMD 14 +#define WFFX_SETCHORUSAMD 15 +#define WFFX_SETEFFECT 16 +#define WFFX_SETBASEALL 17 +#define WFFX_SETREVERBALL 18 +#define WFFX_SETCHORUSALL 20 +#define WFFX_SETREVERBDEF 22 +#define WFFX_SETCHORUSDEF 23 +#define WFFX_DELAYSETINGAIN 24 +#define WFFX_DELAYSETFBGAIN 25 +#define WFFX_DELAYSETFBLPF 26 +#define WFFX_DELAYSETGAIN 27 +#define WFFX_DELAYSETTIME 28 +#define WFFX_DELAYSETFBTIME 29 +#define WFFX_DELAYSETALL 30 +#define WFFX_DELAYSETDEF 32 +#define WFFX_SDELAYSETINGAIN 33 +#define WFFX_SDELAYSETFBGAIN 34 +#define WFFX_SDELAYSETFBLPF 35 +#define WFFX_SDELAYSETGAIN 36 +#define WFFX_SDELAYSETTIME 37 +#define WFFX_SDELAYSETFBTIME 38 +#define WFFX_SDELAYSETALL 39 +#define WFFX_SDELAYSETDEF 41 +#define WFFX_DEQSETINGAIN 42 +#define WFFX_DEQSETFILTER 43 +#define WFFX_DEQSETALL 44 +#define WFFX_DEQSETDEF 46 +#define WFFX_MUTE 47 +#define WFFX_FLANGESETBALANCE 48 +#define WFFX_FLANGESETDELAY 49 +#define WFFX_FLANGESETDWFFX_TH 50 +#define WFFX_FLANGESETFBGAIN 51 +#define WFFX_FLANGESETINGAIN 52 +#define WFFX_FLANGESETLFO 53 +#define WFFX_FLANGESETALL 54 +#define WFFX_FLANGESETDEF 56 +#define WFFX_PITCHSETSHIFT 57 +#define WFFX_PITCHSETBALANCE 58 +#define WFFX_PITCHSETALL 59 +#define WFFX_PITCHSETDEF 61 +#define WFFX_SRSSETINGAIN 62 +#define WFFX_SRSSETSPACE 63 +#define WFFX_SRSSETCENTER 64 +#define WFFX_SRSSETGAIN 65 +#define WFFX_SRSSETMODE 66 +#define WFFX_SRSSETDEF 68 + +/* Allow direct user-space control over FX memory/coefficient data. + In theory this could be used to download the FX microprogram, + but it would be a little slower, and involve some weird code. + */ + +#define WFFX_MEMSET 69 + +#endif /* __SOUND_WAVEFRONT_H__ */ diff --git a/include/sound/wm0010.h b/include/sound/wm0010.h new file mode 100644 index 000000000..13b473935 --- /dev/null +++ b/include/sound/wm0010.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * wm0010.h -- Platform data for WM0010 DSP Driver + * + * Copyright 2012 Wolfson Microelectronics PLC. + * + * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> + */ + +#ifndef WM0010_PDATA_H +#define WM0010_PDATA_H + +struct wm0010_pdata { + int gpio_reset; + + /* Set if there is an inverter between the GPIO controlling + * the reset signal and the device. + */ + int reset_active_high; + int irq_flags; +}; + +#endif diff --git a/include/sound/wm1250-ev1.h b/include/sound/wm1250-ev1.h new file mode 100644 index 000000000..d16614ebe --- /dev/null +++ b/include/sound/wm1250-ev1.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm1250-ev1.h - Platform data for WM1250-EV1 + * + * Copyright 2011 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM1250_EV1_H +#define __LINUX_SND_WM1250_EV1_H + +#define WM1250_EV1_NUM_GPIOS 5 + +#define WM1250_EV1_GPIO_CLK_ENA 0 +#define WM1250_EV1_GPIO_CLK_SEL0 1 +#define WM1250_EV1_GPIO_CLK_SEL1 2 +#define WM1250_EV1_GPIO_OSR 3 +#define WM1250_EV1_GPIO_MASTER 4 + + +struct wm1250_ev1_pdata { + int gpios[WM1250_EV1_NUM_GPIOS]; +}; + +#endif diff --git a/include/sound/wm2000.h b/include/sound/wm2000.h new file mode 100644 index 000000000..affd11073 --- /dev/null +++ b/include/sound/wm2000.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm2000.h -- Platform data for WM2000 + * + * Copyright 2010 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM2000_H +#define __LINUX_SND_WM2000_H + +struct wm2000_platform_data { + /** Filename for system-specific image to download to device. */ + const char *download_file; + + /** Disable speech clarity enhancement, for use when an + * external algorithm is used. */ + unsigned int speech_enh_disable:1; +}; + +#endif diff --git a/include/sound/wm2200.h b/include/sound/wm2200.h new file mode 100644 index 000000000..9987e6c09 --- /dev/null +++ b/include/sound/wm2200.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm2200.h -- Platform data for WM2200 + * + * Copyright 2012 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM2200_H +#define __LINUX_SND_WM2200_H + +#define WM2200_GPIO_SET 0x10000 +#define WM2200_MAX_MICBIAS 2 + +enum wm2200_in_mode { + WM2200_IN_SE = 0, + WM2200_IN_DIFF = 1, + WM2200_IN_DMIC = 2, +}; + +enum wm2200_dmic_sup { + WM2200_DMIC_SUP_MICVDD = 0, + WM2200_DMIC_SUP_MICBIAS1 = 1, + WM2200_DMIC_SUP_MICBIAS2 = 2, +}; + +enum wm2200_mbias_lvl { + WM2200_MBIAS_LVL_1V5 = 1, + WM2200_MBIAS_LVL_1V8 = 2, + WM2200_MBIAS_LVL_1V9 = 3, + WM2200_MBIAS_LVL_2V0 = 4, + WM2200_MBIAS_LVL_2V2 = 5, + WM2200_MBIAS_LVL_2V4 = 6, + WM2200_MBIAS_LVL_2V5 = 7, + WM2200_MBIAS_LVL_2V6 = 8, +}; + +struct wm2200_micbias { + enum wm2200_mbias_lvl mb_lvl; /** Regulated voltage */ + unsigned int discharge:1; /** Actively discharge */ + unsigned int fast_start:1; /** Enable aggressive startup ramp rate */ + unsigned int bypass:1; /** Use bypass mode */ +}; + +struct wm2200_pdata { + int reset; /** GPIO controlling /RESET, if any */ + int ldo_ena; /** GPIO controlling LODENA, if any */ + int irq_flags; + + int gpio_defaults[4]; + + enum wm2200_in_mode in_mode[3]; + enum wm2200_dmic_sup dmic_sup[3]; + + /** MICBIAS configurations */ + struct wm2200_micbias micbias[WM2200_MAX_MICBIAS]; +}; + +#endif diff --git a/include/sound/wm5100.h b/include/sound/wm5100.h new file mode 100644 index 000000000..b94badf72 --- /dev/null +++ b/include/sound/wm5100.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm5100.h -- Platform data for WM5100 + * + * Copyright 2011 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM5100_H +#define __LINUX_SND_WM5100_H + +enum wm5100_in_mode { + WM5100_IN_SE = 0, + WM5100_IN_DIFF = 1, + WM5100_IN_DMIC = 2, +}; + +enum wm5100_dmic_sup { + WM5100_DMIC_SUP_MICVDD = 0, + WM5100_DMIC_SUP_MICBIAS1 = 1, + WM5100_DMIC_SUP_MICBIAS2 = 2, + WM5100_DMIC_SUP_MICBIAS3 = 3, +}; + +enum wm5100_micdet_bias { + WM5100_MICDET_MICBIAS1 = 0, + WM5100_MICDET_MICBIAS2 = 1, + WM5100_MICDET_MICBIAS3 = 2, +}; + +struct wm5100_jack_mode { + enum wm5100_micdet_bias bias; + int hp_pol; + int micd_src; +}; + +#define WM5100_GPIO_SET 0x10000 + +struct wm5100_pdata { + int reset; /** GPIO controlling /RESET, if any */ + int ldo_ena; /** GPIO controlling LODENA, if any */ + int hp_pol; /** GPIO controlling headset polarity, if any */ + int irq_flags; + int gpio_base; + + struct wm5100_jack_mode jack_modes[2]; + + /* Input pin mode selection */ + enum wm5100_in_mode in_mode[4]; + + /* DMIC supply selection */ + enum wm5100_dmic_sup dmic_sup[4]; + + int gpio_defaults[6]; +}; + +#endif diff --git a/include/sound/wm8903.h b/include/sound/wm8903.h new file mode 100644 index 000000000..3e9af639e --- /dev/null +++ b/include/sound/wm8903.h @@ -0,0 +1,263 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm8903.h -- Platform data for WM8903 + * + * Copyright 2010 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM8903_H +#define __LINUX_SND_WM8903_H + +/* + * Used to enable configuration of a GPIO to all zeros; a gpio_cfg value of + * zero in platform data means "don't touch this pin". + */ +#define WM8903_GPIO_CONFIG_ZERO 0x8000 + +/* + * R6 (0x06) - Mic Bias Control 0 + */ +#define WM8903_MICDET_THR_MASK 0x0030 /* MICDET_THR - [5:4] */ +#define WM8903_MICDET_THR_SHIFT 4 /* MICDET_THR - [5:4] */ +#define WM8903_MICDET_THR_WIDTH 2 /* MICDET_THR - [5:4] */ +#define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */ +#define WM8903_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */ +#define WM8903_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */ +#define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */ +#define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */ +#define WM8903_MICDET_ENA_SHIFT 1 /* MICDET_ENA */ +#define WM8903_MICDET_ENA_WIDTH 1 /* MICDET_ENA */ +#define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */ +#define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */ +#define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */ +#define WM8903_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */ + +/* + * WM8903_GPn_FN values + * + * See datasheets for list of valid values per pin + */ +#define WM8903_GPn_FN_GPIO_OUTPUT 0 +#define WM8903_GPn_FN_BCLK 1 +#define WM8903_GPn_FN_IRQ_OUTPT 2 +#define WM8903_GPn_FN_GPIO_INPUT 3 +#define WM8903_GPn_FN_MICBIAS_CURRENT_DETECT 4 +#define WM8903_GPn_FN_MICBIAS_SHORT_DETECT 5 +#define WM8903_GPn_FN_DMIC_LR_CLK_OUTPUT 6 +#define WM8903_GPn_FN_FLL_LOCK_OUTPUT 8 +#define WM8903_GPn_FN_FLL_CLOCK_OUTPUT 9 + +/* + * R116 (0x74) - GPIO Control 1 + */ +#define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */ +#define WM8903_GP1_FN_SHIFT 8 /* GP1_FN - [12:8] */ +#define WM8903_GP1_FN_WIDTH 5 /* GP1_FN - [12:8] */ +#define WM8903_GP1_DIR 0x0080 /* GP1_DIR */ +#define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */ +#define WM8903_GP1_DIR_SHIFT 7 /* GP1_DIR */ +#define WM8903_GP1_DIR_WIDTH 1 /* GP1_DIR */ +#define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */ +#define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */ +#define WM8903_GP1_OP_CFG_SHIFT 6 /* GP1_OP_CFG */ +#define WM8903_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */ +#define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */ +#define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */ +#define WM8903_GP1_IP_CFG_SHIFT 5 /* GP1_IP_CFG */ +#define WM8903_GP1_IP_CFG_WIDTH 1 /* GP1_IP_CFG */ +#define WM8903_GP1_LVL 0x0010 /* GP1_LVL */ +#define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */ +#define WM8903_GP1_LVL_SHIFT 4 /* GP1_LVL */ +#define WM8903_GP1_LVL_WIDTH 1 /* GP1_LVL */ +#define WM8903_GP1_PD 0x0008 /* GP1_PD */ +#define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */ +#define WM8903_GP1_PD_SHIFT 3 /* GP1_PD */ +#define WM8903_GP1_PD_WIDTH 1 /* GP1_PD */ +#define WM8903_GP1_PU 0x0004 /* GP1_PU */ +#define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */ +#define WM8903_GP1_PU_SHIFT 2 /* GP1_PU */ +#define WM8903_GP1_PU_WIDTH 1 /* GP1_PU */ +#define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */ +#define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */ +#define WM8903_GP1_INTMODE_SHIFT 1 /* GP1_INTMODE */ +#define WM8903_GP1_INTMODE_WIDTH 1 /* GP1_INTMODE */ +#define WM8903_GP1_DB 0x0001 /* GP1_DB */ +#define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */ +#define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */ +#define WM8903_GP1_DB_WIDTH 1 /* GP1_DB */ + +/* + * R117 (0x75) - GPIO Control 2 + */ +#define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */ +#define WM8903_GP2_FN_SHIFT 8 /* GP2_FN - [12:8] */ +#define WM8903_GP2_FN_WIDTH 5 /* GP2_FN - [12:8] */ +#define WM8903_GP2_DIR 0x0080 /* GP2_DIR */ +#define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */ +#define WM8903_GP2_DIR_SHIFT 7 /* GP2_DIR */ +#define WM8903_GP2_DIR_WIDTH 1 /* GP2_DIR */ +#define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */ +#define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */ +#define WM8903_GP2_OP_CFG_SHIFT 6 /* GP2_OP_CFG */ +#define WM8903_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */ +#define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */ +#define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */ +#define WM8903_GP2_IP_CFG_SHIFT 5 /* GP2_IP_CFG */ +#define WM8903_GP2_IP_CFG_WIDTH 1 /* GP2_IP_CFG */ +#define WM8903_GP2_LVL 0x0010 /* GP2_LVL */ +#define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */ +#define WM8903_GP2_LVL_SHIFT 4 /* GP2_LVL */ +#define WM8903_GP2_LVL_WIDTH 1 /* GP2_LVL */ +#define WM8903_GP2_PD 0x0008 /* GP2_PD */ +#define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */ +#define WM8903_GP2_PD_SHIFT 3 /* GP2_PD */ +#define WM8903_GP2_PD_WIDTH 1 /* GP2_PD */ +#define WM8903_GP2_PU 0x0004 /* GP2_PU */ +#define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */ +#define WM8903_GP2_PU_SHIFT 2 /* GP2_PU */ +#define WM8903_GP2_PU_WIDTH 1 /* GP2_PU */ +#define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */ +#define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */ +#define WM8903_GP2_INTMODE_SHIFT 1 /* GP2_INTMODE */ +#define WM8903_GP2_INTMODE_WIDTH 1 /* GP2_INTMODE */ +#define WM8903_GP2_DB 0x0001 /* GP2_DB */ +#define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */ +#define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */ +#define WM8903_GP2_DB_WIDTH 1 /* GP2_DB */ + +/* + * R118 (0x76) - GPIO Control 3 + */ +#define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */ +#define WM8903_GP3_FN_SHIFT 8 /* GP3_FN - [12:8] */ +#define WM8903_GP3_FN_WIDTH 5 /* GP3_FN - [12:8] */ +#define WM8903_GP3_DIR 0x0080 /* GP3_DIR */ +#define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */ +#define WM8903_GP3_DIR_SHIFT 7 /* GP3_DIR */ +#define WM8903_GP3_DIR_WIDTH 1 /* GP3_DIR */ +#define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */ +#define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */ +#define WM8903_GP3_OP_CFG_SHIFT 6 /* GP3_OP_CFG */ +#define WM8903_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */ +#define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */ +#define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */ +#define WM8903_GP3_IP_CFG_SHIFT 5 /* GP3_IP_CFG */ +#define WM8903_GP3_IP_CFG_WIDTH 1 /* GP3_IP_CFG */ +#define WM8903_GP3_LVL 0x0010 /* GP3_LVL */ +#define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */ +#define WM8903_GP3_LVL_SHIFT 4 /* GP3_LVL */ +#define WM8903_GP3_LVL_WIDTH 1 /* GP3_LVL */ +#define WM8903_GP3_PD 0x0008 /* GP3_PD */ +#define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */ +#define WM8903_GP3_PD_SHIFT 3 /* GP3_PD */ +#define WM8903_GP3_PD_WIDTH 1 /* GP3_PD */ +#define WM8903_GP3_PU 0x0004 /* GP3_PU */ +#define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */ +#define WM8903_GP3_PU_SHIFT 2 /* GP3_PU */ +#define WM8903_GP3_PU_WIDTH 1 /* GP3_PU */ +#define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */ +#define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */ +#define WM8903_GP3_INTMODE_SHIFT 1 /* GP3_INTMODE */ +#define WM8903_GP3_INTMODE_WIDTH 1 /* GP3_INTMODE */ +#define WM8903_GP3_DB 0x0001 /* GP3_DB */ +#define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */ +#define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */ +#define WM8903_GP3_DB_WIDTH 1 /* GP3_DB */ + +/* + * R119 (0x77) - GPIO Control 4 + */ +#define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */ +#define WM8903_GP4_FN_SHIFT 8 /* GP4_FN - [12:8] */ +#define WM8903_GP4_FN_WIDTH 5 /* GP4_FN - [12:8] */ +#define WM8903_GP4_DIR 0x0080 /* GP4_DIR */ +#define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */ +#define WM8903_GP4_DIR_SHIFT 7 /* GP4_DIR */ +#define WM8903_GP4_DIR_WIDTH 1 /* GP4_DIR */ +#define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */ +#define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */ +#define WM8903_GP4_OP_CFG_SHIFT 6 /* GP4_OP_CFG */ +#define WM8903_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */ +#define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */ +#define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */ +#define WM8903_GP4_IP_CFG_SHIFT 5 /* GP4_IP_CFG */ +#define WM8903_GP4_IP_CFG_WIDTH 1 /* GP4_IP_CFG */ +#define WM8903_GP4_LVL 0x0010 /* GP4_LVL */ +#define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */ +#define WM8903_GP4_LVL_SHIFT 4 /* GP4_LVL */ +#define WM8903_GP4_LVL_WIDTH 1 /* GP4_LVL */ +#define WM8903_GP4_PD 0x0008 /* GP4_PD */ +#define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */ +#define WM8903_GP4_PD_SHIFT 3 /* GP4_PD */ +#define WM8903_GP4_PD_WIDTH 1 /* GP4_PD */ +#define WM8903_GP4_PU 0x0004 /* GP4_PU */ +#define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */ +#define WM8903_GP4_PU_SHIFT 2 /* GP4_PU */ +#define WM8903_GP4_PU_WIDTH 1 /* GP4_PU */ +#define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */ +#define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */ +#define WM8903_GP4_INTMODE_SHIFT 1 /* GP4_INTMODE */ +#define WM8903_GP4_INTMODE_WIDTH 1 /* GP4_INTMODE */ +#define WM8903_GP4_DB 0x0001 /* GP4_DB */ +#define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */ +#define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */ +#define WM8903_GP4_DB_WIDTH 1 /* GP4_DB */ + +/* + * R120 (0x78) - GPIO Control 5 + */ +#define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */ +#define WM8903_GP5_FN_SHIFT 8 /* GP5_FN - [12:8] */ +#define WM8903_GP5_FN_WIDTH 5 /* GP5_FN - [12:8] */ +#define WM8903_GP5_DIR 0x0080 /* GP5_DIR */ +#define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */ +#define WM8903_GP5_DIR_SHIFT 7 /* GP5_DIR */ +#define WM8903_GP5_DIR_WIDTH 1 /* GP5_DIR */ +#define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */ +#define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */ +#define WM8903_GP5_OP_CFG_SHIFT 6 /* GP5_OP_CFG */ +#define WM8903_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */ +#define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */ +#define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */ +#define WM8903_GP5_IP_CFG_SHIFT 5 /* GP5_IP_CFG */ +#define WM8903_GP5_IP_CFG_WIDTH 1 /* GP5_IP_CFG */ +#define WM8903_GP5_LVL 0x0010 /* GP5_LVL */ +#define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */ +#define WM8903_GP5_LVL_SHIFT 4 /* GP5_LVL */ +#define WM8903_GP5_LVL_WIDTH 1 /* GP5_LVL */ +#define WM8903_GP5_PD 0x0008 /* GP5_PD */ +#define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */ +#define WM8903_GP5_PD_SHIFT 3 /* GP5_PD */ +#define WM8903_GP5_PD_WIDTH 1 /* GP5_PD */ +#define WM8903_GP5_PU 0x0004 /* GP5_PU */ +#define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */ +#define WM8903_GP5_PU_SHIFT 2 /* GP5_PU */ +#define WM8903_GP5_PU_WIDTH 1 /* GP5_PU */ +#define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */ +#define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */ +#define WM8903_GP5_INTMODE_SHIFT 1 /* GP5_INTMODE */ +#define WM8903_GP5_INTMODE_WIDTH 1 /* GP5_INTMODE */ +#define WM8903_GP5_DB 0x0001 /* GP5_DB */ +#define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */ +#define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */ +#define WM8903_GP5_DB_WIDTH 1 /* GP5_DB */ + +#define WM8903_NUM_GPIO 5 + +struct wm8903_platform_data { + bool irq_active_low; /* Set if IRQ active low, default high */ + + /* Default register value for R6 (Mic bias), used to configure + * microphone detection. In conjunction with gpio_cfg this + * can be used to route the microphone status signals out onto + * the GPIOs for use with snd_soc_jack_add_gpios(). + */ + u16 micdet_cfg; + + int micdet_delay; /* Delay after microphone detection (ms) */ + + int gpio_base; + u32 gpio_cfg[WM8903_NUM_GPIO]; /* Default register values for GPIO pin mux */ +}; + +#endif diff --git a/include/sound/wm8904.h b/include/sound/wm8904.h new file mode 100644 index 000000000..88ac18705 --- /dev/null +++ b/include/sound/wm8904.h @@ -0,0 +1,158 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Platform data for WM8904 + * + * Copyright 2009 Wolfson Microelectronics PLC. + * + * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> + */ + +#ifndef __MFD_WM8994_PDATA_H__ +#define __MFD_WM8994_PDATA_H__ + +/* Used to enable configuration of a GPIO to all zeros */ +#define WM8904_GPIO_NO_CONFIG 0x8000 + +/* + * R6 (0x06) - Mic Bias Control 0 + */ +#define WM8904_MICDET_THR_MASK 0x0070 /* MICDET_THR - [6:4] */ +#define WM8904_MICDET_THR_SHIFT 4 /* MICDET_THR - [6:4] */ +#define WM8904_MICDET_THR_WIDTH 3 /* MICDET_THR - [6:4] */ +#define WM8904_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */ +#define WM8904_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */ +#define WM8904_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */ +#define WM8904_MICDET_ENA 0x0002 /* MICDET_ENA */ +#define WM8904_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */ +#define WM8904_MICDET_ENA_SHIFT 1 /* MICDET_ENA */ +#define WM8904_MICDET_ENA_WIDTH 1 /* MICDET_ENA */ +#define WM8904_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */ +#define WM8904_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */ +#define WM8904_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */ +#define WM8904_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */ + +/* + * R7 (0x07) - Mic Bias Control 1 + */ +#define WM8904_MIC_DET_FILTER_ENA 0x8000 /* MIC_DET_FILTER_ENA */ +#define WM8904_MIC_DET_FILTER_ENA_MASK 0x8000 /* MIC_DET_FILTER_ENA */ +#define WM8904_MIC_DET_FILTER_ENA_SHIFT 15 /* MIC_DET_FILTER_ENA */ +#define WM8904_MIC_DET_FILTER_ENA_WIDTH 1 /* MIC_DET_FILTER_ENA */ +#define WM8904_MIC_SHORT_FILTER_ENA 0x4000 /* MIC_SHORT_FILTER_ENA */ +#define WM8904_MIC_SHORT_FILTER_ENA_MASK 0x4000 /* MIC_SHORT_FILTER_ENA */ +#define WM8904_MIC_SHORT_FILTER_ENA_SHIFT 14 /* MIC_SHORT_FILTER_ENA */ +#define WM8904_MIC_SHORT_FILTER_ENA_WIDTH 1 /* MIC_SHORT_FILTER_ENA */ +#define WM8904_MICBIAS_SEL_MASK 0x0007 /* MICBIAS_SEL - [2:0] */ +#define WM8904_MICBIAS_SEL_SHIFT 0 /* MICBIAS_SEL - [2:0] */ +#define WM8904_MICBIAS_SEL_WIDTH 3 /* MICBIAS_SEL - [2:0] */ + + +/* + * R121 (0x79) - GPIO Control 1 + */ +#define WM8904_GPIO1_PU 0x0020 /* GPIO1_PU */ +#define WM8904_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */ +#define WM8904_GPIO1_PU_SHIFT 5 /* GPIO1_PU */ +#define WM8904_GPIO1_PU_WIDTH 1 /* GPIO1_PU */ +#define WM8904_GPIO1_PD 0x0010 /* GPIO1_PD */ +#define WM8904_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */ +#define WM8904_GPIO1_PD_SHIFT 4 /* GPIO1_PD */ +#define WM8904_GPIO1_PD_WIDTH 1 /* GPIO1_PD */ +#define WM8904_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */ +#define WM8904_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */ +#define WM8904_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */ + +/* + * R122 (0x7A) - GPIO Control 2 + */ +#define WM8904_GPIO2_PU 0x0020 /* GPIO2_PU */ +#define WM8904_GPIO2_PU_MASK 0x0020 /* GPIO2_PU */ +#define WM8904_GPIO2_PU_SHIFT 5 /* GPIO2_PU */ +#define WM8904_GPIO2_PU_WIDTH 1 /* GPIO2_PU */ +#define WM8904_GPIO2_PD 0x0010 /* GPIO2_PD */ +#define WM8904_GPIO2_PD_MASK 0x0010 /* GPIO2_PD */ +#define WM8904_GPIO2_PD_SHIFT 4 /* GPIO2_PD */ +#define WM8904_GPIO2_PD_WIDTH 1 /* GPIO2_PD */ +#define WM8904_GPIO2_SEL_MASK 0x000F /* GPIO2_SEL - [3:0] */ +#define WM8904_GPIO2_SEL_SHIFT 0 /* GPIO2_SEL - [3:0] */ +#define WM8904_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [3:0] */ + +/* + * R123 (0x7B) - GPIO Control 3 + */ +#define WM8904_GPIO3_PU 0x0020 /* GPIO3_PU */ +#define WM8904_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */ +#define WM8904_GPIO3_PU_SHIFT 5 /* GPIO3_PU */ +#define WM8904_GPIO3_PU_WIDTH 1 /* GPIO3_PU */ +#define WM8904_GPIO3_PD 0x0010 /* GPIO3_PD */ +#define WM8904_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */ +#define WM8904_GPIO3_PD_SHIFT 4 /* GPIO3_PD */ +#define WM8904_GPIO3_PD_WIDTH 1 /* GPIO3_PD */ +#define WM8904_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */ +#define WM8904_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */ +#define WM8904_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */ + +/* + * R124 (0x7C) - GPIO Control 4 + */ +#define WM8904_GPI7_ENA 0x0200 /* GPI7_ENA */ +#define WM8904_GPI7_ENA_MASK 0x0200 /* GPI7_ENA */ +#define WM8904_GPI7_ENA_SHIFT 9 /* GPI7_ENA */ +#define WM8904_GPI7_ENA_WIDTH 1 /* GPI7_ENA */ +#define WM8904_GPI8_ENA 0x0100 /* GPI8_ENA */ +#define WM8904_GPI8_ENA_MASK 0x0100 /* GPI8_ENA */ +#define WM8904_GPI8_ENA_SHIFT 8 /* GPI8_ENA */ +#define WM8904_GPI8_ENA_WIDTH 1 /* GPI8_ENA */ +#define WM8904_GPIO_BCLK_MODE_ENA 0x0080 /* GPIO_BCLK_MODE_ENA */ +#define WM8904_GPIO_BCLK_MODE_ENA_MASK 0x0080 /* GPIO_BCLK_MODE_ENA */ +#define WM8904_GPIO_BCLK_MODE_ENA_SHIFT 7 /* GPIO_BCLK_MODE_ENA */ +#define WM8904_GPIO_BCLK_MODE_ENA_WIDTH 1 /* GPIO_BCLK_MODE_ENA */ +#define WM8904_GPIO_BCLK_SEL_MASK 0x000F /* GPIO_BCLK_SEL - [3:0] */ +#define WM8904_GPIO_BCLK_SEL_SHIFT 0 /* GPIO_BCLK_SEL - [3:0] */ +#define WM8904_GPIO_BCLK_SEL_WIDTH 4 /* GPIO_BCLK_SEL - [3:0] */ + +#define WM8904_MIC_REGS 2 +#define WM8904_GPIO_REGS 4 +#define WM8904_DRC_REGS 4 +#define WM8904_EQ_REGS 24 + +/** + * DRC configurations are specified with a label and a set of register + * values to write (the enable bits will be ignored). At runtime an + * enumerated control will be presented for each DRC block allowing + * the user to choose the configuration to use. + * + * Configurations may be generated by hand or by using the DRC control + * panel provided by the WISCE - see http://www.wolfsonmicro.com/wisce/ + * for details. + */ +struct wm8904_drc_cfg { + const char *name; + u16 regs[WM8904_DRC_REGS]; +}; + +/** + * ReTune Mobile configurations are specified with a label, sample + * rate and set of values to write (the enable bits will be ignored). + * + * Configurations are expected to be generated using the ReTune Mobile + * control panel in WISCE - see http://www.wolfsonmicro.com/wisce/ + */ +struct wm8904_retune_mobile_cfg { + const char *name; + unsigned int rate; + u16 regs[WM8904_EQ_REGS]; +}; + +struct wm8904_pdata { + int num_drc_cfgs; + struct wm8904_drc_cfg *drc_cfgs; + + int num_retune_mobile_cfgs; + struct wm8904_retune_mobile_cfg *retune_mobile_cfgs; + + u32 gpio_cfg[WM8904_GPIO_REGS]; + u32 mic_cfg[WM8904_MIC_REGS]; +}; + +#endif diff --git a/include/sound/wm8955.h b/include/sound/wm8955.h new file mode 100644 index 000000000..62c5fa1e1 --- /dev/null +++ b/include/sound/wm8955.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Platform data for WM8955 + * + * Copyright 2009 Wolfson Microelectronics PLC. + * + * Author: Mark Brown <broonie@opensource.wolfsonmicro.com> + */ + +#ifndef __WM8955_PDATA_H__ +#define __WM8955_PDATA_H__ + +struct wm8955_pdata { + /* Configure LOUT2/ROUT2 to drive a speaker */ + unsigned int out2_speaker:1; + + /* Configure MONOIN+/- in differential mode */ + unsigned int monoin_diff:1; +}; + +#endif diff --git a/include/sound/wm8960.h b/include/sound/wm8960.h new file mode 100644 index 000000000..275fd5b20 --- /dev/null +++ b/include/sound/wm8960.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * wm8960.h -- WM8960 Soc Audio driver platform data + */ + +#ifndef _WM8960_PDATA_H +#define _WM8960_PDATA_H + +#define WM8960_DRES_400R 0 +#define WM8960_DRES_200R 1 +#define WM8960_DRES_600R 2 +#define WM8960_DRES_150R 3 +#define WM8960_DRES_MAX 3 + +struct wm8960_data { + bool capless; /* Headphone outputs configured in capless mode */ + + bool shared_lrclk; /* DAC and ADC LRCLKs are wired together */ + + /* + * Setup for headphone detection + * + * hp_cfg[0]: HPSEL[1:0] of R48 (Additional Control 4) + * hp_cfg[1]: {HPSWEN:HPSWPOL} of R24 (Additional Control 2). + * hp_cfg[2]: {TOCLKSEL:TOEN} of R23 (Additional Control 1). + */ + u32 hp_cfg[3]; + + /* + * Setup for gpio configuration + * + * gpio_cfg[0]: ALRCGPIO of R9 (Audio interface) + * gpio_cfg[1]: {GPIOPOL:GPIOSEL[2:0]} of R48 (Additional Control 4). + */ + u32 gpio_cfg[2]; +}; + +#endif diff --git a/include/sound/wm8962.h b/include/sound/wm8962.h new file mode 100644 index 000000000..f77722573 --- /dev/null +++ b/include/sound/wm8962.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * wm8962.h -- WM8962 Soc Audio driver platform data + */ + +#ifndef _WM8962_PDATA_H +#define _WM8962_PDATA_H + +#define WM8962_MAX_GPIO 6 + +/* Use to set GPIO default values to zero */ +#define WM8962_GPIO_SET 0x10000 + +#define WM8962_GPIO_FN_CLKOUT 0 +#define WM8962_GPIO_FN_LOGIC 1 +#define WM8962_GPIO_FN_SDOUT 2 +#define WM8962_GPIO_FN_IRQ 3 +#define WM8962_GPIO_FN_THERMAL 4 +#define WM8962_GPIO_FN_PLL2_LOCK 6 +#define WM8962_GPIO_FN_PLL3_LOCK 7 +#define WM8962_GPIO_FN_FLL_LOCK 9 +#define WM8962_GPIO_FN_DRC_ACT 10 +#define WM8962_GPIO_FN_WSEQ_DONE 11 +#define WM8962_GPIO_FN_ALC_NG_ACT 12 +#define WM8962_GPIO_FN_ALC_PEAK_LIMIT 13 +#define WM8962_GPIO_FN_ALC_SATURATION 14 +#define WM8962_GPIO_FN_ALC_LEVEL_THR 15 +#define WM8962_GPIO_FN_ALC_LEVEL_LOCK 16 +#define WM8962_GPIO_FN_FIFO_ERR 17 +#define WM8962_GPIO_FN_OPCLK 18 +#define WM8962_GPIO_FN_DMICCLK 19 +#define WM8962_GPIO_FN_DMICDAT 20 +#define WM8962_GPIO_FN_MICD 21 +#define WM8962_GPIO_FN_MICSCD 22 + +struct wm8962_pdata { + struct clk *mclk; + int gpio_base; + u32 gpio_init[WM8962_MAX_GPIO]; + + /* Setup for microphone detection, raw value to be written to + * R48(0x30) - only microphone related bits will be updated. + * Detection may be enabled here for use with signals brought + * out on the GPIOs. */ + u32 mic_cfg; + + bool irq_active_low; + + bool spk_mono; /* Speaker outputs tied together as mono */ + + /** + * This flag should be set if one or both IN4 inputs is wired + * in a DC measurement configuration. + */ + bool in4_dc_measure; +}; + +#endif diff --git a/include/sound/wm8993.h b/include/sound/wm8993.h new file mode 100644 index 000000000..8cf9de85d --- /dev/null +++ b/include/sound/wm8993.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm8993.h -- Platform data for WM8993 + * + * Copyright 2009 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM8993_H +#define __LINUX_SND_WM8993_H + +/* Note that EQ1 only contains the enable/disable bit so will be + ignored but is included for simplicity. + */ +struct wm8993_retune_mobile_setting { + const char *name; + unsigned int rate; + u16 config[24]; +}; + +struct wm8993_platform_data { + struct wm8993_retune_mobile_setting *retune_configs; + int num_retune_configs; + + /* LINEOUT can be differential or single ended */ + unsigned int lineout1_diff:1; + unsigned int lineout2_diff:1; + + /* Common mode feedback */ + unsigned int lineout1fb:1; + unsigned int lineout2fb:1; + + /* Delay to add for microphones to stabalise after power up */ + int micbias1_delay; + int micbias2_delay; + + /* Microphone biases: 0=0.9*AVDD1 1=0.65*AVVD1 */ + unsigned int micbias1_lvl:1; + unsigned int micbias2_lvl:1; + + /* Jack detect threshold levels, see datasheet for values */ + unsigned int jd_scthr:2; + unsigned int jd_thr:2; +}; + +#endif diff --git a/include/sound/wm8996.h b/include/sound/wm8996.h new file mode 100644 index 000000000..247f9917e --- /dev/null +++ b/include/sound/wm8996.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm8996.h -- Platform data for WM8996 + * + * Copyright 2011 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM8996_H +#define __LINUX_SND_WM8996_H + +enum wm8996_inmode { + WM8996_DIFFERRENTIAL_1 = 0, /* IN1xP - IN1xN */ + WM8996_INVERTING = 1, /* IN1xN */ + WM8996_NON_INVERTING = 2, /* IN1xP */ + WM8996_DIFFERENTIAL_2 = 3, /* IN2xP - IN2xP */ +}; + +/** + * ReTune Mobile configurations are specified with a label, sample + * rate and set of values to write (the enable bits will be ignored). + * + * Configurations are expected to be generated using the ReTune Mobile + * control panel in WISCE - see http://www.wolfsonmicro.com/wisce/ + */ +struct wm8996_retune_mobile_config { + const char *name; + int rate; + u16 regs[20]; +}; + +#define WM8996_SET_DEFAULT 0x10000 + +struct wm8996_pdata { + int irq_flags; /** Set IRQ trigger flags; default active low */ + + int ldo_ena; /** GPIO for LDO1; -1 for none */ + + int micdet_def; /** Default MICDET_SRC/HP1FB_SRC/MICD_BIAS */ + + enum wm8996_inmode inl_mode; + enum wm8996_inmode inr_mode; + + u32 spkmute_seq; /** Value for register 0x802 */ + + int gpio_base; + u32 gpio_default[5]; + + int num_retune_mobile_cfgs; + struct wm8996_retune_mobile_config *retune_mobile_cfgs; +}; + +#endif diff --git a/include/sound/wm9081.h b/include/sound/wm9081.h new file mode 100644 index 000000000..2fd4bec8a --- /dev/null +++ b/include/sound/wm9081.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm9081.h -- Platform data for WM9081 + * + * Copyright 2009 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM_9081_H +#define __LINUX_SND_WM_9081_H + +struct wm9081_retune_mobile_setting { + const char *name; + unsigned int rate; + u16 config[20]; +}; + +struct wm9081_pdata { + bool irq_high; /* IRQ is active high */ + bool irq_cmos; /* IRQ is in CMOS mode */ + + struct wm9081_retune_mobile_setting *retune_configs; + int num_retune_configs; +}; + +#endif diff --git a/include/sound/wm9090.h b/include/sound/wm9090.h new file mode 100644 index 000000000..0dd2c9397 --- /dev/null +++ b/include/sound/wm9090.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * linux/sound/wm9090.h -- Platform data for WM9090 + * + * Copyright 2009, 2010 Wolfson Microelectronics. PLC. + */ + +#ifndef __LINUX_SND_WM9090_H +#define __LINUX_SND_WM9090_H + +struct wm9090_platform_data { + /* Line inputs 1 & 2 can optionally be differential */ + unsigned int lin1_diff:1; + unsigned int lin2_diff:1; + + /* AGC configuration. This is intended to protect the speaker + * against overdriving and will therefore depend on the + * hardware setup with incorrect runtime configuration + * potentially causing hardware damage. + */ + unsigned int agc_ena:1; + u16 agc[3]; +}; + +#endif diff --git a/include/sound/wss.h b/include/sound/wss.h new file mode 100644 index 000000000..4bdbb8c57 --- /dev/null +++ b/include/sound/wss.h @@ -0,0 +1,220 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef __SOUND_WSS_H +#define __SOUND_WSS_H + +/* + * Copyright (c) by Jaroslav Kysela <perex@perex.cz> + * Definitions for CS4231 & InterWave chips & compatible chips + */ + +#include <sound/control.h> +#include <sound/pcm.h> +#include <sound/timer.h> + +#include <sound/cs4231-regs.h> + +/* defines for codec.mode */ + +#define WSS_MODE_NONE 0x0000 +#define WSS_MODE_PLAY 0x0001 +#define WSS_MODE_RECORD 0x0002 +#define WSS_MODE_TIMER 0x0004 +#define WSS_MODE_OPEN (WSS_MODE_PLAY|WSS_MODE_RECORD|WSS_MODE_TIMER) + +/* defines for codec.hardware */ + +#define WSS_HW_DETECT 0x0000 /* let CS4231 driver detect chip */ +#define WSS_HW_DETECT3 0x0001 /* allow mode 3 */ +#define WSS_HW_TYPE_MASK 0xff00 /* type mask */ +#define WSS_HW_CS4231_MASK 0x0100 /* CS4231 serie */ +#define WSS_HW_CS4231 0x0100 /* CS4231 chip */ +#define WSS_HW_CS4231A 0x0101 /* CS4231A chip */ +#define WSS_HW_AD1845 0x0102 /* AD1845 chip */ +#define WSS_HW_CS4232_MASK 0x0200 /* CS4232 serie (has control ports) */ +#define WSS_HW_CS4232 0x0200 /* CS4232 */ +#define WSS_HW_CS4232A 0x0201 /* CS4232A */ +#define WSS_HW_CS4236 0x0202 /* CS4236 */ +#define WSS_HW_CS4236B_MASK 0x0400 /* CS4236B serie (has extended control regs) */ +#define WSS_HW_CS4235 0x0400 /* CS4235 - Crystal Clear (tm) stereo enhancement */ +#define WSS_HW_CS4236B 0x0401 /* CS4236B */ +#define WSS_HW_CS4237B 0x0402 /* CS4237B - SRS 3D */ +#define WSS_HW_CS4238B 0x0403 /* CS4238B - QSOUND 3D */ +#define WSS_HW_CS4239 0x0404 /* CS4239 - Crystal Clear (tm) stereo enhancement */ +#define WSS_HW_AD1848_MASK 0x0800 /* AD1848 serie (half duplex) */ +#define WSS_HW_AD1847 0x0801 /* AD1847 chip */ +#define WSS_HW_AD1848 0x0802 /* AD1848 chip */ +#define WSS_HW_CS4248 0x0803 /* CS4248 chip */ +#define WSS_HW_CMI8330 0x0804 /* CMI8330 chip */ +#define WSS_HW_THINKPAD 0x0805 /* Thinkpad 360/750/755 */ +/* compatible, but clones */ +#define WSS_HW_INTERWAVE 0x1000 /* InterWave chip */ +#define WSS_HW_OPL3SA2 0x1101 /* OPL3-SA2 chip, similar to cs4231 */ +#define WSS_HW_OPTI93X 0x1102 /* Opti 930/931/933 */ + +/* defines for codec.hwshare */ +#define WSS_HWSHARE_IRQ (1<<0) +#define WSS_HWSHARE_DMA1 (1<<1) +#define WSS_HWSHARE_DMA2 (1<<2) + +/* IBM Thinkpad specific stuff */ +#define AD1848_THINKPAD_CTL_PORT1 0x15e8 +#define AD1848_THINKPAD_CTL_PORT2 0x15e9 +#define AD1848_THINKPAD_CS4248_ENABLE_BIT 0x02 + +struct snd_wss { + unsigned long port; /* base i/o port */ + struct resource *res_port; + unsigned long cport; /* control base i/o port (CS4236) */ + struct resource *res_cport; + int irq; /* IRQ line */ + int dma1; /* playback DMA */ + int dma2; /* record DMA */ + unsigned short version; /* version of CODEC chip */ + unsigned short mode; /* see to WSS_MODE_XXXX */ + unsigned short hardware; /* see to WSS_HW_XXXX */ + unsigned short hwshare; /* shared resources */ + unsigned short single_dma:1, /* forced single DMA mode (GUS 16-bit */ + /* daughter board) or dma1 == dma2 */ + ebus_flag:1, /* SPARC: EBUS present */ + thinkpad_flag:1; /* Thinkpad CS4248 needs extra help */ + + struct snd_card *card; + struct snd_pcm *pcm; + struct snd_pcm_substream *playback_substream; + struct snd_pcm_substream *capture_substream; + struct snd_timer *timer; + + unsigned char image[32]; /* registers image */ + unsigned char eimage[32]; /* extended registers image */ + unsigned char cimage[16]; /* control registers image */ + int mce_bit; + int calibrate_mute; + int sw_3d_bit; + unsigned int p_dma_size; + unsigned int c_dma_size; + + spinlock_t reg_lock; + struct mutex mce_mutex; + struct mutex open_mutex; + + int (*rate_constraint) (struct snd_pcm_runtime *runtime); + void (*set_playback_format) (struct snd_wss *chip, + struct snd_pcm_hw_params *hw_params, + unsigned char pdfr); + void (*set_capture_format) (struct snd_wss *chip, + struct snd_pcm_hw_params *hw_params, + unsigned char cdfr); + void (*trigger) (struct snd_wss *chip, unsigned int what, int start); +#ifdef CONFIG_PM + void (*suspend) (struct snd_wss *chip); + void (*resume) (struct snd_wss *chip); +#endif + void *dma_private_data; + int (*claim_dma) (struct snd_wss *chip, + void *dma_private_data, int dma); + int (*release_dma) (struct snd_wss *chip, + void *dma_private_data, int dma); +}; + +/* exported functions */ + +void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char val); +unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg); +void snd_cs4236_ext_out(struct snd_wss *chip, + unsigned char reg, unsigned char val); +unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg); +void snd_wss_mce_up(struct snd_wss *chip); +void snd_wss_mce_down(struct snd_wss *chip); + +void snd_wss_overrange(struct snd_wss *chip); + +irqreturn_t snd_wss_interrupt(int irq, void *dev_id); + +const char *snd_wss_chip_id(struct snd_wss *chip); + +int snd_wss_create(struct snd_card *card, + unsigned long port, + unsigned long cport, + int irq, int dma1, int dma2, + unsigned short hardware, + unsigned short hwshare, + struct snd_wss **rchip); +int snd_wss_pcm(struct snd_wss *chip, int device); +int snd_wss_timer(struct snd_wss *chip, int device); +int snd_wss_mixer(struct snd_wss *chip); + +const struct snd_pcm_ops *snd_wss_get_pcm_ops(int direction); + +int snd_cs4236_create(struct snd_card *card, + unsigned long port, + unsigned long cport, + int irq, int dma1, int dma2, + unsigned short hardware, + unsigned short hwshare, + struct snd_wss **rchip); +int snd_cs4236_pcm(struct snd_wss *chip, int device); +int snd_cs4236_mixer(struct snd_wss *chip); + +/* + * mixer library + */ + +#define WSS_SINGLE(xname, xindex, reg, shift, mask, invert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ + .name = xname, \ + .index = xindex, \ + .info = snd_wss_info_single, \ + .get = snd_wss_get_single, \ + .put = snd_wss_put_single, \ + .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) } + +int snd_wss_info_single(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_wss_get_single(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_wss_put_single(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +#define WSS_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ + .name = xname, \ + .index = xindex, \ + .info = snd_wss_info_double, \ + .get = snd_wss_get_double, \ + .put = snd_wss_put_double, \ + .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | \ + (shift_right << 19) | (mask << 24) | (invert << 22) } + +#define WSS_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \ + .name = xname, \ + .index = xindex, \ + .info = snd_wss_info_single, \ + .get = snd_wss_get_single, \ + .put = snd_wss_put_single, \ + .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \ + .tlv = { .p = (xtlv) } } + +#define WSS_DOUBLE_TLV(xname, xindex, left_reg, right_reg, \ + shift_left, shift_right, mask, invert, xtlv) \ +{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \ + .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \ + .name = xname, \ + .index = xindex, \ + .info = snd_wss_info_double, \ + .get = snd_wss_get_double, \ + .put = snd_wss_put_double, \ + .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | \ + (shift_right << 19) | (mask << 24) | (invert << 22), \ + .tlv = { .p = (xtlv) } } + + +int snd_wss_info_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_info *uinfo); +int snd_wss_get_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); +int snd_wss_put_double(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol); + +#endif /* __SOUND_WSS_H */ |