Adding upstream version 6.1.76.upstream/6.1.76upstream

Signed-off-by: Daniel Baumann <daniel.baumann@progress-linux.org>

7 files changed, 2182 insertions, 0 deletions

diff --git a/tools/perf/pmu-events/arch/x86/bonnell/cache.json b/tools/perf/pmu-events/arch/x86/bonnell/cache.json
new file mode 100644
index 000000000..86582bb8a
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/bonnell/cache.json
@@ -0,0 +1,746 @@
+[
+    {
+        "BriefDescription": "L1 Data Cacheable reads and writes",
+        "Counter": "0,1",
+        "EventCode": "0x40",
+        "EventName": "L1D_CACHE.ALL_CACHE_REF",
+        "SampleAfterValue": "2000000",
+        "UMask": "0xa3"
+    },
+    {
+        "BriefDescription": "L1 Data reads and writes",
+        "Counter": "0,1",
+        "EventCode": "0x40",
+        "EventName": "L1D_CACHE.ALL_REF",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x83"
+    },
+    {
+        "BriefDescription": "Modified cache lines evicted from the L1 data cache",
+        "Counter": "0,1",
+        "EventCode": "0x40",
+        "EventName": "L1D_CACHE.EVICT",
+        "SampleAfterValue": "200000",
+        "UMask": "0x10"
+    },
+    {
+        "BriefDescription": "L1 Cacheable Data Reads",
+        "Counter": "0,1",
+        "EventCode": "0x40",
+        "EventName": "L1D_CACHE.LD",
+        "SampleAfterValue": "2000000",
+        "UMask": "0xa1"
+    },
+    {
+        "BriefDescription": "L1 Data line replacements",
+        "Counter": "0,1",
+        "EventCode": "0x40",
+        "EventName": "L1D_CACHE.REPL",
+        "SampleAfterValue": "200000",
+        "UMask": "0x8"
+    },
+    {
+        "BriefDescription": "Modified cache lines allocated in the L1 data cache",
+        "Counter": "0,1",
+        "EventCode": "0x40",
+        "EventName": "L1D_CACHE.REPLM",
+        "SampleAfterValue": "200000",
+        "UMask": "0x48"
+    },
+    {
+        "BriefDescription": "L1 Cacheable Data Writes",
+        "Counter": "0,1",
+        "EventCode": "0x40",
+        "EventName": "L1D_CACHE.ST",
+        "SampleAfterValue": "2000000",
+        "UMask": "0xa2"
+    },
+    {
+        "BriefDescription": "Cycles L2 address bus is in use.",
+        "Counter": "0,1",
+        "EventCode": "0x21",
+        "EventName": "L2_ADS.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "All data requests from the L1 data cache",
+        "Counter": "0,1",
+        "EventCode": "0x2C",
+        "EventName": "L2_DATA_RQSTS.SELF.E_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x44"
+    },
+    {
+        "BriefDescription": "All data requests from the L1 data cache",
+        "Counter": "0,1",
+        "EventCode": "0x2C",
+        "EventName": "L2_DATA_RQSTS.SELF.I_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x41"
+    },
+    {
+        "BriefDescription": "All data requests from the L1 data cache",
+        "Counter": "0,1",
+        "EventCode": "0x2C",
+        "EventName": "L2_DATA_RQSTS.SELF.MESI",
+        "SampleAfterValue": "200000",
+        "UMask": "0x4f"
+    },
+    {
+        "BriefDescription": "All data requests from the L1 data cache",
+        "Counter": "0,1",
+        "EventCode": "0x2C",
+        "EventName": "L2_DATA_RQSTS.SELF.M_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x48"
+    },
+    {
+        "BriefDescription": "All data requests from the L1 data cache",
+        "Counter": "0,1",
+        "EventCode": "0x2C",
+        "EventName": "L2_DATA_RQSTS.SELF.S_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x42"
+    },
+    {
+        "BriefDescription": "Cycles the L2 cache data bus is busy.",
+        "Counter": "0,1",
+        "EventCode": "0x22",
+        "EventName": "L2_DBUS_BUSY.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Cycles the L2 transfers data to the core.",
+        "Counter": "0,1",
+        "EventCode": "0x23",
+        "EventName": "L2_DBUS_BUSY_RD.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "L2 cacheable instruction fetch requests",
+        "Counter": "0,1",
+        "EventCode": "0x28",
+        "EventName": "L2_IFETCH.SELF.E_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x44"
+    },
+    {
+        "BriefDescription": "L2 cacheable instruction fetch requests",
+        "Counter": "0,1",
+        "EventCode": "0x28",
+        "EventName": "L2_IFETCH.SELF.I_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x41"
+    },
+    {
+        "BriefDescription": "L2 cacheable instruction fetch requests",
+        "Counter": "0,1",
+        "EventCode": "0x28",
+        "EventName": "L2_IFETCH.SELF.MESI",
+        "SampleAfterValue": "200000",
+        "UMask": "0x4f"
+    },
+    {
+        "BriefDescription": "L2 cacheable instruction fetch requests",
+        "Counter": "0,1",
+        "EventCode": "0x28",
+        "EventName": "L2_IFETCH.SELF.M_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x48"
+    },
+    {
+        "BriefDescription": "L2 cacheable instruction fetch requests",
+        "Counter": "0,1",
+        "EventCode": "0x28",
+        "EventName": "L2_IFETCH.SELF.S_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x42"
+    },
+    {
+        "BriefDescription": "L2 cache reads",
+        "Counter": "0,1",
+        "EventCode": "0x29",
+        "EventName": "L2_LD.SELF.ANY.E_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x74"
+    },
+    {
+        "BriefDescription": "L2 cache reads",
+        "Counter": "0,1",
+        "EventCode": "0x29",
+        "EventName": "L2_LD.SELF.ANY.I_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x71"
+    },
+    {
+        "BriefDescription": "L2 cache reads",
+        "Counter": "0,1",
+        "EventCode": "0x29",
+        "EventName": "L2_LD.SELF.ANY.MESI",
+        "SampleAfterValue": "200000",
+        "UMask": "0x7f"
+    },
+    {
+        "BriefDescription": "L2 cache reads",
+        "Counter": "0,1",
+        "EventCode": "0x29",
+        "EventName": "L2_LD.SELF.ANY.M_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x78"
+    },
+    {
+        "BriefDescription": "L2 cache reads",
+        "Counter": "0,1",
+        "EventCode": "0x29",
+        "EventName": "L2_LD.SELF.ANY.S_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x72"
+    },
+    {
+        "BriefDescription": "L2 cache reads",
+        "Counter": "0,1",
+        "EventCode": "0x29",
+        "EventName": "L2_LD.SELF.DEMAND.E_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x44"
+    },
+    {
+        "BriefDescription": "L2 cache reads",
+        "Counter": "0,1",
+        "EventCode": "0x29",
+        "EventName": "L2_LD.SELF.DEMAND.I_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x41"
+    },
+    {
+        "BriefDescription": "L2 cache reads",
+        "Counter": "0,1",
+        "EventCode": "0x29",
+        "EventName": "L2_LD.SELF.DEMAND.MESI",
+        "SampleAfterValue": "200000",
+        "UMask": "0x4f"
+    },
+    {
+        "BriefDescription": "L2 cache reads",
+        "Counter": "0,1",
+        "EventCode": "0x29",
+        "EventName": "L2_LD.SELF.DEMAND.M_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x48"
+    },
+    {
+        "BriefDescription": "L2 cache reads",
+        "Counter": "0,1",
+        "EventCode": "0x29",
+        "EventName": "L2_LD.SELF.DEMAND.S_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x42"
+    },
+    {
+        "BriefDescription": "L2 cache reads",
+        "Counter": "0,1",
+        "EventCode": "0x29",
+        "EventName": "L2_LD.SELF.PREFETCH.E_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x54"
+    },
+    {
+        "BriefDescription": "L2 cache reads",
+        "Counter": "0,1",
+        "EventCode": "0x29",
+        "EventName": "L2_LD.SELF.PREFETCH.I_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x51"
+    },
+    {
+        "BriefDescription": "L2 cache reads",
+        "Counter": "0,1",
+        "EventCode": "0x29",
+        "EventName": "L2_LD.SELF.PREFETCH.MESI",
+        "SampleAfterValue": "200000",
+        "UMask": "0x5f"
+    },
+    {
+        "BriefDescription": "L2 cache reads",
+        "Counter": "0,1",
+        "EventCode": "0x29",
+        "EventName": "L2_LD.SELF.PREFETCH.M_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x58"
+    },
+    {
+        "BriefDescription": "L2 cache reads",
+        "Counter": "0,1",
+        "EventCode": "0x29",
+        "EventName": "L2_LD.SELF.PREFETCH.S_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x52"
+    },
+    {
+        "BriefDescription": "All read requests from L1 instruction and data caches",
+        "Counter": "0,1",
+        "EventCode": "0x2D",
+        "EventName": "L2_LD_IFETCH.SELF.E_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x44"
+    },
+    {
+        "BriefDescription": "All read requests from L1 instruction and data caches",
+        "Counter": "0,1",
+        "EventCode": "0x2D",
+        "EventName": "L2_LD_IFETCH.SELF.I_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x41"
+    },
+    {
+        "BriefDescription": "All read requests from L1 instruction and data caches",
+        "Counter": "0,1",
+        "EventCode": "0x2D",
+        "EventName": "L2_LD_IFETCH.SELF.MESI",
+        "SampleAfterValue": "200000",
+        "UMask": "0x4f"
+    },
+    {
+        "BriefDescription": "All read requests from L1 instruction and data caches",
+        "Counter": "0,1",
+        "EventCode": "0x2D",
+        "EventName": "L2_LD_IFETCH.SELF.M_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x48"
+    },
+    {
+        "BriefDescription": "All read requests from L1 instruction and data caches",
+        "Counter": "0,1",
+        "EventCode": "0x2D",
+        "EventName": "L2_LD_IFETCH.SELF.S_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x42"
+    },
+    {
+        "BriefDescription": "L2 cache misses.",
+        "Counter": "0,1",
+        "EventCode": "0x24",
+        "EventName": "L2_LINES_IN.SELF.ANY",
+        "SampleAfterValue": "200000",
+        "UMask": "0x70"
+    },
+    {
+        "BriefDescription": "L2 cache misses.",
+        "Counter": "0,1",
+        "EventCode": "0x24",
+        "EventName": "L2_LINES_IN.SELF.DEMAND",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "L2 cache misses.",
+        "Counter": "0,1",
+        "EventCode": "0x24",
+        "EventName": "L2_LINES_IN.SELF.PREFETCH",
+        "SampleAfterValue": "200000",
+        "UMask": "0x50"
+    },
+    {
+        "BriefDescription": "L2 cache lines evicted.",
+        "Counter": "0,1",
+        "EventCode": "0x26",
+        "EventName": "L2_LINES_OUT.SELF.ANY",
+        "SampleAfterValue": "200000",
+        "UMask": "0x70"
+    },
+    {
+        "BriefDescription": "L2 cache lines evicted.",
+        "Counter": "0,1",
+        "EventCode": "0x26",
+        "EventName": "L2_LINES_OUT.SELF.DEMAND",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "L2 cache lines evicted.",
+        "Counter": "0,1",
+        "EventCode": "0x26",
+        "EventName": "L2_LINES_OUT.SELF.PREFETCH",
+        "SampleAfterValue": "200000",
+        "UMask": "0x50"
+    },
+    {
+        "BriefDescription": "L2 locked accesses",
+        "Counter": "0,1",
+        "EventCode": "0x2B",
+        "EventName": "L2_LOCK.SELF.E_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x44"
+    },
+    {
+        "BriefDescription": "L2 locked accesses",
+        "Counter": "0,1",
+        "EventCode": "0x2B",
+        "EventName": "L2_LOCK.SELF.I_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x41"
+    },
+    {
+        "BriefDescription": "L2 locked accesses",
+        "Counter": "0,1",
+        "EventCode": "0x2B",
+        "EventName": "L2_LOCK.SELF.MESI",
+        "SampleAfterValue": "200000",
+        "UMask": "0x4f"
+    },
+    {
+        "BriefDescription": "L2 locked accesses",
+        "Counter": "0,1",
+        "EventCode": "0x2B",
+        "EventName": "L2_LOCK.SELF.M_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x48"
+    },
+    {
+        "BriefDescription": "L2 locked accesses",
+        "Counter": "0,1",
+        "EventCode": "0x2B",
+        "EventName": "L2_LOCK.SELF.S_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x42"
+    },
+    {
+        "BriefDescription": "L2 cache line modifications.",
+        "Counter": "0,1",
+        "EventCode": "0x25",
+        "EventName": "L2_M_LINES_IN.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Modified lines evicted from the L2 cache",
+        "Counter": "0,1",
+        "EventCode": "0x27",
+        "EventName": "L2_M_LINES_OUT.SELF.ANY",
+        "SampleAfterValue": "200000",
+        "UMask": "0x70"
+    },
+    {
+        "BriefDescription": "Modified lines evicted from the L2 cache",
+        "Counter": "0,1",
+        "EventCode": "0x27",
+        "EventName": "L2_M_LINES_OUT.SELF.DEMAND",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Modified lines evicted from the L2 cache",
+        "Counter": "0,1",
+        "EventCode": "0x27",
+        "EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
+        "SampleAfterValue": "200000",
+        "UMask": "0x50"
+    },
+    {
+        "BriefDescription": "Cycles no L2 cache requests are pending",
+        "Counter": "0,1",
+        "EventCode": "0x32",
+        "EventName": "L2_NO_REQ.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Rejected L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x30",
+        "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x74"
+    },
+    {
+        "BriefDescription": "Rejected L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x30",
+        "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x71"
+    },
+    {
+        "BriefDescription": "Rejected L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x30",
+        "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
+        "SampleAfterValue": "200000",
+        "UMask": "0x7f"
+    },
+    {
+        "BriefDescription": "Rejected L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x30",
+        "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x78"
+    },
+    {
+        "BriefDescription": "Rejected L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x30",
+        "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x72"
+    },
+    {
+        "BriefDescription": "Rejected L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x30",
+        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x44"
+    },
+    {
+        "BriefDescription": "Rejected L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x30",
+        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x41"
+    },
+    {
+        "BriefDescription": "Rejected L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x30",
+        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
+        "SampleAfterValue": "200000",
+        "UMask": "0x4f"
+    },
+    {
+        "BriefDescription": "Rejected L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x30",
+        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x48"
+    },
+    {
+        "BriefDescription": "Rejected L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x30",
+        "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x42"
+    },
+    {
+        "BriefDescription": "Rejected L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x30",
+        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x54"
+    },
+    {
+        "BriefDescription": "Rejected L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x30",
+        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x51"
+    },
+    {
+        "BriefDescription": "Rejected L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x30",
+        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
+        "SampleAfterValue": "200000",
+        "UMask": "0x5f"
+    },
+    {
+        "BriefDescription": "Rejected L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x30",
+        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x58"
+    },
+    {
+        "BriefDescription": "Rejected L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x30",
+        "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x52"
+    },
+    {
+        "BriefDescription": "L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x2E",
+        "EventName": "L2_RQSTS.SELF.ANY.E_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x74"
+    },
+    {
+        "BriefDescription": "L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x2E",
+        "EventName": "L2_RQSTS.SELF.ANY.I_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x71"
+    },
+    {
+        "BriefDescription": "L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x2E",
+        "EventName": "L2_RQSTS.SELF.ANY.MESI",
+        "SampleAfterValue": "200000",
+        "UMask": "0x7f"
+    },
+    {
+        "BriefDescription": "L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x2E",
+        "EventName": "L2_RQSTS.SELF.ANY.M_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x78"
+    },
+    {
+        "BriefDescription": "L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x2E",
+        "EventName": "L2_RQSTS.SELF.ANY.S_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x72"
+    },
+    {
+        "BriefDescription": "L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x2E",
+        "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x44"
+    },
+    {
+        "BriefDescription": "L2 cache demand requests from this core that missed the L2",
+        "Counter": "0,1",
+        "EventCode": "0x2E",
+        "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x41"
+    },
+    {
+        "BriefDescription": "L2 cache demand requests from this core",
+        "Counter": "0,1",
+        "EventCode": "0x2E",
+        "EventName": "L2_RQSTS.SELF.DEMAND.MESI",
+        "SampleAfterValue": "200000",
+        "UMask": "0x4f"
+    },
+    {
+        "BriefDescription": "L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x2E",
+        "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x48"
+    },
+    {
+        "BriefDescription": "L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x2E",
+        "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x42"
+    },
+    {
+        "BriefDescription": "L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x2E",
+        "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x54"
+    },
+    {
+        "BriefDescription": "L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x2E",
+        "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x51"
+    },
+    {
+        "BriefDescription": "L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x2E",
+        "EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
+        "SampleAfterValue": "200000",
+        "UMask": "0x5f"
+    },
+    {
+        "BriefDescription": "L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x2E",
+        "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x58"
+    },
+    {
+        "BriefDescription": "L2 cache requests",
+        "Counter": "0,1",
+        "EventCode": "0x2E",
+        "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x52"
+    },
+    {
+        "BriefDescription": "L2 store requests",
+        "Counter": "0,1",
+        "EventCode": "0x2A",
+        "EventName": "L2_ST.SELF.E_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x44"
+    },
+    {
+        "BriefDescription": "L2 store requests",
+        "Counter": "0,1",
+        "EventCode": "0x2A",
+        "EventName": "L2_ST.SELF.I_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x41"
+    },
+    {
+        "BriefDescription": "L2 store requests",
+        "Counter": "0,1",
+        "EventCode": "0x2A",
+        "EventName": "L2_ST.SELF.MESI",
+        "SampleAfterValue": "200000",
+        "UMask": "0x4f"
+    },
+    {
+        "BriefDescription": "L2 store requests",
+        "Counter": "0,1",
+        "EventCode": "0x2A",
+        "EventName": "L2_ST.SELF.M_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x48"
+    },
+    {
+        "BriefDescription": "L2 store requests",
+        "Counter": "0,1",
+        "EventCode": "0x2A",
+        "EventName": "L2_ST.SELF.S_STATE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x42"
+    },
+    {
+        "BriefDescription": "Retired loads that hit the L2 cache (precise event).",
+        "Counter": "0,1",
+        "EventCode": "0xCB",
+        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
+        "SampleAfterValue": "200000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Retired loads that miss the L2 cache",
+        "Counter": "0,1",
+        "EventCode": "0xCB",
+        "EventName": "MEM_LOAD_RETIRED.L2_MISS",
+        "SampleAfterValue": "10000",
+        "UMask": "0x2"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
new file mode 100644
index 000000000..1fa347d07
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/bonnell/floating-point.json
@@ -0,0 +1,261 @@
+[
+    {
+        "BriefDescription": "Floating point assists for retired operations.",
+        "Counter": "0,1",
+        "EventCode": "0x11",
+        "EventName": "FP_ASSIST.AR",
+        "SampleAfterValue": "10000",
+        "UMask": "0x81"
+    },
+    {
+        "BriefDescription": "Floating point assists.",
+        "Counter": "0,1",
+        "EventCode": "0x11",
+        "EventName": "FP_ASSIST.S",
+        "SampleAfterValue": "10000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "SIMD assists invoked.",
+        "Counter": "0,1",
+        "EventCode": "0xCD",
+        "EventName": "SIMD_ASSIST",
+        "SampleAfterValue": "100000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) packed-single instructions.",
+        "Counter": "0,1",
+        "EventCode": "0xCA",
+        "EventName": "SIMD_COMP_INST_RETIRED.PACKED_SINGLE",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Retired computational Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
+        "Counter": "0,1",
+        "EventCode": "0xCA",
+        "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_DOUBLE",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x8"
+    },
+    {
+        "BriefDescription": "Retired computational Streaming SIMD Extensions (SSE) scalar-single instructions.",
+        "Counter": "0,1",
+        "EventCode": "0xCA",
+        "EventName": "SIMD_COMP_INST_RETIRED.SCALAR_SINGLE",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "SIMD Instructions retired.",
+        "Counter": "0,1",
+        "EventCode": "0xCE",
+        "EventName": "SIMD_INSTR_RETIRED",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "Retired Streaming SIMD Extensions (SSE) packed-single instructions.",
+        "Counter": "0,1",
+        "EventCode": "0xC7",
+        "EventName": "SIMD_INST_RETIRED.PACKED_SINGLE",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) scalar-double instructions.",
+        "Counter": "0,1",
+        "EventCode": "0xC7",
+        "EventName": "SIMD_INST_RETIRED.SCALAR_DOUBLE",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x8"
+    },
+    {
+        "BriefDescription": "Retired Streaming SIMD Extensions (SSE) scalar-single instructions.",
+        "Counter": "0,1",
+        "EventCode": "0xC7",
+        "EventName": "SIMD_INST_RETIRED.SCALAR_SINGLE",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Retired Streaming SIMD Extensions 2 (SSE2) vector instructions.",
+        "Counter": "0,1",
+        "EventCode": "0xC7",
+        "EventName": "SIMD_INST_RETIRED.VECTOR",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x10"
+    },
+    {
+        "BriefDescription": "Saturated arithmetic instructions retired.",
+        "Counter": "0,1",
+        "EventCode": "0xCF",
+        "EventName": "SIMD_SAT_INSTR_RETIRED",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "SIMD saturated arithmetic micro-ops retired.",
+        "Counter": "0,1",
+        "EventCode": "0xB1",
+        "EventName": "SIMD_SAT_UOP_EXEC.AR",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x80"
+    },
+    {
+        "BriefDescription": "SIMD saturated arithmetic micro-ops executed.",
+        "Counter": "0,1",
+        "EventCode": "0xB1",
+        "EventName": "SIMD_SAT_UOP_EXEC.S",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "SIMD micro-ops retired (excluding stores).",
+        "Counter": "0,1",
+        "EventCode": "0xB0",
+        "EventName": "SIMD_UOPS_EXEC.AR",
+        "PEBS": "2",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x80"
+    },
+    {
+        "BriefDescription": "SIMD micro-ops executed (excluding stores).",
+        "Counter": "0,1",
+        "EventCode": "0xB0",
+        "EventName": "SIMD_UOPS_EXEC.S",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "SIMD packed arithmetic micro-ops retired",
+        "Counter": "0,1",
+        "EventCode": "0xB3",
+        "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.AR",
+        "SampleAfterValue": "2000000",
+        "UMask": "0xa0"
+    },
+    {
+        "BriefDescription": "SIMD packed arithmetic micro-ops executed",
+        "Counter": "0,1",
+        "EventCode": "0xB3",
+        "EventName": "SIMD_UOP_TYPE_EXEC.ARITHMETIC.S",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x20"
+    },
+    {
+        "BriefDescription": "SIMD packed logical micro-ops retired",
+        "Counter": "0,1",
+        "EventCode": "0xB3",
+        "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.AR",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x90"
+    },
+    {
+        "BriefDescription": "SIMD packed logical micro-ops executed",
+        "Counter": "0,1",
+        "EventCode": "0xB3",
+        "EventName": "SIMD_UOP_TYPE_EXEC.LOGICAL.S",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x10"
+    },
+    {
+        "BriefDescription": "SIMD packed multiply micro-ops retired",
+        "Counter": "0,1",
+        "EventCode": "0xB3",
+        "EventName": "SIMD_UOP_TYPE_EXEC.MUL.AR",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x81"
+    },
+    {
+        "BriefDescription": "SIMD packed multiply micro-ops executed",
+        "Counter": "0,1",
+        "EventCode": "0xB3",
+        "EventName": "SIMD_UOP_TYPE_EXEC.MUL.S",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "SIMD packed micro-ops retired",
+        "Counter": "0,1",
+        "EventCode": "0xB3",
+        "EventName": "SIMD_UOP_TYPE_EXEC.PACK.AR",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x84"
+    },
+    {
+        "BriefDescription": "SIMD packed micro-ops executed",
+        "Counter": "0,1",
+        "EventCode": "0xB3",
+        "EventName": "SIMD_UOP_TYPE_EXEC.PACK.S",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x4"
+    },
+    {
+        "BriefDescription": "SIMD packed shift micro-ops retired",
+        "Counter": "0,1",
+        "EventCode": "0xB3",
+        "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.AR",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x82"
+    },
+    {
+        "BriefDescription": "SIMD packed shift micro-ops executed",
+        "Counter": "0,1",
+        "EventCode": "0xB3",
+        "EventName": "SIMD_UOP_TYPE_EXEC.SHIFT.S",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "SIMD unpacked micro-ops retired",
+        "Counter": "0,1",
+        "EventCode": "0xB3",
+        "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.AR",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x88"
+    },
+    {
+        "BriefDescription": "SIMD unpacked micro-ops executed",
+        "Counter": "0,1",
+        "EventCode": "0xB3",
+        "EventName": "SIMD_UOP_TYPE_EXEC.UNPACK.S",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x8"
+    },
+    {
+        "BriefDescription": "Floating point computational micro-ops retired.",
+        "Counter": "0,1",
+        "EventCode": "0x10",
+        "EventName": "X87_COMP_OPS_EXE.ANY.AR",
+        "PEBS": "2",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x81"
+    },
+    {
+        "BriefDescription": "Floating point computational micro-ops executed.",
+        "Counter": "0,1",
+        "EventCode": "0x10",
+        "EventName": "X87_COMP_OPS_EXE.ANY.S",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "FXCH uops retired.",
+        "Counter": "0,1",
+        "EventCode": "0x10",
+        "EventName": "X87_COMP_OPS_EXE.FXCH.AR",
+        "PEBS": "2",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x82"
+    },
+    {
+        "BriefDescription": "FXCH uops executed.",
+        "Counter": "0,1",
+        "EventCode": "0x10",
+        "EventName": "X87_COMP_OPS_EXE.FXCH.S",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x2"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/frontend.json b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
new file mode 100644
index 000000000..21fe5fe22
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/bonnell/frontend.json
@@ -0,0 +1,91 @@
+[
+    {
+        "BriefDescription": "BACLEARS asserted.",
+        "Counter": "0,1",
+        "EventCode": "0xE6",
+        "EventName": "BACLEARS.ANY",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Cycles during which instruction fetches are  stalled.",
+        "Counter": "0,1",
+        "EventCode": "0x86",
+        "EventName": "CYCLES_ICACHE_MEM_STALLED.ICACHE_MEM_STALLED",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Decode stall due to IQ full",
+        "Counter": "0,1",
+        "EventCode": "0x87",
+        "EventName": "DECODE_STALL.IQ_FULL",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Decode stall due to PFB empty",
+        "Counter": "0,1",
+        "EventCode": "0x87",
+        "EventName": "DECODE_STALL.PFB_EMPTY",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Instruction fetches.",
+        "Counter": "0,1",
+        "EventCode": "0x80",
+        "EventName": "ICACHE.ACCESSES",
+        "SampleAfterValue": "200000",
+        "UMask": "0x3"
+    },
+    {
+        "BriefDescription": "Icache hit",
+        "Counter": "0,1",
+        "EventCode": "0x80",
+        "EventName": "ICACHE.HIT",
+        "SampleAfterValue": "200000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Icache miss",
+        "Counter": "0,1",
+        "EventCode": "0x80",
+        "EventName": "ICACHE.MISSES",
+        "SampleAfterValue": "200000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "All Instructions decoded",
+        "Counter": "0,1",
+        "EventCode": "0xAA",
+        "EventName": "MACRO_INSTS.ALL_DECODED",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x3"
+    },
+    {
+        "BriefDescription": "CISC macro instructions decoded",
+        "Counter": "0,1",
+        "EventCode": "0xAA",
+        "EventName": "MACRO_INSTS.CISC_DECODED",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Non-CISC nacro instructions decoded",
+        "Counter": "0,1",
+        "EventCode": "0xAA",
+        "EventName": "MACRO_INSTS.NON_CISC_DECODED",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "This event counts the cycles where 1 or more uops are issued by the micro-sequencer (MS), including microcode assists and inserted flows, and written to the IQ.",
+        "Counter": "0,1",
+        "CounterMask": "1",
+        "EventCode": "0xA9",
+        "EventName": "UOPS.MS_CYCLES",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/memory.json b/tools/perf/pmu-events/arch/x86/bonnell/memory.json
new file mode 100644
index 000000000..f8b45b6fb
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/bonnell/memory.json
@@ -0,0 +1,154 @@
+[
+    {
+        "BriefDescription": "Nonzero segbase 1 bubble",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.BUBBLE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x97"
+    },
+    {
+        "BriefDescription": "Nonzero segbase load 1 bubble",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x91"
+    },
+    {
+        "BriefDescription": "Load splits",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.LD_SPLIT",
+        "SampleAfterValue": "200000",
+        "UMask": "0x9"
+    },
+    {
+        "BriefDescription": "Load splits (At Retirement)",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
+        "SampleAfterValue": "200000",
+        "UMask": "0x89"
+    },
+    {
+        "BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x94"
+    },
+    {
+        "BriefDescription": "ld-op-st splits",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
+        "SampleAfterValue": "200000",
+        "UMask": "0x8c"
+    },
+    {
+        "BriefDescription": "Memory references that cross an 8-byte boundary.",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.SPLIT",
+        "SampleAfterValue": "200000",
+        "UMask": "0xf"
+    },
+    {
+        "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.SPLIT.AR",
+        "SampleAfterValue": "200000",
+        "UMask": "0x8f"
+    },
+    {
+        "BriefDescription": "Nonzero segbase store 1 bubble",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x92"
+    },
+    {
+        "BriefDescription": "Store splits",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.ST_SPLIT",
+        "SampleAfterValue": "200000",
+        "UMask": "0xa"
+    },
+    {
+        "BriefDescription": "Store splits (Ar Retirement)",
+        "Counter": "0,1",
+        "EventCode": "0x5",
+        "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
+        "SampleAfterValue": "200000",
+        "UMask": "0x8a"
+    },
+    {
+        "BriefDescription": "L1 hardware prefetch request",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.HW_PREFETCH",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x10"
+    },
+    {
+        "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.PREFETCHNTA",
+        "SampleAfterValue": "200000",
+        "UMask": "0x88"
+    },
+    {
+        "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.PREFETCHT0",
+        "SampleAfterValue": "200000",
+        "UMask": "0x81"
+    },
+    {
+        "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.PREFETCHT1",
+        "SampleAfterValue": "200000",
+        "UMask": "0x82"
+    },
+    {
+        "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.PREFETCHT2",
+        "SampleAfterValue": "200000",
+        "UMask": "0x84"
+    },
+    {
+        "BriefDescription": "Any Software prefetch",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.SOFTWARE_PREFETCH",
+        "SampleAfterValue": "200000",
+        "UMask": "0xf"
+    },
+    {
+        "BriefDescription": "Any Software prefetch",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
+        "SampleAfterValue": "200000",
+        "UMask": "0x8f"
+    },
+    {
+        "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
+        "Counter": "0,1",
+        "EventCode": "0x7",
+        "EventName": "PREFETCH.SW_L2",
+        "SampleAfterValue": "200000",
+        "UMask": "0x86"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/other.json b/tools/perf/pmu-events/arch/x86/bonnell/other.json
new file mode 100644
index 000000000..e0bdcfbfa
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/bonnell/other.json
@@ -0,0 +1,450 @@
+[
+    {
+        "BriefDescription": "Bus queue is empty.",
+        "Counter": "0,1",
+        "EventCode": "0x7D",
+        "EventName": "BUSQ_EMPTY.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Number of Bus Not Ready signals asserted.",
+        "Counter": "0,1",
+        "EventCode": "0x61",
+        "EventName": "BUS_BNR_DRV.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0x20"
+    },
+    {
+        "BriefDescription": "Number of Bus Not Ready signals asserted.",
+        "Counter": "0,1",
+        "EventCode": "0x61",
+        "EventName": "BUS_BNR_DRV.THIS_AGENT",
+        "SampleAfterValue": "200000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "Bus cycles while processor receives data.",
+        "Counter": "0,1",
+        "EventCode": "0x64",
+        "EventName": "BUS_DATA_RCV.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Bus cycles when data is sent on the bus.",
+        "Counter": "0,1",
+        "EventCode": "0x62",
+        "EventName": "BUS_DRDY_CLOCKS.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0x20"
+    },
+    {
+        "BriefDescription": "Bus cycles when data is sent on the bus.",
+        "Counter": "0,1",
+        "EventCode": "0x62",
+        "EventName": "BUS_DRDY_CLOCKS.THIS_AGENT",
+        "SampleAfterValue": "200000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "HITM signal asserted.",
+        "Counter": "0,1",
+        "EventCode": "0x7B",
+        "EventName": "BUS_HITM_DRV.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0x20"
+    },
+    {
+        "BriefDescription": "HITM signal asserted.",
+        "Counter": "0,1",
+        "EventCode": "0x7B",
+        "EventName": "BUS_HITM_DRV.THIS_AGENT",
+        "SampleAfterValue": "200000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "HIT signal asserted.",
+        "Counter": "0,1",
+        "EventCode": "0x7A",
+        "EventName": "BUS_HIT_DRV.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0x20"
+    },
+    {
+        "BriefDescription": "HIT signal asserted.",
+        "Counter": "0,1",
+        "EventCode": "0x7A",
+        "EventName": "BUS_HIT_DRV.THIS_AGENT",
+        "SampleAfterValue": "200000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "IO requests waiting in the bus queue.",
+        "Counter": "0,1",
+        "EventCode": "0x7F",
+        "EventName": "BUS_IO_WAIT.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
+        "Counter": "0,1",
+        "EventCode": "0x63",
+        "EventName": "BUS_LOCK_CLOCKS.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0xe0"
+    },
+    {
+        "BriefDescription": "Bus cycles when a LOCK signal is asserted.",
+        "Counter": "0,1",
+        "EventCode": "0x63",
+        "EventName": "BUS_LOCK_CLOCKS.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Outstanding cacheable data read bus requests duration.",
+        "Counter": "0,1",
+        "EventCode": "0x60",
+        "EventName": "BUS_REQUEST_OUTSTANDING.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0xe0"
+    },
+    {
+        "BriefDescription": "Outstanding cacheable data read bus requests duration.",
+        "Counter": "0,1",
+        "EventCode": "0x60",
+        "EventName": "BUS_REQUEST_OUTSTANDING.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "All bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x70",
+        "EventName": "BUS_TRANS_ANY.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0xe0"
+    },
+    {
+        "BriefDescription": "All bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x70",
+        "EventName": "BUS_TRANS_ANY.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Burst read bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x65",
+        "EventName": "BUS_TRANS_BRD.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0xe0"
+    },
+    {
+        "BriefDescription": "Burst read bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x65",
+        "EventName": "BUS_TRANS_BRD.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Burst (full cache-line) bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x6E",
+        "EventName": "BUS_TRANS_BURST.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0xe0"
+    },
+    {
+        "BriefDescription": "Burst (full cache-line) bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x6E",
+        "EventName": "BUS_TRANS_BURST.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Deferred bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x6D",
+        "EventName": "BUS_TRANS_DEF.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0xe0"
+    },
+    {
+        "BriefDescription": "Deferred bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x6D",
+        "EventName": "BUS_TRANS_DEF.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Instruction-fetch bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x68",
+        "EventName": "BUS_TRANS_IFETCH.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0xe0"
+    },
+    {
+        "BriefDescription": "Instruction-fetch bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x68",
+        "EventName": "BUS_TRANS_IFETCH.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Invalidate bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x69",
+        "EventName": "BUS_TRANS_INVAL.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0xe0"
+    },
+    {
+        "BriefDescription": "Invalidate bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x69",
+        "EventName": "BUS_TRANS_INVAL.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "IO bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x6C",
+        "EventName": "BUS_TRANS_IO.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0xe0"
+    },
+    {
+        "BriefDescription": "IO bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x6C",
+        "EventName": "BUS_TRANS_IO.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Memory bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x6F",
+        "EventName": "BUS_TRANS_MEM.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0xe0"
+    },
+    {
+        "BriefDescription": "Memory bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x6F",
+        "EventName": "BUS_TRANS_MEM.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Partial bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x6B",
+        "EventName": "BUS_TRANS_P.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0xe0"
+    },
+    {
+        "BriefDescription": "Partial bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x6B",
+        "EventName": "BUS_TRANS_P.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Partial write bus transaction.",
+        "Counter": "0,1",
+        "EventCode": "0x6A",
+        "EventName": "BUS_TRANS_PWR.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0xe0"
+    },
+    {
+        "BriefDescription": "Partial write bus transaction.",
+        "Counter": "0,1",
+        "EventCode": "0x6A",
+        "EventName": "BUS_TRANS_PWR.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "RFO bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x66",
+        "EventName": "BUS_TRANS_RFO.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0xe0"
+    },
+    {
+        "BriefDescription": "RFO bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x66",
+        "EventName": "BUS_TRANS_RFO.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Explicit writeback bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x67",
+        "EventName": "BUS_TRANS_WB.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0xe0"
+    },
+    {
+        "BriefDescription": "Explicit writeback bus transactions.",
+        "Counter": "0,1",
+        "EventCode": "0x67",
+        "EventName": "BUS_TRANS_WB.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Cycles during which interrupts are disabled.",
+        "Counter": "0,1",
+        "EventCode": "0xC6",
+        "EventName": "CYCLES_INT_MASKED.CYCLES_INT_MASKED",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Cycles during which interrupts are pending and disabled.",
+        "Counter": "0,1",
+        "EventCode": "0xC6",
+        "EventName": "CYCLES_INT_MASKED.CYCLES_INT_PENDING_AND_MASKED",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason",
+        "Counter": "0,1",
+        "EventCode": "0x9",
+        "EventName": "DISPATCH_BLOCKED.ANY",
+        "SampleAfterValue": "200000",
+        "UMask": "0x20"
+    },
+    {
+        "BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions",
+        "Counter": "0,1",
+        "EventCode": "0x3A",
+        "EventName": "EIST_TRANS",
+        "SampleAfterValue": "200000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "External snoops.",
+        "Counter": "0,1",
+        "EventCode": "0x77",
+        "EventName": "EXT_SNOOP.ALL_AGENTS.ANY",
+        "SampleAfterValue": "200000",
+        "UMask": "0x2b"
+    },
+    {
+        "BriefDescription": "External snoops.",
+        "Counter": "0,1",
+        "EventCode": "0x77",
+        "EventName": "EXT_SNOOP.ALL_AGENTS.CLEAN",
+        "SampleAfterValue": "200000",
+        "UMask": "0x21"
+    },
+    {
+        "BriefDescription": "External snoops.",
+        "Counter": "0,1",
+        "EventCode": "0x77",
+        "EventName": "EXT_SNOOP.ALL_AGENTS.HIT",
+        "SampleAfterValue": "200000",
+        "UMask": "0x22"
+    },
+    {
+        "BriefDescription": "External snoops.",
+        "Counter": "0,1",
+        "EventCode": "0x77",
+        "EventName": "EXT_SNOOP.ALL_AGENTS.HITM",
+        "SampleAfterValue": "200000",
+        "UMask": "0x28"
+    },
+    {
+        "BriefDescription": "External snoops.",
+        "Counter": "0,1",
+        "EventCode": "0x77",
+        "EventName": "EXT_SNOOP.THIS_AGENT.ANY",
+        "SampleAfterValue": "200000",
+        "UMask": "0xb"
+    },
+    {
+        "BriefDescription": "External snoops.",
+        "Counter": "0,1",
+        "EventCode": "0x77",
+        "EventName": "EXT_SNOOP.THIS_AGENT.CLEAN",
+        "SampleAfterValue": "200000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "External snoops.",
+        "Counter": "0,1",
+        "EventCode": "0x77",
+        "EventName": "EXT_SNOOP.THIS_AGENT.HIT",
+        "SampleAfterValue": "200000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "External snoops.",
+        "Counter": "0,1",
+        "EventCode": "0x77",
+        "EventName": "EXT_SNOOP.THIS_AGENT.HITM",
+        "SampleAfterValue": "200000",
+        "UMask": "0x8"
+    },
+    {
+        "BriefDescription": "Hardware interrupts received.",
+        "Counter": "0,1",
+        "EventCode": "0xC8",
+        "EventName": "HW_INT_RCV",
+        "SampleAfterValue": "200000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "Number of segment register loads.",
+        "Counter": "0,1",
+        "EventCode": "0x6",
+        "EventName": "SEGMENT_REG_LOADS.ANY",
+        "SampleAfterValue": "200000",
+        "UMask": "0x80"
+    },
+    {
+        "BriefDescription": "Bus stalled for snoops.",
+        "Counter": "0,1",
+        "EventCode": "0x7E",
+        "EventName": "SNOOP_STALL_DRV.ALL_AGENTS",
+        "SampleAfterValue": "200000",
+        "UMask": "0xe0"
+    },
+    {
+        "BriefDescription": "Bus stalled for snoops.",
+        "Counter": "0,1",
+        "EventCode": "0x7E",
+        "EventName": "SNOOP_STALL_DRV.SELF",
+        "SampleAfterValue": "200000",
+        "UMask": "0x40"
+    },
+    {
+        "BriefDescription": "Number of thermal trips",
+        "Counter": "0,1",
+        "EventCode": "0x3B",
+        "EventName": "THERMAL_TRIP",
+        "SampleAfterValue": "200000",
+        "UMask": "0xc0"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
new file mode 100644
index 000000000..f5123c99a
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/bonnell/pipeline.json
@@ -0,0 +1,356 @@
+[
+    {
+        "BriefDescription": "Bogus branches",
+        "Counter": "0,1",
+        "EventCode": "0xE4",
+        "EventName": "BOGUS_BR",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Branch instructions decoded",
+        "Counter": "0,1",
+        "EventCode": "0xE0",
+        "EventName": "BR_INST_DECODED",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Retired branch instructions.",
+        "Counter": "0,1",
+        "EventCode": "0xC4",
+        "EventName": "BR_INST_RETIRED.ANY",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "Retired branch instructions.",
+        "Counter": "0,1",
+        "EventCode": "0xC4",
+        "EventName": "BR_INST_RETIRED.ANY1",
+        "SampleAfterValue": "2000000",
+        "UMask": "0xf"
+    },
+    {
+        "BriefDescription": "Retired mispredicted branch instructions (precise event).",
+        "Counter": "0,1",
+        "EventCode": "0xC5",
+        "EventName": "BR_INST_RETIRED.MISPRED",
+        "PEBS": "1",
+        "SampleAfterValue": "200000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "Retired branch instructions that were mispredicted not-taken.",
+        "Counter": "0,1",
+        "EventCode": "0xC4",
+        "EventName": "BR_INST_RETIRED.MISPRED_NOT_TAKEN",
+        "SampleAfterValue": "200000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Retired branch instructions that were mispredicted taken.",
+        "Counter": "0,1",
+        "EventCode": "0xC4",
+        "EventName": "BR_INST_RETIRED.MISPRED_TAKEN",
+        "SampleAfterValue": "200000",
+        "UMask": "0x8"
+    },
+    {
+        "BriefDescription": "Retired branch instructions that were predicted not-taken.",
+        "Counter": "0,1",
+        "EventCode": "0xC4",
+        "EventName": "BR_INST_RETIRED.PRED_NOT_TAKEN",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Retired branch instructions that were predicted taken.",
+        "Counter": "0,1",
+        "EventCode": "0xC4",
+        "EventName": "BR_INST_RETIRED.PRED_TAKEN",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x4"
+    },
+    {
+        "BriefDescription": "Retired taken branch instructions.",
+        "Counter": "0,1",
+        "EventCode": "0xC4",
+        "EventName": "BR_INST_RETIRED.TAKEN",
+        "SampleAfterValue": "2000000",
+        "UMask": "0xc"
+    },
+    {
+        "BriefDescription": "All macro conditional branch instructions.",
+        "Counter": "0,1",
+        "EventCode": "0x88",
+        "EventName": "BR_INST_TYPE_RETIRED.COND",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Only taken macro conditional branch instructions",
+        "Counter": "0,1",
+        "EventCode": "0x88",
+        "EventName": "BR_INST_TYPE_RETIRED.COND_TAKEN",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x41"
+    },
+    {
+        "BriefDescription": "All non-indirect calls",
+        "Counter": "0,1",
+        "EventCode": "0x88",
+        "EventName": "BR_INST_TYPE_RETIRED.DIR_CALL",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x10"
+    },
+    {
+        "BriefDescription": "All indirect branches that are not calls.",
+        "Counter": "0,1",
+        "EventCode": "0x88",
+        "EventName": "BR_INST_TYPE_RETIRED.IND",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x4"
+    },
+    {
+        "BriefDescription": "All indirect calls, including both register and memory indirect.",
+        "Counter": "0,1",
+        "EventCode": "0x88",
+        "EventName": "BR_INST_TYPE_RETIRED.IND_CALL",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x20"
+    },
+    {
+        "BriefDescription": "All indirect branches that have a return mnemonic",
+        "Counter": "0,1",
+        "EventCode": "0x88",
+        "EventName": "BR_INST_TYPE_RETIRED.RET",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x8"
+    },
+    {
+        "BriefDescription": "All macro unconditional branch instructions, excluding calls and indirects",
+        "Counter": "0,1",
+        "EventCode": "0x88",
+        "EventName": "BR_INST_TYPE_RETIRED.UNCOND",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Mispredicted cond branch instructions retired",
+        "Counter": "0,1",
+        "EventCode": "0x89",
+        "EventName": "BR_MISSP_TYPE_RETIRED.COND",
+        "SampleAfterValue": "200000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Mispredicted and taken cond branch instructions retired",
+        "Counter": "0,1",
+        "EventCode": "0x89",
+        "EventName": "BR_MISSP_TYPE_RETIRED.COND_TAKEN",
+        "SampleAfterValue": "200000",
+        "UMask": "0x11"
+    },
+    {
+        "BriefDescription": "Mispredicted ind branches that are not calls",
+        "Counter": "0,1",
+        "EventCode": "0x89",
+        "EventName": "BR_MISSP_TYPE_RETIRED.IND",
+        "SampleAfterValue": "200000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Mispredicted indirect calls, including both register and memory indirect.",
+        "Counter": "0,1",
+        "EventCode": "0x89",
+        "EventName": "BR_MISSP_TYPE_RETIRED.IND_CALL",
+        "SampleAfterValue": "200000",
+        "UMask": "0x8"
+    },
+    {
+        "BriefDescription": "Mispredicted return branches",
+        "Counter": "0,1",
+        "EventCode": "0x89",
+        "EventName": "BR_MISSP_TYPE_RETIRED.RETURN",
+        "SampleAfterValue": "200000",
+        "UMask": "0x4"
+    },
+    {
+        "BriefDescription": "Bus cycles when core is not halted",
+        "Counter": "0,1",
+        "EventCode": "0x3C",
+        "EventName": "CPU_CLK_UNHALTED.BUS",
+        "SampleAfterValue": "200000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Core cycles when core is not halted",
+        "Counter": "Fixed counter 2",
+        "EventCode": "0xA",
+        "EventName": "CPU_CLK_UNHALTED.CORE",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "Core cycles when core is not halted",
+        "Counter": "0,1",
+        "EventCode": "0x3C",
+        "EventName": "CPU_CLK_UNHALTED.CORE_P",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "Reference cycles when core is not halted.",
+        "Counter": "Fixed counter 3",
+        "EventCode": "0xA",
+        "EventName": "CPU_CLK_UNHALTED.REF",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "Cycles the divider is busy.",
+        "Counter": "0,1",
+        "EventCode": "0x14",
+        "EventName": "CYCLES_DIV_BUSY",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Divide operations retired",
+        "Counter": "0,1",
+        "EventCode": "0x13",
+        "EventName": "DIV.AR",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x81"
+    },
+    {
+        "BriefDescription": "Divide operations executed.",
+        "Counter": "0,1",
+        "EventCode": "0x13",
+        "EventName": "DIV.S",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Instructions retired.",
+        "Counter": "Fixed counter 1",
+        "EventCode": "0xA",
+        "EventName": "INST_RETIRED.ANY",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "Instructions retired (precise event).",
+        "Counter": "0,1",
+        "EventCode": "0xC0",
+        "EventName": "INST_RETIRED.ANY_P",
+        "PEBS": "2",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x0"
+    },
+    {
+        "BriefDescription": "Self-Modifying Code detected.",
+        "Counter": "0,1",
+        "EventCode": "0xC3",
+        "EventName": "MACHINE_CLEARS.SMC",
+        "SampleAfterValue": "200000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Multiply operations retired",
+        "Counter": "0,1",
+        "EventCode": "0x12",
+        "EventName": "MUL.AR",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x81"
+    },
+    {
+        "BriefDescription": "Multiply operations executed.",
+        "Counter": "0,1",
+        "EventCode": "0x12",
+        "EventName": "MUL.S",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Micro-op reissues for any cause",
+        "Counter": "0,1",
+        "EventCode": "0x3",
+        "EventName": "REISSUE.ANY",
+        "SampleAfterValue": "200000",
+        "UMask": "0x7f"
+    },
+    {
+        "BriefDescription": "Micro-op reissues for any cause (At Retirement)",
+        "Counter": "0,1",
+        "EventCode": "0x3",
+        "EventName": "REISSUE.ANY.AR",
+        "SampleAfterValue": "200000",
+        "UMask": "0xff"
+    },
+    {
+        "BriefDescription": "Micro-op reissues on a store-load collision",
+        "Counter": "0,1",
+        "EventCode": "0x3",
+        "EventName": "REISSUE.OVERLAP_STORE",
+        "SampleAfterValue": "200000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Micro-op reissues on a store-load collision (At Retirement)",
+        "Counter": "0,1",
+        "EventCode": "0x3",
+        "EventName": "REISSUE.OVERLAP_STORE.AR",
+        "SampleAfterValue": "200000",
+        "UMask": "0x81"
+    },
+    {
+        "BriefDescription": "Cycles issue is stalled due to div busy.",
+        "Counter": "0,1",
+        "EventCode": "0xDC",
+        "EventName": "RESOURCE_STALLS.DIV_BUSY",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "All store forwards",
+        "Counter": "0,1",
+        "EventCode": "0x2",
+        "EventName": "STORE_FORWARDS.ANY",
+        "SampleAfterValue": "200000",
+        "UMask": "0x83"
+    },
+    {
+        "BriefDescription": "Good store forwards",
+        "Counter": "0,1",
+        "EventCode": "0x2",
+        "EventName": "STORE_FORWARDS.GOOD",
+        "SampleAfterValue": "200000",
+        "UMask": "0x81"
+    },
+    {
+        "BriefDescription": "Micro-ops retired.",
+        "Counter": "0,1",
+        "EventCode": "0xC2",
+        "EventName": "UOPS_RETIRED.ANY",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x10"
+    },
+    {
+        "BriefDescription": "Cycles no micro-ops retired.",
+        "Counter": "0,1",
+        "EventCode": "0xC2",
+        "EventName": "UOPS_RETIRED.STALLED_CYCLES",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x10"
+    },
+    {
+        "BriefDescription": "Periods no micro-ops retired.",
+        "Counter": "0,1",
+        "EventCode": "0xC2",
+        "EventName": "UOPS_RETIRED.STALLS",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x10"
+    }
+]
diff --git a/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
new file mode 100644
index 000000000..e8512c585
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/bonnell/virtual-memory.json
@@ -0,0 +1,124 @@
+[
+    {
+        "BriefDescription": "Memory accesses that missed the DTLB.",
+        "Counter": "0,1",
+        "EventCode": "0x8",
+        "EventName": "DATA_TLB_MISSES.DTLB_MISS",
+        "SampleAfterValue": "200000",
+        "UMask": "0x7"
+    },
+    {
+        "BriefDescription": "DTLB misses due to load operations.",
+        "Counter": "0,1",
+        "EventCode": "0x8",
+        "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
+        "SampleAfterValue": "200000",
+        "UMask": "0x5"
+    },
+    {
+        "BriefDescription": "DTLB misses due to store operations.",
+        "Counter": "0,1",
+        "EventCode": "0x8",
+        "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
+        "SampleAfterValue": "200000",
+        "UMask": "0x6"
+    },
+    {
+        "BriefDescription": "L0 DTLB misses due to load operations.",
+        "Counter": "0,1",
+        "EventCode": "0x8",
+        "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
+        "SampleAfterValue": "200000",
+        "UMask": "0x9"
+    },
+    {
+        "BriefDescription": "L0 DTLB misses due to store operations",
+        "Counter": "0,1",
+        "EventCode": "0x8",
+        "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
+        "SampleAfterValue": "200000",
+        "UMask": "0xa"
+    },
+    {
+        "BriefDescription": "ITLB flushes.",
+        "Counter": "0,1",
+        "EventCode": "0x82",
+        "EventName": "ITLB.FLUSH",
+        "SampleAfterValue": "200000",
+        "UMask": "0x4"
+    },
+    {
+        "BriefDescription": "ITLB hits.",
+        "Counter": "0,1",
+        "EventCode": "0x82",
+        "EventName": "ITLB.HIT",
+        "SampleAfterValue": "200000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "ITLB misses.",
+        "Counter": "0,1",
+        "EventCode": "0x82",
+        "EventName": "ITLB.MISSES",
+        "PEBS": "2",
+        "SampleAfterValue": "200000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Retired loads that miss the DTLB (precise event).",
+        "Counter": "0,1",
+        "EventCode": "0xCB",
+        "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
+        "PEBS": "1",
+        "SampleAfterValue": "200000",
+        "UMask": "0x4"
+    },
+    {
+        "BriefDescription": "Duration of page-walks in core cycles",
+        "Counter": "0,1",
+        "EventCode": "0xC",
+        "EventName": "PAGE_WALKS.CYCLES",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x3"
+    },
+    {
+        "BriefDescription": "Duration of D-side only page walks",
+        "Counter": "0,1",
+        "EventCode": "0xC",
+        "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Number of D-side only page walks",
+        "Counter": "0,1",
+        "EventCode": "0xC",
+        "EventName": "PAGE_WALKS.D_SIDE_WALKS",
+        "SampleAfterValue": "200000",
+        "UMask": "0x1"
+    },
+    {
+        "BriefDescription": "Duration of I-Side page walks",
+        "Counter": "0,1",
+        "EventCode": "0xC",
+        "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
+        "SampleAfterValue": "2000000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Number of I-Side page walks",
+        "Counter": "0,1",
+        "EventCode": "0xC",
+        "EventName": "PAGE_WALKS.I_SIDE_WALKS",
+        "SampleAfterValue": "200000",
+        "UMask": "0x2"
+    },
+    {
+        "BriefDescription": "Number of page-walks executed.",
+        "Counter": "0,1",
+        "EventCode": "0xC",
+        "EventName": "PAGE_WALKS.WALKS",
+        "SampleAfterValue": "200000",
+        "UMask": "0x3"
+    }
+]