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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas EMMA Mobile EV2 System Management Unit
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Magnus Damm <magnus.damm@gmail.com>
+
+description: |
+ The System Management Unit is described in user's manual R19UH0037EJ1000_SMU.
+ This is not a clock provider, but clocks under SMU depend on it.
+
+properties:
+ compatible:
+ const: renesas,emev2-smu
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 2
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+
+patternProperties:
+ ".*sclkdiv@.*":
+ type: object
+
+ description: |
+ Function block with an input mux and a divider, which corresponds to
+ "Serial clock generator" in fig. "Clock System Overview" of the manual,
+ and "xxx frequency division setting register" (XXXCLKDIV) registers.
+ This makes internal (neither input nor output) clock that is provided
+ to input of xxxGCLK block.
+
+ properties:
+ compatible:
+ const: renesas,emev2-smu-clkdiv
+
+ reg:
+ maxItems: 1
+ description:
+ Byte offset from SMU base and Bit position in the register.
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ '#clock-cells':
+ const: 0
+
+ required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+ additionalProperties: false
+
+ ".*sclk@.*":
+ type: object
+
+ description: |
+ Clock gating node shown as "Clock stop processing block" in the
+ fig. "Clock System Overview" of the manual.
+ Registers are "xxx clock gate control register" (XXXGCLKCTRL).
+
+ properties:
+ compatible:
+ const: renesas,emev2-smu-gclk
+
+ reg:
+ maxItems: 1
+ description:
+ Byte offset from SMU base and Bit position in the register.
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 0
+
+ required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+ additionalProperties: false
+
+additionalProperties: true
+
+examples:
+ - |
+ // Example of clock-tree description:
+ //
+ // This describes a clock path in the clock tree
+ // c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
+ clocks@e0110000 {
+ compatible = "renesas,emev2-smu";
+ reg = <0xe0110000 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ c32ki: c32ki {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+ pll3_fo: pll3_fo {
+ compatible = "fixed-factor-clock";
+ clocks = <&c32ki>;
+ clock-div = <1>;
+ clock-mult = <7000>;
+ #clock-cells = <0>;
+ };
+ usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
+ compatible = "renesas,emev2-smu-clkdiv";
+ reg = <0x610 0>;
+ clocks = <&pll3_fo>;
+ #clock-cells = <0>;
+ };
+ usia_u0_sclk: usia_u0_sclk@4a0,1 {
+ compatible = "renesas,emev2-smu-gclk";
+ reg = <0x4a0 1>;
+ clocks = <&usia_u0_sclkdiv>;
+ #clock-cells = <0>;
+ };
+ };