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-rw-r--r-- | Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 109 |
1 files changed, 109 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml new file mode 100644 index 000000000..3ee77af5a --- /dev/null +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SPI NOR flash ST M25Pxx (and similar) serial flash chips + +maintainers: + - Rob Herring <robh@kernel.org> + +allOf: + - $ref: "mtd.yaml#" + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + oneOf: + - items: + - pattern: "^((((micron|spansion|st),)?\ + (m25p(40|80|16|32|64|128)|\ + n25q(32b|064|128a11|128a13|256a|512a|164k)))|\ + atmel,at25df(321a|641|081a)|\ + everspin,mr25h(10|40|128|256)|\ + (mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|\ + (mxicy|macronix),mx25u(4033|4035)|\ + (spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|\ + (sst|microchip),sst25vf(016b|032b|040b)|\ + (sst,)?sst26wf016b|\ + (sst,)?sst25wf(040b|080)|\ + winbond,w25x(80|32)|\ + (winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$" + - const: jedec,spi-nor + - items: + - enum: + - issi,is25lp016d + - micron,mt25qu02g + - mxicy,mx25r1635f + - mxicy,mx25u6435f + - mxicy,mx25v8035f + - spansion,s25sl12801 + - spansion,s25fs512s + - const: jedec,spi-nor + - const: jedec,spi-nor + description: + Must also include "jedec,spi-nor" for any SPI NOR flash that can be + identified by the JEDEC READ ID opcode (0x9F). + + reg: + minItems: 1 + maxItems: 2 + + m25p,fast-read: + type: boolean + description: + Use the "fast read" opcode to read data from the chip instead of the usual + "read" opcode. This opcode is not supported by all chips and support for + it can not be detected at runtime. Refer to your chips' datasheet to check + if this is supported by your chip. + + broken-flash-reset: + type: boolean + description: + Some flash devices utilize stateful addressing modes (e.g., for 32-bit + addressing) which need to be managed carefully by a system. Because these + sorts of flash don't have a standardized software reset command, and + because some systems don't toggle the flash RESET# pin upon system reset + (if the pin even exists at all), there are systems which cannot reboot + properly if the flash is left in the "wrong" state. This boolean flag can + be used on such systems, to denote the absence of a reliable reset + mechanism. + + partitions: + type: object + + '#address-cells': true + '#size-cells': true + +patternProperties: + # Note: use 'partitions' node for new users + '^partition@': + type: object + + "^otp(-[0-9]+)?$": + type: object + + spi-cpol: true + spi-cpha: true + +dependencies: + spi-cpol: [ spi-cpha ] + spi-cpha: [ spi-cpol ] + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "spansion,m25p80", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + m25p,fast-read; + }; + }; +... |