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Diffstat (limited to 'arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi')
-rw-r--r--arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi86
1 files changed, 86 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi
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index 000000000..1dd4a65cb
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+++ b/arch/arm/boot/dts/intel-ixp45x-ixp46x.dtsi
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: ISC
+/*
+ * Device Tree file for Intel XScale Network Processors
+ * in the IXP45x and IXP46x series. This series has 64 interrupts and adds a
+ * few more peripherals over the 42x and 43x series so this extends the
+ * basic IXP4xx DTSI.
+ */
+#include "intel-ixp4xx.dtsi"
+
+/ {
+ soc {
+ bus@c4000000 {
+ compatible = "intel,ixp46x-expansion-bus-controller", "syscon";
+ /* Uses at least up to 0x124 */
+ reg = <0xc4000000 0x1000>;
+ };
+
+ rng@70002100 {
+ compatible = "intel,ixp46x-rng";
+ reg = <0x70002100 4>;
+ };
+
+ interrupt-controller@c8003000 {
+ compatible = "intel,ixp43x-interrupt";
+ };
+
+ /*
+ * This is the USB Device Mode (UDC) controller, which is used
+ * to present the IXP4xx as a device on a USB bus.
+ */
+ usb@c800b000 {
+ compatible = "intel,ixp4xx-udc";
+ reg = <0xc800b000 0x1000>;
+ interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ i2c@c8011000 {
+ compatible = "intel,ixp4xx-i2c";
+ reg = <0xc8011000 0x18>;
+ interrupts = <33 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ /* This is known as EthB1 */
+ ethernet@c800d000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc800d000 0x1000>;
+ status = "disabled";
+ intel,npe = <1>;
+ /* Dummy values that depend on firmware */
+ queue-rx = <&qmgr 0>;
+ queue-txready = <&qmgr 0>;
+ };
+
+ /* This is known as EthB2 */
+ ethernet@c800e000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc800e000 0x1000>;
+ status = "disabled";
+ intel,npe = <2>;
+ /* Dummy values that depend on firmware */
+ queue-rx = <&qmgr 0>;
+ queue-txready = <&qmgr 0>;
+ };
+
+ /* This is known as EthB3 */
+ ethernet@c800f000 {
+ compatible = "intel,ixp4xx-ethernet";
+ reg = <0xc800f000 0x1000>;
+ status = "disabled";
+ intel,npe = <3>;
+ /* Dummy values that depend on firmware */
+ queue-rx = <&qmgr 0>;
+ queue-txready = <&qmgr 0>;
+ };
+
+ ptp-timer@c8010000 {
+ compatible = "intel,ixp46x-ptp-timer";
+ reg = <0xc8010000 0x1000>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>, <7 IRQ_TYPE_EDGE_FALLING>;
+ interrupt-names = "master", "slave";
+ };
+ };
+};