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Diffstat (limited to '')
| -rw-r--r-- | arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts | 84 |
1 files changed, 84 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts new file mode 100644 index 000000000..eff9e8dbd --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt6797-x20-dev.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for MediaTek X20 Development Board + * + * Copyright (C) 2018, Linaro Ltd. + * + */ + +/dts-v1/; + +#include "mt6797.dtsi" + +/ { + model = "Mediatek X20 Development Board"; + compatible = "archermind,mt6797-x20-dev", "mediatek,mt6797"; + + aliases { + serial0 = &uart1; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* HDMI */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_a>; + status = "okay"; +}; + +/* HS - I2C2 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + status = "okay"; +}; + +/* HS - I2C3 */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins_a>; + status = "okay"; +}; + +/* LS - I2C0 */ +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins_a>; + status = "okay"; +}; + +/* LS - I2C1 */ +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + status = "okay"; +}; + +/* POWER_VPROC */ +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins_a>; + status = "okay"; +}; + +/* FAN53555 */ +&i2c7 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c7_pins_a>; + status = "okay"; +}; + +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>; +}; |