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-rw-r--r--arch/mips/fw/cfe/Makefile6
-rw-r--r--arch/mips/fw/cfe/cfe_api.c480
-rw-r--r--arch/mips/fw/cfe/cfe_api_int.h135
3 files changed, 621 insertions, 0 deletions
diff --git a/arch/mips/fw/cfe/Makefile b/arch/mips/fw/cfe/Makefile
new file mode 100644
index 000000000..55b77633e
--- /dev/null
+++ b/arch/mips/fw/cfe/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+#
+# Makefile for the Broadcom Common Firmware Environment support
+#
+
+lib-y += cfe_api.o
diff --git a/arch/mips/fw/cfe/cfe_api.c b/arch/mips/fw/cfe/cfe_api.c
new file mode 100644
index 000000000..dcdfd962d
--- /dev/null
+++ b/arch/mips/fw/cfe/cfe_api.c
@@ -0,0 +1,480 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
+ */
+
+/*
+ *
+ * Broadcom Common Firmware Environment (CFE)
+ *
+ * This module contains device function stubs (small routines to
+ * call the standard "iocb" interface entry point to CFE).
+ * There should be one routine here per iocb function call.
+ *
+ * Authors: Mitch Lichtenberg, Chris Demetriou
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/printk.h>
+#include <asm/mipsregs.h>
+#include <asm/fw/cfe/cfe_api.h>
+#include "cfe_api_int.h"
+
+unsigned long __initdata cfe_seal;
+
+/* Cast from a native pointer to a cfe_xptr_t and back. */
+#define XPTR_FROM_NATIVE(n) ((cfe_xptr_t) (intptr_t) (n))
+#define NATIVE_FROM_XPTR(x) ((void *) (intptr_t) (x))
+
+int cfe_iocb_dispatch(struct cfe_xiocb *xiocb);
+
+/*
+ * Declare the dispatch function with args of "intptr_t".
+ * This makes sure whatever model we're compiling in
+ * puts the pointers in a single register. For example,
+ * combining -mlong64 and -mips1 or -mips2 would lead to
+ * trouble, since the handle and IOCB pointer will be
+ * passed in two registers each, and CFE expects one.
+ */
+
+static int (*cfe_dispfunc) (intptr_t handle, intptr_t xiocb);
+static u64 cfe_handle;
+
+int cfe_init(u64 handle, u64 ept)
+{
+ cfe_dispfunc = NATIVE_FROM_XPTR(ept);
+ cfe_handle = handle;
+ return 0;
+}
+
+int cfe_iocb_dispatch(struct cfe_xiocb * xiocb)
+{
+ if (!cfe_dispfunc)
+ return -1;
+ return (*cfe_dispfunc) ((intptr_t) cfe_handle, (intptr_t) xiocb);
+}
+
+int cfe_close(int handle)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_CLOSE;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = handle;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = 0;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+
+}
+
+int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(struct xiocb_cpuctl);
+ xiocb.plist.xiocb_cpuctl.cpu_number = cpu;
+ xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_START;
+ xiocb.plist.xiocb_cpuctl.gp_val = gp;
+ xiocb.plist.xiocb_cpuctl.sp_val = sp;
+ xiocb.plist.xiocb_cpuctl.a1_val = a1;
+ xiocb.plist.xiocb_cpuctl.start_addr = (long) fn;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+}
+
+int cfe_cpu_stop(int cpu)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_FW_CPUCTL;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(struct xiocb_cpuctl);
+ xiocb.plist.xiocb_cpuctl.cpu_number = cpu;
+ xiocb.plist.xiocb_cpuctl.cpu_command = CFE_CPU_CMD_STOP;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+}
+
+int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(struct xiocb_envbuf);
+ xiocb.plist.xiocb_envbuf.enum_idx = idx;
+ xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
+ xiocb.plist.xiocb_envbuf.name_length = namelen;
+ xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val);
+ xiocb.plist.xiocb_envbuf.val_length = vallen;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+}
+
+int
+cfe_enummem(int idx, int flags, u64 *start, u64 *length, u64 *type)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_FW_MEMENUM;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = flags;
+ xiocb.xiocb_psize = sizeof(struct xiocb_meminfo);
+ xiocb.plist.xiocb_meminfo.mi_idx = idx;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+
+ *start = xiocb.plist.xiocb_meminfo.mi_addr;
+ *length = xiocb.plist.xiocb_meminfo.mi_size;
+ *type = xiocb.plist.xiocb_meminfo.mi_type;
+
+ return 0;
+}
+
+int cfe_exit(int warm, int status)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_FW_RESTART;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = warm ? CFE_FLG_WARMSTART : 0;
+ xiocb.xiocb_psize = sizeof(struct xiocb_exitstat);
+ xiocb.plist.xiocb_exitstat.status = status;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+}
+
+int cfe_flushcache(int flg)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_FW_FLUSHCACHE;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = flg;
+ xiocb.xiocb_psize = 0;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+}
+
+int cfe_getdevinfo(char *name)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_GETINFO;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
+ xiocb.plist.xiocb_buffer.buf_offset = 0;
+ xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name);
+ xiocb.plist.xiocb_buffer.buf_length = strlen(name);
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+ return xiocb.plist.xiocb_buffer.buf_ioctlcmd;
+}
+
+int cfe_getenv(char *name, char *dest, int destlen)
+{
+ struct cfe_xiocb xiocb;
+
+ *dest = 0;
+
+ xiocb.xiocb_fcode = CFE_CMD_ENV_GET;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(struct xiocb_envbuf);
+ xiocb.plist.xiocb_envbuf.enum_idx = 0;
+ xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
+ xiocb.plist.xiocb_envbuf.name_length = strlen(name);
+ xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(dest);
+ xiocb.plist.xiocb_envbuf.val_length = destlen;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+}
+
+int cfe_getfwinfo(cfe_fwinfo_t * info)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_FW_GETINFO;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(struct xiocb_fwinfo);
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+
+ info->fwi_version = xiocb.plist.xiocb_fwinfo.fwi_version;
+ info->fwi_totalmem = xiocb.plist.xiocb_fwinfo.fwi_totalmem;
+ info->fwi_flags = xiocb.plist.xiocb_fwinfo.fwi_flags;
+ info->fwi_boardid = xiocb.plist.xiocb_fwinfo.fwi_boardid;
+ info->fwi_bootarea_va = xiocb.plist.xiocb_fwinfo.fwi_bootarea_va;
+ info->fwi_bootarea_pa = xiocb.plist.xiocb_fwinfo.fwi_bootarea_pa;
+ info->fwi_bootarea_size =
+ xiocb.plist.xiocb_fwinfo.fwi_bootarea_size;
+
+ return 0;
+}
+
+int cfe_getstdhandle(int flg)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_GETHANDLE;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = flg;
+ xiocb.xiocb_psize = 0;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+ return xiocb.xiocb_handle;
+}
+
+int64_t
+cfe_getticks(void)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_FW_GETTIME;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(struct xiocb_time);
+ xiocb.plist.xiocb_time.ticks = 0;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.plist.xiocb_time.ticks;
+
+}
+
+int cfe_inpstat(int handle)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_INPSTAT;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = handle;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(struct xiocb_inpstat);
+ xiocb.plist.xiocb_inpstat.inp_status = 0;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+ return xiocb.plist.xiocb_inpstat.inp_status;
+}
+
+int
+cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
+ int length, int *retlen, u64 offset)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_IOCTL;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = handle;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
+ xiocb.plist.xiocb_buffer.buf_offset = offset;
+ xiocb.plist.xiocb_buffer.buf_ioctlcmd = ioctlnum;
+ xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
+ xiocb.plist.xiocb_buffer.buf_length = length;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (retlen)
+ *retlen = xiocb.plist.xiocb_buffer.buf_retlen;
+ return xiocb.xiocb_status;
+}
+
+int cfe_open(char *name)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_OPEN;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
+ xiocb.plist.xiocb_buffer.buf_offset = 0;
+ xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(name);
+ xiocb.plist.xiocb_buffer.buf_length = strlen(name);
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+ return xiocb.xiocb_handle;
+}
+
+int cfe_read(int handle, unsigned char *buffer, int length)
+{
+ return cfe_readblk(handle, 0, buffer, length);
+}
+
+int cfe_readblk(int handle, s64 offset, unsigned char *buffer, int length)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_READ;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = handle;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
+ xiocb.plist.xiocb_buffer.buf_offset = offset;
+ xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
+ xiocb.plist.xiocb_buffer.buf_length = length;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+ return xiocb.plist.xiocb_buffer.buf_retlen;
+}
+
+int cfe_setenv(char *name, char *val)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_ENV_SET;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = 0;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(struct xiocb_envbuf);
+ xiocb.plist.xiocb_envbuf.enum_idx = 0;
+ xiocb.plist.xiocb_envbuf.name_ptr = XPTR_FROM_NATIVE(name);
+ xiocb.plist.xiocb_envbuf.name_length = strlen(name);
+ xiocb.plist.xiocb_envbuf.val_ptr = XPTR_FROM_NATIVE(val);
+ xiocb.plist.xiocb_envbuf.val_length = strlen(val);
+
+ cfe_iocb_dispatch(&xiocb);
+
+ return xiocb.xiocb_status;
+}
+
+int cfe_write(int handle, const char *buffer, int length)
+{
+ return cfe_writeblk(handle, 0, buffer, length);
+}
+
+int cfe_writeblk(int handle, s64 offset, const char *buffer, int length)
+{
+ struct cfe_xiocb xiocb;
+
+ xiocb.xiocb_fcode = CFE_CMD_DEV_WRITE;
+ xiocb.xiocb_status = 0;
+ xiocb.xiocb_handle = handle;
+ xiocb.xiocb_flags = 0;
+ xiocb.xiocb_psize = sizeof(struct xiocb_buffer);
+ xiocb.plist.xiocb_buffer.buf_offset = offset;
+ xiocb.plist.xiocb_buffer.buf_ptr = XPTR_FROM_NATIVE(buffer);
+ xiocb.plist.xiocb_buffer.buf_length = length;
+
+ cfe_iocb_dispatch(&xiocb);
+
+ if (xiocb.xiocb_status < 0)
+ return xiocb.xiocb_status;
+ return xiocb.plist.xiocb_buffer.buf_retlen;
+}
+
+void __init cfe_die(char *fmt, ...)
+{
+ unsigned int prid, __maybe_unused rev;
+ char msg[128];
+ va_list ap;
+ int handle;
+ unsigned int count;
+
+ va_start(ap, fmt);
+ vsprintf(msg, fmt, ap);
+ strcat(msg, "\r\n");
+
+ if (cfe_seal != CFE_EPTSEAL)
+ goto no_cfe;
+
+ prid = read_c0_prid();
+ if ((prid & PRID_COMP_MASK) != PRID_COMP_BROADCOM)
+ goto no_cfe;
+
+ rev = prid & PRID_REV_MASK;
+
+ /* disable XKS01 so that CFE can access the registers */
+ switch (prid & PRID_IMP_MASK) {
+#ifdef CONFIG_CPU_BMIPS4380
+ case PRID_IMP_BMIPS43XX:
+ if (rev >= PRID_REV_BMIPS4380_LO &&
+ rev <= PRID_REV_BMIPS4380_HI)
+ __write_32bit_c0_register($22, 3,
+ __read_32bit_c0_register($22, 3) & ~BIT(12));
+ break;
+#endif
+#ifdef CONFIG_CPU_BMIPS5000
+ case PRID_IMP_BMIPS5000:
+ case PRID_IMP_BMIPS5200:
+ __write_32bit_c0_register($22, 5,
+ __read_32bit_c0_register($22, 5) & ~BIT(8));
+ break;
+#endif
+ default:
+ break;
+ }
+
+ handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
+ if (handle < 0)
+ goto no_cfe;
+
+ cfe_write(handle, msg, strlen(msg));
+
+ for (count = 0; count < 0x7fffffff; count++)
+ mb();
+ cfe_exit(0, 1);
+ while (1)
+ ;
+
+no_cfe:
+ /* probably won't print anywhere useful */
+ panic("%s", msg);
+
+ va_end(ap);
+}
diff --git a/arch/mips/fw/cfe/cfe_api_int.h b/arch/mips/fw/cfe/cfe_api_int.h
new file mode 100644
index 000000000..61a665d44
--- /dev/null
+++ b/arch/mips/fw/cfe/cfe_api_int.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
+ */
+#ifndef CFE_API_INT_H
+#define CFE_API_INT_H
+
+/*
+ * Constants.
+ */
+#define CFE_CMD_FW_GETINFO 0
+#define CFE_CMD_FW_RESTART 1
+#define CFE_CMD_FW_BOOT 2
+#define CFE_CMD_FW_CPUCTL 3
+#define CFE_CMD_FW_GETTIME 4
+#define CFE_CMD_FW_MEMENUM 5
+#define CFE_CMD_FW_FLUSHCACHE 6
+
+#define CFE_CMD_DEV_GETHANDLE 9
+#define CFE_CMD_DEV_ENUM 10
+#define CFE_CMD_DEV_OPEN 11
+#define CFE_CMD_DEV_INPSTAT 12
+#define CFE_CMD_DEV_READ 13
+#define CFE_CMD_DEV_WRITE 14
+#define CFE_CMD_DEV_IOCTL 15
+#define CFE_CMD_DEV_CLOSE 16
+#define CFE_CMD_DEV_GETINFO 17
+
+#define CFE_CMD_ENV_ENUM 20
+#define CFE_CMD_ENV_GET 22
+#define CFE_CMD_ENV_SET 23
+#define CFE_CMD_ENV_DEL 24
+
+#define CFE_CMD_MAX 32
+
+#define CFE_CMD_VENDOR_USE 0x8000 /* codes above this are for customer use */
+
+/*
+ * Structures.
+ */
+
+/* eeek, signed "pointers" */
+typedef s64 cfe_xptr_t;
+
+struct xiocb_buffer {
+ u64 buf_offset; /* offset on device (bytes) */
+ cfe_xptr_t buf_ptr; /* pointer to a buffer */
+ u64 buf_length; /* length of this buffer */
+ u64 buf_retlen; /* returned length (for read ops) */
+ u64 buf_ioctlcmd; /* IOCTL command (used only for IOCTLs) */
+};
+
+struct xiocb_inpstat {
+ u64 inp_status; /* 1 means input available */
+};
+
+struct xiocb_envbuf {
+ s64 enum_idx; /* 0-based enumeration index */
+ cfe_xptr_t name_ptr; /* name string buffer */
+ s64 name_length; /* size of name buffer */
+ cfe_xptr_t val_ptr; /* value string buffer */
+ s64 val_length; /* size of value string buffer */
+};
+
+struct xiocb_cpuctl {
+ u64 cpu_number; /* cpu number to control */
+ u64 cpu_command; /* command to issue to CPU */
+ u64 start_addr; /* CPU start address */
+ u64 gp_val; /* starting GP value */
+ u64 sp_val; /* starting SP value */
+ u64 a1_val; /* starting A1 value */
+};
+
+struct xiocb_time {
+ s64 ticks; /* current time in ticks */
+};
+
+struct xiocb_exitstat{
+ s64 status;
+};
+
+struct xiocb_meminfo {
+ s64 mi_idx; /* 0-based enumeration index */
+ s64 mi_type; /* type of memory block */
+ u64 mi_addr; /* physical start address */
+ u64 mi_size; /* block size */
+};
+
+struct xiocb_fwinfo {
+ s64 fwi_version; /* major, minor, eco version */
+ s64 fwi_totalmem; /* total installed mem */
+ s64 fwi_flags; /* various flags */
+ s64 fwi_boardid; /* board ID */
+ s64 fwi_bootarea_va; /* VA of boot area */
+ s64 fwi_bootarea_pa; /* PA of boot area */
+ s64 fwi_bootarea_size; /* size of boot area */
+ s64 fwi_reserved1;
+ s64 fwi_reserved2;
+ s64 fwi_reserved3;
+};
+
+struct cfe_xiocb {
+ u64 xiocb_fcode; /* IOCB function code */
+ s64 xiocb_status; /* return status */
+ s64 xiocb_handle; /* file/device handle */
+ u64 xiocb_flags; /* flags for this IOCB */
+ u64 xiocb_psize; /* size of parameter list */
+ union {
+ /* buffer parameters */
+ struct xiocb_buffer xiocb_buffer;
+
+ /* input status parameters */
+ struct xiocb_inpstat xiocb_inpstat;
+
+ /* environment function parameters */
+ struct xiocb_envbuf xiocb_envbuf;
+
+ /* CPU control parameters */
+ struct xiocb_cpuctl xiocb_cpuctl;
+
+ /* timer parameters */
+ struct xiocb_time xiocb_time;
+
+ /* memory arena info parameters */
+ struct xiocb_meminfo xiocb_meminfo;
+
+ /* firmware information */
+ struct xiocb_fwinfo xiocb_fwinfo;
+
+ /* Exit Status */
+ struct xiocb_exitstat xiocb_exitstat;
+ } plist;
+};
+
+#endif /* CFE_API_INT_H */