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Diffstat (limited to '')
-rw-r--r-- | arch/sh/boot/dts/j2_mimas_v2.dts | 99 |
1 files changed, 99 insertions, 0 deletions
diff --git a/arch/sh/boot/dts/j2_mimas_v2.dts b/arch/sh/boot/dts/j2_mimas_v2.dts new file mode 100644 index 000000000..fa9562f78 --- /dev/null +++ b/arch/sh/boot/dts/j2_mimas_v2.dts @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +/ { + compatible = "jcore,j2-soc"; + model = "J2 FPGA SoC on Mimas v2 board"; + + #address-cells = <1>; + #size-cells = <1>; + + interrupt-parent = <&aic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "jcore,j2"; + reg = <0>; + clock-frequency = <50000000>; + d-cache-size = <8192>; + i-cache-size = <8192>; + d-cache-block-size = <16>; + i-cache-block-size = <16>; + }; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x4000000>; + }; + + aliases { + serial0 = &uart0; + spi0 = &spi0; + }; + + chosen { + stdout-path = "serial0"; + }; + + soc@abcd0000 { + compatible = "simple-bus"; + ranges = <0 0xabcd0000 0x100000>; + + #address-cells = <1>; + #size-cells = <1>; + + aic: interrupt-controller@200 { + compatible = "jcore,aic1"; + reg = <0x200 0x10>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + cache-controller@c0 { + compatible = "jcore,cache"; + reg = <0xc0 4>; + }; + + timer@200 { + compatible = "jcore,pit"; + reg = <0x200 0x30>; + interrupts = <0x48>; + }; + + spi0: spi@40 { + compatible = "jcore,spi2"; + + #address-cells = <1>; + #size-cells = <0>; + + spi-max-frequency = <25000000>; + + reg = <0x40 0x8>; + + sdcard@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <25000000>; + voltage-ranges = <3200 3400>; + mode = <0>; + }; + }; + + uart0: serial@100 { + clock-frequency = <125000000>; + compatible = "xlnx,xps-uartlite-1.00.a"; + current-speed = <19200>; + xlnx,use-parity = <0>; + xlnx,data-bits = <8>; + device_type = "serial"; + interrupts = <0x12>; + port-number = <0>; + reg = <0x100 0x10>; + }; + }; +}; |