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-rw-r--r--debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Add-SOQuartz-Model-A-baseboard.patch279
-rw-r--r--debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Add-SOQuartz-blade-board.patch242
-rw-r--r--debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-HDMI-sound-on-SOQuartz.patch44
-rw-r--r--debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch82
-rw-r--r--debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-video-output-and-HDMI-on-S.patch94
-rw-r--r--debian/patches/features/arm64/quartz64/arm64-dts-rockchip-RK356x-Add-I2S2-device-node.patch50
-rw-r--r--debian/patches/features/arm64/quartz64/dt-bindings-arm-rockchip-Add-SOQuartz-Blade.patch39
-rw-r--r--debian/patches/features/arm64/quartz64/dt-bindings-arm-rockchip-Add-SOQuartz-Model-A.patch39
8 files changed, 869 insertions, 0 deletions
diff --git a/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Add-SOQuartz-Model-A-baseboard.patch b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Add-SOQuartz-Model-A-baseboard.patch
new file mode 100644
index 000000000..ae644e05f
--- /dev/null
+++ b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Add-SOQuartz-Model-A-baseboard.patch
@@ -0,0 +1,279 @@
+From: Andrew Powers-Holmes <aholmes@omnom.net>
+Date: Wed, 16 Nov 2022 12:53:37 +0100
+Subject: [4/4] arm64: dts: rockchip: Add SOQuartz Model A baseboard
+Origin: https://git.kernel.org/linus/afbaed737fb45bcae91e4606025fb31da71b9dfe
+
+This patch adds the device tree for the "Model A" baseboard for
+the SOQuartz CM4 SoM, which is not to be confused with the
+Quartz64 Model A, which is the same form factor and SoC, but is
+not a CM4 carrier board.
+
+The board features a PCIe 2 x1 slot, USB 2 host ports, CSI/DSI
+connectors, an eDP FFC connector, gigabit ethernet, HDMI, and a
+12V DC barrel jack. Also present is a microSD card slot, 40-pin
+GPIO, and a power and reset button.
+
+Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
+[rebase, misc fixes, reword]
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20221116115337.541601-5-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../dts/rockchip/rk3566-soquartz-model-a.dts | 232 ++++++++++++++++++
+ 2 files changed, 233 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts
+
+diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
+index 071284a46bf7..0a76a2ebb5f6 100644
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
+diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts
+new file mode 100644
+index 000000000000..2208dbfb7f0a
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts
+@@ -0,0 +1,232 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include "rk3566-soquartz.dtsi"
++
++/ {
++ model = "PINE64 RK3566 SOQuartz on Model A carrier board";
++ compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566";
++
++ /* labeled DCIN_12V in schematic */
++ vcc12v_dcin: vcc12v-dcin-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc12v_dcin";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <12000000>;
++ regulator-max-microvolt = <12000000>;
++ };
++
++ vcc5v0_usb: vcc5v0-usb-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v0_usb";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ vin-supply = <&vcc12v_dcin>;
++ };
++
++ /*
++ * Labelled VCC3V0_SD in schematic to not conflict with PMIC
++ * regulator, it's 3.3v in actuality
++ */
++ vcc3v0_sd: vcc3v0-sd-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v0_sd";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc3v3_sys>;
++ };
++
++ vcc3v3_pcie: vcc3v3-pcie-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_pcie";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc12v_dcin>;
++ };
++
++ vcc12v_pcie: vcc12v-pcie-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc12v_pcie";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <12000000>;
++ regulator-max-microvolt = <12000000>;
++ vin-supply = <&vcc12v_dcin>;
++ };
++};
++
++/* phy for pcie */
++&combphy2 {
++ phy-supply = <&vcc3v3_sys>;
++ status = "okay";
++};
++
++&gmac1 {
++ status = "okay";
++};
++
++/*
++ * i2c1 is exposed on CM1 / Module1A
++ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
++ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
++ */
++&i2c1 {
++ status = "okay";
++
++ /*
++ * the rtc interrupt is tied to PMIC_PWRON,
++ * it will force reset the board if triggered.
++ */
++ pcf85063: rtc@51 {
++ compatible = "nxp,pcf85063";
++ reg = <0x51>;
++ };
++};
++
++/*
++ * i2c2 is exposed on CM1 / Module1A - to PI40
++ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
++ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
++ */
++&i2c2 {
++ status = "disabled";
++};
++
++/*
++ * i2c3 is exposed on CM1 / Module1A - to PI40
++ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
++ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
++ */
++&i2c3 {
++ status = "disabled";
++};
++
++/*
++ * i2c4 is exposed on CM2 / Module1B - to PI40
++ * pin 45 - GPIO24 - i2c4_scl_m1
++ * pin 47 - GPIO23 - i2c4_sda_m1
++ */
++&i2c4 {
++ status = "disabled";
++};
++
++/*
++ * i2s1_8ch is exposed on CM1 / Module1A - to PI40
++ * pin 24 - GPIO26 - i2s1_sdi1_m1
++ * pin 25 - GPIO21 - i2s1_sdo0_m1
++ * pin 26 - GPIO19 - i2s1_lrck_tx_m1
++ * pin 27 - GPIO20 - i2s1_sdi0_m1
++ * pin 29 - GPIO16 - i2s1_sdi3_m1
++ * pin 30 - GPIO6 - i2s1_sdi2_m1
++ * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
++ * pin 41 - GPIO25 - i2s1_sdo2_m1
++ * pin 49 - GPIO18 - i2s1_sclk_tx_m1
++ * pin 50 - GPIO17 - i2s1_mclk_m1
++ * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
++ */
++&i2s1_8ch {
++ status = "disabled";
++};
++
++&led_diy {
++ status = "okay";
++};
++
++&led_work {
++ status = "okay";
++};
++
++&pcie2x1 {
++ vpcie3v3-supply = <&vcc3v3_pcie>;
++ status = "okay";
++};
++
++&rgmii_phy1 {
++ status = "okay";
++};
++
++&rgmii_phy1 {
++ status = "okay";
++};
++
++/*
++ * saradc is exposed on CM1 / Module1A - to J2
++ * pin 94 - AIN1 - saradc_vin3
++ * pin 96 - AIN0 - saradc_vin2
++ */
++&saradc {
++ status = "disabled";
++};
++
++/*
++ * vmmc-supply is vcc3v3_sd on v1.0 and vcc3v0_sd on v1.1+
++ * the soquartz SoM has SDMMC_PWR (CM1 pin 75) hardwired to vcc3v3_sys,
++ * so we use vcc3v3_sd here to ensure the regulator is enabled on older boards.
++ */
++&sdmmc0 {
++ vmmc-supply = <&vcc3v3_sd>;
++ status = "okay";
++};
++
++/*
++ * spi3 is exposed on CM1 / Module1A - to PI40
++ * pin 37 - GPIO7 - spi3_cs1_m0
++ * pin 38 - GPIO11 - spi3_clk_m0
++ * pin 39 - GPIO8 - spi3_cs0_m0
++ * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
++ * pin 44 - GPIO10 - spi3_mosi_m0
++ */
++&spi3 {
++ status = "disabled";
++};
++
++/*
++ * uart2 is exposed on CM1 / Module1A - to PI40
++ * pin 51 - GPIO15 - uart2_rx_m0
++ * pin 55 - GPIO14 - uart2_tx_m0
++ */
++&uart2 {
++ status = "okay";
++};
++
++/*
++ * uart7 is exposed on CM1 / Module1A - to PI40
++ * pin 46 - GPIO22 - uart7_tx_m2
++ * pin 47 - GPIO23 - uart7_rx_m2
++ */
++&uart7 {
++ status = "okay";
++};
++
++&usb2phy0 {
++ status = "okay";
++};
++
++&usb2phy0_otg {
++ phy-supply = <&vcc5v0_usb>;
++ status = "okay";
++};
++
++&usb_host0_xhci {
++ status = "okay";
++};
++
++&vbus {
++ vin-supply = <&vcc5v0_usb>;
++};
++
++&vcc3v3_sd {
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ status = "okay";
++};
+--
+2.39.0
+
diff --git a/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Add-SOQuartz-blade-board.patch b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Add-SOQuartz-blade-board.patch
new file mode 100644
index 000000000..246d62c12
--- /dev/null
+++ b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Add-SOQuartz-blade-board.patch
@@ -0,0 +1,242 @@
+From: Andrew Powers-Holmes <aholmes@omnom.net>
+Date: Wed, 16 Nov 2022 12:53:35 +0100
+Subject: [2/4] arm64: dts: rockchip: Add SOQuartz blade board
+Origin: https://git.kernel.org/linus/a5c826ecde5222f755e7d8a0c8d795189c5c1228
+
+This adds a device tree for the PINE64 SOQuartz blade baseboard,
+a 1U rack mountable baseboard for the CM4 form factor with PoE
+support designed for the SOQuartz CM4 System-on-Module.
+
+The board takes power from either PoE or a 5V DC input, and allows
+for mounting an M.2 SSD.
+
+The board also features one USB 2.0 host port, one HDMI output,
+a 3.5mm jack for UART, and the aforementioned gigabit networking
+port.
+
+Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
+[rebase, squash, reword, misc fixes]
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20221116115337.541601-3-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 1 +
+ .../dts/rockchip/rk3566-soquartz-blade.dts | 194 ++++++++++++++++++
+ 2 files changed, 195 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts
+
+diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
+index e14390277739..071284a46bf7 100644
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -68,6 +68,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts
+new file mode 100644
+index 000000000000..4e49bebf548b
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts
+@@ -0,0 +1,194 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++
++#include "rk3566-soquartz.dtsi"
++
++/ {
++ model = "PINE64 RK3566 SOQuartz on Blade carrier board";
++ compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566";
++
++ /* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */
++ vcc3v0_sd: vcc3v0-sd-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v0_sd";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vcc3v3_sys>;
++ };
++
++ /* labeled VCC_SSD in schematic */
++ vcc3v3_pcie_p: vcc3v3-pcie-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc3v3_pcie_p";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ vin-supply = <&vbus>;
++ };
++
++ vcc5v_dcin: vcc5v-dcin-regulator {
++ compatible = "regulator-fixed";
++ regulator-name = "vcc5v_dcin";
++ regulator-always-on;
++ regulator-boot-on;
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ };
++};
++
++&combphy2 {
++ phy-supply = <&vcc3v3_sys>;
++ status = "okay";
++};
++
++&gmac1 {
++ status = "okay";
++};
++
++/*
++ * i2c1 is exposed on CM1 / Module1A
++ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
++ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
++ */
++&i2c1 {
++ status = "okay";
++
++};
++
++/*
++ * i2c2 is exposed on CM1 / Module1A - to PI40
++ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
++ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
++ */
++&i2c2 {
++ status = "disabled";
++};
++
++/*
++ * i2c3 is exposed on CM1 / Module1A - to PI40
++ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
++ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
++ */
++&i2c3 {
++ status = "disabled";
++};
++
++/*
++ * i2c4 is exposed on CM2 / Module1B - to PI40
++ * pin 45 - GPIO24 - i2c4_scl_m1
++ * pin 47 - GPIO23 - i2c4_sda_m1
++ */
++&i2c4 {
++ status = "disabled";
++};
++
++/*
++ * i2s1_8ch is exposed on CM1 / Module1A - to PI40
++ * pin 24 - GPIO26 - i2s1_sdi1_m1
++ * pin 25 - GPIO21 - i2s1_sdo0_m1
++ * pin 26 - GPIO19 - i2s1_lrck_tx_m1
++ * pin 27 - GPIO20 - i2s1_sdi0_m1
++ * pin 29 - GPIO16 - i2s1_sdi3_m1
++ * pin 30 - GPIO6 - i2s1_sdi2_m1
++ * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
++ * pin 41 - GPIO25 - i2s1_sdo2_m1
++ * pin 49 - GPIO18 - i2s1_sclk_tx_m1
++ * pin 50 - GPIO17 - i2s1_mclk_m1
++ * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
++ */
++&i2s1_8ch {
++ status = "disabled";
++};
++
++&led_diy {
++ color = <LED_COLOR_ID_RED>;
++ function = LED_FUNCTION_DISK_ACTIVITY;
++ linux,default-trigger = "disk-activity";
++ status = "okay";
++};
++
++&led_work {
++ color = <LED_COLOR_ID_GREEN>;
++ function = LED_FUNCTION_STATUS;
++ linux,default-trigger = "heartbeat";
++ status = "okay";
++};
++
++&pcie2x1 {
++ vpcie3v3-supply = <&vcc3v3_pcie_p>;
++ status = "okay";
++};
++
++&rgmii_phy1 {
++ status = "okay";
++};
++
++/*
++ * saradc is exposed on CM1 / Module1A - to J2
++ * pin 94 - AIN1 - saradc_vin3
++ * pin 96 - AIN0 - saradc_vin2
++ */
++&saradc {
++ status = "disabled";
++};
++
++&sdmmc0 {
++ vmmc-supply = <&vcc3v0_sd>;
++ status = "okay";
++};
++
++/*
++ * spi3 is exposed on CM1 / Module1A - to PI40
++ * pin 37 - GPIO7 - spi3_cs1_m0
++ * pin 38 - GPIO11 - spi3_clk_m0
++ * pin 39 - GPIO8 - spi3_cs0_m0
++ * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
++ * pin 44 - GPIO10 - spi3_mosi_m0
++ */
++&spi3 {
++ status = "disabled";
++};
++
++/*
++ * uart2 is exposed on CM1 / Module1A - to PI40
++ * pin 51 - GPIO15 - uart2_rx_m0
++ * pin 55 - GPIO14 - uart2_tx_m0
++ */
++&uart2 {
++ status = "okay";
++};
++
++/*
++ * uart7 is exposed on CM1 / Module1A - to PI40
++ * pin 46 - GPIO22 - uart7_tx_m2
++ * pin 47 - GPIO23 - uart7_rx_m2
++ */
++&uart7 {
++ status = "okay";
++};
++
++&usb2phy0 {
++ status = "okay";
++};
++
++&usb2phy0_otg {
++ phy-supply = <&vbus>;
++ status = "okay";
++};
++
++&usb_host0_xhci {
++ status = "okay";
++};
++
++&vbus {
++ vin-supply = <&vcc5v_dcin>;
++};
+--
+2.39.0
+
diff --git a/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-HDMI-sound-on-SOQuartz.patch b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-HDMI-sound-on-SOQuartz.patch
new file mode 100644
index 000000000..d4df69e16
--- /dev/null
+++ b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-HDMI-sound-on-SOQuartz.patch
@@ -0,0 +1,44 @@
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Sat, 12 Nov 2022 17:04:00 +0100
+Subject: arm64: dts: rockchip: Enable HDMI sound on SOQuartz
+Origin: https://git.kernel.org/linus/70b620c4ba919a87c607b8d98b08478b213877bd
+
+This patch enables the i2s0 node on SOQuartz, which is responsible
+for hdmi audio, and adds an hdmi-sound node to enable said audio.
+
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20221112160404.70868-4-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+index 0bfb0cea7d6b..1b975822effa 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+@@ -178,6 +178,10 @@
+ };
+ };
+
++&hdmi_sound {
++ status = "okay";
++};
++
+ &i2c0 {
+ status = "okay";
+
+@@ -446,6 +450,10 @@
+ status = "disabled";
+ };
+
++&i2s0_8ch {
++ status = "okay";
++};
++
+ /*
+ * i2s1_8ch is exposed on CM1 / Module1A
+ * pin 24 - i2s1_sdi1_m1
+--
+2.39.0
+
diff --git a/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch
new file mode 100644
index 000000000..1a8063e0f
--- /dev/null
+++ b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch
@@ -0,0 +1,82 @@
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Sat, 12 Nov 2022 17:04:01 +0100
+Subject: arm64: dts: rockchip: Enable PCIe 2 on SOQuartz CM4IO
+Origin: https://git.kernel.org/linus/3736aa7ecc4cd9b4abce30052bad00aba4f0362f
+
+This patch enables the PCIe2 on the CM4IO board when paired with
+a SOQuartz CM4 System-on-Module board. combphy2 also needs to be
+enabled in this case to make the PHY work for this.
+
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20221112160404.70868-5-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 11 +++++++++++
+ arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 15 +++++++++++++++
+ 2 files changed, 26 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
+index e00568a6be5c..263ce40770dd 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
+@@ -30,6 +30,12 @@
+ };
+ };
+
++/* phy for pcie */
++&combphy2 {
++ phy-supply = <&vcc3v3_sys>;
++ status = "okay";
++};
++
+ &gmac1 {
+ status = "okay";
+ };
+@@ -105,6 +111,11 @@
+ status = "okay";
+ };
+
++&pcie2x1 {
++ vpcie3v3-supply = <&vcc_3v3>;
++ status = "okay";
++};
++
+ &rgmii_phy1 {
+ status = "okay";
+ };
+diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+index 1b975822effa..ce7165d7f1a1 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+@@ -487,6 +487,12 @@
+ };
+ };
+
++&pcie2x1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pcie_reset_h>;
++ reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
++};
++
+ &pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+@@ -512,6 +518,15 @@
+ };
+ };
+
++ pcie {
++ pcie_clkreq_h: pcie-clkreq-h {
++ rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ pcie_reset_h: pcie-reset-h {
++ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++ };
++ };
++
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+--
+2.39.0
+
diff --git a/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-video-output-and-HDMI-on-S.patch b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-video-output-and-HDMI-on-S.patch
new file mode 100644
index 000000000..37cfbdb23
--- /dev/null
+++ b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-Enable-video-output-and-HDMI-on-S.patch
@@ -0,0 +1,94 @@
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Sat, 12 Nov 2022 17:03:59 +0100
+Subject: arm64: dts: rockchip: Enable video output and HDMI on SOQuartz
+Origin: https://git.kernel.org/linus/36d7a605706d9648526a0574b8e7b0e02fa70c2a
+
+This patch adds and enables the necessary device tree nodes to
+enable video output and HDMI functionality on the SOQuartz module.
+
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20221112160404.70868-3-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3566-soquartz.dtsi | 47 +++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+index 6e99f049501c..0bfb0cea7d6b 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+@@ -4,6 +4,7 @@
+
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3566.dtsi"
+
+ / {
+@@ -28,6 +29,17 @@
+ #clock-cells = <0>;
+ };
+
++ hdmi-con {
++ compatible = "hdmi-connector";
++ type = "a";
++
++ port {
++ hdmi_con_in: endpoint {
++ remote-endpoint = <&hdmi_out_con>;
++ };
++ };
++ };
++
+ leds {
+ compatible = "gpio-leds";
+
+@@ -148,6 +160,24 @@
+ status = "okay";
+ };
+
++&hdmi {
++ avdd-0v9-supply = <&vdda0v9_image>;
++ avdd-1v8-supply = <&vcca1v8_image>;
++ status = "okay";
++};
++
++&hdmi_in {
++ hdmi_in_vp0: endpoint {
++ remote-endpoint = <&vp0_out_hdmi>;
++ };
++};
++
++&hdmi_out {
++ hdmi_out_con: endpoint {
++ remote-endpoint = <&hdmi_con_in>;
++ };
++};
++
+ &i2c0 {
+ status = "okay";
+
+@@ -619,3 +649,20 @@
+ &usb_host0_xhci {
+ status = "disabled";
+ };
++
++&vop {
++ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++ status = "okay";
++};
++
++&vop_mmu {
++ status = "okay";
++};
++
++&vp0 {
++ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++ remote-endpoint = <&hdmi_in_vp0>;
++ };
++};
+--
+2.39.0
+
diff --git a/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-RK356x-Add-I2S2-device-node.patch b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-RK356x-Add-I2S2-device-node.patch
new file mode 100644
index 000000000..55c6af80b
--- /dev/null
+++ b/debian/patches/features/arm64/quartz64/arm64-dts-rockchip-RK356x-Add-I2S2-device-node.patch
@@ -0,0 +1,50 @@
+From: Shengyu Qu <wiagn233@outlook.com>
+Date: Sun, 30 Oct 2022 01:09:04 +0800
+Subject: arm64: dts: rockchip: RK356x: Add I2S2 device node
+Origin: https://git.kernel.org/linus/755f37010f3eac0bdfa41bdf2308e8380a93f10c
+
+This patch adds I2S2 device tree node for RK3566/RK3568.
+
+Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
+Link: https://lore.kernel.org/r/OS3P286MB259771C12F2B15A4DDF435FE98359@OS3P286MB2597.JPNP286.PROD.OUTLOOK.COM
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+index 10e3a0862602..5706c3e24f0a 100644
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -1091,6 +1091,28 @@
+ status = "disabled";
+ };
+
++ i2s2_2ch: i2s@fe420000 {
++ compatible = "rockchip,rk3568-i2s-tdm";
++ reg = <0x0 0xfe420000 0x0 0x1000>;
++ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
++ assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
++ assigned-clock-rates = <1188000000>;
++ clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
++ clock-names = "mclk_tx", "mclk_rx", "hclk";
++ dmas = <&dmac1 4>, <&dmac1 5>;
++ dma-names = "tx", "rx";
++ resets = <&cru SRST_M_I2S2_2CH>;
++ reset-names = "m";
++ rockchip,grf = <&grf>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&i2s2m0_sclktx
++ &i2s2m0_lrcktx
++ &i2s2m0_sdi
++ &i2s2m0_sdo>;
++ #sound-dai-cells = <0>;
++ status = "disabled";
++ };
++
+ i2s3_2ch: i2s@fe430000 {
+ compatible = "rockchip,rk3568-i2s-tdm";
+ reg = <0x0 0xfe430000 0x0 0x1000>;
+--
+2.39.0
+
diff --git a/debian/patches/features/arm64/quartz64/dt-bindings-arm-rockchip-Add-SOQuartz-Blade.patch b/debian/patches/features/arm64/quartz64/dt-bindings-arm-rockchip-Add-SOQuartz-Blade.patch
new file mode 100644
index 000000000..52fdca25d
--- /dev/null
+++ b/debian/patches/features/arm64/quartz64/dt-bindings-arm-rockchip-Add-SOQuartz-Blade.patch
@@ -0,0 +1,39 @@
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Wed, 16 Nov 2022 12:53:34 +0100
+Subject: [1/4] dt-bindings: arm: rockchip: Add SOQuartz Blade
+Origin: https://git.kernel.org/linus/8c84c2e51f3ee39b40e8078ebe3ad9c01fb17aff
+
+Add a compatible for the SOQuartz Blade base board to the rockchip
+platforms binding.
+
+The SOQuartz Blade is a PoE-capable carrier board for the CM4 SoM
+form factor, designed around the SOQuartz CM4 System-on-Module.
+
+The board features the usual connectivity (GPIO, USB, HDMI,
+Ethernet) and an M.2 slot for SSDs. It may also be powered from
+a 5V barrel jack input, and has a 3.5mm jack for UART debug
+output.
+
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20221116115337.541601-2-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
+index 3f31115ee99a..42f33240ade8 100644
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -593,6 +593,7 @@ properties:
+ - description: Pine64 SoQuartz SoM
+ items:
+ - enum:
++ - pine64,soquartz-blade
+ - pine64,soquartz-cm4io
+ - const: pine64,soquartz
+ - const: rockchip,rk3566
+--
+2.39.0
+
diff --git a/debian/patches/features/arm64/quartz64/dt-bindings-arm-rockchip-Add-SOQuartz-Model-A.patch b/debian/patches/features/arm64/quartz64/dt-bindings-arm-rockchip-Add-SOQuartz-Model-A.patch
new file mode 100644
index 000000000..2983e8a88
--- /dev/null
+++ b/debian/patches/features/arm64/quartz64/dt-bindings-arm-rockchip-Add-SOQuartz-Model-A.patch
@@ -0,0 +1,39 @@
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Wed, 16 Nov 2022 12:53:36 +0100
+Subject: [3/4] dt-bindings: arm: rockchip: Add SOQuartz Model A
+Origin: https://git.kernel.org/linus/7441d8c437883581dddfb616a087b399338244f0
+
+The SOQuartz Model A base board is a carrier board for the CM4
+form factor, designed around the PINE64 SOQuartz CM4 SoM.
+
+The board sports "Model A" dimensions like the Quartz64 Model A,
+but is not to be confused with that.
+
+As for I/O, it features USB 2 ports, Gigabit Ethernet, a PCIe 2
+x1 slot, HDMI, a 40-pin GPIO header, CSI/DSI connectors, an eDP
+flat-flex cable connector, a 12V DC barrel jack for power input
+and power/reset buttons as well as a microSD card slot.
+
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20221116115337.541601-4-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
+index 42f33240ade8..88ff4422a8c1 100644
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -595,6 +595,7 @@ properties:
+ - enum:
+ - pine64,soquartz-blade
+ - pine64,soquartz-cm4io
++ - pine64,soquartz-model-a
+ - const: pine64,soquartz
+ - const: rockchip,rk3566
+
+--
+2.39.0
+